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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/rtl/verilog/ethmac
    from Rev 409 to Rev 439
    ↔ Reverse comparison
  •

Rev 409 → Rev 439

/eth_spram_256x32.v
76,7 → 76,7
 
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
clk, rst, ce, we, oe, addr, di, dato
 
`ifdef ETH_BIST
,
101,7 → 101,7
input oe; // Output enable input, active high
input [7:0] addr; // address bus inputs
input [31:0] di; // input data bus
output [31:0] do; // output data bus
output [31:0] dato; // output data bus
 
`ifdef ETH_BIST
136,7 → 136,7
 
RAMB4_S8 ram0
(
.DO (do[7:0]),
.DO (dato[7:0]),
.ADDR ({1'b0, addr}),
.DI (di[7:0]),
.EN (ce),
147,7 → 147,7
 
RAMB4_S8 ram1
(
.DO (do[15:8]),
.DO (dato[15:8]),
.ADDR ({1'b0, addr}),
.DI (di[15:8]),
.EN (ce),
158,7 → 158,7
 
RAMB4_S8 ram2
(
.DO (do[23:16]),
.DO (dato[23:16]),
.ADDR ({1'b0, addr}),
.DI (di[23:16]),
.EN (ce),
169,7 → 169,7
 
RAMB4_S8 ram3
(
.DO (do[31:24]),
.DO (dato[31:24]),
.ADDR ({1'b0, addr}),
.DI (di[31:24]),
.EN (ce),
194,7 → 194,7
.OEN (!oe),
.ADR (addr),
.DI (di),
.DOUT (do)
.DOUT (dato)
 
`ifdef ETH_BIST
,
222,7 → 222,7
.OEN (!oe),
.A (addr),
.D (di),
.Q (do)
.Q (dato)
 
`ifdef ETH_BIST
,
242,7 → 242,7
.wren (ce & we),
.clock (clk),
.data (di),
.q (do)
.q (dato)
); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
 
`else // !ETH_ALTERA_ALTSYNCRAM
268,7 → 268,7
// Data output drivers
//
//assign do = (oe & ce) ? q : {32{1'bz}};
assign do = (oe & ce) ? q : {32{1'bx}};
assign dato = (oe & ce) ? q : {32{1'bx}};
 
//
// RAM read and write
321,7 → 321,7
input [7:0] finish;
integer rnum;
begin
for (rnum=start;rnum<=finish;rnum=rnum+1)
for (rnum={24'd0,start};rnum<={24'd0,finish};rnum=rnum+1)
$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
end
endtask
/eth_shiftreg.v
118,12 → 118,14
begin
if(|ByteSelect)
begin
/* verilator lint_off CASEINCOMPLETE */
case (ByteSelect[3:0]) // synopsys parallel_case full_case
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
endcase
endcase // case (ByteSelect[3:0])
/* verilator lint_on CASEINCOMPLETE */
end
else
begin
/eth_rxethmac.v
39,339 → 39,332
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.11 2004/03/17 09:32:15 igorm
// Multicast detection fixed. Only the LSB of the first byte is checked.
//
// Revision 1.10 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.9 2002/11/19 17:35:35 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.8 2002/02/16 07:15:27 mohor
// Testbench fixed, code simplified, unused signals removed.
//
// Revision 1.7 2002/02/15 13:44:28 mohor
// RxAbort is an output. No need to have is declared as wire.
//
// Revision 1.6 2002/02/15 11:17:48 mohor
// File format changed.
//
// Revision 1.5 2002/02/14 20:48:43 billditt
// Addition of new module eth_addrcheck.v
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
//
 
`include "timescale.v"
 
 
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
);
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG,
HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm,
ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
CrcError, StateIdle, StatePreamble, StateSFD, StateData,
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss,
PassAll, ControlFrmAddressOK
);
 
parameter Tp = 1;
input MRxClk;
input MRxDV;
input [3:0] MRxD;
input Transmitting;
input HugEn;
input DlyCrcEn;
input [15:0] MaxFL;
input r_IFG;
input Reset;
input [47:0] MAC; // Station Address
input r_Bro; // broadcast disable
input r_Pro; // promiscuous enable
input [31:0] r_HASH0; // lower 4 bytes Hash Table
input [31:0] r_HASH1; // upper 4 bytes Hash Table
input PassAll;
input ControlFrmAddressOK;
 
output [7:0] RxData;
output RxValid;
output RxStartFrm;
output RxEndFrm;
output [15:0] ByteCnt;
output ByteCntEq0;
output ByteCntGreat2;
output ByteCntMaxFrame;
output CrcError;
output StateIdle;
output StatePreamble;
output StateSFD;
output [1:0] StateData;
output RxAbort;
output AddressMiss;
 
reg [7:0] RxData;
reg RxValid;
reg RxStartFrm;
reg RxEndFrm;
reg Broadcast;
reg Multicast;
reg [5:0] CrcHash;
reg CrcHashGood;
reg DelayData;
reg [7:0] LatchedByte;
reg [7:0] RxData_d;
reg RxValid_d;
reg RxStartFrm_d;
reg RxEndFrm_d;
 
input MRxClk;
input MRxDV;
input [3:0] MRxD;
input Transmitting;
input HugEn;
input DlyCrcEn;
input [15:0] MaxFL;
input r_IFG;
input Reset;
input [47:0] MAC; // Station Address
input r_Bro; // broadcast disable
input r_Pro; // promiscuous enable
input [31:0] r_HASH0; // lower 4 bytes Hash Table
input [31:0] r_HASH1; // upper 4 bytes Hash Table
input PassAll;
input ControlFrmAddressOK;
wire MRxDEqD;
wire MRxDEq5;
wire StateDrop;
wire ByteCntEq1;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire ByteCntEq6;
wire ByteCntEq7;
wire ByteCntSmall7;
wire [31:0] Crc;
wire Enable_Crc;
wire Initialize_Crc;
wire [3:0] Data_Crc;
wire GenerateRxValid;
wire GenerateRxStartFrm;
wire GenerateRxEndFrm;
wire DribbleRxEndFrm;
wire [3:0] DlyCrcCnt;
wire IFGCounterEq24;
 
output [7:0] RxData;
output RxValid;
output RxStartFrm;
output RxEndFrm;
output [15:0] ByteCnt;
output ByteCntEq0;
output ByteCntGreat2;
output ByteCntMaxFrame;
output CrcError;
output StateIdle;
output StatePreamble;
output StateSFD;
output [1:0] StateData;
output RxAbort;
output AddressMiss;
assign MRxDEqD = MRxD == 4'hd;
assign MRxDEq5 = MRxD == 4'h5;
 
reg [7:0] RxData;
reg RxValid;
reg RxStartFrm;
reg RxEndFrm;
reg Broadcast;
reg Multicast;
reg [5:0] CrcHash;
reg CrcHashGood;
reg DelayData;
reg [7:0] LatchedByte;
reg [7:0] RxData_d;
reg RxValid_d;
reg RxStartFrm_d;
reg RxEndFrm_d;
 
wire MRxDEqD;
wire MRxDEq5;
wire StateDrop;
wire ByteCntEq1;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire ByteCntEq6;
wire ByteCntEq7;
wire ByteCntSmall7;
wire [31:0] Crc;
wire Enable_Crc;
wire Initialize_Crc;
wire [3:0] Data_Crc;
wire GenerateRxValid;
wire GenerateRxStartFrm;
wire GenerateRxEndFrm;
wire DribbleRxEndFrm;
wire [3:0] DlyCrcCnt;
wire IFGCounterEq24;
// Rx State Machine module
eth_rxstatem rxstatem1
(
.MRxClk(MRxClk),
.Reset(Reset),
.MRxDV(MRxDV),
.ByteCntEq0(ByteCntEq0),
.ByteCntGreat2(ByteCntGreat2),
.Transmitting(Transmitting),
.MRxDEq5(MRxDEq5),
.MRxDEqD(MRxDEqD),
.IFGCounterEq24(IFGCounterEq24),
.ByteCntMaxFrame(ByteCntMaxFrame),
.StateData(StateData),
.StateIdle(StateIdle),
.StatePreamble(StatePreamble),
.StateSFD(StateSFD),
.StateDrop(StateDrop)
);
 
assign MRxDEqD = MRxD == 4'hd;
assign MRxDEq5 = MRxD == 4'h5;
 
// Rx Counters module
eth_rxcounters rxcounters1
(.MRxClk(MRxClk),
.Reset(Reset),
.MRxDV(MRxDV),
.StateIdle(StateIdle),
.StateSFD(StateSFD),
.StateData(StateData),
.StateDrop(StateDrop),
.StatePreamble(StatePreamble),
.MRxDEqD(MRxDEqD),
.DlyCrcEn(DlyCrcEn),
.DlyCrcCnt(DlyCrcCnt),
.Transmitting(Transmitting),
.MaxFL(MaxFL),
.r_IFG(r_IFG),
.HugEn(HugEn),
.IFGCounterEq24(IFGCounterEq24),
.ByteCntEq0(ByteCntEq0),
.ByteCntEq1(ByteCntEq1),
.ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3),
.ByteCntEq4(ByteCntEq4),
.ByteCntEq5(ByteCntEq5),
.ByteCntEq6(ByteCntEq6),
.ByteCntEq7(ByteCntEq7),
.ByteCntGreat2(ByteCntGreat2),
.ByteCntSmall7(ByteCntSmall7),
.ByteCntMaxFrame(ByteCntMaxFrame),
.ByteCntOut(ByteCnt)
);
 
// Rx State Machine module
eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
.ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
.MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
.StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
.StateSFD(StateSFD), .StateDrop(StateDrop)
);
// Rx Address Check
 
eth_rxaddrcheck rxaddrcheck1
(.MRxClk(MRxClk),
.Reset( Reset),
.RxData(RxData),
.Broadcast (Broadcast),
.r_Bro (r_Bro),
.r_Pro(r_Pro),
.ByteCntEq6(ByteCntEq6),
.ByteCntEq7(ByteCntEq7),
.ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3),
.ByteCntEq4(ByteCntEq4),
.ByteCntEq5(ByteCntEq5),
.HASH0(r_HASH0),
.HASH1(r_HASH1),
.CrcHash(CrcHash),
.CrcHashGood(CrcHashGood),
.StateData(StateData),
.Multicast(Multicast),
.MAC(MAC),
.RxAbort(RxAbort),
.RxEndFrm(RxEndFrm),
.AddressMiss(AddressMiss),
.PassAll(PassAll),
.ControlFrmAddressOK(ControlFrmAddressOK)
);
 
// Rx Counters module
eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
.ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
.ByteCntOut(ByteCnt)
);
 
// Rx Address Check
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) &
DlyCrcCnt[3:0] < 4'h9;
 
eth_rxaddrcheck rxaddrcheck1
(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
.HASH0(r_HASH0), .HASH1(r_HASH1),
.CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
.ControlFrmAddressOK(ControlFrmAddressOK)
);
assign Data_Crc[0] = MRxD[3];
assign Data_Crc[1] = MRxD[2];
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[3] = MRxD[0];
 
 
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
// Connecting module Crc
eth_crc crcrx
(.Clk(MRxClk),
.Reset(Reset),
.Data(Data_Crc),
.Enable(Enable_Crc),
.Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
 
assign Data_Crc[0] = MRxD[3];
assign Data_Crc[1] = MRxD[2];
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[3] = MRxD[0];
 
 
// Connecting module Crc
eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Latching CRC for use in the hash table
 
always @ (posedge MRxClk)
begin
CrcHashGood <= StateData[0] & ByteCntEq6;
end
 
always @ (posedge MRxClk)
begin
if(Reset | StateIdle)
CrcHash[5:0] <= 6'h0;
else
if(StateData[0] & ByteCntEq6)
CrcHash[5:0] <= Crc[31:26];
end
 
// Latching CRC for use in the hash table
 
always @ (posedge MRxClk)
begin
CrcHashGood <= StateData[0] & ByteCntEq6;
end
// Output byte stream
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxData_d[7:0] <= 8'h0;
DelayData <= 1'b0;
LatchedByte[7:0] <= 8'h0;
RxData[7:0] <= 8'h0;
end
else
begin
// Latched byte
LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]};
DelayData <= StateData[0];
 
always @ (posedge MRxClk)
begin
if(Reset | StateIdle)
CrcHash[5:0] <= 6'h0;
else
if(StateData[0] & ByteCntEq6)
CrcHash[5:0] <= Crc[31:26];
end
if(GenerateRxValid)
// Data goes through only in data state
RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}};
else
if(~DelayData)
// Delaying data to be valid for two cycles.
// Zero when not active.
RxData_d[7:0] <= 8'h0;
 
RxData[7:0] <= RxData_d[7:0]; // Output data byte
end
end
 
// Output byte stream
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxData_d[7:0] <= 8'h0;
DelayData <= 1'b0;
LatchedByte[7:0] <= 8'h0;
RxData[7:0] <= 8'h0;
end
else
begin
LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]}; // Latched byte
DelayData <= StateData[0];
 
if(GenerateRxValid)
RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
else
if(~DelayData)
RxData_d[7:0] <= 8'h0; // Delaying data to be valid for two cycles. Zero when not active.
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Broadcast <= 1'b0;
else
begin
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
Broadcast <= 1'b0;
else
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
Broadcast <= 1'b1;
else
if(RxAbort | RxEndFrm)
Broadcast <= 1'b0;
end
end
 
RxData[7:0] <= RxData_d[7:0]; // Output data byte
end
end
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Multicast <= 1'b0;
else
begin
if(StateData[0] & ByteCntEq1 & LatchedByte[0])
Multicast <= 1'b1;
else if(RxAbort | RxEndFrm)
Multicast <= 1'b0;
end
end
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Broadcast <= 1'b0;
else
begin
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
Broadcast <= 1'b0;
else
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
Broadcast <= 1'b1;
else
if(RxAbort | RxEndFrm)
Broadcast <= 1'b0;
end
end
 
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Multicast <= 1'b0;
else
begin
if(StateData[0] & ByteCntEq1 & LatchedByte[0])
Multicast <= 1'b1;
else if(RxAbort | RxEndFrm)
Multicast <= 1'b0;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxValid_d <= 1'b0;
RxValid <= 1'b0;
end
else
begin
RxValid_d <= GenerateRxValid;
RxValid <= RxValid_d;
end
end
 
 
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
assign GenerateRxStartFrm = StateData[0] &
((ByteCntEq1 & ~DlyCrcEn) |
((DlyCrcCnt == 4'h3) & DlyCrcEn));
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxValid_d <= 1'b0;
RxValid <= 1'b0;
end
else
begin
RxValid_d <= GenerateRxValid;
RxValid <= RxValid_d;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStartFrm_d <= 1'b0;
RxStartFrm <= 1'b0;
end
else
begin
RxStartFrm_d <= GenerateRxStartFrm;
RxStartFrm <= RxStartFrm_d;
end
end
 
 
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
assign GenerateRxEndFrm = StateData[0] &
(~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStartFrm_d <= 1'b0;
RxStartFrm <= 1'b0;
end
else
begin
RxStartFrm_d <= GenerateRxStartFrm;
RxStartFrm <= RxStartFrm_d;
end
end
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxEndFrm_d <= 1'b0;
RxEndFrm <= 1'b0;
end
else
begin
RxEndFrm_d <= GenerateRxEndFrm;
RxEndFrm <= RxEndFrm_d | DribbleRxEndFrm;
end
end
 
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
 
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxEndFrm_d <= 1'b0;
RxEndFrm <= 1'b0;
end
else
begin
RxEndFrm_d <= GenerateRxEndFrm;
RxEndFrm <= RxEndFrm_d | DribbleRxEndFrm;
end
end
 
 
endmodule
/eth_rxcounters.v
39,58 → 39,18
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/02/15 11:13:29 mohor
// Format of the file changed a bit.
//
// Revision 1.4 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
//
//
 
 
`include "timescale.v"
 
 
module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
);
module eth_rxcounters
(
MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
);
 
parameter Tp = 1;
 
input MRxClk;
input Reset;
input MRxDV;
146,30 → 106,30
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= 16'h0;
ByteCnt[15:0] <= 16'd0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= 16'h0;
ByteCnt[15:0] <= 16'd0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1;
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
 
assign ByteCntDelayed = ByteCnt + 3'h4;
assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
assign ByteCntDelayed = ByteCnt + 16'd4;
assign ByteCntOut = DlyCrcEn ? ByteCntDelayed : ByteCnt;
 
assign ByteCntEq0 = ByteCnt == 16'h0;
assign ByteCntEq1 = ByteCnt == 16'h1;
assign ByteCntEq2 = ByteCnt == 16'h2;
assign ByteCntEq3 = ByteCnt == 16'h3;
assign ByteCntEq4 = ByteCnt == 16'h4;
assign ByteCntEq5 = ByteCnt == 16'h5;
assign ByteCntEq6 = ByteCnt == 16'h6;
assign ByteCntEq7 = ByteCnt == 16'h7;
assign ByteCntGreat2 = ByteCnt > 16'h2;
assign ByteCntSmall7 = ByteCnt < 16'h7;
assign ByteCntEq0 = ByteCnt == 16'd0;
assign ByteCntEq1 = ByteCnt == 16'd1;
assign ByteCntEq2 = ByteCnt == 16'd2;
assign ByteCntEq3 = ByteCnt == 16'd3;
assign ByteCntEq4 = ByteCnt == 16'd4;
assign ByteCntEq5 = ByteCnt == 16'd5;
assign ByteCntEq6 = ByteCnt == 16'd6;
assign ByteCntEq7 = ByteCnt == 16'd7;
assign ByteCntGreat2 = ByteCnt > 16'd2;
assign ByteCntSmall7 = ByteCnt < 16'd7;
assign ByteCntMax = ByteCnt == 16'hffff;
assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
 
188,7 → 148,7
IFGCounter[4:0] <= 5'h0;
else
if(IncrementIFGCounter)
IFGCounter[4:0] <= IFGCounter[4:0] + 1'b1;
IFGCounter[4:0] <= IFGCounter[4:0] + 5'd1;
end
end
 
210,7 → 170,7
DlyCrcCnt[3:0] <= 4'h1;
else
if(DlyCrcEn & (|DlyCrcCnt[3:0]))
DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 1'b1;
DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 4'd1;
end
end
 
/eth_txethmac.v
341,7 → 341,7
RetryCnt[3:0] <= 4'h0;
else
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
RetryCnt[3:0] <= RetryCnt[3:0] + 1'b1;
RetryCnt[3:0] <= RetryCnt[3:0] + 1;
end
end
 
/eth_wishbone.v
69,7 → 69,8
PerPacketPad,
 
//RX
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
RxStatusWriteLatched_sync2,
// Register
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
79,11 → 80,13
// Rx Status
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
AddressMiss,
ReceivedPauseFrm,
// Tx Status
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched,
CarrierSenseLost
 
// Bist
`ifdef ETH_BIST
103,10 → 106,6
);
 
 
//parameter Tp = 1;
parameter Tp = 0;
 
 
// WISHBONE common
input WB_CLK_I; // WISHBONE clock
input [31:0] WB_DAT_I; // WISHBONE data input
261,10 → 260,10
reg TxAbortPacket;
reg TxAbortPacket_NotCleared;
reg RxBDReady;
reg RxBDOK;
reg RxBDOK/* synthesis syn_allow_retiming=0*/;
reg TxBDReady;
 
reg RxBDRead;
reg RxBDRead ;
 
reg [31:0] TxDataLatched;
reg [1:0] TxByteCnt;
340,8 → 339,8
reg [8:0] RxStatusInLatched;
 
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
reg RxEn, RxEn_q /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
reg TxEn, TxEn_q /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
reg r_TxEn_q;
reg r_RxEn_q;
 
358,7 → 357,7
reg RxEn_needed;
 
wire StartRxPointerRead;
reg RxPointerRead;
reg RxPointerRead/* synthesis syn_allow_retiming=0*/;
 
// RX shift ending signals
reg ShiftEnded_rck;
376,11 → 375,68
reg rx_wb_last_writes;
 
`ifdef TXBD_POLL
reg [31:0] TxBDReadySamples; // -- jb
wire TxBDNotReady; // -- jb
`endif
reg StartOccured;
reg TxStartFrm_sync1;
reg TxStartFrm_sync2;
reg TxStartFrm_syncb1;
reg TxStartFrm_syncb2;
 
wire TxFifoClear;
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire SetReadTxDataFromMemory;
reg BlockReadTxDataFromMemory/* synthesis syn_allow_retiming=0*/;
 
reg tx_burst_en;
reg rx_burst_en;
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
wire ReadTxDataFromMemory_2;
wire tx_burst;
 
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
 
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
 
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
 
wire rx_burst;
wire enough_data_in_rxfifo_for_burst;
wire enough_data_in_rxfifo_for_burst_plus1;
 
reg ReadTxDataFromMemory/* synthesis syn_allow_retiming=0*/;
wire WriteRxDataToMemory;
reg WriteRxDataToMemory_r ;
reg MasterWbTX;
reg MasterWbRX;
 
reg [29:0] m_wb_adr_o;
reg m_wb_cyc_o;
reg [3:0] m_wb_sel_o;
reg m_wb_we_o;
 
wire TxLengthEq0;
wire TxLengthLt4;
 
reg BlockingIncrementTxPointer;
reg [31:2] TxPointerMSB;
reg [1:0] TxPointerLSB;
reg [1:0] TxPointerLSB_rst;
reg [31:2] RxPointerMSB;
reg [1:0] RxPointerLSB_rst;
 
wire RxBurstAcc;
wire RxWordAcc;
wire RxHalfAcc;
wire RxByteAcc;
 
`ifdef ETH_WISHBONE_B3
`ifndef BURST_4BEAT
assign m_wb_bte_o = 2'b00; // Linear burst
408,7 → 464,7
.oe (ram_oe),
.addr (ram_addr),
.di (ram_di),
.do (ram_do)
.dato (ram_do)
`ifdef ETH_BIST
,
.mbist_si_i (mbist_si_i),
448,11 → 504,12
ram_addr <= 8'h0;
ram_di <= 32'h0;
BDRead <= 1'b0;
BDWrite <= 1'b0;
BDWrite <= 0;
end
else
begin
// Switching between three stages depends on enable signals
/* verilator lint_off CASEINCOMPLETE */ // JB
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
5'b100_10, 5'b100_11 :
begin
516,7 → 573,8
BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
BDRead <= (|BDCs) & ~WB_WE_I;
end
endcase
endcase //case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})
/* verilator lint_on CASEINCOMPLETE */
end
end
 
573,30 → 631,6
TxBDReady <= 1'b0;
end
 
`ifdef TXBD_POLL
// Register TxBDReady 4 times, when all are low we know this one is not
// good to transmit
always @(posedge WB_CLK_I or posedge Reset) // -- jb
begin
if (Reset) TxBDReadySamples <= 32'hffffffff;
else begin
if (r_TxEn)
begin
if (TxBDNotReady)
TxBDReadySamples <= 32'hffffffff;
else
TxBDReadySamples[31:0] <= {TxBDReadySamples[30:0],TxBDReady};
end
else
TxBDReadySamples <= 32'hffffffff;
end // else: !if(Reset)
end // always @ (posedge WB_CLK_I or posedge Reset)
// When all low, this goes high -- jb
assign TxBDNotReady = ~(|TxBDReadySamples);
 
`endif
 
// Reading the Tx buffer descriptor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) &
~BlockingTxBDRead & ~TxBDReady;
711,9 → 745,6
TxStatus <= ram_do[14:11];
end
 
reg ReadTxDataFromMemory;
wire WriteRxDataToMemory;
reg WriteRxDataToMemory_r;
 
// Register WriteRxDataToMemory in Wishbone clock domain
// so it doesn't get out of sync with burst capability indication signals
722,30 → 753,8
WriteRxDataToMemory_r <= 0;
else
WriteRxDataToMemory_r <= WriteRxDataToMemory;
reg MasterWbTX;
reg MasterWbRX;
 
reg [29:0] m_wb_adr_o;
reg m_wb_cyc_o;
reg [3:0] m_wb_sel_o;
reg m_wb_we_o;
 
wire TxLengthEq0;
wire TxLengthLt4;
 
reg BlockingIncrementTxPointer;
reg [31:2] TxPointerMSB;
reg [1:0] TxPointerLSB;
reg [1:0] TxPointerLSB_rst;
reg [31:2] RxPointerMSB;
reg [1:0] RxPointerLSB_rst;
 
wire RxBurstAcc;
wire RxWordAcc;
wire RxHalfAcc;
wire RxByteAcc;
 
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
761,19 → 770,19
TxLength <= 16'h0;
else
if(TxPointerLSB_rst==2'h0)
TxLength <= TxLength - 3'h4; // Length is subtracted at
TxLength <= TxLength - 16'd4; // Length is subtracted at
// the data request
else
if(TxPointerLSB_rst==2'h1)
TxLength <= TxLength - 3'h3; // Length is subtracted
TxLength <= TxLength - 16'd3; // Length is subtracted
// at the data request
else
if(TxPointerLSB_rst==2'h2)
TxLength <= TxLength - 3'h2; // Length is subtracted
TxLength <= TxLength - 16'd2; // Length is subtracted
// at the data request
else
if(TxPointerLSB_rst==2'h3)
TxLength <= TxLength - 3'h1; // Length is subtracted
TxLength <= TxLength - 16'd1; // Length is subtracted
// at the data request
end
end
809,7 → 818,7
else
if(IncrTxPointer & ~BlockingIncrementTxPointer)
// TxPointer is word-aligned
TxPointerMSB <= TxPointerMSB + 1'b1;
TxPointerMSB <= TxPointerMSB + 1;
end
 
 
862,14 → 871,6
end
 
 
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire SetReadTxDataFromMemory;
 
reg BlockReadTxDataFromMemory;
 
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
 
always @ (posedge WB_CLK_I or posedge Reset)
884,17 → 885,6
ReadTxDataFromMemory <= 1'b1;
end
 
reg tx_burst_en;
reg rx_burst_en;
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
wire ReadTxDataFromMemory_2;
wire tx_burst;
 
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
 
assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory &
~BlockReadTxDataFromMemory | (|tx_burst_cnt);
915,18 → 905,10
BlockReadTxDataFromMemory <= 1'b0;
end
 
`define TX_BURST_EN_CONDITION (txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)))
`define TX_BURST_EN_CONDITION ({1'b0,txfifo_cnt}<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)))
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
 
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
 
wire rx_burst;
wire enough_data_in_rxfifo_for_burst;
wire enough_data_in_rxfifo_for_burst_plus1;
 
// Enabling master wishbone access to the memory for two devices TX and RX.
always @ (posedge WB_CLK_I or posedge Reset)
begin
954,7 → 936,7
else
begin
// Switching between two stages depends on enable signals
casex ({MasterWbTX,
casez ({MasterWbTX,
MasterWbRX,
ReadTxDataFromMemory_2,
WriteRxDataToMemory_r,
964,9 → 946,9
rx_burst}) // synopsys parallel_case
8'b00_10_00_10, // Idle and MRB needed
8'b10_1x_10_1x, // MRB continues
8'b10_1?_10_1?, // MRB continues
8'b10_10_01_10, // Clear (previously MR) and MRB needed
8'b01_1x_01_1x: // Clear (previously MW) and MRB needed
8'b01_1?_01_1?: // Clear (previously MW) and MRB needed
begin
MasterWbTX <= 1'b1; // tx burst
MasterWbRX <= 1'b0;
979,7 → 961,7
if(tx_burst_cnt==0)
m_wb_adr_o <= TxPointerMSB;
else
m_wb_adr_o <= m_wb_adr_o+1'b1;
m_wb_adr_o <= m_wb_adr_o + 1;
 
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
999,10 → 981,10
end
end // case: 8'b00_10_00_10,...
`ifdef ETH_RX_BURST_EN
8'b00_x1_00_x1, // Idle and MWB needed
8'b01_x1_10_x1, // MWB continues
8'b00_?1_00_?1, // Idle and MWB needed
8'b01_?1_10_?1, // MWB continues
8'b01_01_01_01, // Clear (previously MW) and MWB needed
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
8'b10_?1_01_?1 : // Clear (previously MR) and MWB needed
begin
MasterWbTX <= 1'b0; // rx burst
MasterWbRX <= 1'b1;
1011,12 → 993,12
m_wb_sel_o <= RxByteSel;
IncrTxPointer<= 1'b0;
cyc_cleared<= 1'b0;
rx_burst_cnt <= rx_burst_cnt+3'h1;
rx_burst_cnt <= rx_burst_cnt+3'd1;
 
if(rx_burst_cnt==0)
m_wb_adr_o <= RxPointerMSB;
else
m_wb_adr_o <= m_wb_adr_o+1'b1;
m_wb_adr_o <= m_wb_adr_o + 1;
 
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
1036,8 → 1018,8
end
end // case: 8'b00_x1_00_x1,...
`endif // `ifdef ETH_RX_BURST_EN
8'b00_x1_00_x0 ,//idle and MW is needed (data write to rx buffer)
8'b01_x1_00_x0 :// Sometimes gets caught changing states - JB
8'b00_?1_00_?0 ,//idle and MW is needed (data write to rx buffer)
8'b01_?1_00_?0 :// Sometimes gets caught changing states - JB
begin
MasterWbTX <= 1'b0;
MasterWbRX <= !RxBufferEmpty;
1096,7 → 1078,7
`endif
end
8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
8'b01_1x_01_0x :// MW and MR is needed (data read from tx
8'b01_1?_01_0? :// MW and MR is needed (data read from tx
// buffer)
begin
MasterWbTX <= 1'b1; // Only switch to TX here
1132,7 → 1114,7
end
8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
8'b10_x1_01_x0 ://MR and MW is needed (data write to rx buffer)
8'b10_?1_01_?0 ://MR and MW is needed (data write to rx buffer)
begin
MasterWbTX <= 1'b0;
MasterWbRX <= !RxBufferEmpty;
1163,11 → 1145,11
end
8'b01_01_10_00,// MW and MW needed (cycle is cleared between
// previous and next access)
8'b01_1x_10_x0,// MW and MW or MR or MRB needed (cycle is
8'b01_1?_10_?0,// MW and MW or MR or MRB needed (cycle is
// cleared between previous and next access)
8'b10_10_10_00,// MR and MR needed (cycle is cleared between
// previous and next access)
8'b10_x1_10_0x :// MR and MR or MW or MWB (cycle is cleared
8'b10_?1_10_0? :// MR and MR or MW or MWB (cycle is cleared
// between previous and next access)
begin
m_wb_cyc_o <= 1'b0;// whatever and master read or write is
1190,9 → 1172,9
m_wb_cti_o <= 3'b0;
`endif
end
8'bxx_00_10_00,// whatever and no master read or write is needed
8'b??_00_10_00,// whatever and no master read or write is needed
// (ack or err comes finishing previous access)
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
8'b??_00_01_00 : // Between cyc_cleared request was cleared
begin
MasterWbTX <= 1'b0;
MasterWbRX <= 1'b0;
1244,9 → 1226,6
end
end
 
 
wire TxFifoClear;
 
assign TxFifoClear = (TxAbortPacket | TxRetryPacket | StartTxPointerRead);
eth_fifo
1271,16 → 1250,8
.cnt(txfifo_cnt)
);
 
 
reg StartOccured;
reg TxStartFrm_sync1;
reg TxStartFrm_sync2;
reg TxStartFrm_syncb1;
reg TxStartFrm_syncb2;
 
 
 
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
// Start: Generation of the TxStartFrm_wb which is then synchronized to the
// MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
1421,13 → 1392,10
 
 
// Temporary Tx and Rx buffer descriptor address
`ifdef TXBD_POLL
assign TempTxBDAddress[7:1] = {7{ (TxStatusWrite|TxBDNotReady) & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) -- jb
`else
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
`endif
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1) ; // Tx BD increment or wrap (last BD)
 
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
{7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
{7{~WrapRxStatusBit}} & (RxBDAddress + 1) ; // Using next Rx BD (incremenrement address)
 
 
// Latching Tx buffer descriptor address
1437,12 → 1405,8
TxBDAddress <= 7'h0;
else if (r_TxEn & (~r_TxEn_q))
TxBDAddress <= 7'h0;
`ifdef TXBD_POLL
else if (TxStatusWrite | TxBDNotReady) // -- jb
`else
else if (TxStatusWrite)
`endif
TxBDAddress <= TempTxBDAddress;
else if (TxStatusWrite)
TxBDAddress <= TempTxBDAddress;
end
 
 
1966,7 → 1930,7
rx_just_read_bd <= (RxEn & RxEn_q & RxBDRead);
 
// Signal to indicate we've checked and the RxBD we want to use is not free
reg rx_waiting_for_bd_to_become_free;
reg rx_waiting_for_bd_to_become_free/*syn_allow_retiming=0; syn_keep=1; syn_preserve=1*/;
always @ (posedge WB_CLK_I or posedge Reset)
if(Reset)
rx_waiting_for_bd_to_become_free <= 0;
2034,7 → 1998,7
if(MasterWbRX & m_wb_ack_i)
// Word access (always word access. m_wb_sel_o are used for
// selecting bytes)
RxPointerMSB <= RxPointerMSB + 1'b1;
RxPointerMSB <= RxPointerMSB + 1;
end
 
 
2131,7 → 2095,7
endcase
else
if(RxValid & RxEnableWindow /*& RxReady*/ | LastByteIn)
RxByteCnt <= RxByteCnt + 1'b1;
RxByteCnt <= RxByteCnt + 1;
end
 
 
2150,7 → 2114,7
endcase
else
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
RxValidBytes <= RxValidBytes + 1'b1;
RxValidBytes <= RxValidBytes + 1;
end
 
 
2211,11 → 2175,11
 
 
// Indicating start of the reception process
assign SetWriteRxDataToFifo = (RxValid &/* RxReady &*/ ~RxStartFrm &
RxEnableWindow & (&RxByteCnt)) |
(RxValid &/* RxReady &*/ RxStartFrm &
(&RxPointerLSB_rst)) |
(ShiftWillEnd & LastByteIn & (&RxByteCnt));
assign SetWriteRxDataToFifo = (RxValid & ~RxStartFrm &
RxEnableWindow & (&RxByteCnt))
/*| (RxValid & RxStartFrm &
(&RxPointerLSB_rst)) */
|(ShiftWillEnd & LastByteIn & (&RxByteCnt));
 
always @ (posedge MRxClk or posedge Reset)
begin
2263,8 → 2227,8
~WriteRxDataToFifoSync3;
// Receive fifo selection register - JB
reg [3:0] rx_shift_ended_wb_shr;
reg rx_ethside_fifo_sel;
reg rx_wbside_fifo_sel;
reg rx_ethside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
reg rx_wbside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
 
// Shift in this - our detection of end of data RX
always @(posedge WB_CLK_I)
2454,10 → 2418,9
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>(`ETH_BURST_LENGTH - 1);
// While receiving, don't flog the bus too hard, only write out when
// we can burst. But when finishing keep going until we've emptied the fifo
assign write_rx_data_to_memory_go =
RxEnableWindow & (rx_wbside_fifo_sel == rx_ethside_fifo_sel) ?
(rxfifo_cnt>(`ETH_BURST_LENGTH)+2) |
(|rx_burst_cnt) : ~RxBufferEmpty;
assign write_rx_data_to_memory_go
= RxEnableWindow & (rx_wbside_fifo_sel == rx_ethside_fifo_sel) ?
(rxfifo_cnt>(`ETH_BURST_LENGTH) + 2) | (|rx_burst_cnt) : ~RxBufferEmpty;
`else
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2465,7 → 2428,8
assign write_rx_data_to_memory_go = ~RxBufferEmpty;
`endif // !`ifdef ETH_RX_BURST_EN
assign WriteRxDataToMemory = write_rx_data_to_memory_go & !write_rx_data_to_memory_wait;
assign WriteRxDataToMemory = write_rx_data_to_memory_go &
!write_rx_data_to_memory_wait;
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
 
2814,11 → 2778,9
`ifdef WISHBONE_DEBUG
// Top byte, burst progress counters
assign dbg_dat0[31] = 0;
assign dbg_dat0[30] = 0;
assign dbg_dat0[29:28] = rx_burst_cnt;
assign dbg_dat0[30:28] = rx_burst_cnt;
assign dbg_dat0[27] = 0;
assign dbg_dat0[26] = 0;
assign dbg_dat0[25:24] = tx_burst_cnt;
assign dbg_dat0[26:24] = tx_burst_cnt;
// Third byte
assign dbg_dat0[23] = 0;
/eth_txcounters.v
159,7 → 159,7
NibCnt <= 16'h0;
else
if(IncrementNibCnt)
NibCnt <= NibCnt + 1'b1;
NibCnt <= NibCnt + 16'd1;
end
end
 
167,11 → 167,11
assign NibCntEq7 = &NibCnt[2:0];
assign NibCntEq15 = &NibCnt[3:0];
 
assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
assign NibbleMinFl = NibCnt >= (((MinFL-16'd4)<<1) -1); // FCS should not be included in NibbleMinFl
 
assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
assign ExcessiveDeferCnt = NibCnt[13:0] == 14'h17b7;
 
assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
assign ExcessiveDefer = NibCnt[13:0] == 14'h17b7 & ~ExDfrEn; // 6071 nibbles
 
assign IncrementByteCnt = StateData[1] & ~ByteCntMax
| StateBackOff & (&NibCnt[6:0])
191,7 → 191,7
ByteCnt[15:0] <= 16'h0;
else
if(IncrementByteCnt)
ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1;
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
 
212,7 → 212,7
DlyCrcCnt <= 3'h0;
else
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
DlyCrcCnt <= DlyCrcCnt + 1'b1;
DlyCrcCnt <= DlyCrcCnt + 3'd1;
end
end
 
/eth_fifo.v
3,10 → 3,11
//// eth_fifo.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// - Julius Baxter (julius@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
37,33 → 38,16
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/04/22 13:45:52 mohor
// Generic ram or Xilinx ram can be used in fifo (selectable by setting
// ETH_FIFO_XILINX in ethmac_defines.v).
//
// Revision 1.2 2002/03/25 13:33:04 mohor
// When clear and read/write are active at the same time, cnt and pointers are
// set to 1.
//
// Revision 1.1 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
//
 
`include "ethmac_defines.v"
`include "timescale.v"
 
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
module eth_fifo (data_in, data_out, clk, reset, write, read, clear,
almost_full, full, almost_empty, empty, cnt);
 
parameter DATA_WIDTH = 32;
parameter DEPTH = 8;
parameter CNT_WIDTH = 4;
parameter CNT_WIDTH = 3;
 
input clk;
input reset;
94,9 → 78,9
else
if(read ^ write)
if(read)
cnt <= cnt - 1'b1;
cnt <= cnt - 1;
else
cnt <= cnt + 1'b1;
cnt <= cnt + 1;
end
 
105,30 → 89,40
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ;
// This should make the synthesis tool infer RAMs
reg [CNT_WIDTH-2:0] waddr, raddr, raddr_reg;
reg clear_reg; // Register the clear pulse
// This should make the synthesis tool infer a RAM
reg [CNT_WIDTH-1:0] waddr, raddr, raddr_reg;
reg clear_reg; // Register the clear pulse
 
reg fallthrough_read;
reg [CNT_WIDTH-1:0] fallthrough_read_addr;
 
always @(posedge clk)
if (reset)
fallthrough_read <= 0;
else
fallthrough_read <= empty & write;
 
always @(posedge clk)
if (empty & write)
fallthrough_read_addr <= waddr;
always @(posedge clk)
if (reset)
waddr <= 0;
else if (write)
waddr <= waddr + 1;
 
wire raddr_reg_adv;
reg read_reg;
always @(posedge clk)
read_reg <= read;
 
// Advance the address after a read = first/next word fallthrough
assign raddr_reg_adv = (cnt > 2) & read_reg;
always @(posedge clk)
if (reset)
raddr <= 0;
else if (clear)
raddr <= waddr;
else if (read | clear_reg )
else if (read | clear_reg)
raddr <= raddr + 1;
always @ (posedge clk)
142,6 → 136,8
always @ (posedge clk)
if (read | clear_reg)
raddr_reg <= raddr;
else if (fallthrough_read) // To pulse RE for fall-through on Xilinx
raddr_reg <= fallthrough_read_addr;
assign data_out = fifo[raddr_reg];
 
154,16 → 150,15
else if ((cnt == 1) & read & !write)
final_read <= 1; // Indicate last read data has been output
assign empty = ~(|cnt);
assign almost_empty = cnt==1;
assign full = cnt == DEPTH;
assign almost_full = &cnt[CNT_WIDTH-2:0];
assign full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1);
assign almost_full = &cnt[CNT_WIDTH-1:0];
 
`else // !`ifdef ETH_FIFO_GENERIC
reg [CNT_WIDTH-2:0] read_pointer;
reg [CNT_WIDTH-2:0] write_pointer;
reg [CNT_WIDTH-1:0] read_pointer;
reg [CNT_WIDTH-1:0] write_pointer;
 
 
always @ (posedge clk or posedge reset)
172,8 → 167,8
read_pointer <= 0;
else
if(clear)
//read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read};
read_pointer <= { {(CNT_WIDTH-2){1'b0}}, 1'b1};
//read_pointer <= { {(CNT_WIDTH-1){1'b0}}, read};
read_pointer <= { {(CNT_WIDTH-1){1'b0}}, 1'b1};
else
if(read & ~empty)
read_pointer <= read_pointer + 1'b1;
185,7 → 180,7
write_pointer <= 0;
else
if(clear)
write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write};
write_pointer <= { {(CNT_WIDTH-1){1'b0}}, write};
else
if(write & ~full)
write_pointer <= write_pointer + 1'b1;
217,8 → 212,8
assign empty = ~(|cnt);
assign almost_empty = cnt == 1;
assign full = cnt == DEPTH;
assign almost_full = &cnt[CNT_WIDTH-2:0];
assign full = cnt == (DEPTH-1);
assign almost_full = &cnt[CNT_WIDTH-1:0];
`endif // !`ifdef ETH_FIFO_GENERIC
/eth_receivecontrol.v
301,12 → 301,13
DlyCrcCnt <= 3'h0;
else
if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
DlyCrcCnt <= DlyCrcCnt + 1'b1;
DlyCrcCnt <= DlyCrcCnt + 3'd1;
end
 
assign ResetByteCnt = RxEndFrm;
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 &
(~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
 
 
// Byte counter
319,7 → 320,7
ByteCnt[4:0] <= 5'h0;
else
if(IncrementByteCnt)
ByteCnt[4:0] <= ByteCnt[4:0] + 1'b1;
ByteCnt[4:0] <= ByteCnt[4:0] + 5'd1;
end
 
 
352,7 → 353,7
PauseTimer[15:0] <= LatchedTimerValue[15:0];
else
if(DecrementPauseTimer)
PauseTimer[15:0] <= PauseTimer[15:0] - 1'b1;
PauseTimer[15:0] <= PauseTimer[15:0] - 16'd1;
end
 
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
413,7 → 414,7
SlotTimer[5:0] <= 6'h0;
else
if(IncrementSlotTimer)
SlotTimer[5:0] <= SlotTimer[5:0] + 1'b1;
SlotTimer[5:0] <= SlotTimer[5:0] + 6'd1;
end
 
 
/eth_clockgen.v
89,7 → 89,7
 
 
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
 
 
// Counter counts half period
/eth_miim.v
406,7 → 406,7
if(NoPre & ( BitCounter == 7'h0 ))
BitCounter[6:0] <= 7'h21;
else
BitCounter[6:0] <= BitCounter[6:0] + 1'b1;
BitCounter[6:0] <= BitCounter[6:0] + 1;
end
else
BitCounter[6:0] <= 7'h0;
/ethmac.v
3,7 → 3,7
//// eth.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
45,741 → 45,1054
 
 
module ethmac // renamed jb
(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
 
// WISHBONE slave
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
// WISHBONE slave
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
 
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
 
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
m_wb_cti_o, m_wb_bte_o,
`endif
 
//TX
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
//TX
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
 
//RX
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
//RX
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i,
mcrs_pad_i,
// MIIM
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
// MIIM
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
 
int_o
int_o
 
// Bist
// Bist
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
 
);
);
 
 
parameter Tp = 1;
 
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output [31:0] wb_dat_o; // WISHBONE data output
output wb_err_o; // WISHBONE error output
 
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output [31:0] wb_dat_o; // WISHBONE data output
output wb_err_o; // WISHBONE error output
// WISHBONE slave
input [11:2] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output wb_ack_o; // WISHBONE acknowledge output
 
// WISHBONE slave
input [11:2] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output wb_ack_o; // WISHBONE acknowledge output
// WISHBONE master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
input m_wb_err_i;
 
// WISHBONE master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
input m_wb_err_i;
wire [29:0] m_wb_adr_tmp;
 
wire [29:0] m_wb_adr_tmp;
 
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
`endif
 
// Tx
input mtx_clk_pad_i; // Transmit clock (from PHY)
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
output mtxen_pad_o; // Transmit enable (to PHY)
output mtxerr_pad_o; // Transmit error (to PHY)
// Tx
input mtx_clk_pad_i; // Transmit clock (from PHY)
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
output mtxen_pad_o; // Transmit enable (to PHY)
output mtxerr_pad_o; // Transmit error (to PHY)
 
// Rx
input mrx_clk_pad_i; // Receive clock (from PHY)
input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
input mrxdv_pad_i; // Receive data valid (from PHY)
input mrxerr_pad_i; // Receive data error (from PHY)
// Rx
input mrx_clk_pad_i; // Receive clock (from PHY)
input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
input mrxdv_pad_i; // Receive data valid (from PHY)
input mrxerr_pad_i; // Receive data error (from PHY)
 
// Common Tx and Rx
input mcoll_pad_i; // Collision (from PHY)
input mcrs_pad_i; // Carrier sense (from PHY)
// Common Tx and Rx
input mcoll_pad_i; // Collision (from PHY)
input mcrs_pad_i; // Carrier sense (from PHY)
 
// MII Management interface
input md_pad_i; // MII data input (from I/O cell)
output mdc_pad_o; // MII Management data clock (to PHY)
output md_pad_o; // MII data output (to I/O cell)
output md_padoe_o; // MII data output enable (to I/O cell)
// MII Management interface
input md_pad_i; // MII data input (from I/O cell)
output mdc_pad_o; // MII Management data clock (to PHY)
output md_pad_o; // MII data output (to I/O cell)
output md_padoe_o; // MII data output enable (to I/O cell)
 
output int_o; // Interrupt output
output int_o; // Interrupt output
 
// Bist
// Bist
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
 
`ifdef WISHBONE_DEBUG
wire [31:0] wb_dbg_dat0;
wire [31:0] wb_dbg_dat0;
`endif
 
wire [7:0] r_ClkDiv;
wire r_MiiNoPre;
wire [15:0] r_CtrlData;
wire [4:0] r_FIAD;
wire [4:0] r_RGAD;
wire r_WCtrlData;
wire r_RStat;
wire r_ScanStat;
wire NValid_stat;
wire Busy_stat;
wire LinkFail;
wire [15:0] Prsd; // Read Status Data (data read from the PHY)
wire WCtrlDataStart;
wire RStatStart;
wire UpdateMIIRX_DATAReg;
wire [7:0] r_ClkDiv;
wire r_MiiNoPre;
wire [15:0] r_CtrlData;
wire [4:0] r_FIAD;
wire [4:0] r_RGAD;
wire r_WCtrlData;
wire r_RStat;
wire r_ScanStat;
wire NValid_stat;
wire Busy_stat;
wire LinkFail;
wire [15:0] Prsd; // Read Status Data (data read
// from the PHY)
wire WCtrlDataStart;
wire RStatStart;
wire UpdateMIIRX_DATAReg;
 
wire TxStartFrm;
wire TxEndFrm;
wire TxUsedData;
wire [7:0] TxData;
wire TxRetry;
wire TxAbort;
wire TxUnderRun;
wire TxDone;
wire TxStartFrm;
wire TxEndFrm;
wire TxUsedData;
wire [7:0] TxData;
wire TxRetry;
wire TxAbort;
wire TxUnderRun;
wire TxDone;
 
 
reg WillSendControlFrame_sync1;
reg WillSendControlFrame_sync2;
reg WillSendControlFrame_sync3;
reg RstTxPauseRq;
reg WillSendControlFrame_sync1;
reg WillSendControlFrame_sync2;
reg WillSendControlFrame_sync3;
reg RstTxPauseRq;
 
reg TxPauseRq_sync1;
reg TxPauseRq_sync2;
reg TxPauseRq_sync3;
reg TPauseRq;
reg TxPauseRq_sync1;
reg TxPauseRq_sync2;
reg TxPauseRq_sync3;
reg TPauseRq;
 
 
// Connecting Miim module
eth_miim miim1
(
.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
.MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
);
// Connecting Miim module
eth_miim miim1
(
.Clk(wb_clk_i),
.Reset(wb_rst_i),
.Divider(r_ClkDiv),
.NoPre(r_MiiNoPre),
.CtrlData(r_CtrlData),
.Rgad(r_RGAD),
.Fiad(r_FIAD),
.WCtrlData(r_WCtrlData),
.RStat(r_RStat),
.ScanStat(r_ScanStat),
.Mdi(md_pad_i),
.Mdo(md_pad_o),
.MdoEn(md_padoe_o),
.Mdc(mdc_pad_o),
.Busy(Busy_stat),
.Prsd(Prsd),
.LinkFail(LinkFail),
.Nvalid(NValid_stat),
.WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart),
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
);
 
 
 
 
wire [3:0] RegCs; // Connected to registers
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
wire r_RecSmall; // Receive small frames
wire r_LoopBck; // Loopback
wire r_TxEn; // Tx Enable
wire r_RxEn; // Rx Enable
wire [3:0] RegCs; // Connected to registers
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
wire r_RecSmall; // Receive small frames
wire r_LoopBck; // Loopback
wire r_TxEn; // Tx Enable
wire r_RxEn; // Rx Enable
 
wire MRxDV_Lb; // Muxed MII receive data valid
wire MRxErr_Lb; // Muxed MII Receive Error
wire [3:0] MRxD_Lb; // Muxed MII Receive Data
wire Transmitting; // Indication that TxEthMAC is transmitting
wire r_HugEn; // Huge packet enable
wire r_DlyCrcEn; // Delayed CRC enabled
wire [15:0] r_MaxFL; // Maximum frame length
wire MRxDV_Lb; // Muxed MII receive data valid
wire MRxErr_Lb; // Muxed MII Receive Error
wire [3:0] MRxD_Lb; // Muxed MII Receive Data
wire Transmitting; // Indication that TxEthMAC is transmitting
wire r_HugEn; // Huge packet enable
wire r_DlyCrcEn; // Delayed CRC enabled
wire [15:0] r_MaxFL; // Maximum frame length
 
wire [15:0] r_MinFL; // Minimum frame length
wire ShortFrame;
wire DribbleNibble; // Extra nibble received
wire ReceivedPacketTooBig; // Received packet is too big
wire [47:0] r_MAC; // MAC address
wire LoadRxStatus; // Rx status was loaded
wire [31:0] r_HASH0; // HASH table, lower 4 bytes
wire [31:0] r_HASH1; // HASH table, upper 4 bytes
wire [7:0] r_TxBDNum; // Receive buffer descriptor number
wire [6:0] r_IPGT; //
wire [6:0] r_IPGR1; //
wire [6:0] r_IPGR2; //
wire [5:0] r_CollValid; //
wire [15:0] r_TxPauseTV; // Transmit PAUSE value
wire r_TxPauseRq; // Transmit PAUSE request
wire [15:0] r_MinFL; // Minimum frame length
wire ShortFrame;
wire DribbleNibble; // Extra nibble received
wire ReceivedPacketTooBig; // Received packet is too big
wire [47:0] r_MAC; // MAC address
wire LoadRxStatus; // Rx status was loaded
wire [31:0] r_HASH0; // HASH table, lower 4 bytes
wire [31:0] r_HASH1; // HASH table, upper 4 bytes
wire [7:0] r_TxBDNum; // Receive buffer descriptor number
wire [6:0] r_IPGT; //
wire [6:0] r_IPGR1; //
wire [6:0] r_IPGR2; //
wire [5:0] r_CollValid; //
wire [15:0] r_TxPauseTV; // Transmit PAUSE value
wire r_TxPauseRq; // Transmit PAUSE request
 
wire [3:0] r_MaxRet; //
wire r_NoBckof; //
wire r_ExDfrEn; //
wire r_TxFlow; // Tx flow control enable
wire r_IFG; // Minimum interframe gap for incoming packets
wire [3:0] r_MaxRet; //
wire r_NoBckof; //
wire r_ExDfrEn; //
wire r_TxFlow; // Tx flow control enable
wire r_IFG; // Minimum interframe gap for incoming packets
 
wire TxB_IRQ; // Interrupt Tx Buffer
wire TxE_IRQ; // Interrupt Tx Error
wire RxB_IRQ; // Interrupt Rx Buffer
wire RxE_IRQ; // Interrupt Rx Error
wire Busy_IRQ; // Interrupt Busy (lack of buffers)
wire TxB_IRQ; // Interrupt Tx Buffer
wire TxE_IRQ; // Interrupt Tx Error
wire RxB_IRQ; // Interrupt Rx Buffer
wire RxE_IRQ; // Interrupt Rx Error
wire Busy_IRQ; // Interrupt Busy (lack of buffers)
 
//wire DWord;
wire ByteSelected;
wire BDAck;
wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
wire [3:0] BDCs; // Buffer descriptor CS
wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
// but data is not valid.
wire r_Pad;
wire r_CrcEn;
wire r_FullD;
wire r_Pro;
wire r_Bro;
wire r_NoPre;
wire r_RxFlow;
wire r_PassAll;
wire TxCtrlEndFrm;
wire StartTxDone;
wire SetPauseTimer;
wire TxUsedDataIn;
wire TxDoneIn;
wire TxAbortIn;
wire PerPacketPad;
wire PadOut;
wire PerPacketCrcEn;
wire CrcEnOut;
wire TxStartFrmOut;
wire TxEndFrmOut;
wire ReceivedPauseFrm;
wire ControlFrmAddressOK;
wire RxStatusWriteLatched_sync2;
wire LateCollision;
wire DeferIndication;
wire LateCollLatched;
wire DeferLatched;
wire RstDeferLatched;
wire CarrierSenseLost;
//wire DWord;
wire ByteSelected;
wire BDAck;
wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
wire [3:0] BDCs; // Buffer descriptor CS
wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
// but data is not valid.
wire r_Pad;
wire r_CrcEn;
wire r_FullD;
wire r_Pro;
wire r_Bro;
wire r_NoPre;
wire r_RxFlow;
wire r_PassAll;
wire TxCtrlEndFrm;
wire StartTxDone;
wire SetPauseTimer;
wire TxUsedDataIn;
wire TxDoneIn;
wire TxAbortIn;
wire PerPacketPad;
wire PadOut;
wire PerPacketCrcEn;
wire CrcEnOut;
wire TxStartFrmOut;
wire TxEndFrmOut;
wire ReceivedPauseFrm;
wire ControlFrmAddressOK;
wire RxStatusWriteLatched_sync2;
wire LateCollision;
wire DeferIndication;
wire LateCollLatched;
wire DeferLatched;
wire RstDeferLatched;
wire CarrierSenseLost;
 
wire temp_wb_ack_o;
wire [31:0] temp_wb_dat_o;
wire temp_wb_err_o;
wire temp_wb_ack_o;
wire [31:0] temp_wb_dat_o;
wire temp_wb_err_o;
 
`ifdef ETH_REGISTERED_OUTPUTS
reg temp_wb_ack_o_reg;
reg [31:0] temp_wb_dat_o_reg;
reg temp_wb_err_o_reg;
reg temp_wb_ack_o_reg;
reg [31:0] temp_wb_dat_o_reg;
reg temp_wb_err_o_reg;
`endif
 
//assign DWord = &wb_sel_i;
assign ByteSelected = |wb_sel_i;
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
//assign DWord = &wb_sel_i;
assign ByteSelected = |wb_sel_i;
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
 
`ifdef ETH_REGISTERED_OUTPUTS
assign wb_ack_o = temp_wb_ack_o_reg;
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
assign wb_err_o = temp_wb_err_o_reg;
assign wb_ack_o = temp_wb_ack_o_reg;
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
assign wb_err_o = temp_wb_err_o_reg;
`else
assign wb_ack_o = temp_wb_ack_o;
assign wb_dat_o[31:0] = temp_wb_dat_o;
assign wb_err_o = temp_wb_err_o;
assign wb_ack_o = temp_wb_ack_o;
assign wb_dat_o[31:0] = temp_wb_dat_o;
assign wb_err_o = temp_wb_err_o;
`endif
 
`ifdef ETH_AVALON_BUS
// As Avalon has no corresponding "error" signal, I (erroneously) will
// send an ack to Avalon, even when accessing undefined memory. This
// is a grey area in Avalon vs. Wishbone specs: My understanding
// is that Avalon expects all memory addressable by the addr bus feeding
// a slave to be, at the very minimum, readable.
assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
// As Avalon has no corresponding "error" signal, I (erroneously) will
// send an ack to Avalon, even when accessing undefined memory. This
// is a grey area in Avalon vs. Wishbone specs: My understanding
// is that Avalon expects all memory addressable by the addr bus feeding
// a slave to be, at the very minimum, readable.
assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
`else // WISHBONE
assign temp_wb_ack_o = (|RegCs) | BDAck;
assign temp_wb_ack_o = (|RegCs) | BDAck;
`endif
 
`ifdef ETH_REGISTERED_OUTPUTS
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
temp_wb_ack_o_reg <= 1'b0;
temp_wb_dat_o_reg <= 32'h0;
temp_wb_err_o_reg <= 1'b0;
end
else
begin
temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
temp_wb_dat_o_reg <= temp_wb_dat_o;
temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
end
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
temp_wb_ack_o_reg <= 1'b0;
temp_wb_dat_o_reg <= 32'h0;
temp_wb_err_o_reg <= 1'b0;
end
else
begin
temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
temp_wb_dat_o_reg <= temp_wb_dat_o;
temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
end
end
`endif
 
 
// Connecting Ethernet registers
eth_registers ethreg1
(
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
.r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
.r_IPGT(r_IPGT),
.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
.r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
.r_TxBDNum(r_TxBDNum), .int_o(int_o),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
.dbg_dat(wb_dbg_dat0),
.SetPauseTimer(SetPauseTimer)
);
// Connecting Ethernet registers
eth_registers ethreg1
(
.DataIn(wb_dat_i),
.Address(wb_adr_i[9:2]),
.Rw(wb_we_i),
.Cs(RegCs),
.Clk(wb_clk_i),
.Reset(wb_rst_i),
.DataOut(RegDataOut),
.r_RecSmall(r_RecSmall),
.r_Pad(r_Pad),
.r_HugEn(r_HugEn),
.r_CrcEn(r_CrcEn),
.r_DlyCrcEn(r_DlyCrcEn),
.r_FullD(r_FullD),
.r_ExDfrEn(r_ExDfrEn),
.r_NoBckof(r_NoBckof),
.r_LoopBck(r_LoopBck),
.r_IFG(r_IFG),
.r_Pro(r_Pro),
.r_Iam(),
.r_Bro(r_Bro),
.r_NoPre(r_NoPre),
.r_TxEn(r_TxEn),
.r_RxEn(r_RxEn),
.Busy_IRQ(Busy_IRQ),
.RxE_IRQ(RxE_IRQ),
.RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ),
.TxB_IRQ(TxB_IRQ),
.r_IPGT(r_IPGT),
.r_IPGR1(r_IPGR1),
.r_IPGR2(r_IPGR2),
.r_MinFL(r_MinFL),
.r_MaxFL(r_MaxFL),
.r_MaxRet(r_MaxRet),
.r_CollValid(r_CollValid),
.r_TxFlow(r_TxFlow),
.r_RxFlow(r_RxFlow),
.r_PassAll(r_PassAll),
.r_MiiNoPre(r_MiiNoPre),
.r_ClkDiv(r_ClkDiv),
.r_WCtrlData(r_WCtrlData),
.r_RStat(r_RStat),
.r_ScanStat(r_ScanStat),
.r_RGAD(r_RGAD),
.r_FIAD(r_FIAD),
.r_CtrlData(r_CtrlData),
.NValid_stat(NValid_stat),
.Busy_stat(Busy_stat),
.LinkFail(LinkFail),
.r_MAC(r_MAC),
.WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart),
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),
.Prsd(Prsd),
.r_TxBDNum(r_TxBDNum),
.int_o(int_o),
.r_HASH0(r_HASH0),
.r_HASH1(r_HASH1),
.r_TxPauseRq(r_TxPauseRq),
.r_TxPauseTV(r_TxPauseTV),
.RstTxPauseRq(RstTxPauseRq),
.TxCtrlEndFrm(TxCtrlEndFrm),
.StartTxDone(StartTxDone),
.TxClk(mtx_clk_pad_i),
.RxClk(mrx_clk_pad_i),
.dbg_dat(wb_dbg_dat0),
.SetPauseTimer(SetPauseTimer)
);
 
 
 
wire [7:0] RxData;
wire RxValid;
wire RxStartFrm;
wire RxEndFrm;
wire RxAbort;
wire [7:0] RxData;
wire RxValid;
wire RxStartFrm;
wire RxEndFrm;
wire RxAbort;
 
wire WillTransmit; // Will transmit (to RxEthMAC)
wire ResetCollision; // Reset Collision (for synchronizing collision)
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
wire WillSendControlFrame;
wire ReceiveEnd;
wire ReceivedPacketGood;
wire ReceivedLengthOK;
wire InvalidSymbol;
wire LatchedCrcError;
wire RxLateCollision;
wire [3:0] RetryCntLatched;
wire [3:0] RetryCnt;
wire StartTxAbort;
wire MaxCollisionOccured;
wire RetryLimit;
wire StatePreamble;
wire [1:0] StateData;
wire WillTransmit; // Will transmit (to RxEthMAC)
wire ResetCollision; // Reset Collision (for synchronizing
// collision)
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
wire WillSendControlFrame;
wire ReceiveEnd;
wire ReceivedPacketGood;
wire ReceivedLengthOK;
wire InvalidSymbol;
wire LatchedCrcError;
wire RxLateCollision;
wire [3:0] RetryCntLatched;
wire [3:0] RetryCnt;
wire StartTxAbort;
wire MaxCollisionOccured;
wire RetryLimit;
wire StatePreamble;
wire [1:0] StateData;
 
// Connecting MACControl
eth_maccontrol maccontrol1
(
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
.RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
.TxFlow(r_TxFlow),
.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
.MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
.PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
.CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
.RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
.TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
.TxDoneOut(TxDone), .TxAbortOut(TxAbort),
.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
.ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
.SetPauseTimer(SetPauseTimer),
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
);
// Connecting MACControl
eth_maccontrol maccontrol1
(
.MTxClk(mtx_clk_pad_i),
.TPauseRq(TPauseRq),
.TxPauseTV(r_TxPauseTV),
.TxDataIn(TxData),
.TxStartFrmIn(TxStartFrm),
.TxEndFrmIn(TxEndFrm),
.TxUsedDataIn(TxUsedDataIn),
.TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn),
.MRxClk(mrx_clk_pad_i),
.RxData(RxData),
.RxValid(RxValid),
.RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm),
.ReceiveEnd(ReceiveEnd),
.ReceivedPacketGood(ReceivedPacketGood),
.TxFlow(r_TxFlow),
.RxFlow(r_RxFlow),
.DlyCrcEn(r_DlyCrcEn),
.MAC(r_MAC),
.PadIn(r_Pad | PerPacketPad),
.PadOut(PadOut),
.CrcEnIn(r_CrcEn | PerPacketCrcEn),
.CrcEnOut(CrcEnOut),
.TxReset(wb_rst_i),
.RxReset(wb_rst_i),
.ReceivedLengthOK(ReceivedLengthOK),
.TxDataOut(TxDataOut),
.TxStartFrmOut(TxStartFrmOut),
.TxEndFrmOut(TxEndFrmOut),
.TxUsedDataOut(TxUsedData),
.TxDoneOut(TxDone),
.TxAbortOut(TxAbort),
.WillSendControlFrame(WillSendControlFrame),
.TxCtrlEndFrm(TxCtrlEndFrm),
.ReceivedPauseFrm(ReceivedPauseFrm),
.ControlFrmAddressOK(ControlFrmAddressOK),
.SetPauseTimer(SetPauseTimer),
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
.r_PassAll(r_PassAll)
);
 
 
 
wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
wire Collision; // Synchronized Collision
wire TxCarrierSense; // Synchronized CarrierSense (to Tx
// clock)
wire Collision; // Synchronized Collision
 
reg CarrierSense_Tx1;
reg CarrierSense_Tx2;
reg Collision_Tx1;
reg Collision_Tx2;
reg CarrierSense_Tx1;
reg CarrierSense_Tx2;
reg Collision_Tx1;
reg Collision_Tx2;
 
reg RxEnSync; // Synchronized Receive Enable
reg WillTransmit_q;
reg WillTransmit_q2;
reg RxEnSync; // Synchronized Receive Enable
reg WillTransmit_q;
reg WillTransmit_q2;
 
 
 
// Muxed MII receive data valid
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
// Muxed MII receive data valid
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
 
// Muxed MII Receive Error
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
// Muxed MII Receive Error
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
 
// Muxed MII Receive Data
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
// Muxed MII Receive Data
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
 
 
 
// Connecting TxEthMAC
eth_txethmac txethmac1
(
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
.MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
.MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
.MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
.ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
.DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
);
// Connecting TxEthMAC
eth_txethmac txethmac1
(
.MTxClk(mtx_clk_pad_i),
.Reset(wb_rst_i),
.CarrierSense(TxCarrierSense),
.Collision(Collision),
.TxData(TxDataOut),
.TxStartFrm(TxStartFrmOut),
.TxUnderRun(TxUnderRun),
.TxEndFrm(TxEndFrmOut),
.Pad(PadOut),
.MinFL(r_MinFL),
.CrcEn(CrcEnOut),
.FullD(r_FullD),
.HugEn(r_HugEn),
.DlyCrcEn(r_DlyCrcEn),
.IPGT(r_IPGT),
.IPGR1(r_IPGR1),
.IPGR2(r_IPGR2),
.CollValid(r_CollValid),
.MaxRet(r_MaxRet),
.NoBckof(r_NoBckof),
.ExDfrEn(r_ExDfrEn),
.MaxFL(r_MaxFL),
.MTxEn(mtxen_pad_o),
.MTxD(mtxd_pad_o),
.MTxErr(mtxerr_pad_o),
.TxUsedData(TxUsedDataIn),
.TxDone(TxDoneIn),
.TxRetry(TxRetry),
.TxAbort(TxAbortIn),
.WillTransmit(WillTransmit),
.ResetCollision(ResetCollision),
.RetryCnt(RetryCnt),
.StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort),
.MaxCollisionOccured(MaxCollisionOccured),
.LateCollision(LateCollision),
.DeferIndication(DeferIndication),
.StatePreamble(StatePreamble),
.StateData(StateData)
);
 
 
 
 
wire [15:0] RxByteCnt;
wire RxByteCntEq0;
wire RxByteCntGreat2;
wire RxByteCntMaxFrame;
wire RxCrcError;
wire RxStateIdle;
wire RxStatePreamble;
wire RxStateSFD;
wire [1:0] RxStateData;
wire AddressMiss;
wire [15:0] RxByteCnt;
wire RxByteCntEq0;
wire RxByteCntGreat2;
wire RxByteCntMaxFrame;
wire RxCrcError;
wire RxStateIdle;
wire RxStatePreamble;
wire RxStateSFD;
wire [1:0] RxStateData;
wire AddressMiss;
 
 
 
// Connecting RxEthMAC
eth_rxethmac rxethmac1
(
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
.StateSFD(RxStateSFD), .StateData(RxStateData),
.MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
.AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
);
// Connecting RxEthMAC
eth_rxethmac rxethmac1
(
.MRxClk(mrx_clk_pad_i),
.MRxDV(MRxDV_Lb),
.MRxD(MRxD_Lb),
.Transmitting(Transmitting),
.HugEn(r_HugEn),
.DlyCrcEn(r_DlyCrcEn),
.MaxFL(r_MaxFL),
.r_IFG(r_IFG),
.Reset(wb_rst_i),
.RxData(RxData),
.RxValid(RxValid),
.RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm),
.ByteCnt(RxByteCnt),
.ByteCntEq0(RxByteCntEq0),
.ByteCntGreat2(RxByteCntGreat2),
.ByteCntMaxFrame(RxByteCntMaxFrame),
.CrcError(RxCrcError),
.StateIdle(RxStateIdle),
.StatePreamble(RxStatePreamble),
.StateSFD(RxStateSFD),
.StateData(RxStateData),
.MAC(r_MAC),
.r_Pro(r_Pro),
.r_Bro(r_Bro),
.r_HASH0(r_HASH0),
.r_HASH1(r_HASH1),
.RxAbort(RxAbort),
.AddressMiss(AddressMiss),
.PassAll(r_PassAll),
.ControlFrmAddressOK(ControlFrmAddressOK)
);
 
 
// MII Carrier Sense Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
CarrierSense_Tx1 <= 1'b0;
CarrierSense_Tx2 <= 1'b0;
end
else
begin
CarrierSense_Tx1 <= mcrs_pad_i;
CarrierSense_Tx2 <= CarrierSense_Tx1;
end
end
// MII Carrier Sense Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
CarrierSense_Tx1 <= 1'b0;
CarrierSense_Tx2 <= 1'b0;
end
else
begin
CarrierSense_Tx1 <= mcrs_pad_i;
CarrierSense_Tx2 <= CarrierSense_Tx1;
end
end
 
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
 
 
// MII Collision Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
Collision_Tx1 <= 1'b0;
Collision_Tx2 <= 1'b0;
end
else
begin
Collision_Tx1 <= mcoll_pad_i;
if(ResetCollision)
Collision_Tx2 <= 1'b0;
else
if(Collision_Tx1)
Collision_Tx2 <= 1'b1;
end
end
// MII Collision Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
Collision_Tx1 <= 1'b0;
Collision_Tx2 <= 1'b0;
end
else
begin
Collision_Tx1 <= mcoll_pad_i;
if(ResetCollision)
Collision_Tx2 <= 1'b0;
else
if(Collision_Tx1)
Collision_Tx2 <= 1'b1;
end
end
 
 
// Synchronized Collision
assign Collision = ~r_FullD & Collision_Tx2;
// Synchronized Collision
assign Collision = ~r_FullD & Collision_Tx2;
 
 
 
// Delayed WillTransmit
always @ (posedge mrx_clk_pad_i)
begin
WillTransmit_q <= WillTransmit;
WillTransmit_q2 <= WillTransmit_q;
end
// Delayed WillTransmit
always @ (posedge mrx_clk_pad_i)
begin
WillTransmit_q <= WillTransmit;
WillTransmit_q2 <= WillTransmit_q;
end
 
 
assign Transmitting = ~r_FullD & WillTransmit_q2;
assign Transmitting = ~r_FullD & WillTransmit_q2;
 
 
 
// Synchronized Receive Enable
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxEnSync <= 1'b0;
else
if(~mrxdv_pad_i)
RxEnSync <= r_RxEn;
end
// Synchronized Receive Enable
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxEnSync <= 1'b0;
else
if(~mrxdv_pad_i)
RxEnSync <= r_RxEn;
end
 
 
 
// Synchronizing WillSendControlFrame to WB_CLK;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync1 <= 1'b0;
else
WillSendControlFrame_sync1 <= WillSendControlFrame;
end
// Synchronizing WillSendControlFrame to WB_CLK;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync1 <= 1'b0;
else
WillSendControlFrame_sync1 <= WillSendControlFrame;
end
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync2 <= 1'b0;
else
WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync2 <= 1'b0;
else
WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
end
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync3 <= 1'b0;
else
WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync3 <= 1'b0;
else
WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
end
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RstTxPauseRq <= 1'b0;
else
RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RstTxPauseRq <= 1'b0;
else
RstTxPauseRq <= WillSendControlFrame_sync2 &
~WillSendControlFrame_sync3;
end
 
 
 
 
// TX Pause request Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
TxPauseRq_sync1 <= 1'b0;
TxPauseRq_sync2 <= 1'b0;
TxPauseRq_sync3 <= 1'b0;
end
else
begin
TxPauseRq_sync1 <= (r_TxPauseRq & r_TxFlow);
TxPauseRq_sync2 <= TxPauseRq_sync1;
TxPauseRq_sync3 <= TxPauseRq_sync2;
end
end
// TX Pause request Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
TxPauseRq_sync1 <= 1'b0;
TxPauseRq_sync2 <= 1'b0;
TxPauseRq_sync3 <= 1'b0;
end
else
begin
TxPauseRq_sync1 <= (r_TxPauseRq & r_TxFlow);
TxPauseRq_sync2 <= TxPauseRq_sync1;
TxPauseRq_sync3 <= TxPauseRq_sync2;
end
end
 
 
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
TPauseRq <= 1'b0;
else
TPauseRq <= TxPauseRq_sync2 & (~TxPauseRq_sync3);
end
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
TPauseRq <= 1'b0;
else
TPauseRq <= TxPauseRq_sync2 & (~TxPauseRq_sync3);
end
 
 
wire LatchedMRxErr;
reg RxAbort_latch;
reg RxAbort_sync1;
reg RxAbort_wb;
reg RxAbortRst_sync1;
reg RxAbortRst;
wire LatchedMRxErr;
reg RxAbort_latch;
reg RxAbort_sync1;
reg RxAbort_wb;
reg RxAbortRst_sync1;
reg RxAbortRst;
 
// Synchronizing RxAbort to the WISHBONE clock
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxAbort_latch <= 1'b0;
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
RxAbort_latch <= 1'b1;
else if(RxAbortRst)
RxAbort_latch <= 1'b0;
end
// Synchronizing RxAbort to the WISHBONE clock
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxAbort_latch <= 1'b0;
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr &
~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
RxAbort_latch <= 1'b1;
else if(RxAbortRst)
RxAbort_latch <= 1'b0;
end
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbort_sync1 <= 1'b0;
RxAbort_wb <= 1'b0;
RxAbort_wb <= 1'b0;
end
else
begin
RxAbort_sync1 <= RxAbort_latch;
RxAbort_wb <= RxAbort_sync1;
end
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbort_sync1 <= 1'b0;
RxAbort_wb <= 1'b0;
RxAbort_wb <= 1'b0;
end
else
begin
RxAbort_sync1 <= RxAbort_latch;
RxAbort_wb <= RxAbort_sync1;
end
end
 
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbortRst_sync1 <= 1'b0;
RxAbortRst <= 1'b0;
end
else
begin
RxAbortRst_sync1 <= RxAbort_wb;
RxAbortRst <= RxAbortRst_sync1;
end
end
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbortRst_sync1 <= 1'b0;
RxAbortRst <= 1'b0;
end
else
begin
RxAbortRst_sync1 <= RxAbort_wb;
RxAbortRst <= RxAbortRst_sync1;
end
end
 
 
 
// Connecting Wishbone module
eth_wishbone wishbone
(
.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
.WB_DAT_O(BD_WB_DAT_O),
// Connecting Wishbone module
eth_wishbone wishbone
(
.WB_CLK_I(wb_clk_i),
.WB_DAT_I(wb_dat_i),
.WB_DAT_O(BD_WB_DAT_O),
 
// WISHBONE slave
.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
.BDCs(BDCs), .WB_ACK_O(BDAck),
// WISHBONE slave
.WB_ADR_I(wb_adr_i[9:2]),
.WB_WE_I(wb_we_i),
.BDCs(BDCs),
.WB_ACK_O(BDAck),
 
.Reset(wb_rst_i),
.Reset(wb_rst_i),
 
// WISHBONE master
.m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
// WISHBONE master
.m_wb_adr_o(m_wb_adr_tmp),
.m_wb_sel_o(m_wb_sel_o),
.m_wb_we_o(m_wb_we_o),
.m_wb_dat_i(m_wb_dat_i),
.m_wb_dat_o(m_wb_dat_o),
.m_wb_cyc_o(m_wb_cyc_o),
.m_wb_stb_o(m_wb_stb_o),
.m_wb_ack_i(m_wb_ack_i),
.m_wb_err_i(m_wb_err_i),
`ifdef ETH_WISHBONE_B3
.m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
.m_wb_cti_o(m_wb_cti_o),
.m_wb_bte_o(m_wb_bte_o),
`endif
 
//TX
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
.TxUsedData(TxUsedData), .TxData(TxData),
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
.TxDone(TxDone),
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
//TX
.MTxClk(mtx_clk_pad_i),
.TxStartFrm(TxStartFrm),
.TxEndFrm(TxEndFrm),
.TxUsedData(TxUsedData),
.TxData(TxData),
.TxRetry(TxRetry),
.TxAbort(TxAbort),
.TxUnderRun(TxUnderRun),
.TxDone(TxDone),
.PerPacketCrcEn(PerPacketCrcEn),
.PerPacketPad(PerPacketPad),
 
// Register
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
.r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
// Register
.r_TxEn(r_TxEn),
.r_RxEn(r_RxEn),
.r_TxBDNum(r_TxBDNum),
.r_RxFlow(r_RxFlow),
.r_PassAll(r_PassAll),
 
//RX
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
//RX
.MRxClk(mrx_clk_pad_i),
.RxData(RxData),
.RxValid(RxValid),
.RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm),
.Busy_IRQ(Busy_IRQ),
.RxE_IRQ(RxE_IRQ),
.RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ),
.TxB_IRQ(TxB_IRQ),
 
.RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
.RxAbort(RxAbort_wb),
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
 
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
.RstDeferLatched(RstDeferLatched),
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
.ReceivedPauseFrm(ReceivedPauseFrm)
.InvalidSymbol(InvalidSymbol),
.LatchedCrcError(LatchedCrcError),
.RxLength(RxByteCnt),
.RxLateCollision(RxLateCollision),
.ShortFrame(ShortFrame),
.DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig),
.LoadRxStatus(LoadRxStatus),
.RetryCntLatched(RetryCntLatched),
.RetryLimit(RetryLimit),
.LateCollLatched(LateCollLatched),
.DeferLatched(DeferLatched),
.RstDeferLatched(RstDeferLatched),
.CarrierSenseLost(CarrierSenseLost),
.ReceivedPacketGood(ReceivedPacketGood),
.AddressMiss(AddressMiss),
.ReceivedPauseFrm(ReceivedPauseFrm)
`ifdef ETH_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
`ifdef WISHBONE_DEBUG
,
.dbg_dat0(wb_dbg_dat0)
`ifdef WISHBONE_DEBUG
,
.dbg_dat0(wb_dbg_dat0)
`endif
 
);
);
 
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
 
// Connecting MacStatus module
eth_macstatus macstatus1
(
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
.InvalidSymbol(InvalidSymbol),
.MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
.CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
.r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
.LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
.LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
.RstDeferLatched(RstDeferLatched),
.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
.LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
);
// Connecting MacStatus module
eth_macstatus macstatus1
(
.MRxClk(mrx_clk_pad_i),
.Reset(wb_rst_i),
.ReceiveEnd(ReceiveEnd),
.ReceivedPacketGood(ReceivedPacketGood),
.ReceivedLengthOK(ReceivedLengthOK),
.RxCrcError(RxCrcError),
.MRxErr(MRxErr_Lb),
.MRxDV(MRxDV_Lb),
.RxStateSFD(RxStateSFD),
.RxStateData(RxStateData),
.RxStatePreamble(RxStatePreamble),
.RxStateIdle(RxStateIdle),
.Transmitting(Transmitting),
.RxByteCnt(RxByteCnt),
.RxByteCntEq0(RxByteCntEq0),
.RxByteCntGreat2(RxByteCntGreat2),
.RxByteCntMaxFrame(RxByteCntMaxFrame),
.InvalidSymbol(InvalidSymbol),
.MRxD(MRxD_Lb),
.LatchedCrcError(LatchedCrcError),
.Collision(mcoll_pad_i),
.CollValid(r_CollValid),
.RxLateCollision(RxLateCollision),
.r_RecSmall(r_RecSmall),
.r_MinFL(r_MinFL),
.r_MaxFL(r_MaxFL),
.ShortFrame(ShortFrame),
.DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig),
.r_HugEn(r_HugEn),
.LoadRxStatus(LoadRxStatus),
.RetryCnt(RetryCnt),
.StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort),
.RetryCntLatched(RetryCntLatched),
.MTxClk(mtx_clk_pad_i),
.MaxCollisionOccured(MaxCollisionOccured),
.RetryLimit(RetryLimit),
.LateCollision(LateCollision),
.LateCollLatched(LateCollLatched),
.DeferIndication(DeferIndication),
.DeferLatched(DeferLatched),
.RstDeferLatched(RstDeferLatched),
.TxStartFrm(TxStartFrmOut),
.StatePreamble(StatePreamble),
.StateData(StateData),
.CarrierSense(CarrierSense_Tx2),
.CarrierSenseLost(CarrierSenseLost),
.TxUsedData(TxUsedDataIn),
.LatchedMRxErr(LatchedMRxErr),
.Loopback(r_LoopBck),
.r_FullD(r_FullD)
);
 
 
endmodule
/eth_transmitcontrol.v
252,7 → 252,7
DlyCrcCnt <= 4'h0;
else
if(IncrementDlyCrcCnt)
DlyCrcCnt <= DlyCrcCnt + 1'b1;
DlyCrcCnt <= DlyCrcCnt + 4'd1;
end
 
271,10 → 271,10
ByteCnt <= 6'h0;
else
if(IncrementByteCntBy2 & EnableCnt)
ByteCnt <= (ByteCnt[5:0] ) + 2'h2;
ByteCnt <= (ByteCnt[5:0] ) + 6'd2;
else
if(IncrementByteCnt & EnableCnt)
ByteCnt <= (ByteCnt[5:0] ) + 1'b1;
ByteCnt <= (ByteCnt[5:0] ) + 6'd1;
end
 
 
/eth_rxstatem.v
135,9 → 135,8
 
assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
 
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & MRxDEqD
| StateData0 & ByteCntMaxFrame
);
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &
MRxDEqD | StateData0 & ByteCntMaxFrame);
 
// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
/eth_registers.v
859,33 → 859,33
if(Read) // read
begin
case(Address)
`ETH_MODER_ADR : DataOut<=MODEROut;
`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
`ETH_IPGT_ADR : DataOut<=IPGTOut;
`ETH_IPGR1_ADR : DataOut<=IPGR1Out;
`ETH_IPGR2_ADR : DataOut<=IPGR2Out;
`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
`ETH_HASH0_ADR : DataOut<=HASH0Out;
`ETH_HASH1_ADR : DataOut<=HASH1Out;
`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
`ETH_DBG_ADR : DataOut<=dbg_dat; // debug data out -- JB
default: DataOut<=32'h0;
`ETH_MODER_ADR : DataOut=MODEROut;
`ETH_INT_SOURCE_ADR : DataOut=INT_SOURCEOut;
`ETH_INT_MASK_ADR : DataOut=INT_MASKOut;
`ETH_IPGT_ADR : DataOut=IPGTOut;
`ETH_IPGR1_ADR : DataOut=IPGR1Out;
`ETH_IPGR2_ADR : DataOut=IPGR2Out;
`ETH_PACKETLEN_ADR : DataOut=PACKETLENOut;
`ETH_COLLCONF_ADR : DataOut=COLLCONFOut;
`ETH_CTRLMODER_ADR : DataOut=CTRLMODEROut;
`ETH_MIIMODER_ADR : DataOut=MIIMODEROut;
`ETH_MIICOMMAND_ADR : DataOut=MIICOMMANDOut;
`ETH_MIIADDRESS_ADR : DataOut=MIIADDRESSOut;
`ETH_MIITX_DATA_ADR : DataOut=MIITX_DATAOut;
`ETH_MIIRX_DATA_ADR : DataOut=MIIRX_DATAOut;
`ETH_MIISTATUS_ADR : DataOut=MIISTATUSOut;
`ETH_MAC_ADDR0_ADR : DataOut=MAC_ADDR0Out;
`ETH_MAC_ADDR1_ADR : DataOut=MAC_ADDR1Out;
`ETH_TX_BD_NUM_ADR : DataOut=TX_BD_NUMOut;
`ETH_HASH0_ADR : DataOut=HASH0Out;
`ETH_HASH1_ADR : DataOut=HASH1Out;
`ETH_TX_CTRL_ADR : DataOut=TXCTRLOut;
`ETH_DBG_ADR : DataOut=dbg_dat; // debug data out -- JB
default: DataOut=32'h0;
endcase
end
else
DataOut<=32'h0;
DataOut=32'h0;
end
 
 
893,7 → 893,7
assign r_Pad = MODEROut[15];
assign r_HugEn = MODEROut[14];
assign r_CrcEn = MODEROut[13];
assign r_DlyCrcEn = MODEROut[12];
assign r_DlyCrcEn = /*MODEROut[12]*/1'b0; // Synthesis bugfix JB
// assign r_Rst = MODEROut[11]; This signal is not used any more
assign r_FullD = MODEROut[10];
assign r_ExDfrEn = MODEROut[9];

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