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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/rtl/verilog/include
- from Rev 361 to Rev 363
- ↔ Reverse comparison
Rev 361 → Rev 363
/dbg_cpu_defines.v
39,32 → 39,6
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: dbg_cpu_defines.v,v $ |
// Revision 1.6 2004/04/05 13:52:54 igorm |
// CPU_WR_CTRL and CPU_RD_CTRL defines changed. |
// |
// Revision 1.5 2004/03/31 14:34:09 igorm |
// data_cnt_lim length changed to reduce number of warnings. |
// |
// Revision 1.4 2004/03/28 20:27:02 igorm |
// New release of the debug interface (3rd. release). |
// |
// Revision 1.3 2004/03/22 16:35:46 igorm |
// Temp version before changing dbg interface. |
// |
// Revision 1.2 2004/01/17 17:01:14 mohor |
// Almost finished. |
// |
// Revision 1.1 2004/01/16 14:53:33 mohor |
// *** empty log message *** |
// |
// |
// |
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// Defining length of the command |
`define DBG_CPU_CMD_LEN 3'd4 |
71,17 → 45,16
`define DBG_CPU_CMD_CNT_WIDTH 3 |
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// Defining length of the access_type field |
`define DBG_CPU_ACC_TYPE_LEN 3'd4 |
`define DBG_CPU_ACC_TYPE_LEN 4 |
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// Defining length of the address |
`define DBG_CPU_ADR_LEN 6'd32 |
`define DBG_CPU_ADR_LEN 32 |
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// Defining length of the length register |
`define DBG_CPU_LEN_LEN 5'd16 |
`define DBG_CPU_LEN_LEN 16 |
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// Defining total length of the DR needed |
//define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN) |
`define DBG_CPU_DR_LEN 52 |
`define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN) |
// Defining length of the CRC |
`define DBG_CPU_CRC_LEN 6'd32 |
`define DBG_CPU_CRC_CNT_WIDTH 6 |
/or1200_defines.v
867,7 → 867,7
// |
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// Define it if you want DU implemented |
`define OR1200_DU_IMPLEMENTED |
//`define OR1200_DU_IMPLEMENTED |
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// |
// Define if you want HW Breakpoints |
922,10 → 922,10
`define OR1200_DU_DRR 11'd21 |
`ifdef OR1200_DU_TB_IMPLEMENTED |
`define OR1200_DU_TBADR 11'h0ff |
`define OR1200_DU_TBIA 11'h1xx |
`define OR1200_DU_TBIM 11'h2xx |
`define OR1200_DU_TBAR 11'h3xx |
`define OR1200_DU_TBTS 11'h4xx |
`define OR1200_DU_TBIA 11'h1?? |
`define OR1200_DU_TBIM 11'h2?? |
`define OR1200_DU_TBAR 11'h3?? |
`define OR1200_DU_TBTS 11'h4?? |
`endif |
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// Position of offset bits inside SPR address |
1631,7 → 1631,7
`else |
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way |
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets |
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block |
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block |
`ifdef OR1200_DC_WRITETHROUGH |
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy |
`else |
1679,7 → 1679,7
`else |
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way |
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets |
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block |
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1 // 16 byte cache block |
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant |
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl. |
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl. |
1707,7 → 1707,7
`define OR1200_DCFGR_NDP 4'h0 // Zero DVR/DCR pairs |
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. |
`endif |
`define OR1200_DCFGR_RES1 28'h0000000 |
`define OR1200_DCFGR_RES1 27'd0 |
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/////////////////////////////////////////////////////////////////////////////// |
// Boot Address Selection // |
/orpsoc-defines.v
38,7 → 38,7
`define BOARD_CLOCK_PERIOD_NS 20 |
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// Included modules: define to include |
`define JTAG_DEBUG |
//`define JTAG_DEBUG |
`define UART0 |
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// end of included module defines - keep this comment line here |
/dbg_wb_defines.v
69,16 → 69,18
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// Defining length of the command |
`define DBG_WB_CMD_LEN 3'd4 |
`define DBG_WB_CMD_LEN_INT 4 |
`define DBG_WB_CMD_CNT_WIDTH 3 |
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// Defining length of the access_type field |
`define DBG_WB_ACC_TYPE_LEN 3'd4 |
`define DBG_WB_ACC_TYPE_LEN 4 |
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// Defining length of the address |
`define DBG_WB_ADR_LEN 6'd32 |
`define DBG_WB_ADR_LEN 32 |
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// Defining length of the length register |
`define DBG_WB_LEN_LEN 5'd16 |
`define DBG_WB_LEN_LEN 16 |
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// Defining total length of the DR needed |
`define DBG_WB_DR_LEN (`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN) |