URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/rtl/verilog
- from Rev 570 to Rev 618
- ↔ Reverse comparison
Rev 570 → Rev 618
/ethmac/eth_shiftreg.v
79,8 → 79,6
LatchByte, ShiftedBit, Prsd, LinkFail); |
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parameter Tp=1; |
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input Clk; // Input clock (Host clock) |
input Reset; // Reset signal |
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. |
/ethmac/eth_txethmac.v
103,9 → 103,7
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); |
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parameter Tp = 1; |
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input MTxClk; // Transmit clock (from PHY) |
input Reset; // Reset |
input TxStartFrm; // Transmit packet start frame |
/ethmac/eth_txcounters.v
92,8 → 92,6
ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt |
); |
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parameter Tp = 1; |
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input MTxClk; // Tx clock |
input Reset; // Reset |
input StatePreamble; // Preamble state |
/ethmac/eth_random.v
82,8 → 82,6
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt, |
RandomEq0, RandomEqByteCnt); |
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parameter Tp = 1; |
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input MTxClk; |
input Reset; |
input StateJam; |
/ethmac/eth_rxaddrcheck.v
75,7 → 75,6
ControlFrmAddressOK |
); |
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parameter Tp = 1; |
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input MRxClk; |
input Reset; |
/ethmac/eth_receivecontrol.v
84,9 → 84,7
RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer |
); |
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parameter Tp = 1; |
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input MTxClk; |
input MRxClk; |
input TxReset; |
/ethmac/eth_clockgen.v
70,8 → 70,6
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module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc); |
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parameter Tp=1; |
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input Clk; // Input clock (Host clock) |
input Reset; // Reset signal |
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0]) |
/ethmac/eth_miim.v
135,9 → 135,7
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register |
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data |
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parameter Tp = 1; |
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reg Nvalid; |
reg EndBusy_d; // Pre-end Busy signal |
reg EndBusy; // End Busy signal (stops the operation in progress) |
/ethmac/eth_outputcontrol.v
70,8 → 70,6
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module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn); |
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parameter Tp = 1; |
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input Clk; // Host Clock |
input Reset; // General Reset |
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress) |
/ethmac/eth_maccontrol.v
94,9 → 94,7
); |
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parameter Tp = 1; |
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input MTxClk; // Transmit clock (from PHY) |
input MRxClk; // Receive clock (from PHY) |
input TxReset; // Transmit reset |
/ethmac/eth_transmitcontrol.v
88,9 → 88,7
ControlData, WillSendControlFrame, BlockTxDone |
); |
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parameter Tp = 1; |
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input MTxClk; |
input TxReset; |
input TxUsedDataIn; |
/ethmac/eth_macstatus.v
126,9 → 126,7
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parameter Tp = 1; |
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input MRxClk; |
input Reset; |
input RxCrcError; |
/ethmac/eth_rxstatem.v
90,8 → 90,6
StateDrop |
); |
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parameter Tp = 1; |
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input MRxClk; |
input Reset; |
input MRxDV; |
/ethmac/eth_registers.v
182,8 → 182,6
StartTxDone, TxClk, RxClk, SetPauseTimer |
); |
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parameter Tp = 1; |
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input [31:0] DataIn; |
input [7:0] Address; |
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/ethmac/eth_crc.v
79,8 → 79,6
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError); |
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parameter Tp = 1; |
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input Clk; |
input Reset; |
input [3:0] Data; |
/ethmac/eth_txstatem.v
96,8 → 96,6
StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG |
); |
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parameter Tp = 1; |
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input MTxClk; |
input Reset; |
input ExcessiveDefer; |