URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/rtl
- from Rev 805 to Rev 807
- ↔ Reverse comparison
Rev 805 → Rev 807
/verilog/or1200/or1200_sprs.v
57,7 → 57,7
|
// Internal CPU interface |
flagforw, flag_we, flag, cyforw, cy_we, carry, |
ovforw, ov_we, |
ovforw, ov_we, dsx, |
addrbase, addrofs, dat_i, branch_op, ex_spr_read, |
ex_spr_write, |
epcr, eear, esr, except_started, |
99,6 → 99,7
output carry; // SR[CY] |
input ovforw; // From ALU |
input ov_we; // From ALU |
input dsx; // From except |
input [width-1:0] addrbase; // SPR base address |
input [15:0] addrofs; // SPR offset |
input [width-1:0] dat_i; // SPR write data |
289,7 → 290,7
// What to write into SR |
// |
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OVE] |
= (except_started) ? {sr[`OR1200_SR_FO:`OR1200_SR_DSX],1'b0} : |
= (except_started) ? {sr[`OR1200_SR_FO:`OR1200_SR_EPH],dsx,1'b0} : |
(branch_op == `OR1200_BRANCHOP_RFE) ? |
esr[`OR1200_SR_FO:`OR1200_SR_OVE] : (spr_we && sr_sel) ? |
{1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OVE]} : |
/verilog/or1200/or1200_cpu.v
289,6 → 289,7
wire sr_we; |
wire [`OR1200_SR_WIDTH-1:0] to_sr; |
wire [`OR1200_SR_WIDTH-1:0] sr; |
wire dsx; |
wire except_flushpipe; |
wire except_start; |
wire except_started; |
723,7 → 724,8
.sr_we(sr_we), |
.to_sr(to_sr), |
.sr(sr), |
.branch_op(branch_op) |
.branch_op(branch_op), |
.dsx(dsx) |
); |
|
// |
877,7 → 879,8
.sr_we(sr_we), |
.to_sr(to_sr), |
.sr(sr), |
.abort_ex(abort_ex) |
.abort_ex(abort_ex), |
.dsx(dsx) |
); |
|
// |
/verilog/or1200/or1200_except.v
78,7 → 78,8
except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc, |
spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear, |
du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr, |
abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee |
abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee, |
dsx |
|
); |
|
147,7 → 148,8
input icpu_err_i; |
input dcpu_ack_i; |
input dcpu_err_i; |
|
output dsx; |
|
// |
// Internal regs and wires |
// |
177,6 → 179,7
wire tick_pending; |
wire fp_pending; |
wire range_pending; |
reg dsx; |
|
reg trace_trap ; |
reg ex_freeze_prev; |
462,6 → 465,7
eear <= 32'b0; |
esr <= {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1}; |
extend_flush_last <= 1'b0; |
dsx <= 1'b0; |
end |
else begin |
`ifdef OR1200_CASE_DEFAULT |
482,6 → 486,7
ex_pc : ex_pc; |
epcr <= ex_dslot ? |
wb_pc : ex_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_IPF |
495,6 → 500,7
wb_pc : delayed1_ex_dslot ? |
id_pc : delayed2_ex_dslot ? |
id_pc : id_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_BUSERR |
504,6 → 510,7
wb_pc : ex_pc; |
epcr <= ex_dslot ? |
wb_pc : ex_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_ILLEGAL |
512,6 → 519,7
eear <= ex_pc; |
epcr <= ex_dslot ? |
wb_pc : ex_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_ALIGN |
520,6 → 528,7
eear <= lsu_addr; |
epcr <= ex_dslot ? |
wb_pc : ex_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_DTLBMISS |
529,6 → 538,7
epcr <= ex_dslot ? |
wb_pc : delayed1_ex_dslot ? |
dl_pc : ex_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_TRAP |
537,6 → 547,7
epcr <= ex_dslot ? |
wb_pc : delayed1_ex_dslot ? |
id_pc : ex_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_SYSCALL |
546,6 → 557,7
wb_pc : delayed1_ex_dslot ? |
id_pc : delayed2_ex_dslot ? |
id_pc : id_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_DPF |
555,6 → 567,7
epcr <= ex_dslot ? |
wb_pc : delayed1_ex_dslot ? |
dl_pc : ex_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_BUSERR |
564,6 → 577,7
epcr <= ex_dslot ? |
wb_pc : delayed1_ex_dslot ? |
dl_pc : ex_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_RANGE |
573,6 → 587,7
wb_pc : delayed1_ex_dslot ? |
dl_pc : delayed2_ex_dslot ? |
id_pc : ex_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_FLOAT |
579,6 → 594,7
14'b00_0000_0000_01??: begin |
except_type <= `OR1200_EXCEPT_FLOAT; |
epcr <= id_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_INT |
585,6 → 601,7
14'b00_0000_0000_001?: begin |
except_type <= `OR1200_EXCEPT_INT; |
epcr <= id_pc; |
dsx <= ex_dslot; |
end |
`endif |
`ifdef OR1200_EXCEPT_TICK |
591,6 → 608,7
14'b00_0000_0000_0001: begin |
except_type <= `OR1200_EXCEPT_TICK; |
epcr <= id_pc; |
dsx <= ex_dslot; |
end |
`endif |
default: |