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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/sim
    from Rev 411 to Rev 425
    ↔ Reverse comparison
  •

Rev 411 → Rev 425

/bin/Makefile
314,7 → 314,7
 
 
.PHONY: rtl-test
rtl-test: clean-sim-test-sw sw clean-test-defines $(TEST_DEFINES_VLG) \
rtl-test: clean-sim-test-sw sw-vmem clean-test-defines $(TEST_DEFINES_VLG) \
$(SIMULATOR)
 
# Run an RTL test followed by checking of generated results
361,14 → 361,14
# Path for the current test
TEST_SW_DIR=$(SW_DIR)/tests/$(shell echo $(TEST) | cut -d "-" -f 1)/sim
 
# Name of the image the RAM model will attempt to load via Verilog $readmemh
# system function.
# This SHOULD be a VMEM file. sram.vmem is the name of the image the ram models
# attempt to load.
SIM_SW_IMAGE ?=sram.vmem
 
.PHONY : sw
sw: $(SIM_SW_IMAGE)
.PHONY : sw-vmem sw-elf
sw-vmem: $(SIM_SW_IMAGE)
 
sram.vmem: $(TEST_SW_DIR)/$(TEST).vmem
$(SIM_SW_IMAGE): $(TEST_SW_DIR)/$(TEST).vmem
$(Q)if [ -L $@ ]; then unlink $@; fi
$(Q)ln -s $< $@
 
377,6 → 377,15
$(Q) echo; echo "\t### Compiling software ###"; echo;
$(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).vmem
 
# Compile ELF and copy it here
sw-elf: $(TEST_SW_DIR)/$(TEST).elf
$(Q)cp -v $< .
 
$(TEST_SW_DIR)/$(TEST).elf:
$(Q) echo; echo "\t### Compiling software ###"; echo;
$(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).elf
 
 
# Rule to force generation of the processed orpsoc-defines.h file
processed-verilog-headers-in-c-for-vlt:
$(Q)$(MAKE) -C $(SW_DIR)/lib processed-verilog-headers
622,7 → 631,7
# Verilator model test rules
################################################################################
 
vlt-test: build-vlt clean-sim-test-sw sw
vlt-test: build-vlt clean-sim-test-sw sw-vmem
$(SIM_VLT_DIR)/$(VLT_EXE) $(TEST)
 
vlt-tests:
675,4 → 684,29
lint-vlt: $(SIM_VLT_DIR) rtl $(DUMMY_FILES_FOR_VLT) $(SIM_VLT_DIR)/$(VLT_SCRIPT)
$(Q)echo; echo "\tLinting design with Verilator"; echo
$(Q)cd $(SIM_VLT_DIR) && \
verilator -language 1364-2001 --top-module orpsoc_top --lint-only -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
verilator -language 1364-2001 --top-module orpsoc_top --lint-only -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
 
################################################################################
# Architectural simulator test rules
################################################################################
 
ARCH_SIM_EXE ?=or32-elf-sim
ARCH_SIM_CFG ?= ../bin/or1ksim-orpsocv2.cfg
ARCH_SIM_OPTS ?= -q
 
.PHONY: rtl-test
sim-test: clean-sim-test-sw sw-elf
$(Q)$(ARCH_SIM_EXE) $(ARCH_SIM_OPTS) -f $(ARCH_SIM_CFG) $(TEST).elf > \
$(RTL_SIM_RESULTS_DIR)/$(TEST)$(TEST_OUT_FILE_SUFFIX)
 
# Run tests in simulation, check output
sim-test-with-check: sim-test check-test-log
 
# Main architectural simulations test loop
sim-tests:
$(Q)for test in $(TESTS); do \
export TEST=$$test; \
$(MAKE) sim-test-with-check; \
if [ $$? -ne 0 ]; then break; fi; \
echo; echo "\t### $$test test OK ###"; echo; \
done
/bin/or1ksim-orpsocv2.cfg
1,126 → 1,7
/* sim.cfg -- Simulator configuration script file
Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
It contains the default configuration and help about configuring
the simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
/* INTRODUCTION
 
The ork1sim has various parameters, that are set in configuration files
like this one. The user can switch between configurations at startup by
specifying the required configuration file with the -f <filename.cfg> option.
If no configuration file is specified or1ksim searches for the default
configuration file sim.cfg. First it searches for './sim.cfg'. If this
file is not found, it searches for '~/or1k/sim.cfg'. If this file is
not found too, it reverts to the built-in default configuration.
NOTE: Users should not rely on the built-in configuration, since the
default configuration may differ between version.
Rather create a configuration file that sets all critical values.
 
This file may contain (standard C) comments only - no // support.
Configure files may be be included, using:
include "file_name_to_include"
 
Like normal configuration files, the included file is divided into
sections. Each section is described in detail also.
 
Some section have subsections. One example of such a subsection is:
 
device <index>
instance specific parameters...
enddevice
 
which creates a device instance.
*/
 
 
/* MEMORY SECTION
 
This section specifies how the memory is generated and the blocks
it consists of.
 
type = random/unknown/pattern
Specifies the initial memory values.
'random' generates random memory using seed 'random_seed'.
'pattern' fills memory with 'pattern'.
'unknown' does not specify how memory should be generated,
leaving the memory in a undefined state. This is the fastest
option.
 
random_seed = <value>
random seed for randomizer, used if type = 'random'.
 
pattern = <value>
pattern to fill memory, used if type = 'pattern'.
 
nmemories = <value>
number of memory instances connected
 
baseaddr = <hex_value>
memory start address
 
size = <hex_value>
memory size
 
name = "<string>"
memory block name
 
ce = <value>
chip enable index of the memory instance
 
mc = <value>
memory controller this memory is connected to
 
delayr = <value>
cycles, required for read access, -1 if instance does not support reading
 
delayw = <value>
cycles, required for write access, -1 if instance does not support writing
 
log = "<filename>"
filename, where to log memory accesses to, no log, if log command is not specified
*/
 
 
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
 
name = "FLASH"
ce = 0
mc = 0
baseaddr = 0x04000000
size = 0x00200000
delayr = 1
delayw = -1
end
 
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
 
name = "RAM"
ce = 1
mc = 0
130,22 → 11,6
delayw = 1
end
 
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
 
name = "ICM"
mc = 0
ce = 2
baseaddr = 0x02000000
size = 0x00004000
delayr = 1
delayw = 1
end
 
 
/* IMMU SECTION
 
This section configures the Instruction Memory Manangement Unit
255,7 → 120,7
*/
 
section ic
enabled = 1
enabled = 0
nsets = 512
nways = 1
blocksize = 16
299,7 → 164,7
*/
 
section dc
enabled = 1
enabled = 0
nsets = 512
nways = 1
blocksize = 16
371,7 → 236,7
*/
 
section sim
verbose = 1
verbose = 0
debug = 0
profile = 0
prof_fn = "sim.profile"
390,40 → 255,6
end
 
 
/* SECTION VAPI
 
This section configures the Verification API, used for Advanced
Core Verification.
 
enabled = 0/1
'0': disbable VAPI server
'1': enable/start VAPI server
 
server_port = <value>
TCP/IP port to start VAPI server on
 
log_enabled = 0/1
'0': disable VAPI requests logging
'1': enable VAPI requests logging
 
hide_device_id = 0/1
'0': don't log device id (for compatability with old version)
'1': log device id
 
vapi_fn = <filename>
filename for the log file.
valid only if log_enabled is set
*/
 
section VAPI
enabled = 0
server_port = 9998
log_enabled = 0
vapi_log_fn = "vapi.log"
end
 
 
/* CPU SECTION
 
This section specifies various CPU parameters.
460,8 → 291,8
*/
 
section cpu
ver = 0x1200
rev = 0x0001
ver = 0x12
rev = 0x0008
/* upr = */
superscalar = 0
hazards = 1
484,98 → 315,6
end
 
 
/* BPB SECTION
 
This section specifies how branch prediction should behave.
enabled = 0/1
'0': disable branch prediction
'1': enable branch prediction
btic = 0/1
'0': disable branch target instruction cache model
'1': enable branch target instruction cache model
 
sbp_bf_fwd = 0/1
Static branch prediction for 'l.bf'
'0': don't use forward prediction
'1': use forward prediction
sbp_bnf_fwd = 0/1
Static branch prediction for 'l.bnf'
'0': don't use forward prediction
'1': use forward prediction
 
hitdelay = <value>
number of cycles bpb hit costs
missdelay = <value>
number of cycles bpb miss costs
*/
 
section bpb
enabled = 1
btic = 1
sbp_bf_fwd = 0
sbp_bnf_fwd = 0
hitdelay = 0
missdelay = 0
end
 
 
/* DEBUG SECTION
 
This sections specifies how the debug unit should behave.
 
enabled = 0/1
'0': disable debug unit
'1': enable debug unit
 
gdb_enabled = 0/1
'0': don't start gdb server
'1': start gdb server at port 'server_port'
 
server_port = <value>
TCP/IP port to start gdb server on
valid only if gdb_enabled is set
 
vapi_id = <hex_value>
Used to create "fake" vapi log file containing the JTAG proxy messages.
*/
/*
section debug
enabled = 1
gdb_enabled = 1
server_port = 12345
end
*/
 
/* MC SECTION
 
This section configures the memory controller
 
enabled = 0/1
'0': disable memory controller
'1': enable memory controller
 
baseaddr = <hex_value>
address of first MC register
 
POC = <hex_value>
Power On Configuration register
 
index = <value>
Index of this memory controller amongst all the memory controllers
*/
 
section mc
enabled = 0
baseaddr = 0x60000000
POC = 0x00000008 /* Power on configuration register */
index = 0
end
 
 
/* UART SECTION
 
This section configures the UARTs
643,261 → 382,3
16550 = 1
end
 
 
/* DMA SECTION
 
This section configures the DMAs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first DMA register for this device
 
irq = <value>
irq number for this device
 
vapi_id = <hex_value>
VAPI id of this instance
*/
 
section dma
enabled = 0
baseaddr = 0x9a000000
irq = 11
end
 
 
/* ETHERNET SECTION
 
This section configures the ETHERNETs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first ethernet register for this device
 
dma = <value>
which controller is this ethernet "connected" to
 
irq = <value>
ethernet mac IRQ level
 
rtx_type = <value>
use 0 - file interface, 1 - socket interface
 
rx_channel = <value>
DMA channel used for RX
 
tx_channel = <value>
DMA channel used for TX
 
rxfile = "<filename>"
filename, where to read data from
 
txfile = "<filename>"
filename, where to write data to
 
sockif = "<ifacename>"
interface name of ethernet socket
 
vapi_id = <hex_value>
VAPI id of this instance
*/
 
section ethernet
enabled = 0
baseaddr = 0x92000000
dma = 0
irq = 4
rtx_type = 0
tx_channel = 0
rx_channel = 1
rxfile = "eth0.rx"
txfile = "eth0.tx"
sockif = "eth0"
end
 
 
/* GPIO SECTION
 
This section configures the GPIOs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first GPIO register for this device
 
irq = <value>
irq number for this device
 
base_vapi_id = <hex_value>
first VAPI id of this instance
GPIO uses 8 consecutive VAPI IDs
*/
 
section gpio
enabled = 0
baseaddr = 0x91000000
irq = 3
base_vapi_id = 0x0200
end
 
/* VGA SECTION
This section configures the VGA/LCD controller
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first VGA register
irq = <value>
irq number for this device
refresh_rate = <value>
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
 
section vga
enabled = 0
baseaddr = 0x97100000
irq = 8
refresh_rate = 100000
filename = "primary"
end
 
 
/* TICK TIMER SECTION
 
This section configures tick timer
 
enabled = 0/1
whether tick timer is enabled
*/
/*
section tick
enabled = 1
irq = 3
end
*/
/*
section pic
enabled = 1
edge_trigger = 1
end
*/
 
/* FB SECTION
This section configures the frame buffer
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
base address of frame buffer
paladdr = <hex_value>
base address of first palette entry
refresh_rate = <value>
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
 
section fb
enabled = 0
baseaddr = 0x97000000
refresh_rate = 1000000
filename = "primary"
end
 
 
/* KBD SECTION
 
This section configures the PS/2 compatible keyboard
baseaddr = <hex_value>
base address of the keyboard device
rxfile = "<filename>"
filename, where to read data from
*/
 
section kbd
enabled = 0
irq = 5
baseaddr = 0x94000000
rxfile = "kbd.rx"
end
 
 
/* ATA SECTION
This section configures the ATA/ATAPI host controller
baseaddr = <hex_value>
address of first ATA register
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
irq = <value>
irq number for this device
 
debug = <value>
debug level for ata models.
0: no debug messages
1: verbose messages
3: normal messages (more messages than verbose)
5: debug messages (normal debug messages)
7: flow control messages (debug statemachine flows)
9: low priority message (display everything the code does)
 
dev_type0/1 = <value>
ata device 0 type
0: NO_CONNeCT: none (not connected)
1: FILE : simulated harddisk
2: LOCAL : local system harddisk
 
dev_file0/1 = "<filename>"
filename for simulated ATA device
valid only if dev_type0 == 1
 
dev_size0/1 = <value>
size of simulated hard-disk (in MBytes)
valid only if dev_type0 == 1
 
dev_packet0/1 = <value>
0: simulated ATA device does NOT implement PACKET command feature set
1: simulated ATA device does implement PACKET command feature set
 
FIXME: irq number
*/
/*
section ata
enabled = 0
baseaddr = 0x9e000000
irq = 15
 
dev_type0 = 1
dev_file0 = "/tmp/sim_atadev0"
dev_size0 = 1
dev_packet0 = 0
 
dev_type1 = 0
dev_file1 = ""
dev_size1 = 0
dev_packet1 = 0
end
*/
 

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