URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/sim
- from Rev 468 to Rev 475
- ↔ Reverse comparison
Rev 468 → Rev 475
/bin/or1ksim-orpsocv2.cfg
File deleted
bin/or1ksim-orpsocv2.cfg
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: bin/refdesign-or1ksim.cfg
===================================================================
--- bin/refdesign-or1ksim.cfg (nonexistent)
+++ bin/refdesign-or1ksim.cfg (revision 475)
@@ -0,0 +1,384 @@
+section memory
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "RAM"
+ ce = 1
+ mc = 0
+ baseaddr = 0x00000000
+ size = 0x02000000
+ delayr = 1
+ delayw = 1
+end
+
+/* IMMU SECTION
+
+ This section configures the Instruction Memory Manangement Unit
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of ITLB sets; must be power of two
+
+ nways =
+ number of ITLB ways
+
+ pagesize =
+ instruction page size; must be power of two
+
+ entrysize =
+ instruction entry size in bytes
+
+ ustates =
+ number of ITLB usage states (2, 3, 4 etc., max is 4)
+
+ hitdelay =
+ number of cycles immu hit costs
+
+ missdelay =
+ number of cycles immu miss costs
+*/
+
+section immu
+
+ enabled = 1
+ nsets = 64
+ nways = 1
+ pagesize = 8192
+
+end
+
+
+/* DMMU SECTION
+
+ This section configures the Data Memory Manangement Unit
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of DTLB sets; must be power of two
+
+ nways =
+ number of DTLB ways
+
+ pagesize =
+ data page size; must be power of two
+
+ entrysize =
+ data entry size in bytes
+
+ ustates =
+ number of DTLB usage states (2, 3, 4 etc., max is 4)
+
+ hitdelay =
+ number of cycles dmmu hit costs
+
+ missdelay =
+ number of cycles dmmu miss costs
+*/
+
+section dmmu
+ enabled = 1
+ nsets = 64
+ nways = 1
+ pagesize = 8192
+end
+
+
+/* IC SECTION
+
+ This section configures the Instruction Cache
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of IC sets; must be power of two
+
+ nways =
+ number of IC ways
+
+ blocksize =
+ IC block size in bytes; must be power of two
+
+ ustates =
+ number of IC usage states (2, 3, 4 etc., max is 4)
+
+ hitdelay =
+ number of cycles ic hit costs
+
+ missdelay =
+ number of cycles ic miss costs
+*/
+
+section ic
+ enabled = 0
+ nsets = 512
+ nways = 1
+ blocksize = 16
+ hitdelay = 1
+ missdelay = 10
+end
+
+
+/* DC SECTION
+
+ This section configures the Data Cache
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of DC sets; must be power of two
+
+ nways =
+ number of DC ways
+
+ blocksize =
+ DC block size in bytes; must be power of two
+
+ ustates =
+ number of DC usage states (2, 3, 4 etc., max is 4)
+
+ load_hitdelay =
+ number of cycles dc load hit costs
+
+ load_missdelay =
+ number of cycles dc load miss costs
+
+ store_hitdelay =
+ number of cycles dc load hit costs
+
+ store_missdelay =
+ number of cycles dc load miss costs
+*/
+
+section dc
+ enabled = 0
+ nsets = 512
+ nways = 1
+ blocksize = 16
+end
+
+
+/* SIM SECTION
+
+ This section specifies how or1ksim should behave.
+
+ verbose = 0/1
+ '0': don't print extra messages
+ '1': print extra messages
+
+ debug = 0-9
+ 0 : no debug messages
+ 1-9: debug message level.
+ higher numbers produce more messages
+
+ profile = 0/1
+ '0': don't generate profiling file 'sim.profile'
+ '1': don't generate profiling file 'sim.profile'
+
+ prof_fn = ""
+ optional filename for the profiling file.
+ valid only if 'profile' is set
+
+ mprofile = 0/1
+ '0': don't generate memory profiling file 'sim.mprofile'
+ '1': generate memory profiling file 'sim.mprofile'
+
+ mprof_fn = ""
+ optional filename for the memory profiling file.
+ valid only if 'mprofile' is set
+
+ history = 0/1
+ '0': don't track execution flow
+ '1': track execution flow
+ Execution flow can be tracked for the simulator's
+ 'hist' command. Useful for back-trace debugging.
+
+ iprompt = 0/1
+ '0': start in (so what do we start in ???)
+ '1': start in interactive prompt.
+
+ exe_log = 0/1
+ '0': don't generate execution log.
+ '1': generate execution log.
+
+ exe_log = default/hardware/simple/software
+ type of execution log, default is used when not specified
+
+ exe_log_start =
+ index of first instruction to start logging, default = 0
+
+ exe_log_end =
+ index of last instruction to end logging; not limited, if omitted
+
+ exe_log_marker =
+ specifies number of instructions before horizontal marker is
+ printed; if zero, markers are disabled (default)
+
+ exe_log_fn = ""
+ filename for the exection log file.
+ valid only if 'exe_log' is set
+
+ clkcycle = [ps|ns|us|ms]
+ specifies time measurement for one cycle
+*/
+
+section sim
+ verbose = 0
+ debug = 0
+ profile = 0
+ prof_fn = "sim.profile"
+ history = 1
+ /* iprompt = 0 */
+ exe_log = 0
+ exe_log_type = hardware
+ exe_log_fn = "executed.log"
+ clkcycle = 20ns
+end
+
+
+/* CPU SECTION
+
+ This section specifies various CPU parameters.
+
+ ver =
+ rev =
+ specifies version and revision of the CPU used
+
+ upr =
+ changes the upr register
+
+ sr =
+ sets the initial Supervision Register value
+
+ superscalar = 0/1
+ '0': CPU is scalar
+ '1': CPU is superscalar
+ (modify cpu/or32/execute.c to tune superscalar model)
+
+ hazards = 0/1
+ '0': don't track data hazards in superscalar CPU
+ '1': track data hazards in superscalar CPU
+ If tracked, data hazards can be displayed using the
+ simulator's 'r' command.
+
+ dependstats = 0/1
+ '0': don't calculate inter-instruction dependencies.
+ '1': calculate inter-instruction dependencies.
+ If calculated, inter-instruction dependencies can be
+ displayed using the simulator's 'stat' command.
+
+ sbuf_len =
+ length of store buffer (<= 256), 0 = disabled
+*/
+
+section cpu
+ ver = 0x12
+ rev = 0x0008
+ /* upr = */
+ superscalar = 0
+ hazards = 1
+ dependstats = 1
+ sbuf_len = 1
+end
+
+
+/* PM SECTION
+
+ This section specifies Power Management parameters
+
+ enabled = 0/1
+ '0': disable power management
+ '1': enable power management
+*/
+
+section pm
+ enabled = 0
+end
+
+
+section pic
+ enabled = 1
+ edge_trigger = 1
+end
+
+
+/* UART SECTION
+
+ This section configures the UARTs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ address of first UART register for this device
+
+
+ channel = :
+
+ The channel parameter indicates the source of received UART characters
+ and the sink for transmitted UART characters.
+
+ The can be either "file", "xterm", "tcp", "fd", or "tty"
+ (without quotes).
+
+ A) To send/receive characters from a pair of files, use a file
+ channel:
+
+ channel=file:,
+
+ B) To create an interactive terminal window, use an xterm channel:
+
+ channel=xterm:[]*
+
+ C) To create a bidirectional tcp socket which one could, for example,
+ access via telnet, use a tcp channel:
+
+ channel=tcp:
+
+ D) To cause the UART to read/write from existing numeric file
+ descriptors, use an fd channel:
+
+ channel=fd:,
+
+ E) To connect the UART to a physical serial port, create a tty
+ channel:
+
+ channel=tty:device=/dev/ttyS0,baud=9600
+
+ irq =
+ irq number for this device
+
+ 16550 = 0/1
+ '0': this device is a UART16450
+ '1': this device is a UART16550
+
+ jitter =
+ in msecs... time to block, -1 to disable it
+
+ vapi_id =
+ VAPI id of this instance
+*/
+
+section uart
+ enabled = 1
+ baseaddr = 0x90000000
+ irq = 2
+ /*channel = "file:uart0.rx,uart0.tx"*/
+ channel = "tcp:10084"
+ jitter = -1 /* async behaviour */
+ 16550 = 1
+end
+
bin/refdesign-or1ksim.cfg
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/Makefile
===================================================================
--- bin/Makefile (revision 468)
+++ bin/Makefile (revision 475)
@@ -179,9 +179,12 @@
endif
# VSIM commands
# Suppressed warnings - 3009: Failed to open $readmemh() file
-# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
-# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
-MGC_VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
+# Suppressed warnings - 3009: Module 'blah' does not have a `timescale
+# directive in effect, but previous modules do.
+# Suppressed warnings - 8598: Non-positive replication multiplier inside
+# concat. Replication will be ignored
+MGC_VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) \
+ -do "set StdArithNoWarnings 1; run -all; exit"
# Options required when VPI option used
ifeq ($(VPI), 1)
MGC_VPI_LIB=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
@@ -206,15 +209,25 @@
#
# A list of paths under rtl/verilog we wish to exclude for module searching
VERILOG_MODULES_EXCLUDE= include components
-VERILOG_MODULES_EXCLUDE_LIST_E=$(shell for exclude in $(VERILOG_MODULES_EXCLUDE); do echo "-e $$exclude"; done)
-RTL_VERILOG_MODULES=$(shell ls $(RTL_VERILOG_DIR) | grep -v $(VERILOG_MODULES_EXCLUDE_LIST_E) )
+VERILOG_MODULES_EXCLUDE_LIST_E=$(shell for exclude in \
+ $(VERILOG_MODULES_EXCLUDE); do echo "-e $$exclude"; done)
+RTL_VERILOG_MODULES=$(shell ls $(RTL_VERILOG_DIR) | grep -v \
+ $(VERILOG_MODULES_EXCLUDE_LIST_E) )
# Specific files to exclude, currently none.
#VERILOG_EXCLUDE=
-#VERILOG_EXCLUDE_LIST_E=$(shell for exclude in $(VERILOG_EXCLUDE); do echo "-e $$exclude"; done)
+#VERILOG_EXCLUDE_LIST_E=$(shell for exclude in $(VERILOG_EXCLUDE); \
+ do echo "-e $$exclude"; done)
# List of verilog source files, minus excluded files
-#RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do if [ -d $(RTL_VERILOG_DIR)/$$module ]; then ls $(RTL_VERILOG_DIR)/$$module/*.v | grep -v $(VERILOG_EXCLUDE_LIST_E); fi; done)
+#RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do \
+ if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
+ ls $(RTL_VERILOG_DIR)/$$module/*.v | grep -v \
+ $(VERILOG_EXCLUDE_LIST_E); \
+ fi; done)
# List of verilog source files, ignoring excludes
-RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do if [ -d $(RTL_VERILOG_DIR)/$$module ]; then ls $(RTL_VERILOG_DIR)/$$module/*.v; fi; done)
+RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do \
+ if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
+ ls $(RTL_VERILOG_DIR)/$$module/*.v; \
+ fi; done)
# List of verilog includes
RTL_VERILOG_INCLUDES=$(shell ls $(RTL_VERILOG_INCLUDE_DIR)/*.*)
@@ -241,7 +254,10 @@
# VHDL modules
#RTL_VHDL_MODULES=$(shell ls $(RTL_VHDL_DIR))
# VHDL sources
-#RTL_VHDL_SRC=$(shell for module in $(RTL_VHDL_MODULES); do if [ -d $(RTL_VHDL_DIR)/$$module ]; then ls $(RTL_VHDL_DIR)/$$module/*.vhd; fi; done)
+#RTL_VHDL_SRC=$(shell for module in $(RTL_VHDL_MODULES); do \
+ if [ -d $(RTL_VHDL_DIR)/$$module ]; then \
+ ls $(RTL_VHDL_DIR)/$$module/*.vhd; \
+ fi; done)
#print-vhdl-src:
# @echo echo; echo "\t### VHDL modules and source ###"; echo
# @echo "modules: "; echo $(RTL_VHDL_MODULES); echo
@@ -249,7 +265,8 @@
# Testbench verilog source
-BENCH_VERILOG_SRC=$(shell ls $(BENCH_VERILOG_DIR)/*.v | grep -v $(DESIGN_NAME)_testbench )
+BENCH_VERILOG_SRC=$(shell ls $(BENCH_VERILOG_DIR)/*.v | grep -v \
+ $(DESIGN_NAME)_testbench )
print-bench-src:
$(Q)echo "\tBench verilog source"; \
@@ -256,23 +273,34 @@
echo $(BENCH_VERILOG_SRC)
# Testbench source subdirectory detection
-BENCH_VERILOG_SRC_SUBDIRS +=$(shell for file in `ls $(BENCH_VERILOG_DIR)`; do if [ -d $(BENCH_VERILOG_DIR)/$$file ]; then echo $(BENCH_VERILOG_DIR)/$$file; fi; done)
+BENCH_VERILOG_SRC_SUBDIRS +=$(shell for file in `ls $(BENCH_VERILOG_DIR)`; do \
+ if [ -d $(BENCH_VERILOG_DIR)/$$file ]; then \
+ echo $(BENCH_VERILOG_DIR)/$$file; \
+ fi; done)
# Compile script generation rules:
-modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
+modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
+ $(BOOTROM_VERILOG)
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
$(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
$(Q)echo "+incdir+"$(BENCH_VERILOG_INCLUDE_DIR) >> $@;
$(Q)echo "+libext+.v" >> $@;
- $(Q)for module in $(RTL_VERILOG_MODULES); do if [ -d $(RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; fi; done
+ $(Q)for module in $(RTL_VERILOG_MODULES); do \
+ if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
+ echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
+ fi; done
$(Q)echo >> $@
modelsim_bench.scr: $(BENCH_VERILOG_SRC)
$(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) > $@;
- $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do echo "+incdir+"$$path >> $@; done
- $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do echo "-y "$$path >> $@; done
+ $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
+ echo "+incdir+"$$path >> $@; \
+ done
+ $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
+ echo "-y "$$path >> $@; \
+ done
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) >> $@;
$(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
$(Q)echo "+libext+.v" >> $@;
@@ -301,7 +329,8 @@
# Icarus Verilog simulator build and run rules
#
.PHONY: $(ICARUS_SCRIPT)
-$(ICARUS_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG) $(BENCH_VERILOG_SRC)
+$(ICARUS_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
+ $(BOOTROM_VERILOG) $(BENCH_VERILOG_SRC)
$(Q)echo "# Icarus Verilog simulation script" > $@
$(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
@@ -308,9 +337,15 @@
$(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
$(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) >> $@;
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
- $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do echo "+incdir+"$$path >> $@; done
- $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do echo "-y "$$path >> $@; done
- $(Q)for module in $(RTL_VERILOG_MODULES); do echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; done
+ $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
+ echo "+incdir+"$$path >> $@; \
+ done
+ $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
+ echo "-y "$$path >> $@; \
+ done
+ $(Q)for module in $(RTL_VERILOG_MODULES); do \
+ echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
+ done
$(Q)echo "-y" $(RTL_SIM_SRC_DIR) >> $@;
$(Q)echo "-y" $(BENCH_VERILOG_DIR) >> $@;
$(Q)echo $(BENCH_TOP) >> $@;
@@ -366,9 +401,6 @@
# Include the test-defines.v generation rule
include ../bin/definesgen.inc
-# $(Q)for module in $(GATELEVEL_MODULES); do echo "\`define "$$module"_IS_GATELEVEL " >> $@; done
-# More possible test defines go here
-
#
# Software make rules (called recursively)
#
@@ -478,7 +510,8 @@
# Clean away verilator build path and objects in SystemC path
clean-vlt:
$(Q)rm -rf $(SIM_VLT_DIR)
- $(Q)$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make clean
+ $(Q)$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f \
+ $(BENCH_SYSC_SRC_DIR)/Modules.make clean
clean-test-defines:
$(Q)rm -f $(TEST_DEFINES_VLG)
@@ -511,7 +544,8 @@
VLT_SCRIPT=verilator.scr
# Script for Verilator
-$(SIM_VLT_DIR)/$(VLT_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
+$(SIM_VLT_DIR)/$(VLT_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
+ $(BOOTROM_VERILOG)
$(Q)echo "\tGenerating Verilator script"
$(Q)echo "# Verilator sources script" > $@
$(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
@@ -518,7 +552,9 @@
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
$(Q)echo "+incdir+"$(SIM_RUN_DIR) >> $@;
- $(Q)for module in $(RTL_VERILOG_MODULES); do echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; done
+ $(Q)for module in $(RTL_VERILOG_MODULES); do \
+ echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
+ done
$(Q)echo $(DUT_TOP) >> $@;
$(Q) echo >> $@
@@ -558,7 +594,8 @@
# checking the efficiency of the model - not really useful for checking code
# or the function of the model.
ifdef VLT_DO_PERFORMANCE_PROFILE_BUILD
-VLT_CPPFLAGS += -fprofile-generate -fbranch-probabilities -fvpt -funroll-loops -fpeel-loops -ftracer
+VLT_CPPFLAGS += -fprofile-generate -fbranch-probabilities -fvpt \
+ -funroll-loops -fpeel-loops -ftracer
else
VLT_CPPFLAGS +=-fprofile-use -Wcoverage-mismatch
endif
@@ -581,7 +618,8 @@
VLT_FLAGS +=--inline-mult 1
# Optimisation option for Verilator scripts
VLT_FLAGS +=-O3
-# X-assign - at reset, all signals are set to random values, helps find rst bugs
+# X-assign - at reset, all signals are set to random values, helps find
+# reset bugs
VLT_FLAGS +=-x-assign unique
VLT_TRACEOBJ = verilated_vcd_c
@@ -595,9 +633,13 @@
SYSC_MODEL_SOURCES=$(shell ls $(BENCH_SYSC_SRC_DIR)/*.cpp)
SYSC_MODEL_SOURCES +=$(shell ls $(BENCH_SYSC_INCLUDE_DIR)/*.h)
-VLT_MODULES_OBJS=$(shell for mod in $(SYSC_MODELS_BUILD); do echo $(SIM_VLT_DIR)/$$mod.o; done)
+VLT_MODULES_OBJS=$(shell for mod in $(SYSC_MODELS_BUILD); do \
+ echo $(SIM_VLT_DIR)/$$mod.o; \
+ done)
-VLT_MODEL_LINKS=$(shell for SYSCMODEL in $(SYSC_MODELS); do echo $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; done)
+VLT_MODEL_LINKS=$(shell for SYSCMODEL in $(SYSC_MODELS); do \
+ echo $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
+ done)
# Make Verilator build path if it doesn't exist
$(SIM_VLT_DIR):
@@ -618,18 +660,32 @@
$(SIM_VLT_DIR)/$(VLT_EXE) -h
@echo;echo
-$(SIM_VLT_DIR)/$(VLT_EXE): $(SIM_VLT_DIR)/lib$(VLT_EXE).a $(SIM_VLT_DIR)/OrpsocMain.o
-# Final linking of the simulation executable. Order of libraries here is important!
+$(SIM_VLT_DIR)/$(VLT_EXE): $(SIM_VLT_DIR)/lib$(VLT_EXE).a \
+ $(SIM_VLT_DIR)/OrpsocMain.o
+# Final linking of the simulation executable. Order of libraries here is
+# important!
$(Q)echo; echo "\tGenerating simulation executable"; echo
- $(Q)cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o $(VLT_EXE) -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) OrpsocMain.o -l$(VLT_EXE) -lmodules -lsystemc
+ $(Q)cd $(SIM_VLT_DIR) && \
+ g++ $(VLT_DEBUG_COMPILE_FLAGS) \
+ $(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) \
+ -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o $(VLT_EXE) \
+ -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) \
+ OrpsocMain.o -l$(VLT_EXE) -lmodules -lsystemc
-# Now compile the top level systemC "testbench" module from the systemC source path
+# Now compile the top level systemC "testbench" module from the systemC source
+# path
$(SIM_VLT_DIR)/OrpsocMain.o: $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
@echo; echo "\tCompiling top level SystemC testbench"; echo
- cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
+ cd $(SIM_VLT_DIR) && \
+ g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) \
+ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) \
+ -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c \
+ $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
-$(SIM_VLT_DIR)/lib$(VLT_EXE).a: $(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a $(VLT_MODULES_OBJS) $(SIM_VLT_DIR)/verilated.o
-# Now archive all of the libraries from verilator witht he other modules we might have
+$(SIM_VLT_DIR)/lib$(VLT_EXE).a: $(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a \
+ $(VLT_MODULES_OBJS) $(SIM_VLT_DIR)/verilated.o
+# Now archive all of the libraries from verilator witht he other modules we
+# might have
@echo; echo "\tArchiving libraries into lib"$(VLT_EXE)".a"; echo
$(Q)cd $(SIM_VLT_DIR) && \
cp $(VLT_EXE)__ALL.a lib$(VLT_EXE).a && \
@@ -661,7 +717,8 @@
$(MAKE) -f $(VLT_EXE).mk $$SYSCMODEL.o; \
done
-$(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a: $(SIM_VLT_DIR)/$(VLT_EXE).mk $(SYSC_MODEL_SOURCES)
+$(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a: $(SIM_VLT_DIR)/$(VLT_EXE).mk \
+ $(SYSC_MODEL_SOURCES)
@echo; echo "\tCompiling main design"; echo
$(Q)cd $(SIM_VLT_DIR) && \
export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
@@ -668,17 +725,21 @@
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
$(MAKE) -f $(VLT_EXE).mk $(VLT_EXE)__ALL.a
-$(SIM_VLT_DIR)/$(VLT_EXE).mk: $(SIM_VLT_DIR)/$(VLT_SCRIPT) $(BENCH_SYSC_SRC_DIR)/libmodules.a
+$(SIM_VLT_DIR)/$(VLT_EXE).mk: $(SIM_VLT_DIR)/$(VLT_SCRIPT) \
+ $(BENCH_SYSC_SRC_DIR)/libmodules.a
# Now call verilator to generate the .mk files
$(Q)echo; echo "\tGenerating makefiles with Verilator"; echo
$(Q)cd $(SIM_VLT_DIR) && \
- verilator -language 1364-2001 --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
+ verilator -language 1364-2001 --top-module orpsoc_top -Mdir . -sc \
+ $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) \
+ -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
# SystemC modules library
$(BENCH_SYSC_SRC_DIR)/libmodules.a:
@echo; echo "\tCompiling SystemC modules"; echo
$(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
- $(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
+ $(MAKE) -C $(BENCH_SYSC_SRC_DIR) \
+ -f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
print-vlt-model-link-paths:
$(Q)echo $(VLT_MODEL_LINKS)
@@ -688,8 +749,10 @@
for SYSCMODEL in $(SYSC_MODELS); do \
if [ ! -e $(SIM_VLT_DIR)/$$SYSCMODEL.cpp ]; then \
echo "\tLinking SystemC model $$SYSCMODEL Verilator model build path"; \
- ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
- ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h $(SIM_VLT_DIR)/$$SYSCMODEL.h; \
+ ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp \
+ $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
+ ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h \
+ $(SIM_VLT_DIR)/$$SYSCMODEL.h; \
fi; \
done
@@ -727,7 +790,6 @@
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
$(MAKE) -C $(SW_DIR)/apps/dhry dhry.elf NUM_RUNS=5000
-# $(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/dhry/dhry.elf -v -l sim.log --crash-monitor
$(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/apps/dhry/dhry.elf
# Clean all compiled things
@@ -751,7 +813,9 @@
lint-vlt: $(SIM_VLT_DIR) rtl $(DUMMY_FILES_FOR_VLT) $(SIM_VLT_DIR)/$(VLT_SCRIPT)
$(Q)echo; echo "\tLinting design with Verilator"; echo
$(Q)cd $(SIM_VLT_DIR) && \
- verilator -language 1364-2001 --top-module orpsoc_top --lint-only -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
+ verilator -language 1364-2001 --top-module orpsoc_top --lint-only \
+ -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) \
+ -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
################################################################################
# Architectural simulator test rules
@@ -758,7 +822,7 @@
################################################################################
ARCH_SIM_EXE ?=or32-elf-sim
-ARCH_SIM_CFG ?= ../bin/or1ksim-orpsocv2.cfg
+ARCH_SIM_CFG ?= ../bin/refdesign-or1ksim.cfg
ARCH_SIM_OPTS ?= -q
.PHONY: rtl-test