OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/rtos
    from Rev 669 to Rev 675
    Reverse comparison

Rev 669 → Rev 675

/freertos-6.1.1/Source/portable/GCC/OpenRISC/port.c
74,31 → 74,27
static void prvSetupTimerInterrupt( void );
 
/* For writing into SPR. */
static inline void mtspr(unsigned long spr, unsigned long value) {
static inline void mtspr(unsigned long spr, unsigned long value)
{
asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value));
}
 
/* For reading SPR. */
static inline unsigned long mfspr(unsigned long spr) {
static inline unsigned long mfspr(unsigned long spr)
{
unsigned long value;
asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr));
return value;
}
 
inline void vPortDisableInterrupts( void )
{
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_TEE|SPR_SR_IEE)); // Tick, interrupt stop
}
/* forward decleation */
inline void vPortDisableInterrupts( void );
inline void vPortEnableInterrupts( void );
 
inline void vPortEnableInterrupts( void )
{
mtspr(SPR_SR, mfspr(SPR_SR) | (SPR_SR_TEE|SPR_SR_IEE)); // Tick, interrupt start
}
 
 
/*
* Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
* portSAVE_CONTEXT had been called. Context layout is described in
* portmarco.h
*
* See header file for description.
*/
107,6 → 103,9
unsigned portLONG uTaskSR = mfspr(SPR_SR);
uTaskSR |= SPR_SR_SM; // Supervisor mode
uTaskSR |= (SPR_SR_TEE | SPR_SR_IEE); // Tick interrupt enable, All External interupt enable
// allocate redzone
pxTopOfStack -= REDZONE_SIZE/4;
 
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
155,7 → 154,58
prvSetupTimerInterrupt();
 
/* Start the first task. */
portRESTORE_CONTEXT();
asm volatile (
" .global pxCurrentTCB \n\t"
/* restore stack pointer */
" l.movhi r3, hi(pxCurrentTCB) \n\t"
" l.ori r3, r3, lo(pxCurrentTCB) \n\t"
" l.lwz r3, 0x0(r3) \n\t"
" l.lwz r1, 0x0(r3) \n\t"
/* restore context */
" l.lwz r9, 0x00(r1) \n\t"
" l.lwz r2, 0x04(r1) \n\t"
" l.lwz r6, 0x14(r1) \n\t"
" l.lwz r7, 0x18(r1) \n\t"
" l.lwz r8, 0x1C(r1) \n\t"
" l.lwz r10, 0x20(r1) \n\t"
" l.lwz r11, 0x24(r1) \n\t"
" l.lwz r12, 0x28(r1) \n\t"
" l.lwz r13, 0x2C(r1) \n\t"
" l.lwz r14, 0x30(r1) \n\t"
" l.lwz r15, 0x34(r1) \n\t"
" l.lwz r16, 0x38(r1) \n\t"
" l.lwz r17, 0x3C(r1) \n\t"
" l.lwz r18, 0x40(r1) \n\t"
" l.lwz r19, 0x44(r1) \n\t"
" l.lwz r20, 0x48(r1) \n\t"
" l.lwz r21, 0x4C(r1) \n\t"
" l.lwz r22, 0x50(r1) \n\t"
" l.lwz r23, 0x54(r1) \n\t"
" l.lwz r24, 0x58(r1) \n\t"
" l.lwz r25, 0x5C(r1) \n\t"
" l.lwz r26, 0x60(r1) \n\t"
" l.lwz r27, 0x64(r1) \n\t"
" l.lwz r28, 0x68(r1) \n\t"
" l.lwz r29, 0x6C(r1) \n\t"
" l.lwz r30, 0x70(r1) \n\t"
" l.lwz r31, 0x74(r1) \n\t"
/* restore SPR_ESR_BASE(0), SPR_EPCR_BASE(0) */
" l.lwz r3, 0x78(r1) \n\t"
" l.lwz r4, 0x7C(r1) \n\t"
" l.mtspr r0, r3, %1 \n\t"
" l.mtspr r0, r4, %2 \n\t"
/* restore clobber register */
" l.lwz r3, 0x08(r1) \n\t"
" l.lwz r4, 0x0C(r1) \n\t"
" l.lwz r5, 0x10(r1) \n\t"
" l.addi r1, r1, %0 \n\t"
" l.rfe \n\t"
" l.nop \n\t"
:
: "n"(STACKFRAME_SIZE),
"n"(SPR_ESR_BASE),
"n"(SPR_EPCR_BASE)
);
/* Should not get here! */
} else {
194,6 → 244,16
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
}
 
inline void vPortDisableInterrupts( void )
{
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_TEE|SPR_SR_IEE)); // Tick, interrupt stop
}
 
inline void vPortEnableInterrupts( void )
{
mtspr(SPR_SR, mfspr(SPR_SR) | (SPR_SR_TEE|SPR_SR_IEE)); // Tick, interrupt start
}
 
/*
* naked attribute is ignored or32-elf-gcc 4.5.1-or32-1.0rc1
* use assemble routines in portasm.S
/freertos-6.1.1/Source/portable/GCC/OpenRISC/portasm.S
1,4 → 1,7
#include "port_spr_defs.h"
#include "portmacro.h"
#include "FreeRTOSConfig.h"
 
.file "portasm.S"
.section .text
6,7 → 9,7
.macro portSAVE_CONTEXT
.global pxCurrentTCB
# make rooms in stack
l.addi r1, r1, -132
l.addi r1, r1, -STACKFRAME_SIZE
# early save r3-r5, these are clobber register
l.sw 0x08(r1), r3
l.sw 0x0C(r1), r4
16,8 → 19,8
l.mfspr r4, r0, SPR_EPCR_BASE
l.sw 0x78(r1), r3
l.sw 0x7C(r1), r4
# Save Context
l.sw 0x00(r1), r9
# Save Context
l.sw 0x04(r1), r2
l.sw 0x14(r1), r6
l.sw 0x18(r1), r7
62,11 → 65,11
l.lwz r3, 0x0(r3)
l.lwz r1, 0x0(r3)
# restore context
l.lwz r9, 0x00(r1)
l.lwz r2, 0x04(r1)
l.lwz r6, 0x14(r1)
l.lwz r7, 0x18(r1)
l.lwz r8, 0x1C(r1)
l.lwz r9, 0x00(r1)
l.lwz r2, 0x04(r1)
l.lwz r6, 0x14(r1)
l.lwz r7, 0x18(r1)
l.lwz r8, 0x1C(r1)
l.lwz r10, 0x20(r1)
l.lwz r11, 0x24(r1)
l.lwz r12, 0x28(r1)
90,15 → 93,15
l.lwz r30, 0x70(r1)
l.lwz r31, 0x74(r1)
# restore SPR_ESR_BASE(0), SPR_EPCR_BASE(0)
l.lwz r3, 0x78(r1)
l.lwz r4, 0x7C(r1)
l.mtspr r0, r3, SPR_ESR_BASE
l.mtspr r0, r4, SPR_EPCR_BASE
l.lwz r3, 0x78(r1)
l.lwz r4, 0x7C(r1)
l.mtspr r0, r3, SPR_ESR_BASE
l.mtspr r0, r4, SPR_EPCR_BASE
# restore clobber register
l.lwz r3, 0x08(r1)
l.lwz r4, 0x0C(r1)
l.lwz r5, 0x10(r1)
l.addi r1, r1, 132
l.lwz r3, 0x08(r1)
l.lwz r4, 0x0C(r1)
l.lwz r5, 0x10(r1)
l.addi r1, r1, STACKFRAME_SIZE
l.rfe
l.nop
.endm
/freertos-6.1.1/Source/portable/GCC/OpenRISC/portmacro.h
84,79 → 84,66
#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 )
 
#define portYIELD_FROM_ISR() portYIELD()
#define portYIELD() { \
__asm__ __volatile__ ( "l.nop " ); \
__asm__ __volatile__ ( "l.sys 0x0FCC" ); \
__asm__ __volatile__ ( "l.nop " ); \
}
#define portYIELD() \
__asm__ __volatile__ ( "l.nop \n\t" \
"l.sys 0x0FCC\n\t" \
"l.nop \n\t" \
);
#define portNOP() __asm__ __volatile__ ( "l.nop" )
 
 
void vPortDisableInterrupts( void );
void vPortEnableInterrupts( void );
#define portDISABLE_INTERRUPTS() vPortDisableInterrupts()
#define portENABLE_INTERRUPTS() vPortEnableInterrupts()
/*-----------------------------------------------------------*/
#define portDISABLE_INTERRUPTS() { extern inline void vPortDisableInterrupts( void ); vPortDisableInterrupts(); }
#define portENABLE_INTERRUPTS() { extern inline void vPortEnableInterrupts( void ); vPortEnableInterrupts(); }
 
#define portENTER_CRITICAL() { extern void vTaskEnterCritical( void ); vTaskEnterCritical(); }
#define portEXIT_CRITICAL() { extern void vTaskExitCritical( void ); vTaskExitCritical(); }
/*-----------------------------------------------------------*/
extern void vTaskEnterCritical( void );
extern void vTaskExitCritical( void );
#define portENTER_CRITICAL() vTaskEnterCritical()
#define portEXIT_CRITICAL() vTaskExitCritical()
 
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
#define portRESTORE_CONTEXT() \
asm volatile ( \
" .global pxCurrentTCB \n\t" \
" # restore stack pointer \n\t" \
" l.movhi r3, hi(pxCurrentTCB) \n\t" \
" l.ori r3, r3, lo(pxCurrentTCB)\n\t" \
" l.lwz r3, 0x0(r3) \n\t" \
" l.lwz r1, 0x0(r3) \n\t" \
" # restore context \n\t" \
" l.lwz r9, 0x00(r1) \n\t" \
" l.lwz r2, 0x04(r1) \n\t" \
" l.lwz r6, 0x14(r1) \n\t" \
" l.lwz r7, 0x18(r1) \n\t" \
" l.lwz r8, 0x1C(r1) \n\t" \
" l.lwz r10, 0x20(r1) \n\t" \
" l.lwz r11, 0x24(r1) \n\t" \
" l.lwz r12, 0x28(r1) \n\t" \
" l.lwz r13, 0x2C(r1) \n\t" \
" l.lwz r14, 0x30(r1) \n\t" \
" l.lwz r15, 0x34(r1) \n\t" \
" l.lwz r16, 0x38(r1) \n\t" \
" l.lwz r17, 0x3C(r1) \n\t" \
" l.lwz r18, 0x40(r1) \n\t" \
" l.lwz r19, 0x44(r1) \n\t" \
" l.lwz r20, 0x48(r1) \n\t" \
" l.lwz r21, 0x4C(r1) \n\t" \
" l.lwz r22, 0x50(r1) \n\t" \
" l.lwz r23, 0x54(r1) \n\t" \
" l.lwz r24, 0x58(r1) \n\t" \
" l.lwz r25, 0x5C(r1) \n\t" \
" l.lwz r26, 0x60(r1) \n\t" \
" l.lwz r27, 0x64(r1) \n\t" \
" l.lwz r28, 0x68(r1) \n\t" \
" l.lwz r29, 0x6C(r1) \n\t" \
" l.lwz r30, 0x70(r1) \n\t" \
" l.lwz r31, 0x74(r1) \n\t" \
" # restore SPR_ESR_BASE(0), SPR_EPCR_BASE(0)\n\t" \
" l.lwz r3, 0x78(r1) \n\t" \
" l.lwz r4, 0x7C(r1) \n\t" \
" l.mtspr r0, r3, ((0<<11) + 64) \n\t" \
" l.mtspr r0, r4, ((0<<11) + 32) \n\t" \
" # restore clobber register \n\t" \
" l.lwz r3, 0x08(r1) \n\t" \
" l.lwz r4, 0x0C(r1) \n\t" \
" l.lwz r5, 0x10(r1) \n\t" \
" l.addi r1, r1, 132 \n\t" \
" l.rfe \n\t" \
" l.nop \n\t" \
);
/*
Context layout
0x00 r9
0x04 r2
0x08 r3
0x0C r4
0x10 r5
0x14 r6
0x18 r7
0x1C r8
0x20 r10
0x24 r11
0x28 r12
0x2C r13
0x30 r14
0x34 r15
0x38 r16
0x3C r17
0x40 r18
0x44 r19
0x48 r20
0x4C r21
0x50 r22
0x54 r23
0x58 r24
0x5C r25
0x60 r26
0x64 r27
0x68 r28
0x6C r29
0x70 r30
0x74 r31
0x78 ESR
0x7C EPCR
*/
 
#define REDZONE_SIZE (128)
#define CONTEXT_SIZE (128)
#define STACKFRAME_SIZE (CONTEXT_SIZE + REDZONE_SIZE)
 
#ifdef __cplusplus
}
#endif
/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/reset.S
52,7 → 52,7
l.nop
l.sw -4(r1), r3
l.addi r3, r0, 0x200
l.sw -132(r1), r3
l.sw -260(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
63,7 → 63,7
l.nop
l.sw -4(r1), r3
l.addi r3, r0, 0x300
l.sw -132(r1), r3
l.sw -260(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
74,7 → 74,7
l.nop
l.sw -4(r1), r3
l.addi r3, r0, 0x400
l.sw -132(r1), r3
l.sw -260(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
92,7 → 92,7
l.nop
l.sw -4(r1), r3
l.addi r3, r0, 0x600
l.sw -132(r1), r3
l.sw -260(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
103,7 → 103,7
l.nop
l.sw -4(r1), r3
l.addi r3, r0, 0x700
l.sw -132(r1), r3
l.sw -260(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
121,7 → 121,7
l.nop
l.sw -4(r1), r3
l.addi r3, r0, 0x900
l.sw -132(r1), r3
l.sw -260(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
132,7 → 132,7
l.nop
l.sw -4(r1), r3
l.addi r3, r0, 0xa00
l.sw -132(r1), r3
l.sw -260(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
143,7 → 143,7
l.nop
l.sw -4(r1), r3
l.addi r3, r0, 0xb00
l.sw -132(r1), r3
l.sw -260(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
162,7 → 162,7
l.nop
l.sw -4(r1), r3
l.addi r3, r0, 0xd00
l.sw -132(r1), r3
l.sw -260(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
173,7 → 173,7
l.nop
l.sw -4(r1), r3
l.addi r3, r0, 0xe00
l.sw -132(r1), r3
l.sw -260(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
184,7 → 184,7
l.nop
l.sw -4(r1), r3
l.addi r3, r0, 0xf00
l.sw -132(r1), r3
l.sw -260(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.