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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/rtos
    from Rev 811 to Rev 838
    ↔ Reverse comparison
  •

Rev 811 → Rev 838

/ecos-3.0/packages/hal/openrisc/orpsoc/current/cdl/hal_openrisc_orpsoc.cdl
161,7 → 161,8
"-g -O2 -fno-omit-frame-pointer -fno-rtti -fno-exceptions " .
(CYGHWR_MUL_IMPLEMENTED ? "-mhard-mul " : "-msoft-mul ") .
(CYGHWR_DIV_IMPLEMENTED ? "-mhard-div " : "-msoft-div ") .
(CYGHWR_FPU_IMPLEMENTED ? "-mhard-float " : "-msoft-float ") }
(CYGHWR_FPU_IMPLEMENTED ? "-mhard-float " : "-msoft-float ") .
(CYGHWR_BRANCH_SLOT_IMPLEMENTED ? "" : "-mno-branch-delay " ) }
description "
This option controls the global compiler flags which
are used to compile all packages by
309,6 → 310,15
Select this option only if FPU is implemented."
}
 
cdl_option CYGHWR_BRANCH_SLOT_IMPLEMENTED {
display "Branch slot implemented"
flavor bool
default_value 1
description "
Select this option if your implementation of OpenRISC
has branch slot."
}
 
cdl_component CYGHWR_ICACHE_IMPLEMENTED {
display "Instruction cache implemented"
flavor bool
/ecos-3.0/packages/hal/openrisc/arch/current/src/redboot_linux_exec.c
49,6 → 49,7
//#####DESCRIPTIONBEGIN####
//
// Author(s): Piotr Skrzypek
// Contributor: R.Diez
// Date: 2012-06-08
// Purpose:
// Description: Based on ARM code
171,6 → 172,15
 
// This code is executed from the trampoline address. Trampoline never returns.
asm volatile (
 
// All code below must be position independent,
// as it will run on another memory address.
// Accorting to ABI:
// R3 is base_addr
// R4 is base_addr + length
// R5 is target
// R6 is the entry point to jump to at the end
 
"__tramp_start__:\n"
"1: l.sfeq r3, r4\n"
" l.bf 2f\n"
177,10 → 187,17
" l.lwz r13,0x00(r3)\n"
" l.sw 0x00(r5), r13\n"
" l.addi r3, r3, 4\n"
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
" l.j 1b\n"
" l.addi r5, r5, 4\n"
#else
" l.addi r5, r5, 4\n"
" l.j 1b\n"
#endif
"2: l.jr r6\n"
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
" l.nop\n"
#endif
"__tramp_end__:\n"
: /* no output registers */
: /* no input registers */
/ecos-3.0/packages/hal/openrisc/arch/current/src/context.S
217,7 → 217,9
l.lwz sp, 1 * OR1K_GPRSIZE(sp)
 
l.jr lr
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # delay slot - must be nop
#endif
 
FUNC_END(hal_thread_load_context)
267,7 → 269,10
l.sw CYGARC_JMP_BUF_R30 * OR1K_GPRSIZE(r3), r30
l.movhi rv, 0
l.jr lr
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # delay slot
#endif
 
FUNC_END(hal_setjmp)
 
 
289,7 → 294,10
l.movhi rv, 0
l.or rv, rv, r4
l.jr lr
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # delay slot
#endif
 
FUNC_END(hal_longjmp)
 
/ecos-3.0/packages/hal/openrisc/arch/current/src/vectors.S
99,9 → 99,12
.p2align 8
.globl __exception_\name
__exception_\name:
l.movhi r0, 0
load32i r3,start
l.jr r3
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # delay slot
#endif
.endm
# Generic vector macro
190,11 → 193,14
# Arg 1: Vector #
load32i r5,hal_vsr_table+(\org>>6)
l.lwz r5,0(r5)
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.jr r5 # To the VSR, Batman
l.or r3,r0,sp # First arg to VSR is SP
#else
l.or r3,r0,sp # First arg to VSR is SP
l.jr r5 # To the VSR, Batman
#endif
 
# First arg to VSR is SP
l.or r3,r0,sp # Delay slot
.endm
#---------------------------------------------------------------------------
238,8 → 244,14
1: l.sw 0(r4),r3
l.addi r5,r5,-1
l.sfgtsi r5,0
 
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.bf 1b
l.addi r4,r4,4 # delay slot
l.addi r4,r4,4
#else
l.addi r4,r4,4
l.bf 1b
#endif
 
# Then fill in the interrupt handlers
load32i r4,hal_vsr_table
284,9 → 296,14
1:
l.mtspr r0,r13,SPR_ICBIR
l.sfne r13,r11
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.bf 1b
l.addi r13,r13,HAL_ICACHE_LINE_SIZE
#else
l.addi r13,r13,HAL_ICACHE_LINE_SIZE
l.bf 1b
#endif
 
/* Enable I-Cache */
l.mfspr r13,r0,SPR_SR
l.ori r13,r13,SPR_SR_ICE
309,8 → 326,13
1:
l.mtspr r0,r10,SPR_DCBIR
l.sfne r10,r11
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.bf 1b
l.addi r10,r10,HAL_DCACHE_LINE_SIZE
#else
l.addi r10,r10,HAL_DCACHE_LINE_SIZE
l.bf 1b
#endif
 
/* Enable DC */
l.mfspr r10,r0,SPR_SR
383,8 → 405,13
l.lwz r6,0(r3)
l.sw 0(r4),r6
l.addi r3,r3,4
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.j 1b
l.addi r4,r4,4 # delay slot
#else
l.addi r4,r4,4
l.j 1b
#endif
2:
 
# Copy .data section into RAM
396,8 → 423,13
l.lwz r6,0(r3)
l.sw 0(r4),r6
l.addi r3,r3,4
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.j 1b
l.addi r4,r4,4 # delay slot
#else
l.addi r4,r4,4
l.j 1b
#endif
2:
 
#endif
407,10 → 439,17
load32i r5,__bss_end
1: l.sfeq r4,r5
l.bf 2f
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop
#endif
l.sw 0(r4),r0
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.j 1b
l.addi r4,r4,4
#else
l.addi r4,r4,4
l.j 1b
#endif
2:
 
# Note: no SBSS section to clear with OpenRISC target
417,29 → 456,41
# Platform-specific initialization
l.jal hal_platform_init
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # delay slot
#endif
# call c++ constructors
l.jal cyg_hal_invoke_constructors
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # delay slot
#endif
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
l.jal initialize_stub
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # delay slot
#endif
#endif
 
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
.extern hal_ctrlc_isr_init
l.jal hal_ctrlc_isr_init
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # delay slot
#endif
#endif
l.jal cyg_start # call cyg_start()
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # delay slot
#endif
9:
l.j 9b # if we return, loop
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # delay slot
#endif
 
FUNC_END(start)
466,8 → 517,13
# directly to restore_state(), which will resume execution
# at the location of the exception.
l.movhi r9, hi(restore_state)
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.j cyg_hal_exception_handler
l.ori r9,r9,lo(restore_state) #Delay slot
#else
l.ori r9,r9,lo(restore_state)
l.j cyg_hal_exception_handler
#endif
 
# Control never reaches this point,
 
513,7 → 569,9
l.bf 1f # switch to interrupt stack
l.sfltu sp,r7 # if (sp < __interrupt_stack_top)
l.bf 2f # already on interrupt stack
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # delay slot
#endif
1: l.or sp,r7,r7 # Switch to interrupt stack
2: l.addi sp,sp,-8 # Make space to save old SP...
l.sw 0(sp),r6 # ...and save it on the stack
527,6 → 585,9
# arg2 = vector number
l.ori r5,r0,r0 # arg3 = 0
l.jal _cyg_instrument # call instrument function
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop
#endif
#endif
 
555,18 → 616,31
# Any pending external interrupts ?
l.sfnei r9,0
l.bf check_for_external_interrupts
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop
#endif
 
# Theoretically, the only way we could get here is if the tick timer
# interrupt fired, but we check to be sure that's what happened.
l.sfeqi r4,CYGNUM_HAL_VECTOR_TICK_TIMER
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.bf 3f
l.ori r3,r0,CYGNUM_HAL_INTERRUPT_RTC # delay slot
#else
l.ori r3,r0,CYGNUM_HAL_INTERRUPT_RTC
l.bf 3f
#endif
 
#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
l.jal hal_spurious_IRQ
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop
#endif
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
l.j ignore_spurious_interrupt
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop
#endif
# Identify the lowest numbered interrupt bit in the PIC's PSR,
# numbering the MSB as 31 and the LSB as 0
576,8 → 650,13
l.sfnei r11,0
l.bf 3f
l.srli r9,r9,1 # Shift right 1 bit
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.j 2b
l.addi r3,r3,1 # Delay slot
#else
l.addi r3,r3,1
l.j 2b
#endif
3:
 
# At this point, r3 contains the ISR number, from 0-32
594,7 → 673,9
# arg0 = ISR #
# arg1 = data arg associated with interrupt
l.jalr r11
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop
#endif
 
ignore_spurious_interrupt:
636,8 → 717,10
 
.extern interrupt_end
l.jal interrupt_end # call into C to finish off
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop
#endif
#endif
 
# Fall through to restore_state...
 
712,7 → 795,9
 
# All done, restore CPU state and continue
l.rfe
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # Delay slot
#endif
 
 
##-----------------------------------------------------------------------------
733,11 → 818,13
l.sw 4(sp), r4 # Save interrupt state
l.ori r4, r4, SPR_SR_IEE|SPR_SR_TEE
l.sw 8(sp),lr
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.jal cyg_interrupt_call_pending_DSRs
# Enable interrupts before calling DSRs
l.mtspr r0, r4, SPR_SR # Delay slot
 
l.mtspr r0, r4, SPR_SR # Enable interrupts before calling DSRs
#else
l.mtspr r0, r4, SPR_SR # Enable interrupts before calling DSRs
l.jal cyg_interrupt_call_pending_DSRs
#endif
l.lwz r4, 4(sp)
l.lwz lr, 8(sp)
l.lwz sp, 0(sp)
748,10 → 835,14
load32i r6, ~(SPR_SR_IEE|SPR_SR_TEE)
l.and r5, r5, r6
l.or r4, r4, r5
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.jr r9
l.mtspr r0, r4, SPR_SR # Delay slot
#else
l.mtspr r0, r4, SPR_SR
l.jr r9
#endif
 
FUNC_END(hal_interrupt_stack_call_pending_DSRs)
#endif
 
785,13 → 876,20
 
# Call function
l.jalr r3
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop
#endif
l.lwz sp, 8(sp) # Restore original SP
l.lwz lr, 4(sp)
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.jr lr # Return to caller
l.addi sp,sp, 8 # Delay slot
#else
l.addi sp,sp, 8
l.jr lr # Return to caller
#endif
 
FUNC_END(hal_program_new_stack)
 
#---------------------------------------------------------------------------

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