OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /openrisc/trunk
    from Rev 842 to Rev 843
    Reverse comparison

Rev 842 → Rev 843

/rtos/ecos-3.0/packages/devs/eth/opencores/ethmac/current/src/if_ethmac.c
54,6 → 54,7
#include <cyg/hal/drv_api.h>
#include <cyg/io/eth/netdev.h>
#include <cyg/io/eth/eth_drv.h>
#include <string.h>
 
// Settings exported from CDL
#include <pkgconf/devs_eth_opencores_ethmac.h>
/rtos/ecos-3.0/packages/hal/openrisc/arch/current/src/redboot_linux_exec.c
184,7 → 184,7
"__tramp_start__:\n"
"1: l.sfeq r3, r4\n"
" l.bf 2f\n"
" l.lwz r13,0x00(r3)\n"
" l.lwz r13,0x00(r3)\n" // Note that this might be a branch slot
" l.sw 0x00(r5), r13\n"
" l.addi r3, r3, 4\n"
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
/rtos/ecos-3.0/packages/hal/openrisc/arch/current/src/vectors.S
402,7 → 402,7
load32i r5,rom_vectors_end
1: l.sfeq r3,r5
l.bf 2f
l.lwz r6,0(r3)
l.lwz r6,0(r3) # Note that this might be a branch slot
l.sw 0(r4),r6
l.addi r3,r3,4
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
420,7 → 420,7
load32i r5,__ram_data_end
1: l.sfeq r4,r5
l.bf 2f
l.lwz r6,0(r3)
l.lwz r6,0(r3) # Note that this might be a branch slot
l.sw 0(r4),r6
l.addi r3,r3,4
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
567,7 → 567,8
load32i r8,__interrupt_stack_base # stack base (lowest addr)
l.sfltu sp,r8 # if (sp < __interrupt_stack_base)
l.bf 1f # switch to interrupt stack
l.sfltu sp,r7 # if (sp < __interrupt_stack_top)
l.sfltu sp,r7 # Note that this might be a branch slot
# if (sp < __interrupt_stack_top)
l.bf 2f # already on interrupt stack
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # delay slot
649,7 → 650,7
2: l.andi r11,r9,1 # Test low bit
l.sfnei r11,0
l.bf 3f
l.srli r9,r9,1 # Shift right 1 bit
l.srli r9,r9,1 # Shift right 1 bit, note that this might be a branch slot
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.j 2b
l.addi r3,r3,1 # Delay slot
795,9 → 796,7
 
# All done, restore CPU state and continue
l.rfe
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
l.nop # Delay slot
#endif
# l.rfe does not have a branch slot
 
 
##-----------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.