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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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Rev 1213 → Rev 1214

/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_1024x8.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
97,7 → 100,7
module or1200_spram_1024x8(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
113,11 → 116,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
136,12 → 137,15
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
153,15 → 157,25
`ifdef UNUSED
art_hssp_1024x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_1024x8_bist artisan_ssp(
`else
art_hssp_1024x8 artisan_ssp(
`endif
.clk(clk),
.cen(~ce),
.wen(~we),
.a(addr),
.d(di),
.oen(~oe),
.q(do)
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(do)
);
 
`else
224,11 → 238,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.7 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
112,7 → 115,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// SPRs
164,11 → 167,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
204,11 → 205,11
//
// RAM BIST
//
wire scanb_ram_so;
wire scanb_tag_so;
wire scanb_ram_si = scanb_si;
wire scanb_tag_si = scanb_ram_so;
assign scanb_so = scanb_tag_so;
wire mbist_ram_so;
wire mbist_tag_so;
wire mbist_ram_si = mbist_si_i;
wire mbist_tag_si = mbist_ram_so;
assign mbist_so_o = mbist_tag_so;
`endif
 
//
300,11 → 301,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram_si),
.scanb_so(scanb_ram_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_ram_si),
.mbist_so_o(mbist_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(ic_addr[`OR1200_ICINDXH:2]),
.en(ic_en),
321,11 → 320,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_tag_si),
.scanb_so(scanb_tag_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_tag_si),
.mbist_so_o(mbist_tag_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(ictag_addr),
.en(ictag_en),
/branches/branch_qmem/or1200/rtl/verilog/or1200_dc_tag.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
75,7 → 78,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// Internal i/f
101,11 → 104,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
`ifdef OR1200_NO_DC
116,7 → 117,7
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
 
`else
132,11 → 133,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
/branches/branch_qmem/or1200/rtl/verilog/or1200_qmem_top.v
47,7 → 47,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.2.1 2003/07/08 15:45:26 lampret
// Added embedded memory QMEM.
//
//
 
// synopsys translate_off
`include "timescale.v"
68,7 → 71,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// QMEM and CPU/IMMU
132,11 → 135,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
370,11 → 371,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(qmem_addr[12:2]),
.ce(qmem_en),
/branches/branch_qmem/or1200/rtl/verilog/or1200_dc_ram.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
76,7 → 79,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// Internal i/f
101,11 → 104,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
`ifdef OR1200_NO_DC
115,7 → 116,7
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
 
`else
124,15 → 125,15
//
// RAM BIST
//
wire scanb_ram0_so;
wire scanb_ram1_so;
wire scanb_ram2_so;
wire scanb_ram3_so;
wire scanb_ram0_si = scanb_si;
wire scanb_ram1_si = scanb_ram0_so;
wire scanb_ram2_si = scanb_ram1_so;
wire scanb_ram3_si = scanb_ram2_so;
assign scanb_so = scanb_ram3_so;
wire mbist_ram0_so;
wire mbist_ram1_so;
wire mbist_ram2_so;
wire mbist_ram3_so;
wire mbist_ram0_si = mbist_si_i;
wire mbist_ram1_si = mbist_ram0_so;
wire mbist_ram2_si = mbist_ram1_so;
wire mbist_ram3_si = mbist_ram2_so;
assign mbist_so_o = mbist_ram3_so;
`endif
 
//
146,11 → 147,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram0_si),
.scanb_so(scanb_ram0_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_ram0_si),
.mbist_so_o(mbist_ram0_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
173,11 → 172,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram1_si),
.scanb_so(scanb_ram1_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_ram1_si),
.mbist_so_o(mbist_ram1_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
200,11 → 197,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram2_si),
.scanb_so(scanb_ram2_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_ram2_si),
.mbist_so_o(mbist_ram2_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
227,11 → 222,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram3_si),
.scanb_so(scanb_ram3_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_ram3_si),
.mbist_so_o(mbist_ram3_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_1024x32.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
100,7 → 103,7
module or1200_spram_1024x32(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
116,11 → 119,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
139,12 → 140,15
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
154,17 → 158,27
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hdsp_1024x32 #(dw, 1<<aw, aw) artisan_ssp(
art_hssp_1024x32 #(dw, 1<<aw, aw) artisan_ssp(
`else
art_hdsp_1024x32 artisan_ssp(
`ifdef OR1200_BIST
art_hssp_1024x32_bist artisan_ssp(
`else
art_hssp_1024x32 artisan_ssp(
`endif
.clk(clk),
.cen(~ce),
.wen(~we),
.a(addr),
.d(di),
.oen(~oe),
.q(do)
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(do)
);
 
`else
227,11 → 241,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
388,7 → 400,7
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=OFF";
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
/branches/branch_qmem/or1200/rtl/verilog/or1200_cpu.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.11 2002/08/28 01:44:25 lampret
// Removed some commented RTL. Fixed SR/ESR flag bug.
//
406,6 → 409,7
.spr_pc_we(pc_we),
.genpc_refetch(genpc_refetch),
.genpc_freeze(genpc_freeze),
.genpc_stop_prefetch(1'b0),
.no_more_dslot(no_more_dslot)
);
 
/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_64x22.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
97,7 → 100,7
module or1200_spram_64x22(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
113,11 → 116,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
137,12 → 138,15
//
wire [9:0] unconnected;
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
154,15 → 158,25
`ifdef UNUSED
art_hssp_64x22 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x22_bist artisan_ssp(
`else
art_hssp_64x22 artisan_ssp(
`endif
.clk(clk),
.cen(~ce),
.wen(~we),
.a(addr),
.d(di),
.oen(~oe),
.q(do)
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(do)
);
 
`else
225,11 → 239,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/branches/branch_qmem/or1200/rtl/verilog/or1200_immu_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.12 2003/06/06 02:54:47 lampret
// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
//
122,7 → 125,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// QMEM i/f
168,11 → 171,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
264,7 → 265,7
assign icpu_err_o = qmemimmu_err_i;
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`else
 
397,11 → 398,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// SPR access
/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_64x24.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
100,7 → 103,7
module or1200_spram_64x24(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
116,11 → 119,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
140,12 → 141,15
//
wire [7:0] unconnected;
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
157,15 → 161,25
`ifdef UNUSED
art_hssp_64x24 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x24_bist artisan_ssp(
`else
art_hssp_64x24 artisan_ssp(
`endif
.clk(clk),
.cen(~ce),
.wen(~we),
.a(addr),
.d(di),
.oen(~oe),
.q(do)
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(do)
);
 
`else
228,11 → 242,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_2048x32.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.3 2002/10/28 15:03:50 mohor
// Signal scanb_sen renamed to scanb_en.
//
100,7 → 103,7
module or1200_spram_2048x32(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
116,11 → 119,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
139,12 → 140,15
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
156,15 → 160,25
`ifdef UNUSED
art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp(
`else
art_hdsp_2048x32 artisan_ssp(
`ifdef OR1200_BIST
art_hssp_2048x32_bist artisan_ssp(
`else
art_hssp_2048x32 artisan_ssp(
`endif
.clk(clk),
.cen(~ce),
.wen(~we),
.a(addr),
.d(di),
.oen(~oe),
.q(do)
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(do)
);
 
`else
227,11 → 241,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/branches/branch_qmem/or1200/rtl/verilog/or1200_immu_tlb.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/10/28 16:34:32 mohor
// RAMs wrong connected to the BIST scan chain.
//
// Revision 1.5 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
88,7 → 91,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// SPR access
123,11 → 126,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
240,9 → 241,9
 
 
`ifdef OR1200_BIST
assign itlb_mr_ram_si = scanb_si;
assign itlb_mr_ram_si = mbist_si_i;
assign itlb_tr_ram_si = itlb_mr_ram_so;
assign scanb_so = itlb_tr_ram_so;
assign mbist_so_o = itlb_tr_ram_so;
`endif
 
 
254,11 → 255,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(itlb_mr_ram_si),
.scanb_so(itlb_mr_ram_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(itlb_mr_ram_si),
.mbist_so_o(itlb_mr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
276,11 → 275,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(itlb_tr_ram_si),
.scanb_so(itlb_tr_ram_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(itlb_tr_ram_si),
.mbist_so_o(itlb_tr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
/branches/branch_qmem/or1200/rtl/verilog/or1200_dc_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.6 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
109,7 → 112,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// SPRs
163,11 → 166,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
204,11 → 205,11
//
// RAM BIST
//
wire scanb_ram_so;
wire scanb_tag_so;
wire scanb_ram_si = scanb_si;
wire scanb_tag_si = scanb_ram_so;
assign scanb_so = scanb_tag_so;
wire mbist_ram_so;
wire mbist_tag_so;
wire mbist_ram_si = mbist_si_i;
wire mbist_tag_si = mbist_ram_so;
assign mbist_so_o = mbist_tag_so;
`endif
 
//
304,11 → 305,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram_si),
.scanb_so(scanb_ram_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_ram_si),
.mbist_so_o(mbist_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(dc_addr[`OR1200_DCINDXH:2]),
.en(dc_en),
325,11 → 324,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_tag_si),
.scanb_so(scanb_tag_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_tag_si),
.mbist_so_o(mbist_tag_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(dctag_addr),
.en(dctag_en),
/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_256x21.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
106,7 → 109,7
module or1200_spram_256x21(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
122,11 → 125,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
146,12 → 147,15
//
wire [10:0] unconnected;
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
163,15 → 167,25
`ifdef UNUSED
art_hssp_256x21 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_256x21_bist artisan_ssp(
`else
art_hssp_256x21 artisan_ssp(
`endif
.clk(clk),
.cen(~ce),
.wen(~we),
.a(addr),
.d(di),
.oen(~oe),
.q(do)
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(do)
);
 
`else
234,11 → 248,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
317,7 → 329,7
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=OFF";
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_2048x8.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
97,7 → 100,7
module or1200_spram_2048x8(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
113,11 → 116,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
136,12 → 137,15
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
153,15 → 157,25
`ifdef UNUSED
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x8_bist artisan_ssp(
`else
art_hssp_2048x8 artisan_ssp(
`endif
.clk(clk),
.cen(~ce),
.wen(~we),
.a(addr),
.d(di),
.oen(~oe),
.q(do)
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(do)
);
 
`else
224,11 → 238,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/branches/branch_qmem/or1200/rtl/verilog/or1200_dmmu_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.7 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
107,7 → 110,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// DC i/f
152,11 → 155,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
214,7 → 215,7
assign dcpu_err_o = qmemdmmu_err_i;
assign qmemdmmu_ci_o = `OR1200_DMMU_CI;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
 
`else
327,11 → 328,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// SPR access
/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_tag.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/10/24 22:19:04 mohor
// Signal scanb_eni renamed to scanb_en
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
78,7 → 81,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// Internal i/f
102,11 → 105,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
127,7 → 128,7
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
 
`else
143,11 → 144,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_64x14.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
97,7 → 100,7
module or1200_spram_64x14(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
113,11 → 116,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
137,12 → 138,15
//
wire [1:0] unconnected;
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
154,15 → 158,25
`ifdef UNUSED
art_hssp_64x14 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x14_bist artisan_ssp(
`else
art_hssp_64x14 artisan_ssp(
`endif
.clk(clk),
.cen(~ce),
.wen(~we),
.a(addr),
.d(di),
.oen(~oe),
.q(do)
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(do)
);
 
`else
225,11 → 239,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_ram.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
78,7 → 81,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// Internal i/f
103,11 → 106,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
`ifdef OR1200_NO_IC
117,7 → 118,7
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
 
`else
133,11 → 134,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
/branches/branch_qmem/or1200/rtl/verilog/or1200_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10.4.3 2003/12/05 00:08:44 lampret
// Fixed instantiation name.
//
// Revision 1.10.4.2 2003/07/11 01:10:35 lampret
// Added three missing wire declarations. No functional changes.
//
146,7 → 149,7
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Power Management
pm_cpustall_i,
235,11 → 238,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
444,18 → 445,22
//
// RAM BIST
//
wire scanb_immu_so;
wire scanb_ic_so;
wire scanb_dmmu_so;
wire scanb_dc_so;
wire scanb_immu_si = scanb_si;
wire scanb_ic_si = scanb_immu_so;
wire scanb_qmem_si = scanb_ic_so;
wire scanb_dmmu_si = scanb_qmem_so;
wire scanb_dc_si = scanb_dmmu_so;
assign scanb_so = scanb_dc_so;
wire mbist_immu_so;
wire mbist_ic_so;
wire mbist_dmmu_so;
wire mbist_dc_so;
wire mbist_qmem_so;
wire mbist_immu_si = mbist_si_i;
wire mbist_ic_si = mbist_immu_so;
wire mbist_qmem_si = mbist_ic_so;
wire mbist_dmmu_si = mbist_qmem_so;
wire mbist_dc_si = mbist_dmmu_so;
assign mbist_so_o = mbist_dc_so;
`endif
 
wire [3:0] icqmem_sel_qmem;
wire [3:0] icqmem_tag_qmem;
wire [3:0] dcqmem_tag_qmem;
 
//
// Instantiation of Instruction WISHBONE BIU
553,11 → 558,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_immu_si),
.scanb_so(scanb_immu_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_immu_si),
.mbist_so_o(mbist_immu_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// CPU and IMMU
596,11 → 599,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ic_si),
.scanb_so(scanb_ic_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_ic_si),
.mbist_so_o(mbist_ic_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// IC and QMEM
718,11 → 719,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_dmmu_si),
.scanb_so(scanb_dmmu_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_dmmu_si),
.mbist_so_o(mbist_dmmu_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// CPU i/f
759,11 → 758,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_dc_si),
.scanb_so(scanb_dc_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_dc_si),
.mbist_so_o(mbist_dc_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// DC and QMEM
808,11 → 805,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_qmem_si),
.scanb_so(scanb_qmem_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_qmem_si),
.mbist_so_o(mbist_qmem_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// QMEM and CPU/IMMU
/branches/branch_qmem/or1200/rtl/verilog/or1200_dmmu_tlb.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
82,7 → 85,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// SPR access
119,11 → 122,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
153,11 → 154,11
//
// RAM BIST
//
wire scanb_mr_so;
wire scanb_tr_so;
wire scanb_mr_si = scanb_si;
wire scanb_tr_si = scanb_mr_so;
assign scanb_so = scanb_tr_so;
wire mbist_mr_so;
wire mbist_tr_so;
wire mbist_mr_si = mbist_si_i;
wire mbist_tr_si = mbist_mr_so;
assign mbist_so_o = mbist_tr_so;
`endif
 
//
246,11 → 247,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_mr_si),
.scanb_so(scanb_mr_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_mr_si),
.mbist_so_o(mbist_mr_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
268,11 → 267,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_tr_si),
.scanb_so(scanb_tr_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_tr_si),
.mbist_so_o(mbist_tr_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_512x20.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
103,7 → 106,7
module or1200_spram_512x20(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
119,11 → 122,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
143,12 → 144,15
//
wire [3:0] unconnected;
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
160,15 → 164,25
`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_512x20_bist artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
.clk(clk),
.cen(~ce),
.wen(~we),
.a(addr),
.d(di),
.oen(~oe),
.q(do)
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(do)
);
 
`else
231,11 → 245,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),

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