URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 1246 to Rev 1247
- ↔ Reverse comparison
Rev 1246 → Rev 1247
/trunk/jtag/jp2.c
527,7 → 527,7
#define SDRAM_BASE_ADD 0x00000000 |
#define SDRAM_TMS_VAL 0x07248230 |
|
dbg_cpu_write_reg(4, 0x00000001); |
dbg_cpu_write_reg(0, 0x01); |
|
dbg_wb_write32(MC_BASE_ADD + MC_CSC(0),(((FLASH_BASE_ADD & 0xffff0000) >> 5) | 0x25)); |
dbg_wb_write32(MC_BASE_ADD + MC_TMS(0), FLASH_TMS_VAL); |
545,7 → 545,7
|
#define RAM_BASE 0x00000000 |
/* Stall risc */ |
dbg_cpu_write_reg(4, 0x00000001); |
dbg_cpu_write_reg(0, 0x01); |
|
dbg_wb_write32(RAM_BASE+0x00, 0x9c200000); /* l.addi r1,r0,0x0*/ |
dbg_wb_write32(RAM_BASE+0x04, 0x18400000+(RAM_BASE >> 16)); /* l.movhi r2,0x4000*/ |
563,7 → 563,7
dbg_cpu_write32((6 << 11) + 20, 0x2000); /* Trap causes stall */ |
dbg_cpu_write32((0 << 11) + 16, RAM_BASE); /* Set PC */ |
dbg_cpu_write32((6 << 11) + 16, 1 << 22); /* Set step bit */ |
for(i = 0; i < 10; i++) dbg_cpu_write_reg(4, 0x00000000); /* 10x Unstall */ |
for(i = 0; i < 10; i++) dbg_cpu_write_reg(0, 0x00); /* 10x Unstall */ |
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */ |
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */ |
dbg_cpu_read32(0x401, &r1); /* Read R1 */ |
574,7 → 574,7
dbg_cpu_write32((6 << 11) + 16, 0); /* Reset step bit */ |
dbg_wb_read32(RAM_BASE + 0x24, &insn); /* Set trap insn in delay slot */ |
dbg_wb_write32(RAM_BASE + 0x24, 0x21000001); |
dbg_cpu_write_reg(4, 0x00000000); /* Unstall */ |
dbg_cpu_write_reg(0, 0x00); /* Unstall */ |
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */ |
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */ |
dbg_cpu_read32(0x401, &r1); /* Read R1 */ |
586,7 → 586,7
dbg_wb_read32(RAM_BASE + 0x20, &insn); /* Set trap insn in place of branch insn */ |
dbg_wb_write32(RAM_BASE + 0x20, 0x21000001); |
dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x0c); /* Set PC */ |
dbg_cpu_write_reg(4, 0x00000000); /* Unstall */ |
dbg_cpu_write_reg(0, 0x00); /* Unstall */ |
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */ |
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */ |
dbg_cpu_read32(0x401, &r1); /* Read R1 */ |
598,7 → 598,7
dbg_wb_read32(RAM_BASE + 0x1c, &insn); /* Set trap insn before branch insn */ |
dbg_wb_write32(RAM_BASE + 0x1c, 0x21000001); |
dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x20); /* Set PC */ |
dbg_cpu_write_reg(4, 0x00000000); /* Unstall */ |
dbg_cpu_write_reg(0, 0x00); /* Unstall */ |
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */ |
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */ |
dbg_cpu_read32(0x401, &r1); /* Read R1 */ |
611,7 → 611,7
dbg_wb_read32(RAM_BASE + 0x18, &insn); /* Set trap insn behind lsu insn */ |
dbg_wb_write32(RAM_BASE + 0x18, 0x21000001); |
dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x1c); /* Set PC */ |
dbg_cpu_write_reg(4, 0x00000000); /* Unstall */ |
dbg_cpu_write_reg(0, 0x00); /* Unstall */ |
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */ |
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */ |
dbg_cpu_read32(0x401, &r1); /* Read R1 */ |
623,7 → 623,7
dbg_wb_read32(RAM_BASE + 0x1c, &insn); /* Set trap insn very near previous one */ |
dbg_wb_write32(RAM_BASE + 0x1c, 0x21000001); |
dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x18); /* Set PC */ |
dbg_cpu_write_reg(4, 0x00000000); /* Unstall */ |
dbg_cpu_write_reg(0, 0x00); /* Unstall */ |
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */ |
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */ |
dbg_cpu_read32(0x401, &r1); /* Read R1 */ |
635,7 → 635,7
dbg_wb_read32(RAM_BASE + 0x0c, &insn); /* Set trap insn to the start */ |
dbg_wb_write32(RAM_BASE + 0x0c, 0x21000001); |
dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x1c) /* Set PC */; |
dbg_cpu_write_reg(4, 0x00000000); /* Unstall */ |
dbg_cpu_write_reg(0, 0x00); /* Unstall */ |
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */ |
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */ |
dbg_cpu_read32(0x401, &r1); /* Read R1 */ |
645,7 → 645,7
result = npc + ppc + r1 + result; |
|
dbg_cpu_write32((6 << 11) + 16, 1 << 22); /* Set step bit */ |
for(i = 0; i < 5; i++) dbg_cpu_write_reg(4, 0x00000000); /* Unstall */ |
for(i = 0; i < 5; i++) dbg_cpu_write_reg(0, 0x00); /* Unstall */ |
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */ |
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */ |
dbg_cpu_read32(0x401, &r1); /* Read R1 */ |
654,7 → 654,7
result = npc + ppc + r1 + result; |
|
dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x20); /* Set PC */ |
for(i = 0; i < 2; i++) dbg_cpu_write_reg(4, 0x00000000); /* Unstall */ |
for(i = 0; i < 2; i++) dbg_cpu_write_reg(0, 0x00); /* Unstall */ |
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */ |
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */ |
dbg_cpu_read32(0x401, &r1); /* Read R1 */ |