OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

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Rev 1750 → Rev 1751

/trunk/or1ksim/configure
1,7 → 1,7
#! /bin/sh
# From configure.ac Id: configure.ac,v 1.1 2008/10/12 17:27:52 jeremybennett Exp using automake version AC_ACVERSION.
# From configure.ac Id: configure.ac 239 2008-11-08 17:09:03Z jeremy using automake version AC_ACVERSION.
# Guess values for system-dependent variables and create Makefiles.
# Generated by GNU Autoconf 2.61 for or1ksim 0.3.0rc1.
# Generated by GNU Autoconf 2.61 for or1ksim 0.3.0rc2.
#
# Report bugs to <openrisc@opencores.org>.
#
729,8 → 729,8
# Identity of this package.
PACKAGE_NAME='or1ksim'
PACKAGE_TARNAME='or1ksim'
PACKAGE_VERSION='0.3.0rc1'
PACKAGE_STRING='or1ksim 0.3.0rc1'
PACKAGE_VERSION='0.3.0rc2'
PACKAGE_STRING='or1ksim 0.3.0rc2'
PACKAGE_BUGREPORT='openrisc@opencores.org'
 
ac_unique_file="cpu/or32/execute.c"
1418,7 → 1418,7
# Omit some internal or obsolete options to make the list less imposing.
# This message is too long to be a string in the A/UX 3.1 sh.
cat <<_ACEOF
\`configure' configures or1ksim 0.3.0rc1 to adapt to many kinds of systems.
\`configure' configures or1ksim 0.3.0rc2 to adapt to many kinds of systems.
 
Usage: $0 [OPTION]... [VAR=VALUE]...
 
1489,7 → 1489,7
 
if test -n "$ac_init_help"; then
case $ac_init_help in
short | recursive ) echo "Configuration of or1ksim 0.3.0rc1:";;
short | recursive ) echo "Configuration of or1ksim 0.3.0rc2:";;
esac
cat <<\_ACEOF
 
1598,7 → 1598,7
test -n "$ac_init_help" && exit $ac_status
if $ac_init_version; then
cat <<\_ACEOF
or1ksim configure 0.3.0rc1
or1ksim configure 0.3.0rc2
generated by GNU Autoconf 2.61
 
Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
1612,7 → 1612,7
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
 
It was created by or1ksim $as_me 0.3.0rc1, which was
It was created by or1ksim $as_me 0.3.0rc2, which was
generated by GNU Autoconf 2.61. Invocation command line was
 
$ $0 $@
19044,7 → 19044,7
 
# Define the identity of the package.
PACKAGE='or1ksim'
VERSION='0.3.0rc1'
VERSION='0.3.0rc2'
 
 
cat >>confdefs.h <<_ACEOF
19414,7 → 19414,7
# make sure we are using a recent autoconf version
 
 
# yuck
# yuck.
case "$target_cpu" in
or32*) CPU_ARCH=or32;
ARCH_ISA=OR32;
19436,8 → 19436,23
;;
esac
 
# determine endianism from target CPU name. If it has "little" in the name,
# then its litte endian, otherwise its big endian (default for OR1K)
case "$target_cpu" in
*little*)
cat >>confdefs.h <<\_ACEOF
#define OR32_LITTLE_ENDIAN 1
_ACEOF
;;
*)
cat >>confdefs.h <<\_ACEOF
#define OR32_BIG_ENDIAN 1
_ACEOF
;;
esac
 
 
 
# We want these before the checks, so the checks can modify their values.
test -z "$CFLAGS" && CFLAGS="-g -Wall" auto_cflags=1
 
21532,6 → 21547,74
 
done
 
{ echo "$as_me:$LINENO: checking whether I_PUSH is declared" >&5
echo $ECHO_N "checking whether I_PUSH is declared... $ECHO_C" >&6; }
if test "${ac_cv_have_decl_I_PUSH+set}" = set; then
echo $ECHO_N "(cached) $ECHO_C" >&6
else
cat >conftest.$ac_ext <<_ACEOF
/* confdefs.h. */
_ACEOF
cat confdefs.h >>conftest.$ac_ext
cat >>conftest.$ac_ext <<_ACEOF
/* end confdefs.h. */
$ac_includes_default
int
main ()
{
#ifndef I_PUSH
(void) I_PUSH;
#endif
 
;
return 0;
}
_ACEOF
rm -f conftest.$ac_objext
if { (ac_try="$ac_compile"
case "(($ac_try" in
*\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
*) ac_try_echo=$ac_try;;
esac
eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
(eval "$ac_compile") 2>conftest.er1
ac_status=$?
grep -v '^ *+' conftest.er1 >conftest.err
rm -f conftest.er1
cat conftest.err >&5
echo "$as_me:$LINENO: \$? = $ac_status" >&5
(exit $ac_status); } && {
test -z "$ac_c_werror_flag" ||
test ! -s conftest.err
} && test -s conftest.$ac_objext; then
ac_cv_have_decl_I_PUSH=yes
else
echo "$as_me: failed program was:" >&5
sed 's/^/| /' conftest.$ac_ext >&5
 
ac_cv_have_decl_I_PUSH=no
fi
 
rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
fi
{ echo "$as_me:$LINENO: result: $ac_cv_have_decl_I_PUSH" >&5
echo "${ECHO_T}$ac_cv_have_decl_I_PUSH" >&6; }
if test $ac_cv_have_decl_I_PUSH = yes; then
 
cat >>confdefs.h <<_ACEOF
#define HAVE_DECL_I_PUSH 1
_ACEOF
 
 
else
cat >>confdefs.h <<_ACEOF
#define HAVE_DECL_I_PUSH 0
_ACEOF
 
 
fi
 
 
{ echo "$as_me:$LINENO: checking whether byte ordering is bigendian" >&5
echo $ECHO_N "checking whether byte ordering is bigendian... $ECHO_C" >&6; }
if test "${ac_cv_c_bigendian+set}" = set; then
25075,6 → 25158,70
 
 
 
#Check for compare function type for qsort (needed by some Linuxes)
{ echo "$as_me:$LINENO: checking for __compar_fn_t" >&5
echo $ECHO_N "checking for __compar_fn_t... $ECHO_C" >&6; }
if test "${ac_cv_type___compar_fn_t+set}" = set; then
echo $ECHO_N "(cached) $ECHO_C" >&6
else
cat >conftest.$ac_ext <<_ACEOF
/* confdefs.h. */
_ACEOF
cat confdefs.h >>conftest.$ac_ext
cat >>conftest.$ac_ext <<_ACEOF
/* end confdefs.h. */
$ac_includes_default
typedef __compar_fn_t ac__type_new_;
int
main ()
{
if ((ac__type_new_ *) 0)
return 0;
if (sizeof (ac__type_new_))
return 0;
;
return 0;
}
_ACEOF
rm -f conftest.$ac_objext
if { (ac_try="$ac_compile"
case "(($ac_try" in
*\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
*) ac_try_echo=$ac_try;;
esac
eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
(eval "$ac_compile") 2>conftest.er1
ac_status=$?
grep -v '^ *+' conftest.er1 >conftest.err
rm -f conftest.er1
cat conftest.err >&5
echo "$as_me:$LINENO: \$? = $ac_status" >&5
(exit $ac_status); } && {
test -z "$ac_c_werror_flag" ||
test ! -s conftest.err
} && test -s conftest.$ac_objext; then
ac_cv_type___compar_fn_t=yes
else
echo "$as_me: failed program was:" >&5
sed 's/^/| /' conftest.$ac_ext >&5
 
ac_cv_type___compar_fn_t=no
fi
 
rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
fi
{ echo "$as_me:$LINENO: result: $ac_cv_type___compar_fn_t" >&5
echo "${ECHO_T}$ac_cv_type___compar_fn_t" >&6; }
if test $ac_cv_type___compar_fn_t = yes; then
 
cat >>confdefs.h <<_ACEOF
#define HAVE___COMPAR_FN_T 1
_ACEOF
 
 
fi
 
 
# check for GNU readline
 
{ echo "$as_me:$LINENO: checking for add_history in -lreadline" >&5
25173,7 → 25320,7
if test "${enable_profiling+set}" = set; then
enableval=$enable_profiling;
case "$enableval" in
yes) profile="-pg -a" ;;
yes) profile="-pg" ;;
esac
 
fi
25263,8 → 25410,8
if test "${enable_ov_flag+set}" = set; then
enableval=$enable_ov_flag;
case "$enableval" in
no) set_ov_flag="0" ;;
yes) set_ov_flag="1" ;;
no) set_ov_flag="0" ;;
yes) set_ov_flag="1" ;;
esac
 
fi
25293,8 → 25440,8
if test "${enable_debug+set}" = set; then
enableval=$enable_debug;
case $enableval in
yes) echo "enabling debugging symbols" & DEBUGFLAGS="-g -UNDEBUG";;
no) echo "disabling debugging symbols" & DEBUGFLAGS="-DNDEBUG";;
yes) echo "enabling argtable2 debugging symbols" & DEBUGFLAGS="-g -UNDEBUG";;
no) echo "disabling argtable2 debugging symbols" & DEBUGFLAGS="-DNDEBUG";;
*) echo "illegal argument to --enable-debug" & exit 1;;
esac
 
25861,7 → 26008,7
# report actual input values of CONFIG_FILES etc. instead of their
# values after options handling.
ac_log="
This file was extended by or1ksim $as_me 0.3.0rc1, which was
This file was extended by or1ksim $as_me 0.3.0rc2, which was
generated by GNU Autoconf 2.61. Invocation command line was
 
CONFIG_FILES = $CONFIG_FILES
25914,7 → 26061,7
_ACEOF
cat >>$CONFIG_STATUS <<_ACEOF
ac_cs_version="\\
or1ksim config.status 0.3.0rc1
or1ksim config.status 0.3.0rc2
configured by $0, generated by GNU Autoconf 2.61,
with options \\"`echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\"
 
/trunk/or1ksim/sim-config.h
48,8 → 48,6
 
#define PRINTF(x...) fprintf (runtime.sim.fout, x)
 
#define CONFIG_ERROR(s) {fprintf (stderr, "ERROR: config.%s:%s\n", cur_section->name, s); if (runtime.sim.init) exit (1);}
 
/*! Data structure for configuration data */
struct config
{
149,8 → 147,10
struct
{
int enabled; /* Is debug module enabled */
int gdb_enabled; /* Is debugging with gdb possible */
int server_port; /* A user specified port for services */
int gdb_enabled; /* Is legacy debugging with GDB possible */
int rsp_enabled; /* Is RSP debugging with GDB possible */
int server_port; /* Port for legacy GDB connection */
int rsp_port; /* Port for RSP GDB connection */
unsigned long vapi_id; /* "Fake" vapi dev id for JTAG proxy */
} debug;
};
164,7 → 164,6
FILE *fmprof; /* Memory profiler file */
FILE *fexe_log; /* RTL state comparison file */
FILE *fout; /* file for standard output */
int init; /* Whether we are still initilizing sim */
char *filename; /* Original Command Simulator file (CZ) */
int iprompt; /* Interactive prompt */
int iprompt_run; /* Interactive prompt is running */
183,7 → 182,7
 
long long reset_cycles;
 
int hush; /* Is simulator to do reg dumps */
int hush; /* Is simulator to do reg dumps */
} sim;
 
struct
/trunk/or1ksim/port/port.h
31,7 → 31,7
#include <string.h>
#include <ctype.h>
 
#ifdef HAVE_INTTYPES_H
#if HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
/trunk/or1ksim/toplevel-support.c
50,9 → 50,11
#include "opcode/or32.h"
#include "parse.h"
#include "gdbcomm.h"
#include "rsp-server.h"
#include "vapi.h"
#include "abstract.h"
#include "mc.h"
#include "except.h"
 
 
/*! Struct for list of reset hooks */
285,19 → 287,32
}
}
 
/* Disable gdb debugging, if debug unit is not available. */
if (config.debug.gdb_enabled && !config.debug.enabled)
/* Disable GDB debugging, if debug unit is not available. */
if ((config.debug.gdb_enabled || config.debug.rsp_enabled) &&
!config.debug.enabled)
{
config.debug.gdb_enabled = 0;
config.debug.rsp_enabled = 0;
 
if (config.sim.verbose)
{
fprintf (stderr, "WARNING: sim_init: Debug module not enabled, "
"cannot start GDB\n");
"cannot start remote service to GDB\n");
}
}
 
if (config.debug.gdb_enabled)
/* Start either RSP or legacy GDB debugging service */
if (config.debug.rsp_enabled)
{
rsp_init ();
 
/* RSP always starts stalled as though we have just reset the
processor. */
rsp_exception (EXCEPT_TRAP);
set_stall_state (1);
}
else if (config.debug.gdb_enabled)
{
gdbcomm_init ();
}
 
351,10 → 366,6
}
PRINTF ("All devices connected\n");
}
 
/* simulator is initialized */
runtime.sim.init = 0;
 
} /* sim_init() */
 
 
/trunk/or1ksim/debug/Makefile.in
66,7 → 66,7
CONFIG_CLEAN_FILES =
LTLIBRARIES = $(noinst_LTLIBRARIES)
libdebug_la_LIBADD =
am_libdebug_la_OBJECTS = debug-unit.lo gdbcomm.lo
am_libdebug_la_OBJECTS = debug-unit.lo gdbcomm.lo rsp-server.lo
libdebug_la_OBJECTS = $(am_libdebug_la_OBJECTS)
DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
depcomp = $(SHELL) $(top_srcdir)/depcomp
210,9 → 210,11
noinst_LTLIBRARIES = libdebug.la
libdebug_la_SOURCES = debug-unit.c \
gdbcomm.c \
rsp-server.c \
debug-unit.h \
gdbcomm.h \
gdb.h
gdb.h \
rsp-server.h
 
all: all-am
 
267,6 → 269,7
 
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/debug-unit.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/gdbcomm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rsp-server.Plo@am__quote@
 
.c.o:
@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
/trunk/or1ksim/debug/debug-unit.c
57,12 → 57,10
#include "spr-defs.h"
#include "execute.h"
#include "sprs.h"
#include "debug.h"
#include "toplevel-support.h"
#include "rsp-server.h"
 
 
DECLARE_DEBUG_CHANNEL (jtag);
 
/*! The fields for the RISCOP register in the development interface scan chain
(JTAG_CHAIN_DEVELOPMENT). */
#define RISCOP_STALL 0x00000001 /*!< Stall processor */
667,15 → 665,10
{
int err = ERR_NONE;
 
TRACE_ (jtag) ("Debug get register %x\n", address);
 
switch (current_scan_chain)
{
case JTAG_CHAIN_DEBUG_UNIT:
*data = mfspr (address);
TRACE_ (jtag) ("READ spr: %s\n", dump_spr (address, *data));
/* printf ("=== R SPR 0x%04x = 0x%08x\n", address, *data); */
/* fflush (stdout); */
break;
 
case JTAG_CHAIN_TRACE:
684,14 → 677,10
 
case JTAG_CHAIN_DEVELOPMENT:
err = get_devint_reg (address, (unsigned long *)data);
/* printf ("=== R DEV 0x%1x = 0x%08x\n", address, *data); */
/* fflush (stdout); */
break;
 
case JTAG_CHAIN_WISHBONE:
err = debug_get_mem (address, data);
/* printf ("=== R WB 0x%08x = 0x%08x\n", address, *data); */
/* fflush (stdout); */
break;
 
default:
698,8 → 687,6
err = JTAG_PROXY_INVALID_CHAIN;
}
 
TRACE_ (jtag) ("!get reg %" PRIxREG "\n", *data);
 
return err;
 
} /* debug_get_register () */
721,16 → 708,10
{
int err = ERR_NONE;
 
TRACE_ (jtag) ("Debug set register %" PRIxADDR " <- %" PRIxREG "\n",
address, data);
 
switch (current_scan_chain)
{
case JTAG_CHAIN_DEBUG_UNIT:
TRACE_ (jtag) ("WRITE spr: %s\n", dump_spr (address, data));
mtspr (address, data);
/* printf ("=== W SPR 0x%04x = 0x%08x\n", address, data); */
/* fflush (stdout); */
break;
 
case JTAG_CHAIN_TRACE:
739,14 → 720,10
 
case JTAG_CHAIN_DEVELOPMENT:
err = set_devint_reg (address, data);
/* printf ("=== W DEV 0x%1x = 0x%08x\n", address, data); */
/* fflush (stdout); */
break;
 
case JTAG_CHAIN_WISHBONE:
err = debug_set_mem (address, data);
/* printf ("=== W WB 0x%08x = 0x%08x\n", address, data); */
/* fflush (stdout); */
break;
 
default:
753,8 → 730,6
err = JTAG_PROXY_INVALID_CHAIN;
}
 
TRACE_ (jtag) ("!set reg\n");
 
return err;
 
} /* debug_set_register () */
772,7 → 747,6
int
debug_set_chain (enum debug_scan_chain_ids chain)
{
TRACE_ (jtag) ("Debug set chain %x\n", chain);
switch (chain)
{
case JTAG_CHAIN_DEBUG_UNIT:
818,8 → 792,6
err = JTAG_PROXY_INVALID_ADDRESS;
}
 
TRACE_ (jtag) ("get_devint_reg %08x = %08lx\n", address, *data);
 
return err;
 
} /* get_devint_reg () */
866,8 → 838,6
err = JTAG_PROXY_INVALID_ADDRESS;
}
 
TRACE_ (jtag) ("set_devint_reg %08x = %08lx\n", address, data);
 
return err;
 
} /* set_devint_reg() */
896,8 → 866,6
*data = eval_direct32 (address, 0, 0);
}
 
TRACE_ (jtag) ("MEMREAD (%" PRIxADDR ") = %" PRIxADDR "\n", address,
*data);
return err;
 
} /* debug_get_mem () */
917,8 → 885,6
{
int err = ERR_NONE;
 
TRACE_ (jtag) ("MEMWRITE (%" PRIxADDR ") = %" PRIx32 "\n", address, data);
 
if (!verify_memoryarea (address))
{
err = JTAG_PROXY_INVALID_ADDRESS;
970,6 → 936,14
cpu_state.sprs[SPR_DRR] |= result;
set_stall_state (result != 0);
 
/* Notify RSP if enabled. TODO: Should we actually notify ALL exceptions,
not just those maked in the DSR? */
 
if (config.debug.rsp_enabled && (0 != result))
{
rsp_exception (except);
}
 
return (result != 0);
 
} /* debug_ignore_exception () */
983,7 → 957,7
@param[in] val The value to use
@param[in] dat The config data structure (not used here) */
/*---------------------------------------------------------------------------*/
void
static void
debug_enabled (union param_val val, void *dat)
{
if (val.int_val)
1001,36 → 975,71
 
 
/*---------------------------------------------------------------------------*/
/*!Enable or disable the GDB interface to the debug unit
/*!Enable or disable the legacy GDB interface to the debug unit
 
Set the corresponding field in the UPR
This is for use with the OpenRISC Remote JTAG protocol (now deprecated). It
may only be specified if the RSP interface is not specified. If both are
specified, the RSP will be used.
 
@param[in] val The value to use
@param[in] dat The config data structure (not used here) */
/*---------------------------------------------------------------------------*/
void
static void
debug_gdb_enabled (union param_val val, void *dat)
{
config.debug.gdb_enabled = val.int_val;
 
if (config.debug.gdb_enabled && config.debug.rsp_enabled)
{
fprintf (stderr, "WARNING. Cannot specify both legacy and RSP GDB "
"interfaces: legacy interface ignored\n");
config.debug.gdb_enabled = 0;
}
} /* debug_gdb_enabled () */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the GDB server port
/*!Enable or disable Remote Serial Protocol GDB interface to the debug unit
 
This is the preferred interface. It may only be specified if the RSP
interface is not specified. If both are specified, the RSP will be used.
 
@param[in] val The value to use
@param[in] dat The config data structure (not used here) */
/*---------------------------------------------------------------------------*/
static void
debug_rsp_enabled (union param_val val, void *dat)
{
config.debug.rsp_enabled = val.int_val;
 
if (config.debug.gdb_enabled && config.debug.rsp_enabled)
{
fprintf (stderr, "WARNING. Cannot specify both legacy and RSP GDB "
"interfaces: legacy interface ignored\n");
config.debug.gdb_enabled = 0;
}
} /* debug_rsp_enabled () */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the legacy GDB server port
 
This is for use with the OpenRISC Remote JTAG protocol (now deprecated).
Ensure the value chosen is valid. Note that 0 is permitted, meaning the
connection should be to the "or1ksim" service, rather than a port.
 
Both this and the RSP port may be specified, but only one may be enabled
(see debug_gdb_enabled() and debug_rsp_enabled()).
 
@param[in] val The value to use
@param[in] dat The config data structure (not used here) */
/*---------------------------------------------------------------------------*/
void
static void
debug_server_port (union param_val val, void *dat)
{
if ((val.int_val < 0) || (val.int_val > 65535))
{
fprintf (stderr, "Warning: invalid GDB port specified: ignored\n");
fprintf (stderr, "Warning: invalid legacy GDB port specified: ignored\n");
}
else
{
1040,12 → 1049,39
 
 
/*---------------------------------------------------------------------------*/
/*!Set the Remote Serial Protocol GDB server port
 
This is for use with the RSP, which is now the preferred interface. Ensure
the value chosen is valid. Note that 0 is permitted, meaning the connection
should be to the "or1ksim-rsp" service, rather than a port.
 
Both this and the legacy port may be specified, but only one may be enabled
(see debug_gdb_enabled() and debug_rsp_enabled()).
 
@param[in] val The value to use
@param[in] dat The config data structure (not used here) */
/*---------------------------------------------------------------------------*/
static void
debug_rsp_port (union param_val val, void *dat)
{
if ((val.int_val < 0) || (val.int_val > 65535))
{
fprintf (stderr, "Warning: invalid RSP GDB port specified: ignored\n");
}
else
{
config.debug.rsp_port = val.int_val;
}
} /* debug_rsp_port() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the VAPI ID for the debug unit
 
@param[in] val The value to use
@param[in] dat The config data structure (not used here) */
/*---------------------------------------------------------------------------*/
void
static void
debug_vapi_id (union param_val val, void *dat)
{
config.debug.vapi_id = val.int_val;
1063,7 → 1099,9
 
reg_config_param (sec, "enabled", paramt_int, debug_enabled);
reg_config_param (sec, "gdb_enabled", paramt_int, debug_gdb_enabled);
reg_config_param (sec, "rsp_enabled", paramt_int, debug_rsp_enabled);
reg_config_param (sec, "server_port", paramt_int, debug_server_port);
reg_config_param (sec, "rsp_port", paramt_int, debug_rsp_port);
reg_config_param (sec, "vapi_id", paramt_int, debug_vapi_id);
 
} /* reg_debug_sec () */
/trunk/or1ksim/debug/Makefile.am
22,8 → 22,11
 
 
noinst_LTLIBRARIES = libdebug.la
 
libdebug_la_SOURCES = debug-unit.c \
gdbcomm.c \
rsp-server.c \
debug-unit.h \
gdbcomm.h \
gdb.h
gdb.h \
rsp-server.h
/trunk/or1ksim/debug/gdbcomm.c
33,6 → 33,9
#include <unistd.h>
#include <stdio.h>
#include <sys/poll.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <netinet/in.h>
#include <fcntl.h>
#include <netdb.h>
#include <netinet/tcp.h>
111,7 → 114,8
}
 
/* The server should also be non blocking. Get the current flags. */
if (fcntl (sockfd, F_GETFL, &flags) < 0)
flags = fcntl (sockfd, F_GETFL, flags);
if (flags < 0)
{
sprintf (sTemp, "Unable to get flags for socket %d", sockfd);
perror (sTemp);
/trunk/or1ksim/debug/rsp-server.c
0,0 → 1,2562
/* rsp-server.c -- Remote Serial Protocol server for GDB
 
Copyright (C) 2008 Embecosm Limited
 
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
 
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
 
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>. */
 
/* This program is commented throughout in a fashion suitable for processing
with Doxygen. */
 
 
/* Autoconf and/or portability configuration */
#include "config.h"
#include "port.h"
 
/* System includes */
#include <stdlib.h>
#include <unistd.h>
#include <netdb.h>
#include <stdio.h>
#include <errno.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <fcntl.h>
#include <arpa/inet.h>
#include <poll.h>
#include <netinet/tcp.h>
 
/* Package includes */
#include "sim-config.h"
#include "except.h"
#include "opcode/or32.h"
#include "spr-defs.h"
#include "execute.h"
#include "debug-unit.h"
#include "sprs.h"
 
 
/* Do we log each packet */
#define RSP_TRACE 1
 
/*! Name of the Or1ksim RSP service */
#define OR1KSIM_RSP_SERVICE "or1ksim-rsp"
 
/*! Protocol used by Or1ksim */
#define OR1KSIM_RSP_PROTOCOL "tcp"
 
/* Indices of GDB registers that are not GPRs. Must match GDB settings! */
#define PPC_REGNUM (MAX_GPRS + 0) /*!< Previous PC */
#define NPC_REGNUM (MAX_GPRS + 1) /*!< Next PC */
#define SR_REGNUM (MAX_GPRS + 2) /*!< Supervision Register */
#define NUM_REGS (MAX_GRPS + 3) /*!< Total GDB registers */
 
/*! Trap instruction for OR32 */
#define OR1K_TRAP_INSTR 0x21000001
 
/*! Definition of GDB target signals. Data taken from the GDB 6.8
source. Only those we use defined here. */
enum target_signal {
TARGET_SIGNAL_NONE = 0,
TARGET_SIGNAL_INT = 2,
TARGET_SIGNAL_ILL = 4,
TARGET_SIGNAL_TRAP = 5,
TARGET_SIGNAL_FPE = 8,
TARGET_SIGNAL_BUS = 10,
TARGET_SIGNAL_SEGV = 11,
TARGET_SIGNAL_ALRM = 14,
TARGET_SIGNAL_USR2 = 31,
TARGET_SIGNAL_PWR = 32
};
 
/*! The maximum number of characters in inbound/outbound buffers. The largest
packets are the 'G' packet, which must hold the 'G' and all the registers
with two hex digits per byte and the 'g' reply, which must hold all the
registers, and (in our implementation) an end-of-string (0)
character. Adding the EOS allows us to print out the packet as a
string. So at least NUMREGBYTES*2 + 1 (for the 'G' or the EOS) are needed
for register packets */
#define GDB_BUF_MAX ((NUM_REGS) * 8 + 1)
 
/*! Size of the matchpoint hash table. Largest prime < 2^10 */
#define MP_HASH_SIZE 1021
 
/*! String to map hex digits to chars */
static const char hexchars[]="0123456789abcdef";
 
/*! Data structure for RSP buffers. Can't be null terminated, since it may
include zero bytes */
struct rsp_buf
{
char data[GDB_BUF_MAX];
int len;
};
 
/*! Enumeration of different types of matchpoint. These have explicit values
matching the second digit of 'z' and 'Z' packets. */
enum mp_type {
BP_MEMORY = 0,
BP_HARDWARE = 1,
WP_WRITE = 2,
WP_READ = 3,
WP_ACCESS = 4
};
 
/*! Data structure for a matchpoint hash table entry */
struct mp_entry
{
enum mp_type type; /*!< Type of matchpoint */
unsigned long int addr; /*!< Address with the matchpoint */
unsigned long int instr; /*!< Substituted instruction */
struct mp_entry *next; /*!< Next entry with this hash */
};
 
/*! Central data for the RSP connection */
static struct
{
int client_waiting; /*!< Is client waiting a response? */
int proto_num; /*!< Number of the protocol used */
int server_fd; /*!< FD for new connections */
int client_fd; /*!< FD for talking to GDB */
int sigval; /*!< GDB signal for any exception */
unsigned long int start_addr; /*!< Start of last run */
struct mp_entry *mp_hash[MP_HASH_SIZE]; /*!< Matchpoint hash table */
} rsp;
 
/* Forward declarations of static functions */
static void rsp_server_request ();
static void rsp_client_request ();
static void rsp_server_close ();
static void rsp_client_close ();
static void put_packet (struct rsp_buf *buf);
static void put_str_packet (const char *str);
static struct rsp_buf *get_packet ();
static void put_rsp_char (char c);
static int get_rsp_char ();
static int rsp_unescape (char *data,
int len);
static void mp_hash_init ();
static void mp_hash_add (enum mp_type type,
unsigned long int addr,
unsigned long int instr);
static struct mp_entry *mp_hash_lookup (enum mp_type type,
unsigned long int addr);
static struct mp_entry *mp_hash_delete (enum mp_type type,
unsigned long int addr);
static int hex (int c);
static void reg2hex (unsigned long int val,
char *buf);
static unsigned long int hex2reg (char *buf);
static void ascii2hex (char *dest,
char *src);
static void hex2ascii (char *dest,
char *src);
static void set_npc (unsigned long int addr);
static void rsp_report_exception ();
static void rsp_continue (struct rsp_buf *buf);
static void rsp_continue_with_signal (struct rsp_buf *buf);
static void rsp_continue_generic (unsigned long int addr,
unsigned long int except);
static void rsp_read_all_regs ();
static void rsp_write_all_regs (struct rsp_buf *buf);
static void rsp_read_mem (struct rsp_buf *buf);
static void rsp_write_mem (struct rsp_buf *buf);
static void rsp_read_reg (struct rsp_buf *buf);
static void rsp_write_reg (struct rsp_buf *buf);
static void rsp_query (struct rsp_buf *buf);
static void rsp_command (struct rsp_buf *buf);
static void rsp_set (struct rsp_buf *buf);
static void rsp_restart ();
static void rsp_step (struct rsp_buf *buf);
static void rsp_step_with_signal (struct rsp_buf *buf);
static void rsp_step_generic (unsigned long int addr,
unsigned long int except);
static void rsp_vpkt (struct rsp_buf *buf);
static void rsp_write_mem_bin (struct rsp_buf *buf);
static void rsp_remove_matchpoint (struct rsp_buf *buf);
static void rsp_insert_matchpoint (struct rsp_buf *buf);
 
 
/*---------------------------------------------------------------------------*/
/*!Initialize the Remote Serial Protocol connection
 
This involves setting up a socket to listen on a socket for attempted
connections from a single GDB instance (we couldn't be talking to multiple
GDBs at once!).
 
The service is specified either as a port number in the Or1ksim configuration
(parameter rsp_port in section debug, default 51000) or as a service name
in the constant OR1KSIM_RSP_SERVICE.
 
The protocol used for communication is specified in OR1KSIM_RSP_PROTOCOL. */
/*---------------------------------------------------------------------------*/
void
rsp_init ()
{
struct protoent *protocol; /* Protocol number */
struct hostent *host_entry; /* Our host entry */
struct sockaddr_in sock_addr; /* Socket address */
 
int optval; /* Socket options */
int flags; /* Socket flags */
char name[256]; /* Our name */
 
/* Clear out the central data structure */
rsp.client_waiting = 0; /* GDB client is not waiting for us */
rsp.proto_num = -1; /* i.e. invalid */
rsp.server_fd = -1; /* i.e. invalid */
rsp.client_fd = -1; /* i.e. invalid */
rsp.sigval = 0; /* No exception */
rsp.start_addr = EXCEPT_RESET; /* Default restart point */
 
/* Set up the matchpoint hash table */
mp_hash_init ();
 
/* Get the protocol number of TCP and save it for future use */
protocol = getprotobyname (OR1KSIM_RSP_PROTOCOL);
if (NULL == protocol)
{
fprintf (stderr, "Warning: RSP unable to load protocol \"%s\": %s\n",
OR1KSIM_RSP_PROTOCOL, strerror (errno));
return;
}
 
rsp.proto_num = protocol->p_proto; /* Saved for future client use */
 
/* 0 is used as the RSP port number to indicate that we should use the
service name instead. */
if (0 == config.debug.rsp_port)
{
struct servent *service =
getservbyname (OR1KSIM_RSP_SERVICE, protocol->p_name);
 
if (NULL == service)
{
fprintf (stderr, "Warning: RSP unable to find service \"%s\": %s\n",
OR1KSIM_RSP_SERVICE, strerror (errno));
return;
}
 
config.debug.rsp_port = ntohs (service->s_port);
}
 
/* Create the socket using the TCP protocol */
rsp.server_fd = socket (PF_INET, SOCK_STREAM, protocol->p_proto);
if (rsp.server_fd < 0)
{
fprintf (stderr, "Warning: RSP could not create server socket: %s\n",
strerror (errno));
return;
}
 
/* Set this socket to reuse its address. This allows the server to keep
trying before a GDB session has got going. */
optval = 1;
if (setsockopt(rsp.server_fd, SOL_SOCKET,
SO_REUSEADDR, &optval, sizeof (optval)) < 0)
{
fprintf (stderr, "Cannot set SO_REUSEADDR option on server socket %d: "
"%s\n", rsp.server_fd, strerror (errno));
rsp_server_close();
return;
}
 
/* The server should be non-blocking. Get the current flags and then set the
non-blocking flags */
flags = fcntl (rsp.server_fd, F_GETFL);
if (flags < 0)
{
fprintf (stderr, "Warning: Unable to get flags for RSP server socket "
"%d: %s\n", rsp.server_fd, strerror (errno));
rsp_server_close();
return;
}
 
flags |= O_NONBLOCK;
if (fcntl (rsp.server_fd, F_SETFL, flags) < 0)
{
fprintf (stderr, "Warning: Unable to set flags for RSP server socket "
"%d to 0x%08x: %s\n", rsp.server_fd, flags, strerror (errno));
rsp_server_close();
return;
}
 
/* Find out what our name is */
if (gethostname (name, sizeof (name)) < 0)
{
fprintf (stderr, "Warning: Unable to get hostname for RSP server: %s\n",
strerror (errno));
rsp_server_close();
return;
}
 
/* Find out what our address is */
host_entry = gethostbyname (name);
if (NULL == host_entry)
{
fprintf (stderr, "Warning: Unable to get host entry for RSP server: "
"%s\n", strerror (errno));
rsp_server_close();
return;
}
 
/* Bind our socket to the appropriate address */
memset (&sock_addr, 0, sizeof (sock_addr));
sock_addr.sin_family = host_entry->h_addrtype;
sock_addr.sin_port = htons (config.debug.rsp_port);
 
if (bind (rsp.server_fd,
(struct sockaddr *)&sock_addr, sizeof (sock_addr)) < 0)
{
fprintf (stderr, "Warning: Unable to bind RSP server socket %d to port "
"%d: %s\n", rsp.server_fd, config.debug.rsp_port,
strerror (errno));
rsp_server_close();
return;
}
 
/* Mark us as a passive port, with a maximum backlog of 1 connection (we
never connect simultaneously to more than one RSP client!) */
if (listen (rsp.server_fd, 1) < 0)
{
fprintf (stderr, "Warning: Unable to set RSP backlog on server socket "
"%d to %d: %s\n", rsp.server_fd, 1, strerror (errno));
rsp_server_close();
return;
}
} /* rsp_init () */
 
 
/*---------------------------------------------------------------------------*/
/*!Look for action on RSP
 
This function is called when the processor has stalled, which, except for
initialization, must be due to an interrupt.
 
If we have no RSP client, we poll the RSP server for a client requesting to
join. We can make no progress until the client is available.
 
Then if the cause is an interrupt, and the interrupt not been notified to
GDB, a packet reporting the cause of the interrupt is sent.
 
The function then polls the RSP client port (if open)
for available input. It then processes the GDB RSP request and return.
 
If an error occurs when polling the RSP server, other than an interrupt, a
warning message is printed out and the RSP server and client (if open)
connections are closed.
 
If an error occurs when polling the RSP client, other than an interrupt, a
warning message is printed out and the RSP client connection is closed.
 
Polling is always blocking (i.e. timeout -1). */
/*---------------------------------------------------------------------------*/
void
handle_rsp ()
{
struct pollfd fds[1]; /* The FD to poll for */
 
/* Give up if no RSP server port (this should not occur) */
if (-1 == rsp.server_fd)
{
fprintf (stderr, "Warning: No RSP server port open\n");
return;
}
 
/* If we have no RSP client, poll the server until we get one. */
while (-1 == rsp.client_fd)
{
/* Poll for a client on the RSP server socket */
fds[0].fd = rsp.server_fd; /* FD for the server socket */
fds[0].events = POLLIN; /* Poll for input activity */
 
/* Poll is always blocking. We can't do anything more until something
happens here. */
switch (poll (fds, 1, -1))
{
case -1:
/* Error. Only one we ignore is an interrupt */
if (EINTR != errno)
{
fprintf (stderr, "Warning: poll for RSP failed: closing "
"server connection: %s\n", strerror (errno));
rsp_client_close();
rsp_server_close();
return;
}
break;
 
case 0:
/* Timeout. This can't occur! */
fprintf (stderr, "Warning: Unexpected RSP server poll timeout\n");
break;
 
default:
/* Is the poll due to input available? If we succeed ignore any
outstanding reports of exceptions. */
if (POLLIN == (fds[0].revents & POLLIN))
{
rsp_server_request ();
rsp.client_waiting = 0; /* No longer waiting */
}
else
{
/* Error leads to closing the client and server */
fprintf (stderr, "Warning: RSP server received flags "
"0x%08x: closing server connection\n", fds[0].revents);
rsp_client_close();
rsp_server_close();
}
}
}
 
/* If we have an unacknowledged exception and a client is available, tell
GDB. If this exception was a trap due to a memory breakpoint, then
adjust the NPC. */
if (rsp.client_waiting)
{
if ((TARGET_SIGNAL_TRAP == rsp.sigval) &&
(NULL != mp_hash_lookup (BP_MEMORY, cpu_state.sprs[SPR_PPC])))
{
set_npc (cpu_state.sprs[SPR_PPC]);
}
 
rsp_report_exception();
rsp.client_waiting = 0; /* No longer waiting */
}
/* Poll the RSP client socket for a message from GDB */
fds[0].fd = rsp.client_fd; /* FD for the client socket */
fds[0].events = POLLIN; /* Poll for input activity */
 
/* Poll is always blocking. We can't do anything more until something
happens here. */
switch (poll (fds, 1, -1))
{
case -1:
/* Error. Only one we ignore is an interrupt */
if (EINTR != errno)
{
fprintf (stderr, "Warning: poll for RSP failed: closing "
"server connection: %s\n", strerror (errno));
rsp_client_close();
rsp_server_close();
}
 
return;
 
case 0:
/* Timeout. This can't occur! */
fprintf (stderr, "Warning: Unexpected RSP client poll timeout\n");
return;
 
default:
/* Is the client activity due to input available? */
if (POLLIN == (fds[0].revents & POLLIN))
{
rsp_client_request ();
}
else
{
/* Error leads to closing the client, but not the server. */
fprintf (stderr, "Warning: RSP client received flags "
"0x%08x: closing client connection\n", fds[0].revents);
rsp_client_close();
}
}
} /* handle_rsp () */
 
 
/*---------------------------------------------------------------------------*/
/*!Note an exception for future processing
 
The simulator has encountered an exception. Record it here, so that a
future call to handle_exception will report it back to the client. The
signal is supplied in Or1ksim form and recorded in GDB form.
 
We flag up a warning if an exception is already pending, and ignore the
earlier exception.
 
@param[in] except The exception (Or1ksim form) */
/*---------------------------------------------------------------------------*/
void
rsp_exception (unsigned long int except)
{
int sigval; /* GDB signal equivalent to exception */
 
switch (except)
{
case EXCEPT_RESET: sigval = TARGET_SIGNAL_PWR; break;
case EXCEPT_BUSERR: sigval = TARGET_SIGNAL_BUS; break;
case EXCEPT_DPF: sigval = TARGET_SIGNAL_SEGV; break;
case EXCEPT_IPF: sigval = TARGET_SIGNAL_SEGV; break;
case EXCEPT_TICK: sigval = TARGET_SIGNAL_ALRM; break;
case EXCEPT_ALIGN: sigval = TARGET_SIGNAL_BUS; break;
case EXCEPT_ILLEGAL: sigval = TARGET_SIGNAL_ILL; break;
case EXCEPT_INT: sigval = TARGET_SIGNAL_INT; break;
case EXCEPT_DTLBMISS: sigval = TARGET_SIGNAL_SEGV; break;
case EXCEPT_ITLBMISS: sigval = TARGET_SIGNAL_SEGV; break;
case EXCEPT_RANGE: sigval = TARGET_SIGNAL_FPE; break;
case EXCEPT_SYSCALL: sigval = TARGET_SIGNAL_USR2; break;
case EXCEPT_FPE: sigval = TARGET_SIGNAL_FPE; break;
case EXCEPT_TRAP: sigval = TARGET_SIGNAL_TRAP; break;
 
default:
fprintf (stderr, "Warning: Unknown RSP exception %lu: Ignored\n", except);
return;
}
 
if ((0 != rsp.sigval) && (sigval != rsp.sigval))
{
fprintf (stderr, "Warning: RSP signal %d received while signal "
"%d pending: Pending exception replaced\n", sigval, rsp.sigval);
}
 
rsp.sigval = sigval; /* Save the signal value */
 
} /* rsp_exception () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a request to the server for a new client
 
We may already have a client. If we do, we will accept an immediately close
the new client. */
/*---------------------------------------------------------------------------*/
static void
rsp_server_request ()
{
struct sockaddr_in sock_addr; /* The socket address */
socklen_t len; /* Size of the socket address */
int fd; /* The client FD */
int flags; /* fcntl () flags */
int optval; /* Option value for setsockopt () */
 
/* Get the client FD */
len = sizeof (sock_addr);
fd = accept (rsp.server_fd, (struct sockaddr *)&sock_addr, &len);
if (fd < 0)
{
/* This is can happen, because a connection could have started, and then
terminated due to a protocol error or user initiation before the
accept could take place.
 
Two of the errors we can ignore (a retry is permissible). All other
errors, we assume the server port has gone tits up and close. */
 
if ((errno != EWOULDBLOCK) && (errno != EAGAIN))
{
fprintf (stderr, "Warning: RSP server error creating client: "
"closing connection %s\n", strerror (errno));
rsp_client_close ();
rsp_server_close ();
}
 
return;
}
 
/* If we already have a client, then immediately close the new one */
if (-1 != rsp.client_fd)
{
fprintf (stderr, "Warning: Additional RSP client request refused\n");
close (fd);
return;
}
 
/* We have a new client, which should be non-blocking. Get the current flags
and then set the non-blocking flags */
flags = fcntl (fd, F_GETFL);
if (flags < 0)
{
fprintf (stderr, "Warning: Unable to get flags for RSP client socket "
"%d: %s\n", fd, strerror (errno));
close (fd);
return;
}
 
flags |= O_NONBLOCK;
if (fcntl (fd, F_SETFL, flags) < 0)
{
fprintf (stderr, "Warning: Unable to set flags for RSP client socket "
"%d to 0x%08x: %s\n", fd, flags, strerror (errno));
close (fd);
return;
}
 
/* Turn of Nagel's algorithm for the client socket. This means the client
sends stuff immediately, it doesn't wait to fill up a packet. */
optval = 0;
len = sizeof (optval);
if (setsockopt (fd, rsp.proto_num, TCP_NODELAY, &optval, len) < 0)
{
fprintf (stderr, "Warning: Unable to disable Nagel's algorithm for "
"RSP client socket %d: %s\n", fd, strerror (errno));
close (fd);
return;
}
 
/* We have a new client socket */
rsp.client_fd = fd;
 
} /* rsp_server_request () */
 
 
/*---------------------------------------------------------------------------*/
/*!Deal with a request from the GDB client session
 
In general, apart from the simplest requests, this function replies on
other functions to implement the functionality. */
/*---------------------------------------------------------------------------*/
static void
rsp_client_request ()
{
struct rsp_buf *buf = get_packet (); /* Message sent to us */
 
// Null packet means we hit EOF or the link was closed for some other
// reason. Close the client and return
if (NULL == buf)
{
rsp_client_close ();
return;
}
 
#if RSP_TRACE
printf ("Packet received %s: %d chars\n", buf->data, buf->len );
fflush (stdout);
#endif
 
switch (buf->data[0])
{
case '!':
/* Request for extended remote mode */
put_str_packet ("OK");
return;
 
case '?':
/* Return last signal ID */
rsp_report_exception();
return;
 
case 'A':
/* Initialization of argv not supported */
fprintf (stderr, "Warning: RSP 'A' packet not supported: ignored\n");
put_str_packet ("E01");
return;
 
case 'b':
/* Setting baud rate is deprecated */
fprintf (stderr, "Warning: RSP 'b' packet is deprecated and not "
"supported: ignored\n");
return;
 
case 'B':
/* Breakpoints should be set using Z packets */
fprintf (stderr, "Warning: RSP 'B' packet is deprecated (use 'Z'/'z' "
"packets instead): ignored\n");
return;
 
case 'c':
/* Continue */
rsp_continue (buf);
return;
 
case 'C':
/* Continue with signal */
rsp_continue_with_signal (buf);
return;
 
case 'd':
/* Disable debug using a general query */
fprintf (stderr, "Warning: RSP 'd' packet is deprecated (define a 'Q' "
"packet instead: ignored\n");
return;
 
case 'D':
/* Detach GDB. Do this by closing the client. The rules say that
execution should continue. TODO. Is this really then intended
meaning? Or does it just mean that only vAttach will be recognized
after this? */
put_str_packet ("OK");
rsp_client_close ();
set_stall_state (0);
return;
 
case 'F':
/* File I/O is not currently supported */
fprintf (stderr, "Warning: RSP file I/O not currently supported: 'F' "
"packet ignored\n");
return;
 
case 'g':
rsp_read_all_regs ();
return;
 
case 'G':
rsp_write_all_regs (buf);
return;
case 'H':
/* Set the thread number of subsequent operations. For now ignore
silently and just reply "OK" */
put_str_packet ("OK");
return;
 
case 'i':
/* Single instruction step */
fprintf (stderr, "Warning: RSP cycle stepping not supported: target "
"stopped immediately\n");
rsp.client_waiting = 1; /* Stop reply will be sent */
return;
 
case 'I':
/* Single instruction step with signal */
fprintf (stderr, "Warning: RSP cycle stepping not supported: target "
"stopped immediately\n");
rsp.client_waiting = 1; /* Stop reply will be sent */
return;
 
case 'k':
/* Kill request. Do nothing for now. */
return;
 
case 'm':
/* Read memory (symbolic) */
rsp_read_mem (buf);
return;
 
case 'M':
/* Write memory (symbolic) */
rsp_write_mem (buf);
return;
 
case 'p':
/* Read a register */
rsp_read_reg (buf);
return;
 
case 'P':
/* Write a register */
rsp_write_reg (buf);
return;
 
case 'q':
/* Any one of a number of query packets */
rsp_query (buf);
return;
 
case 'Q':
/* Any one of a number of set packets */
rsp_set (buf);
return;
 
case 'r':
/* Reset the system. Deprecated (use 'R' instead) */
fprintf (stderr, "Warning: RSP 'r' packet is deprecated (use 'R' "
"packet instead): ignored\n");
return;
 
case 'R':
/* Restart the program being debugged. */
rsp_restart ();
return;
 
case 's':
/* Single step (one high level instruction). This could be hard without
DWARF2 info */
rsp_step (buf);
return;
 
case 'S':
/* Single step (one high level instruction) with signal. This could be
hard without DWARF2 info */
rsp_step_with_signal (buf);
return;
 
case 't':
/* Search. This is not well defined in the manual and for now we don't
support it. No response is defined. */
fprintf (stderr, "Warning: RSP 't' packet not supported: ignored\n");
return;
 
case 'T':
/* Is the thread alive. We are bare metal, so don't have a thread
context. The answer is always "OK". */
put_str_packet ("OK");
return;
 
case 'v':
/* Any one of a number of packets to control execution */
rsp_vpkt (buf);
return;
 
case 'X':
/* Write memory (binary) */
rsp_write_mem_bin (buf);
return;
 
case 'z':
/* Remove a breakpoint/watchpoint. */
rsp_remove_matchpoint (buf);
return;
 
case 'Z':
/* Insert a breakpoint/watchpoint. */
rsp_insert_matchpoint (buf);
return;
 
default:
/* Unknown commands are ignored */
fprintf (stderr, "Warning: Unknown RSP request %s\n", buf->data);
return;
}
} /* rsp_client_request () */
 
 
/*---------------------------------------------------------------------------*/
/*!Close the server if it is open */
/*---------------------------------------------------------------------------*/
static void
rsp_server_close ()
{
if (-1 != rsp.server_fd)
{
close (rsp.server_fd);
rsp.server_fd = -1;
}
} /* rsp_server_close () */
 
 
/*---------------------------------------------------------------------------*/
/*!Close the client if it is open */
/*---------------------------------------------------------------------------*/
static void
rsp_client_close ()
{
if (-1 != rsp.client_fd)
{
close (rsp.client_fd);
rsp.client_fd = -1;
}
} /* rsp_client_close () */
 
 
/*---------------------------------------------------------------------------*/
/*!Send a packet to the GDB client
 
Modeled on the stub version supplied with GDB. Put out the data preceded by
a '$', followed by a '#' and a one byte checksum. '$', '#', '*' and '}' are
escaped by preceding them with '}' and then XORing the character with
0x20.
 
@param[in] buf The data to send */
/*---------------------------------------------------------------------------*/
static void
put_packet (struct rsp_buf *buf)
{
int ch; /* Ack char */
 
/* Construct $<packet info>#<checksum>. Repeat until the GDB client
acknowledges satisfactory receipt. */
do
{
unsigned char checksum = 0; /* Computed checksum */
int count = 0; /* Index into the buffer */
 
#if RSP_TRACE
printf ("Putting %s\n", buf->data);
fflush (stdout);
#endif
 
put_rsp_char ('$'); /* Start char */
 
/* Body of the packet */
for (count = 0; count < buf->len; count++)
{
unsigned char ch = buf->data[count];
 
/* Check for escaped chars */
if (('$' == ch) || ('#' == ch) || ('*' == ch) || ('}' == ch))
{
ch ^= 0x20;
checksum += (unsigned char)'}';
put_rsp_char ('}');
}
 
checksum += ch;
put_rsp_char (ch);
}
 
put_rsp_char ('#'); /* End char */
 
/* Computed checksum */
put_rsp_char (hexchars[checksum >> 4]);
put_rsp_char (hexchars[checksum % 16]);
 
/* Check for ack of connection failure */
ch = get_rsp_char ();
if (-1 == ch)
{
return; /* Fail the put silently. */
}
}
while ('+' != ch);
 
} /* put_packet () */
 
 
/*---------------------------------------------------------------------------*/
/*!Convenience to put a constant string packet
 
param[in] str The text of the packet */
/*---------------------------------------------------------------------------*/
static void
put_str_packet (const char *str)
{
struct rsp_buf buf;
int len = strlen (str);
 
/* Construct the packet to send, so long as string is not too big,
otherwise truncate. Add EOS at the end for convenient debug printout */
 
if (len >= GDB_BUF_MAX)
{
fprintf (stderr, "Warning: String %s too large for RSP packet: "
"truncated\n", str);
len = GDB_BUF_MAX - 1;
}
 
strncpy (buf.data, str, len);
buf.data[len] = 0;
buf.len = len;
 
put_packet (&buf);
 
} /* put_str_packet () */
 
 
/*---------------------------------------------------------------------------*/
/*!Get a packet from the GDB client
Modeled on the stub version supplied with GDB. The data is in a static
buffer. The data should be copied elsewhere if it is to be preserved across
a subsequent call to get_packet().
 
Unlike the reference implementation, we don't deal with sequence
numbers. GDB has never used them, and this implementation is only intended
for use with GDB 6.8 or later. Sequence numbers were removed from the RSP
standard at GDB 5.0.
 
@return A pointer to the static buffer containing the data */
/*---------------------------------------------------------------------------*/
static struct rsp_buf *
get_packet ()
{
static struct rsp_buf buf; /* Survives the return */
 
/* Keep getting packets, until one is found with a valid checksum */
while (1)
{
unsigned char checksum; /* The checksum we have computed */
int count; /* Index into the buffer */
int ch; /* Current character */
 
/* Wait around for the start character ('$'). Ignore all other
characters */
ch = get_rsp_char ();
while (ch != '$')
{
if (-1 == ch)
{
return NULL; /* Connection failed */
}
 
ch = get_rsp_char ();
}
 
/* Read until a '#' or end of buffer is found */
checksum = 0;
count = 0;
while (count < GDB_BUF_MAX - 1)
{
ch = get_rsp_char ();
 
/* Check for connection failure */
if (-1 == ch)
{
return NULL;
}
 
/* If we hit a start of line char begin all over again */
if ('$' == ch)
{
checksum = 0;
count = 0;
 
continue;
}
 
/* Break out if we get the end of line char */
if ('#' == ch)
{
break;
}
 
/* Update the checksum and add the char to the buffer */
 
checksum = checksum + (unsigned char)ch;
buf.data[count] = (char)ch;
count = count + 1;
}
 
/* Mark the end of the buffer with EOS - it's convenient for non-binary
data to be valid strings. */
buf.data[count] = 0;
buf.len = count;
 
/* If we have a valid end of packet char, validate the checksum */
if ('#' == ch)
{
unsigned char xmitcsum; /* The checksum in the packet */
 
ch = get_rsp_char ();
if (-1 == ch)
{
return NULL; /* Connection failed */
}
xmitcsum = hex (ch) << 4;
 
ch = get_rsp_char ();
if (-1 == ch)
{
return NULL; /* Connection failed */
}
 
xmitcsum += hex (ch);
 
/* If the checksums don't match print a warning, and put the
negative ack back to the client. Otherwise put a positive ack. */
if (checksum != xmitcsum)
{
fprintf (stderr, "Warning: Bad RSP checksum: Computed "
"0x%02x, received 0x%02x\n", checksum, xmitcsum);
 
put_rsp_char ('-'); /* Failed checksum */
}
else
{
put_rsp_char ('+'); /* successful transfer */
break;
}
}
else
{
fprintf (stderr, "Warning: RSP packet overran buffer\n");
}
}
 
return &buf; /* Success */
 
} /* get_packet () */
 
 
/*---------------------------------------------------------------------------*/
/*!Put a single character out onto the client socket
 
This should only be called if the client is open, but we check for safety.
 
@param[in] c The character to put out */
/*---------------------------------------------------------------------------*/
static void
put_rsp_char (char c)
{
if (-1 == rsp.client_fd)
{
fprintf (stderr, "Warning: Attempt to write '%c' to unopened RSP "
"client: Ignored\n", c);
return;
}
 
/* Write until successful (we retry after interrupts) or catastrophic
failure. */
while (1)
{
switch (write (rsp.client_fd, &c, sizeof (c)))
{
case -1:
/* Error: only allow interrupts or would block */
if ((EAGAIN != errno) && (EINTR != errno))
{
fprintf (stderr, "Warning: Failed to write to RSP client: "
"Closing client connection: %s\n",
strerror (errno));
rsp_client_close ();
return;
}
break;
 
case 0:
break; /* Nothing written! Try again */
 
default:
return; /* Success, we can return */
}
}
} /* put_rsp_char () */
 
 
/*---------------------------------------------------------------------------*/
/*!Get a single character from the client socket
 
This should only be called if the client is open, but we check for safety.
 
@return The character read, or -1 on failure */
/*---------------------------------------------------------------------------*/
static int
get_rsp_char ()
{
unsigned char c; /* The character read */
 
if (-1 == rsp.client_fd)
{
fprintf (stderr, "Warning: Attempt to read from unopened RSP "
"client: Ignored\n");
return -1;
}
 
/* Read until successful (we retry after interrupts) or catastrophic
failure. */
while (1)
{
switch (read (rsp.client_fd, &c, sizeof (c)))
{
case -1:
/* Error: only allow interrupts or would block */
if ((EAGAIN != errno) && (EINTR != errno))
{
fprintf (stderr, "Warning: Failed to read from RSP client: "
"Closing client connection: %s\n",
strerror (errno));
rsp_client_close ();
return -1;
}
break;
 
case 0:
// EOF
rsp_client_close ();
return -1;
 
default:
return c & 0xff; /* Success, we can return (no sign extend!) */
}
}
} /* get_rsp_char () */
 
 
/*---------------------------------------------------------------------------*/
/*!"Unescape" RSP binary data
 
'#', '$' and '}' are escaped by preceding them by '}' and oring with 0x20.
 
This function reverses that, modifying the data in place.
 
@param[in] data The array of bytes to convert
@para[in] len The number of bytes to be converted
 
@return The number of bytes AFTER conversion */
/*---------------------------------------------------------------------------*/
static int
rsp_unescape (char *data,
int len)
{
int from_off = 0; /* Offset to source char */
int to_off = 0; /* Offset to dest char */
 
while (from_off < len)
{
/* Is it escaped */
if ( '}' == data[from_off])
{
from_off++;
data[to_off] = data[from_off] ^ 0x20;
}
else
{
data[to_off] = data[from_off];
}
 
from_off++;
to_off++;
}
 
return to_off;
 
} /* rsp_unescape () */
 
 
/*---------------------------------------------------------------------------*/
/*!Initialize the matchpoint hash table
 
This is an open hash table, so this function clears all the links to
NULL. */
/*---------------------------------------------------------------------------*/
static void
mp_hash_init ()
{
int i;
 
for (i = 0; i < MP_HASH_SIZE; i++)
{
rsp.mp_hash[i] = NULL;
}
} /* mp_hash_init () */
 
 
/*---------------------------------------------------------------------------*/
/*!Add an entry to the matchpoint hash table
 
Add the entry if it wasn't already there. If it was there do nothing. The
match just be on type and addr. The instr need not match, since if this is
a duplicate insertion (perhaps due to a lost packet) they will be
different.
 
@param[in] type The type of matchpoint
@param[in] addr The address of the matchpoint
@para[in] instr The instruction to associate with the address */
/*---------------------------------------------------------------------------*/
static void
mp_hash_add (enum mp_type type,
unsigned long int addr,
unsigned long int instr)
{
int hv = addr % MP_HASH_SIZE;
struct mp_entry *curr;
 
/* See if we already have the entry */
for(curr = rsp.mp_hash[hv]; NULL != curr; curr = curr->next)
{
if ((type == curr->type) && (addr == curr->addr))
{
return; /* We already have the entry */
}
}
 
/* Insert the new entry at the head of the chain */
curr = malloc (sizeof (*curr));
 
curr->type = type;
curr->addr = addr;
curr->instr = instr;
curr->next = rsp.mp_hash[hv];
 
rsp.mp_hash[hv] = curr;
 
} /* mp_hash_add () */
 
 
/*---------------------------------------------------------------------------*/
/*!Look up an entry in the matchpoint hash table
 
The match must be on type AND addr.
 
@param[in] type The type of matchpoint
@param[in] addr The address of the matchpoint
 
@return The entry deleted, or NULL if the entry was not found */
/*---------------------------------------------------------------------------*/
static struct mp_entry *
mp_hash_lookup (enum mp_type type,
unsigned long int addr)
{
int hv = addr % MP_HASH_SIZE;
struct mp_entry *curr;
 
/* Search */
for (curr = rsp.mp_hash[hv]; NULL != curr; curr = curr->next)
{
if ((type == curr->type) && (addr == curr->addr))
{
return curr; /* The entry found */
}
}
 
/* Not found */
return NULL;
} /* mp_hash_lookup () */
 
 
/*---------------------------------------------------------------------------*/
/*!Delete an entry from the matchpoint hash table
 
If it is there the entry is deleted from the hash table. If it is not
there, no action is taken. The match must be on type AND addr.
 
The usual fun and games tracking the previous entry, so we can delete
things.
 
@note The deletion DOES NOT free the memory associated with the entry,
since that is returned. The caller should free the memory when they
have used the information.
 
@param[in] type The type of matchpoint
@param[in] addr The address of the matchpoint
 
@return The entry deleted, or NULL if the entry was not found */
/*---------------------------------------------------------------------------*/
static struct mp_entry *
mp_hash_delete (enum mp_type type,
unsigned long int addr)
{
int hv = addr % MP_HASH_SIZE;
struct mp_entry *prev = NULL;
struct mp_entry *curr;
 
/* Search */
for (curr = rsp.mp_hash[hv]; NULL != curr; curr = curr->next)
{
if ((type == curr->type) && (addr == curr->addr))
{
/* Found - delete. Method depends on whether we are the head of
chain. */
if (NULL == prev)
{
rsp.mp_hash[hv] = curr->next;
}
else
{
prev->next = curr->next;
}
 
return curr; /* The entry deleted */
}
 
prev = curr;
}
 
/* Not found */
return NULL;
} /* mp_hash_delete () */
 
 
/*---------------------------------------------------------------------------*/
/*!Utility to give the value of a hex char
 
@param[in] ch A character representing a hexadecimal digit. Done as -1,
for consistency with other character routines, which can use
-1 as EOF.
 
@return The value of the hex character, or -1 if the character is
invalid. */
/*---------------------------------------------------------------------------*/
static int
hex (int c)
{
return ((c >= 'a') && (c <= 'f')) ? c - 'a' + 10 :
((c >= '0') && (c <= '9')) ? c - '0' :
((c >= 'A') && (c <= 'F')) ? c - 'A' + 10 : -1;
 
} /* hex () */
 
 
/*---------------------------------------------------------------------------*/
/*!Convert a register to a hex digit string
 
The supplied 32-bit value is converted to an 8 digit hex string according
the target endianism. It is null terminated for convenient printing.
 
@param[in] val The value to convert
@param[out] buf The buffer for the text string */
/*---------------------------------------------------------------------------*/
static void
reg2hex (unsigned long int val,
char *buf)
{
int n; /* Counter for digits */
 
for (n = 0; n < 8; n++)
{
#ifdef WORDSBIGENDIAN
int nyb_shift = n * 4;
#else
int nyb_shift = 28 - (n * 4);
#endif
buf[n] = hexchars[(val >> nyb_shift) & 0xf];
}
 
buf[8] = 0; /* Useful to terminate as string */
 
} /* reg2hex () */
 
 
/*---------------------------------------------------------------------------*/
/*!Convert a hex digit string to a register value
 
The supplied 8 digit hex string is converted to a 32-bit value according
the target endianism
 
@param[in] buf The buffer with the hex string
 
@return The value to convert */
/*---------------------------------------------------------------------------*/
static unsigned long int
hex2reg (char *buf)
{
int n; /* Counter for digits */
unsigned long int val = 0; /* The result */
 
for (n = 0; n < 8; n++)
{
#ifdef WORDSBIGENDIAN
int nyb_shift = n * 4;
#else
int nyb_shift = 28 - (n * 4);
#endif
val |= hex (buf[n]) << nyb_shift;
}
 
return val;
 
} /* hex2reg () */
 
 
/*---------------------------------------------------------------------------*/
/*!Convert an ASCII character string to pairs of hex digits
 
Both source and destination are null terminated.
 
@param[out] dest Buffer to store the hex digit pairs (null terminated)
@param[in] src The ASCII string (null terminated) */
/*---------------------------------------------------------------------------*/
static void ascii2hex (char *dest,
char *src)
{
int i;
 
/* Step through converting the source string */
for (i = 0; src[i] != '\0'; i++)
{
char ch = src[i];
 
dest[i * 2] = hexchars[ch >> 4 & 0xf];
dest[i * 2 + 1] = hexchars[ch & 0xf];
}
 
dest[i * 2] = '\0';
} /* ascii2hex () */
 
 
/*---------------------------------------------------------------------------*/
/*!Convert pairs of hex digits to an ASCII character string
 
Both source and destination are null terminated.
 
@param[out] dest The ASCII string (null terminated)
@param[in] src Buffer holding the hex digit pairs (null terminated) */
/*---------------------------------------------------------------------------*/
static void hex2ascii (char *dest,
char *src)
{
int i;
 
/* Step through convering the source hex digit pairs */
for (i = 0; src[i * 2] != '\0' && src[i * 2 + 1] != '\0'; i++)
{
dest[i] = ((hex (src[i * 2]) & 0xf) << 4) | (hex (src[i * 2 + 1]) & 0xf);
}
 
dest[i] = '\0';
 
} /* hex2ascii () */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the program counter
 
This sets the value in the NPC SPR. Not completely trivial, since this is
actually cached in cpu_state.pc. Any reset of the NPC also involves
clearing the delay state and setting the pcnext global.
 
Only actually do this if the requested address is different to the current
NPC (avoids clearing the delay pipe).
 
@param[in] addr The address to use */
/*---------------------------------------------------------------------------*/
static void
set_npc (unsigned long int addr)
{
if (cpu_state.pc != addr)
{
cpu_state.pc = addr;
cpu_state.delay_insn = 0;
pcnext = addr + 4;
}
} /* set_npc () */
 
 
/*---------------------------------------------------------------------------*/
/*!Send a packet acknowledging an exception has occurred
 
This is only called if there is a client FD to talk to */
/*---------------------------------------------------------------------------*/
static void
rsp_report_exception ()
{
struct rsp_buf buf;
 
/* Construct a signal received packet */
buf.data[0] = 'S';
buf.data[1] = hexchars[rsp.sigval >> 4];
buf.data[2] = hexchars[rsp.sigval % 16];
buf.data[3] = 0;
buf.len = strlen (buf.data);
 
put_packet (&buf);
 
} /* rsp_report_exception () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP continue request
 
Parse the command to see if there is an address. Uses the underlying
generic continue function, with EXCEPT_NONE.
 
@param[in] buf The full continue packet */
/*---------------------------------------------------------------------------*/
static void
rsp_continue (struct rsp_buf *buf)
{
unsigned long int addr; /* Address to continue from, if any */
 
if (0 == strcmp ("c", buf->data))
{
addr = cpu_state.pc; /* Default uses current NPC */
}
else if (1 != sscanf (buf->data, "c%lx", &addr))
{
fprintf (stderr,
"Warning: RSP continue address %s not recognized: ignored\n",
buf->data);
addr = cpu_state.pc; /* Default uses current NPC */
}
 
rsp_continue_generic (addr, EXCEPT_NONE);
 
} /* rsp_continue () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP continue with signal request
 
Currently null. Will use the underlying generic continue function.
 
@param[in] buf The full continue with signal packet */
/*---------------------------------------------------------------------------*/
static void
rsp_continue_with_signal (struct rsp_buf *buf)
{
printf ("RSP continue with signal '%s' received\n", buf->data);
 
} /* rsp_continue_with_signal () */
 
 
/*---------------------------------------------------------------------------*/
/*!Generic processing of a continue request
 
The signal may be EXCEPT_NONE if there is no exception to be
handled. Currently the exception is ignored.
 
The single step flag is cleared in the debug registers and then the
processor is unstalled.
 
@param[in] addr Address from which to step
@param[in] except The exception to use (if any) */
/*---------------------------------------------------------------------------*/
static void
rsp_continue_generic (unsigned long int addr,
unsigned long int except)
{
/* Set the address as the value of the next program counter */
set_npc (addr);
 
/* Clear Debug Reason Register and watchpoint break generation in Debug Mode
Register 2 */
cpu_state.sprs[SPR_DRR] = 0;
cpu_state.sprs[SPR_DMR2] &= ~SPR_DMR2_WGB;
 
/* Clear the single step trigger in Debug Mode Register 1 and set traps to be
handled by the debug unit in the Debug Stop Register */
cpu_state.sprs[SPR_DMR1] &= ~SPR_DMR1_ST;
cpu_state.sprs[SPR_DSR] |= SPR_DSR_TE;
 
/* Unstall the processor */
set_stall_state (0);
 
/* Note the GDB client is now waiting for a reply. */
rsp.client_waiting = 1;
 
} /* rsp_continue_generic () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP read all registers request
 
The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PPC
(i.e. SPR PPC), NPC (i.e. SPR NPC) and SR (i.e. SPR SR). Each register is
returned as a sequence of bytes in target endian order.
 
Each byte is packed as a pair of hex digits. */
/*---------------------------------------------------------------------------*/
static void
rsp_read_all_regs ()
{
struct rsp_buf buf; /* Buffer for the reply */
int r; /* Register index */
 
/* The GPRs */
for (r = 0; r < MAX_GPRS; r++)
{
reg2hex (cpu_state.reg[r], &(buf.data[r * 8]));
}
 
/* PPC, NPC and SR */
reg2hex (cpu_state.sprs[SPR_PPC], &(buf.data[PPC_REGNUM * 8]));
reg2hex (cpu_state.pc, &(buf.data[NPC_REGNUM * 8]));
reg2hex (cpu_state.sprs[SPR_SR], &(buf.data[SR_REGNUM * 8]));
 
/* Finalize the packet and send it */
buf.data[NUM_REGS * 8] = 0;
buf.len = NUM_REGS * 8;
 
put_packet (&buf);
 
} /* rsp_read_all_regs () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP write all registers request
 
The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PPC
(i.e. SPR PPC), NPC (i.e. SPR NPC) and SR (i.e. SPR SR). Each register is
supplied as a sequence of bytes in target endian order.
 
Each byte is packed as a pair of hex digits.
 
@todo There is no error checking at present. Non-hex chars will generate a
warning message, but there is no other check that the right amount
of data is present. The result is always "OK".
 
@param[in] buf The original packet request. */
/*---------------------------------------------------------------------------*/
static void
rsp_write_all_regs (struct rsp_buf *buf)
{
int r; /* Register index */
 
/* The GPRs */
for (r = 0; r < MAX_GPRS; r++)
{
cpu_state.reg[r] = hex2reg (&(buf->data[r * 8]));
}
 
/* PPC, NPC and SR */
cpu_state.sprs[SPR_PPC] = hex2reg (&(buf->data[PPC_REGNUM * 8]));
cpu_state.sprs[SPR_SR] = hex2reg (&(buf->data[SR_REGNUM * 8]));
set_npc (hex2reg (&(buf->data[NPC_REGNUM * 8])));
 
/* Acknowledge. TODO: We always succeed at present, even if the data was
defective. */
put_str_packet ("OK");
 
} /* rsp_write_all_regs () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP read memory (symbolic) request
 
Syntax is:
 
m<addr>,<length>:
 
The response is the bytes, lowest address first, encoded as pairs of hex
digits.
 
The length given is the number of bytes to be read.
 
@note This function reuses buf, so trashes the original command.
 
@param[in] buf The command received */
/*---------------------------------------------------------------------------*/
static void
rsp_read_mem (struct rsp_buf *buf)
{
unsigned int addr; /* Where to read the memory */
int len; /* Number of bytes to read */
int off; /* Offset into the memory */
 
if (2 != sscanf (buf->data, "m%x,%x:", &addr, &len))
{
fprintf (stderr, "Warning: Failed to recognize RSP read memory "
"command: %s\n", buf->data);
put_str_packet ("E01");
return;
}
 
/* Make sure we won't overflow the buffer (2 chars per byte) */
if ((len * 2) >= GDB_BUF_MAX)
{
fprintf (stderr, "Warning: Memory read %s too large for RSP packet: "
"truncated\n", buf->data);
len = (GDB_BUF_MAX - 1) / 2;
}
 
/* Refill the buffer with the reply */
for (off = 0; off < len; off++)
{
unsigned char ch; /* The byte at the address */
 
/* Check memory area is valid */
if (NULL == verify_memoryarea (addr + off))
{
/* The error number doesn't matter. The GDB client will substitute
its own */
put_str_packet ("E01");
return;
}
 
// Get the memory direct - no translation.
ch = eval_direct8 (addr + off, 0, 0);
 
buf->data[off * 2] = hexchars[ch >> 4];
buf->data[off * 2 + 1] = hexchars[ch & 0xf];
}
 
buf->data[off * 2] = 0; /* End of string */
buf->len = strlen (buf->data);
put_packet (buf);
 
} /* rsp_read_mem () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP write memory (symbolic) request
 
Syntax is:
 
m<addr>,<length>:<data>
 
The data is the bytes, lowest address first, encoded as pairs of hex
digits.
 
The length given is the number of bytes to be written.
 
@note This function reuses buf, so trashes the original command.
 
@param[in] buf The command received */
/*---------------------------------------------------------------------------*/
static void
rsp_write_mem (struct rsp_buf *buf)
{
unsigned int addr; /* Where to write the memory */
int len; /* Number of bytes to write */
char *symdat; /* Pointer to the symboli data */
int datlen; /* Number of digits in symbolic data */
int off; /* Offset into the memory */
 
if (2 != sscanf (buf->data, "M%x,%x:", &addr, &len))
{
fprintf (stderr, "Warning: Failed to recognize RSP write memory "
"command: %s\n", buf->data);
put_str_packet ("E01");
return;
}
 
/* Find the start of the data and check there is the amount we expect. */
symdat = memchr ((const void *)buf->data, ':', GDB_BUF_MAX) + 1;
datlen = buf->len - (symdat - buf->data);
 
/* Sanity check */
if (len * 2 != datlen)
{
fprintf (stderr, "Warning: Write of %d digits requested, but %d digits "
"supplied: packet ignored\n", len * 2, datlen );
put_str_packet ("E01");
return;
}
 
/* Write the bytes to memory */
for (off = 0; off < len; off++)
{
if (NULL == verify_memoryarea (addr + off))
{
/* The error number doesn't matter. The GDB client will substitute
its own */
put_str_packet ("E01");
return;
}
else
{
unsigned char nyb1 = hex (symdat[off * 2]);
unsigned char nyb2 = hex (symdat[off * 2 + 1]);
 
// circumvent the read-only check usually done for mem accesses
// data is in host order, because that's what set_direct32 needs
set_program8 (addr + off, (nyb1 << 4) | nyb2);
}
}
 
put_str_packet ("OK");
 
} /* rsp_write_mem () */
 
 
/*---------------------------------------------------------------------------*/
/*!Read a single register
 
The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
(i.e. SPR NPC) and SR (i.e. SPR SR). The register is returned as a
sequence of bytes in target endian order.
 
Each byte is packed as a pair of hex digits.
 
@param[in] buf The original packet request. Reused for the reply. */
/*---------------------------------------------------------------------------*/
static void
rsp_read_reg (struct rsp_buf *buf)
{
unsigned int regnum;
 
/* Break out the fields from the data */
if (2 != sscanf (buf->data, "p%x", &regnum))
{
fprintf (stderr, "Warning: Failed to recognize RSP read register "
"command: %s\n", buf->data);
put_str_packet ("E01");
return;
}
 
/* Get the relevant register */
if (regnum < MAX_GPRS)
{
reg2hex (cpu_state.reg[regnum], buf->data);
}
else if (PPC_REGNUM == regnum)
{
reg2hex (cpu_state.sprs[SPR_PPC], buf->data);
}
else if (NPC_REGNUM == regnum)
{
reg2hex (cpu_state.pc, buf->data);
}
else if (SR_REGNUM == regnum)
{
reg2hex (cpu_state.sprs[SPR_SR], buf->data);
}
else
{
/* Error response if we don't know the register */
fprintf (stderr, "Warning: Attempt to read unknown register 0x%x: "
"ignored\n", regnum);
put_str_packet ("E01");
return;
}
 
buf->len = strlen (buf->data);
put_packet (buf);
 
} /* rsp_write_reg () */
 
/*---------------------------------------------------------------------------*/
/*!Write a single register
 
The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
(i.e. SPR NPC) and SR (i.e. SPR SR). The register is specified as a
sequence of bytes in target endian order.
 
Each byte is packed as a pair of hex digits.
 
@param[in] buf The original packet request. */
/*---------------------------------------------------------------------------*/
static void
rsp_write_reg (struct rsp_buf *buf)
{
unsigned int regnum;
char valstr[9]; /* Allow for EOS on the string */
 
/* Break out the fields from the data */
if (2 != sscanf (buf->data, "P%x=%8s", &regnum, valstr))
{
fprintf (stderr, "Warning: Failed to recognize RSP write register "
"command: %s\n", buf->data);
put_str_packet ("E01");
return;
}
/* Set the relevant register */
if (regnum < MAX_GPRS)
{
cpu_state.reg[regnum] = hex2reg (valstr);
}
else if (PPC_REGNUM == regnum)
{
cpu_state.sprs[SPR_PPC] = hex2reg (valstr);
}
else if (NPC_REGNUM == regnum)
{
set_npc (hex2reg (valstr));
}
else if (SR_REGNUM == regnum)
{
cpu_state.sprs[SPR_SR] = hex2reg (valstr);
}
else
{
/* Error response if we don't know the register */
fprintf (stderr, "Warning: Attempt to write unknown register 0x%x: "
"ignored\n", regnum);
put_str_packet ("E01");
return;
}
 
put_str_packet ("OK");
 
} /* rsp_write_reg () */
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP query request
 
@param[in] buf The request */
/*---------------------------------------------------------------------------*/
static void
rsp_query (struct rsp_buf *buf)
{
if (0 == strcmp ("qC", buf->data))
{
/* Return the current thread ID (unsigned hex). A null response
indicates to use the previously selected thread. Since we do not
support a thread concept, this is the appropriate response. */
put_str_packet ("");
}
else if (0 == strncmp ("qCRC", buf->data, strlen ("qCRC")))
{
/* Return CRC of memory area */
fprintf (stderr, "Warning: RSP CRC query not supported\n");
put_str_packet ("E01");
}
else if (0 == strcmp ("qfThreadInfo", buf->data))
{
/* Return info about active threads. We return just '-1' */
put_str_packet ("m-1");
}
else if (0 == strcmp ("qsThreadInfo", buf->data))
{
/* Return info about more active threads. We have no more, so return the
end of list marker, 'l' */
put_str_packet ("l");
}
else if (0 == strncmp ("qGetTLSAddr:", buf->data, strlen ("qGetTLSAddr:")))
{
/* We don't support this feature */
put_str_packet ("");
}
else if (0 == strncmp ("qL", buf->data, strlen ("qL")))
{
/* Deprecated and replaced by 'qfThreadInfo' */
fprintf (stderr, "Warning: RSP qL deprecated: no info returned\n");
put_str_packet ("qM001");
}
else if (0 == strcmp ("qOffsets", buf->data))
{
/* Report any relocation */
put_str_packet ("Text=0;Data=0;Bss=0");
}
else if (0 == strncmp ("qP", buf->data, strlen ("qP")))
{
/* Deprecated and replaced by 'qThreadExtraInfo' */
fprintf (stderr, "Warning: RSP qP deprecated: no info returned\n");
put_str_packet ("");
}
else if (0 == strncmp ("qRcmd,", buf->data, strlen ("qRcmd,")))
{
/* This is used to interface to commands to do "stuff" */
rsp_command (buf);
}
else if (0 == strncmp ("qSupported", buf->data, strlen ("qSupported")))
{
/* Report a list of the features we support. For now we just ignore any
supplied specific feature queries, but in the future these may be
supported as well. Note that the packet size allows for 'G' + all the
registers sent to us, or a reply to 'g' with all the registers and an
EOS so the buffer is a well formed string. */
 
char reply[GDB_BUF_MAX];
 
sprintf (reply, "PacketSize=%x", GDB_BUF_MAX);
put_str_packet (reply);
}
else if (0 == strncmp ("qSymbol:", buf->data, strlen ("qSymbol:")))
{
/* Offer to look up symbols. Nothing we want (for now). TODO. This just
ignores any replies to symbols we looked up, but we didn't want to
do that anyway! */
put_str_packet ("OK");
}
else if (0 == strncmp ("qThreadExtraInfo,", buf->data,
strlen ("qThreadExtraInfo,")))
{
/* Report that we are runnable, but the text must be hex ASCI
digits. For now do this by steam, reusing the original packet */
sprintf (buf->data, "%02x%02x%02x%02x%02x%02x%02x%02x%02x",
'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
buf->len = strlen (buf->data);
put_packet (buf);
}
else if (0 == strncmp ("qXfer:", buf->data, strlen ("qXfer:")))
{
/* For now we support no 'qXfer' requests, but these should not be
expected, since they were not reported by 'qSupported' */
fprintf (stderr, "Warning: RSP 'qXfer' not supported: ignored\n");
put_str_packet ("");
}
else
{
fprintf (stderr, "Unrecognized RSP query: ignored\n");
}
} /* rsp_query () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP qRcmd request
 
The actual command follows the "qRcmd," in ASCII encoded to hex
 
@param[in] buf The request in full */
/*---------------------------------------------------------------------------*/
static void
rsp_command (struct rsp_buf *buf)
{
char cmd[GDB_BUF_MAX];
 
hex2ascii (cmd, &(buf->data[strlen ("qRcmd,")]));
 
/* Work out which command it is */
if (0 == strncmp ("readspr ", cmd, strlen ("readspr")))
{
unsigned int regno;
 
/* Parse and return error if we fail */
if( 1 != sscanf (cmd, "readspr %4x", &regno))
{
fprintf (stderr, "Warning: qRcmd %s not recognized: ignored\n",
cmd);
put_str_packet ("E01");
return;
}
 
/* SPR out of range */
if (regno > MAX_SPRS)
{
fprintf (stderr, "Warning: qRcmd readspr %x too large: ignored\n",
regno);
put_str_packet ("E01");
return;
}
 
/* Construct the reply */
sprintf (cmd, "%8x", mfspr (regno));
ascii2hex (buf->data, cmd);
buf->len = strlen (buf->data);
put_packet (buf);
}
else if (0 == strncmp ("writespr ", cmd, strlen ("writespr")))
{
unsigned int regno;
unsigned long int val;
 
/* Parse and return error if we fail */
if( 2 != sscanf (cmd, "writespr %4x %8lx", &regno, &val))
{
fprintf (stderr, "Warning: qRcmd %s not recognized: ignored\n",
cmd);
put_str_packet ("E01");
return;
}
 
/* SPR out of range */
if (regno > MAX_SPRS)
{
fprintf (stderr, "Warning: qRcmd writespr %x too large: ignored\n",
regno);
put_str_packet ("E01");
return;
}
 
/* Update the SPR and reply "OK" */
mtspr (regno, val);
put_str_packet ("OK");
}
} /* rsp_command () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP set request
 
@param[in] buf The request */
/*---------------------------------------------------------------------------*/
static void
rsp_set (struct rsp_buf *buf)
{
if (0 == strncmp ("QPassSignals:", buf->data, strlen ("QPassSignals:")))
{
/* Passing signals not supported */
put_str_packet ("");
}
else if ((0 == strncmp ("QTDP", buf->data, strlen ("QTDP"))) ||
(0 == strncmp ("QFrame", buf->data, strlen ("QFrame"))) ||
(0 == strcmp ("QTStart", buf->data)) ||
(0 == strcmp ("QTStop", buf->data)) ||
(0 == strcmp ("QTinit", buf->data)) ||
(0 == strncmp ("QTro", buf->data, strlen ("QTro"))))
{
/* All tracepoint features are not supported. This reply is really only
needed to 'QTDP', since with that the others should not be
generated. */
put_str_packet ("");
}
else
{
fprintf (stderr, "Unrecognized RSP set request: ignored\n");
}
} /* rsp_set () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP restart request
 
For now we just put the program counter back to the one used with the last
vRun request. There is no point in unstalling the processor, since we'll
never get control back. */
/*---------------------------------------------------------------------------*/
static void
rsp_restart ()
{
set_npc (rsp.start_addr);
 
} /* rsp_restart () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP step request
 
Parse the command to see if there is an address. Uses the underlying
generic step function, with EXCEPT_NONE.
 
@param[in] buf The full step packet */
/*---------------------------------------------------------------------------*/
static void
rsp_step (struct rsp_buf *buf)
{
unsigned long int addr; /* The address to step from, if any */
 
if (0 == strcmp ("s", buf->data))
{
addr = cpu_state.pc; /* Default uses current NPC */
}
else if (1 != sscanf (buf->data, "s%lx", &addr))
{
fprintf (stderr,
"Warning: RSP step address %s not recognized: ignored\n",
buf->data);
addr = cpu_state.pc; /* Default uses current NPC */
}
 
rsp_step_generic (addr, EXCEPT_NONE);
 
} /* rsp_step () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP step with signal request
 
Currently null. Will use the underlying generic step function.
 
@param[in] buf The full step with signal packet */
/*---------------------------------------------------------------------------*/
static void
rsp_step_with_signal (struct rsp_buf *buf)
{
printf ("RSP step with signal '%s' received\n", buf->data);
 
} /* rsp_step_with_signal () */
 
 
/*---------------------------------------------------------------------------*/
/*!Generic processing of a step request
 
The signal may be EXCEPT_NONE if there is no exception to be
handled. Currently the exception is ignored.
 
The single step flag is set in the debug registers and then the processor
is unstalled.
 
@param[in] addr Address from which to step
@param[in] except The exception to use (if any) */
/*---------------------------------------------------------------------------*/
static void
rsp_step_generic (unsigned long int addr,
unsigned long int except)
{
printf ("Stepping from %lx\n", addr);
fflush (stdout);
 
/* Set the address as the value of the next program counter */
set_npc (addr);
 
/* Clear Debug Reason Register and watchpoint break generation in Debug Mode
Register 2 */
cpu_state.sprs[SPR_DRR] = 0;
cpu_state.sprs[SPR_DMR2] &= ~SPR_DMR2_WGB;
 
/* Set the single step trigger in Debug Mode Register 1 and set traps to be
handled by the debug unit in the Debug Stop Register */
cpu_state.sprs[SPR_DMR1] |= SPR_DMR1_ST;
cpu_state.sprs[SPR_DSR] |= SPR_DSR_TE;
 
/* Unstall the processor */
set_stall_state (0);
 
/* Note the GDB client is now waiting for a reply. */
rsp.client_waiting = 1;
 
} /* rsp_step_generic () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP 'v' packet
 
These are commands associated with executing the code on the target
 
@param[in] buf The request */
/*---------------------------------------------------------------------------*/
static void
rsp_vpkt (struct rsp_buf *buf)
{
if (0 == strncmp ("vAttach;", buf->data, strlen ("vAttach;")))
{
/* Attaching is a null action, since we have no other process. We just
return a stop packet (using TRAP) to indicate we are stopped. */
put_str_packet ("S05");
return;
}
else if (0 == strcmp ("vCont?", buf->data))
{
/* For now we don't support this. */
put_str_packet ("");
return;
}
else if (0 == strncmp ("vCont", buf->data, strlen ("vCont")))
{
/* This shouldn't happen, because we've reported non-support via vCont?
above */
fprintf (stderr, "Warning: RSP vCont not supported: ignored\n" );
return;
}
else if (0 == strncmp ("vFile:", buf->data, strlen ("vFile:")))
{
/* For now we don't support this. */
fprintf (stderr, "Warning: RSP vFile not supported: ignored\n" );
put_str_packet ("");
return;
}
else if (0 == strncmp ("vFlashErase:", buf->data, strlen ("vFlashErase:")))
{
/* For now we don't support this. */
fprintf (stderr, "Warning: RSP vFlashErase not supported: ignored\n" );
put_str_packet ("E01");
return;
}
else if (0 == strncmp ("vFlashWrite:", buf->data, strlen ("vFlashWrite:")))
{
/* For now we don't support this. */
fprintf (stderr, "Warning: RSP vFlashWrite not supported: ignored\n" );
put_str_packet ("E01");
return;
}
else if (0 == strcmp ("vFlashDone", buf->data))
{
/* For now we don't support this. */
fprintf (stderr, "Warning: RSP vFlashDone not supported: ignored\n" );
put_str_packet ("E01");
return;
}
else if (0 == strncmp ("vRun;", buf->data, strlen ("vRun;")))
{
/* We shouldn't be given any args, but check for this */
if (buf->len > strlen ("vRun;"))
{
fprintf (stderr, "Warning: Unexpected arguments to RSP vRun "
"command: ignored\n");
}
 
/* Restart the current program. However unlike a "R" packet, "vRun"
should behave as though it has just stopped. We use signal
5 (TRAP). */
rsp_restart ();
put_str_packet ("S05");
}
else
{
fprintf (stderr, "Warning: Unknown RSP 'v' packet type %s: ignored\n",
buf->data);
put_str_packet ("E01");
return;
}
} /* rsp_vpkt () */
 
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP write memory (binary) request
 
Syntax is:
 
X<addr>,<length>:
 
Followed by the specified number of bytes as raw binary. Response should be
"OK" if all copied OK, E<nn> if error <nn> has occurred.
 
The length given is the number of bytes to be written. However the number
of data bytes may be greater, since '#', '$' and '}' are escaped by
preceding them by '}' and oring with 0x20.
 
@param[in] buf The command received */
/*---------------------------------------------------------------------------*/
static void
rsp_write_mem_bin (struct rsp_buf *buf)
{
unsigned int addr; /* Where to write the memory */
int len; /* Number of bytes to write */
char *bindat; /* Pointer to the binary data */
int off; /* Offset to start of binary data */
int newlen; /* Number of bytes in bin data */
 
if (2 != sscanf (buf->data, "X%x,%x:", &addr, &len))
{
fprintf (stderr, "Warning: Failed to recognize RSP write memory "
"command: %s\n", buf->data);
put_str_packet ("E01");
return;
}
 
/* Find the start of the data and "unescape" it */
bindat = memchr ((const void *)buf->data, ':', GDB_BUF_MAX) + 1;
off = bindat - buf->data;
newlen = rsp_unescape (bindat, buf->len - off);
 
/* Sanity check */
if (newlen != len)
{
int minlen = len < newlen ? len : newlen;
 
fprintf (stderr, "Warning: Write of %d bytes requested, but %d bytes "
"supplied. %d will be written\n", len, newlen, minlen);
len = minlen;
}
 
/* Write the bytes to memory */
for (off = 0; off < len; off++)
{
if (NULL == verify_memoryarea (addr + off))
{
/* The error number doesn't matter. The GDB client will substitute
its own */
put_str_packet ("E01");
return;
}
else
{
// circumvent the read-only check usually done for mem accesses
// data is in host order, because that's what set_direct32 needs
set_program8 (addr + off, bindat[off]);
}
}
 
put_str_packet ("OK");
 
} /* rsp_write_mem_bin () */
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP remove breakpoint or matchpoint request
 
For now only memory breakpoints are implemented, which are implemented by
substituting a breakpoint at the specified address. The implementation must
cope with the possibility of duplicate packets.
 
@todo This doesn't work with icache/immu yet
 
@param[in] buf The command received */
/*---------------------------------------------------------------------------*/
static void
rsp_remove_matchpoint (struct rsp_buf *buf)
{
enum mp_type type; /* What sort of matchpoint */
unsigned long int addr; /* Address specified */
int len; /* Matchpoint length (not used) */
struct mp_entry *mpe; /* Info about the replaced instr */
 
/* Break out the instruction */
if (3 != sscanf (buf->data, "z%1d,%lx,%1d", (int *)&type, &addr, &len))
{
fprintf (stderr, "Warning: RSP matchpoint deletion request not "
"recognized: ignored\n");
put_str_packet ("E01");
return;
}
 
/* Sanity check that the length is 4 */
if (4 != len)
{
fprintf (stderr, "Warning: RSP matchpoint deletion length %d not "
"valid: 4 assumed\n", len);
len = 4;
}
 
/* Sort out the type of matchpoint */
switch (type)
{
case BP_MEMORY:
/* Memory breakpoint - replace the original instruction. */
mpe = mp_hash_delete (type, addr);
 
/* If the BP hasn't yet been deleted, put the original instruction
back. Don't forget to free the hash table entry afterwards. */
if (NULL != mpe)
{
set_program32 (addr, mpe->instr);
free (mpe);
}
 
put_str_packet ("OK");
 
return;
case BP_HARDWARE:
put_str_packet (""); /* Not supported */
return;
 
case WP_WRITE:
put_str_packet (""); /* Not supported */
return;
 
case WP_READ:
put_str_packet (""); /* Not supported */
return;
 
case WP_ACCESS:
put_str_packet (""); /* Not supported */
return;
 
default:
fprintf (stderr, "Warning: RSP matchpoint type %d not "
"recognized: ignored\n", type);
put_str_packet ("E01");
return;
 
}
} /* rsp_remove_matchpoint () */
 
/*---------------------------------------------------------------------------*/
/*!Handle a RSP insert breakpoint or matchpoint request
 
For now only memory breakpoints are implemented, which are implemented by
substituting a breakpoint at the specified address. The implementation must
cope with the possibility of duplicate packets.
 
@todo This doesn't work with icache/immu yet
 
@param[in] buf The command received */
/*---------------------------------------------------------------------------*/
static void
rsp_insert_matchpoint (struct rsp_buf *buf)
{
enum mp_type type; /* What sort of matchpoint */
unsigned long int addr; /* Address specified */
int len; /* Matchpoint length (not used) */
 
/* Break out the instruction */
if (3 != sscanf (buf->data, "Z%1d,%lx,%1d", (int *)&type, &addr, &len))
{
fprintf (stderr, "Warning: RSP matchpoint insertion request not "
"recognized: ignored\n");
put_str_packet ("E01");
return;
}
 
/* Sanity check that the length is 4 */
if (4 != len)
{
fprintf (stderr, "Warning: RSP matchpoint insertion length %d not "
"valid: 4 assumed\n", len);
len = 4;
}
 
/* Sort out the type of matchpoint */
switch (type)
{
case BP_MEMORY:
/* Memory breakpoint - substitute a TRAP instruction */
mp_hash_add (type, addr, eval_direct32 (addr, 0, 0));
set_program32 (addr, OR1K_TRAP_INSTR);
put_str_packet ("OK");
 
return;
case BP_HARDWARE:
put_str_packet (""); /* Not supported */
return;
 
case WP_WRITE:
put_str_packet (""); /* Not supported */
return;
 
case WP_READ:
put_str_packet (""); /* Not supported */
return;
 
case WP_ACCESS:
put_str_packet (""); /* Not supported */
return;
 
default:
fprintf (stderr, "Warning: RSP matchpoint type %d not "
"recognized: ignored\n", type);
put_str_packet ("E01");
return;
 
}
 
} /* rsp_insert_matchpoint () */
/trunk/or1ksim/debug/rsp-server.h
0,0 → 1,35
/* rsp-server.c -- Remote Serial Protocol server for GDB
 
Copyright (C) 2008 Embecosm Limited
 
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
 
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
 
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>. */
 
/* This program is commented throughout in a fashion suitable for processing
with Doxygen. */
 
 
#ifndef RSP_SERVER__H
#define RSP_SERVER__H
 
 
/* Function prototypes for external use */
extern void rsp_init ();
extern void handle_rsp ();
extern void rsp_exception (unsigned long int except);
 
#endif /* RSP_SERVER__H */
/trunk/or1ksim/toplevel-mprofile.c
19,12 → 19,22
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>. */
 
/* This program is commented throughout in a fashion suitable for processing
with Doxygen. */
 
/* Main program for standalone memory profiling simulator */
 
 
/* Autoconf and/or portability configuration */
#include "config.h"
 
/* System includes */
#include <stdlib.h>
#include <sys/types.h>
#include <unistd.h>
 
#include "config.h"
/* Package includes */
#include "sim-config.h"
#include "mprofiler.h"
 
 
/trunk/or1ksim/cpu/or32/def_op_t.h File deleted
/trunk/or1ksim/cpu/or32/Makefile.in
69,7 → 69,7
CONFIG_CLEAN_FILES =
LTLIBRARIES = $(noinst_LTLIBRARIES)
libarch_la_LIBADD =
am__libarch_la_SOURCES_DIST = execute.c insnset.c or32.c common-i386.h \
am__libarch_la_SOURCES_DIST = execute.c or32.c common-i386.h \
dyn32-defs.h dyngen.h dyn-rec.h i386-regs.h op-arith-op.h \
op-comp-op.h op-extend-op.h op-ff1-op.h op-i386.h op-lwhb-op.h \
op-mac-op.h op-mftspr-op.h op-support.h op-swhb-op.h \
77,7 → 77,6
dyn-rec.c op-support.c
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_FALSE@am_libarch_la_OBJECTS = \
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_FALSE@ execute.lo \
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_FALSE@ insnset.lo \
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_FALSE@ or32.lo
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_TRUE@am_libarch_la_OBJECTS = \
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_TRUE@ execute.lo \
86,20 → 85,11
@DYNAMIC_EXECUTION_TRUE@ op.lo dyn-rec.lo op-support.lo
@DYNAMIC_EXECUTION_TRUE@nodist_libarch_la_OBJECTS = gen-ops.lo \
@DYNAMIC_EXECUTION_TRUE@ gen-ops-gen.lo gen-ops-rel.lo
am__dist_EXTRA_libarch_la_SOURCES_DIST = insnset.c
libarch_la_OBJECTS = $(am_libarch_la_OBJECTS) \
$(nodist_libarch_la_OBJECTS)
@DYNAMIC_EXECUTION_FALSE@am_libarch_la_rpath =
@DYNAMIC_EXECUTION_TRUE@am_libarch_la_rpath =
libop_la_LIBADD =
am__libop_la_SOURCES_DIST = op.c op-t-reg-mov-op.h op-i386.h \
op-arith-op.h op-comp-op.h op-extend-op.h op-mac-op.h \
op-mftspr-op.h op-lwhb-op.h op-swhb-op.h
@DYNAMIC_EXECUTION_TRUE@am_libop_la_OBJECTS = libop_la-op.lo
libop_la_OBJECTS = $(am_libop_la_OBJECTS)
libop_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \
--mode=link $(CCLD) $(libop_la_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
$(LDFLAGS) -o $@
@DYNAMIC_EXECUTION_TRUE@am_libop_la_rpath =
PROGRAMS = $(noinst_PROGRAMS)
am__dyngen_SOURCES_DIST = dyngen.c dyngen-i386.c dyngen-elf.c \
common-i386.h dyn32-defs.h dyngen.h dyn-rec.h i386-regs.h \
140,10 → 130,11
--mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
$(LDFLAGS) -o $@
SOURCES = $(libarch_la_SOURCES) $(nodist_libarch_la_SOURCES) \
$(libop_la_SOURCES) $(dyngen_SOURCES) $(generate_SOURCES)
$(dist_EXTRA_libarch_la_SOURCES) $(dyngen_SOURCES) \
$(generate_SOURCES)
DIST_SOURCES = $(am__libarch_la_SOURCES_DIST) \
$(am__libop_la_SOURCES_DIST) $(am__dyngen_SOURCES_DIST) \
$(am__generate_SOURCES_DIST)
$(am__dist_EXTRA_libarch_la_SOURCES_DIST) \
$(am__dyngen_SOURCES_DIST) $(am__generate_SOURCES_DIST)
ETAGS = etags
CTAGS = ctags
DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
270,33 → 261,8
top_builddir = @top_builddir@
top_srcdir = @top_srcdir@
@DYNAMIC_EXECUTION_FALSE@noinst_LTLIBRARIES = libarch.la
@DYNAMIC_EXECUTION_TRUE@noinst_LTLIBRARIES = libarch.la libop.la
@DYNAMIC_EXECUTION_TRUE@dyngen_SOURCES = dyngen.c \
@DYNAMIC_EXECUTION_TRUE@ dyngen-i386.c \
@DYNAMIC_EXECUTION_TRUE@ dyngen-elf.c \
@DYNAMIC_EXECUTION_TRUE@ common-i386.h \
@DYNAMIC_EXECUTION_TRUE@ dyn32-defs.h \
@DYNAMIC_EXECUTION_TRUE@ dyngen.h \
@DYNAMIC_EXECUTION_TRUE@ dyn-rec.h \
@DYNAMIC_EXECUTION_TRUE@ i386-regs.h \
@DYNAMIC_EXECUTION_TRUE@ op-arith-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-comp-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-extend-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-ff1-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-i386.h \
@DYNAMIC_EXECUTION_TRUE@ op-lwhb-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-mac-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-mftspr-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-support.h \
@DYNAMIC_EXECUTION_TRUE@ op-swhb-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-t-reg-mov-op.h \
@DYNAMIC_EXECUTION_TRUE@ rec-i386.h \
@DYNAMIC_EXECUTION_TRUE@ sched-i386.h \
@DYNAMIC_EXECUTION_TRUE@ simpl32-defs.h
 
@DYNAMIC_EXECUTION_TRUE@dyngen_CFLAGS = $(AM_CFLAGS)
@DYNAMIC_EXECUTION_TRUE@noinst_LTLIBRARIES = libarch.la
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_FALSE@libarch_la_SOURCES = execute.c \
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_FALSE@ insnset.c \
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_FALSE@ or32.c \
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_FALSE@ common-i386.h \
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_FALSE@ dyn32-defs.h \
372,21 → 338,35
 
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_TRUE@BUILT_SOURCES = execgen.c
@DYNAMIC_EXECUTION_TRUE@BUILT_SOURCES = gen-ops.h \
@DYNAMIC_EXECUTION_TRUE@ gen-ops.c \
@DYNAMIC_EXECUTION_TRUE@ gen-ops-gen.c \
@DYNAMIC_EXECUTION_TRUE@ gen-ops-rel.c
@DYNAMIC_EXECUTION_TRUE@ gen-ops.c \
@DYNAMIC_EXECUTION_TRUE@ gen-ops-gen.c \
@DYNAMIC_EXECUTION_TRUE@ gen-ops-rel.c
 
@DYNAMIC_EXECUTION_TRUE@libop_la_SOURCES = op.c \
@DYNAMIC_EXECUTION_TRUE@ op-t-reg-mov-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-i386.h op-arith-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-comp-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-extend-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-mac-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-mftspr-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-lwhb-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-swhb-op.h
@DYNAMIC_EXECUTION_TRUE@dyngen_SOURCES = dyngen.c \
@DYNAMIC_EXECUTION_TRUE@ dyngen-i386.c \
@DYNAMIC_EXECUTION_TRUE@ dyngen-elf.c \
@DYNAMIC_EXECUTION_TRUE@ common-i386.h \
@DYNAMIC_EXECUTION_TRUE@ dyn32-defs.h \
@DYNAMIC_EXECUTION_TRUE@ dyngen.h \
@DYNAMIC_EXECUTION_TRUE@ dyn-rec.h \
@DYNAMIC_EXECUTION_TRUE@ i386-regs.h \
@DYNAMIC_EXECUTION_TRUE@ op-arith-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-comp-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-extend-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-ff1-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-i386.h \
@DYNAMIC_EXECUTION_TRUE@ op-lwhb-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-mac-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-mftspr-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-support.h \
@DYNAMIC_EXECUTION_TRUE@ op-swhb-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-t-reg-mov-op.h \
@DYNAMIC_EXECUTION_TRUE@ rec-i386.h \
@DYNAMIC_EXECUTION_TRUE@ sched-i386.h \
@DYNAMIC_EXECUTION_TRUE@ simpl32-defs.h
 
@DYNAMIC_EXECUTION_TRUE@libop_la_CFLAGS = -Wall -fomit-frame-pointer -fno-reorder-blocks -O2
@DYNAMIC_EXECUTION_TRUE@dyngen_CFLAGS = $(AM_CFLAGS)
@DYNAMIC_EXECUTION_TRUE@OP_CFLAGS = -Wall -fomit-frame-pointer -fno-reorder-blocks -O2
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_TRUE@EXTRA_DIST = insnset.c
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_TRUE@generate_SOURCES = or32.c \
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_TRUE@ generate.c \
411,6 → 391,7
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_TRUE@ simpl32-defs.h
 
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_TRUE@generate_CFLAGS = $(AM_CFLAGS)
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_FALSE@dist_EXTRA_libarch_la_SOURCES = insnset.c
 
# If the simulator was first built without --enable-simple and then with it,
# then also remove these two files
466,8 → 447,6
done
libarch.la: $(libarch_la_OBJECTS) $(libarch_la_DEPENDENCIES)
$(LINK) $(am_libarch_la_rpath) $(libarch_la_OBJECTS) $(libarch_la_LIBADD) $(LIBS)
libop.la: $(libop_la_OBJECTS) $(libop_la_DEPENDENCIES)
$(libop_la_LINK) $(am_libop_la_rpath) $(libop_la_OBJECTS) $(libop_la_LIBADD) $(LIBS)
 
clean-noinstPROGRAMS:
@list='$(noinst_PROGRAMS)'; for p in $$list; do \
499,7 → 478,6
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/generate-generate.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/generate-or32.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insnset.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libop_la-op.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/op-support.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/op.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or32.Plo@am__quote@
525,13 → 503,6
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(LTCOMPILE) -c -o $@ $<
 
libop_la-op.lo: op.c
@am__fastdepCC_TRUE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libop_la_CFLAGS) $(CFLAGS) -MT libop_la-op.lo -MD -MP -MF $(DEPDIR)/libop_la-op.Tpo -c -o libop_la-op.lo `test -f 'op.c' || echo '$(srcdir)/'`op.c
@am__fastdepCC_TRUE@ mv -f $(DEPDIR)/libop_la-op.Tpo $(DEPDIR)/libop_la-op.Plo
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='op.c' object='libop_la-op.lo' libtool=yes @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libop_la_CFLAGS) $(CFLAGS) -c -o libop_la-op.lo `test -f 'op.c' || echo '$(srcdir)/'`op.c
 
dyngen-dyngen.o: dyngen.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(dyngen_CFLAGS) $(CFLAGS) -MT dyngen-dyngen.o -MD -MP -MF $(DEPDIR)/dyngen-dyngen.Tpo -c -o dyngen-dyngen.o `test -f 'dyngen.c' || echo '$(srcdir)/'`dyngen.c
@am__fastdepCC_TRUE@ mv -f $(DEPDIR)/dyngen-dyngen.Tpo $(DEPDIR)/dyngen-dyngen.Po
789,9 → 760,14
tags uninstall uninstall-am
 
 
@DYNAMIC_EXECUTION_TRUE@gen-ops.h gen-ops.c gen-ops-gen.c gen-ops-rel.c: dyngen$(EXEEXT) op.lo
@DYNAMIC_EXECUTION_TRUE@ ./dyngen$(EXEEXT) op.lo gen-ops.c gen-ops-gen.c gen-ops-rel.c gen-ops.h
@DYNAMIC_EXECUTION_TRUE@gen-ops.h gen-ops.c gen-ops-gen.c gen-ops-rel.c: dyngen$(EXEEXT) op-tmp.o
@DYNAMIC_EXECUTION_TRUE@ ./dyngen$(EXEEXT) op-tmp.o gen-ops.c gen-ops-gen.c gen-ops-rel.c gen-ops.h
 
@DYNAMIC_EXECUTION_TRUE@op-tmp.o: op.c op-t-reg-mov-op.h op-i386.h op-arith-op.h op-comp-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-extend-op.h op-ff1-op.h op-mac-op.h op-mftspr-op.h op-lwhb-op.h \
@DYNAMIC_EXECUTION_TRUE@ op-swhb-op.h
@DYNAMIC_EXECUTION_TRUE@ $(CC) $(INCLUDES) -I$(top_builddir) $(OP_CFLAGS) -o $@ -c $<
 
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_TRUE@execgen.c: generate$(EXEEXT) insnset.c
@DYNAMIC_EXECUTION_FALSE@@GENERATE_NEEDED_TRUE@ ./generate$(EXEEXT) $(srcdir)/insnset.c execgen.c
# Tell versions [3.59,3.63) of GNU make to not export all variables.
/trunk/or1ksim/cpu/or32/op-mftspr-op.h
24,10 → 24,6
with Doxygen. */
 
 
#ifndef OP_MFTSPR_OP__H
#define OP_MFTSPR_OP__H
 
 
#ifdef OP_2T
__or_dynop void glue (op_mfspr, T) (void)
{
79,4 → 75,4
if (env->sprs[SPR_SR] & SPR_SR_SM)
mtspr (OP_PARAM1, 0);
}
#endif /* OP_MFTSPR_OP__H */
#endif
/trunk/or1ksim/cpu/or32/op.c
30,7 → 30,7
 
#include "port.h"
#include "arch.h"
#include "spr_defs.h"
#include "spr-defs.h"
#include "opcode/or32.h"
#include "sim-config.h"
#include "except.h"
40,15 → 40,15
#include "sched.h"
#include "immu.h"
 
#include "op_support.h"
#include "op-support.h"
 
#include "i386_regs.h"
#include "i386-regs.h"
 
#include "dyn_rec.h"
#include "dyn-rec.h"
 
register struct cpu_state *env asm(CPU_STATE_REG);
 
#include "op_i386.h"
#include "op-i386.h"
 
/*
* WARNING: Before going of and wildly editing everything in this file remember
492,25 → 492,25
env->delay_insn = 1;
}
 
#define OP_FILE "op_1t_op.h"
#include "op_1t.h"
#define OP_FILE "op-1t-op.h"
#include "op-1t.h"
#undef OP_FILE
 
#define OP_FILE "op_2t_op.h"
#include "op_2t.h"
#define OP_FILE "op-2t-op.h"
#include "op-2t.h"
#undef OP_FILE
 
#define OP_FILE "op_3t_op.h"
#include "op_3t.h"
#define OP_FILE "op-3t-op.h"
#include "op-3t.h"
#undef OP_FILE
 
#define OP_FILE "op_arith_op.h"
#define OP_FILE "op-arith-op.h"
#define OP_EXTRA
 
#define OP /
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME div
#include "op_3t.h"
#include "op-3t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
518,7 → 518,7
#define OP /
#define OP_CAST(x) (x)
#define OP_NAME divu
#include "op_3t.h"
#include "op-3t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
526,7 → 526,7
#define OP *
#define OP_CAST(x) (x)
#define OP_NAME mulu
#include "op_3t.h"
#include "op-3t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
534,7 → 534,7
#define OP -
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME sub
#include "op_3t.h"
#include "op-3t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
545,8 → 545,8
#define OP +
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME addc
#include "op_3t.h"
#include "op_2t.h"
#include "op-3t.h"
#include "op-2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
557,8 → 557,8
#define OP +
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME add
#include "op_3t.h"
#include "op_2t.h"
#include "op-3t.h"
#include "op-2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
566,8 → 566,8
#define OP &
#define OP_CAST(x) (x)
#define OP_NAME and
#include "op_3t.h"
#include "op_2t.h"
#include "op-3t.h"
#include "op-2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
575,8 → 575,8
#define OP *
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME mul
#include "op_3t.h"
#include "op_2t.h"
#include "op-3t.h"
#include "op-2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
584,8 → 584,8
#define OP |
#define OP_CAST(x) (x)
#define OP_NAME or
#include "op_3t.h"
#include "op_2t.h"
#include "op-3t.h"
#include "op-2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
593,8 → 593,8
#define OP <<
#define OP_CAST(x) (x)
#define OP_NAME sll
#include "op_3t.h"
#include "op_2t.h"
#include "op-3t.h"
#include "op-2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
602,8 → 602,8
#define OP >>
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME sra
#include "op_3t.h"
#include "op_2t.h"
#include "op-3t.h"
#include "op-2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
611,8 → 611,8
#define OP >>
#define OP_CAST(x) (x)
#define OP_NAME srl
#include "op_3t.h"
#include "op_2t.h"
#include "op-3t.h"
#include "op-2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
620,8 → 620,8
#define OP ^
#define OP_CAST(x) (x)
#define OP_NAME xor
#include "op_3t.h"
#include "op_2t.h"
#include "op-3t.h"
#include "op-2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
629,12 → 629,12
#undef OP_EXTRA
#undef OP_FILE
 
#define OP_FILE "op_extend_op.h"
#define OP_FILE "op-extend-op.h"
 
#define EXT_NAME extbs
#define EXT_TYPE int8_t
#define EXT_CAST (orreg_t)
#include "op_2t.h"
#include "op-2t.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
642,7 → 642,7
#define EXT_NAME extbz
#define EXT_TYPE uint8_t
#define EXT_CAST (uorreg_t)
#include "op_2t.h"
#include "op-2t.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
650,7 → 650,7
#define EXT_NAME exths
#define EXT_TYPE int16_t
#define EXT_CAST (orreg_t)
#include "op_2t.h"
#include "op-2t.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
658,7 → 658,7
#define EXT_NAME exthz
#define EXT_TYPE uint16_t
#define EXT_CAST (uorreg_t)
#include "op_2t.h"
#include "op-2t.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
665,13 → 665,13
 
#undef OP_FILE
 
#define OP_FILE "op_comp_op.h"
#define OP_FILE "op-comp-op.h"
 
#define COMP ==
#define COMP_NAME sfeq
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
679,8 → 679,8
#define COMP !=
#define COMP_NAME sfne
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
688,8 → 688,8
#define COMP >
#define COMP_NAME sfgtu
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
697,8 → 697,8
#define COMP >=
#define COMP_NAME sfgeu
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
706,8 → 706,8
#define COMP <
#define COMP_NAME sfltu
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
715,8 → 715,8
#define COMP <=
#define COMP_NAME sfleu
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
724,8 → 724,8
#define COMP >
#define COMP_NAME sfgts
#define COMP_CAST(x) (orreg_t)(x)
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
733,8 → 733,8
#define COMP >=
#define COMP_NAME sfges
#define COMP_CAST(x) (orreg_t)(x)
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
742,8 → 742,8
#define COMP <
#define COMP_NAME sflts
#define COMP_CAST(x) (orreg_t)(x)
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
751,8 → 751,8
#define COMP <=
#define COMP_NAME sfles
#define COMP_CAST(x) (orreg_t)(x)
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
759,39 → 759,39
 
#undef OP_FILE
 
#define OP_FILE "op_t_reg_mov_op.h"
#include "op_1t.h"
#define OP_FILE "op-t-reg-mov-op.h"
#include "op-1t.h"
#undef OP_FILE
 
#define OP_FILE "op_mftspr_op.h"
#include "op_1t.h"
#include "op_2t.h"
#define OP_FILE "op-mftspr-op.h"
#include "op-1t.h"
#include "op-2t.h"
#undef OP_FILE
#include "op_mftspr_op.h"
#include "op-mftspr-op.h"
 
#define OP_FILE "op_mac_op.h"
#define OP_FILE "op-mac-op.h"
 
#define OP +=
#define OP_NAME mac
#include "op_2t.h"
#include "op-2t.h"
#undef OP_NAME
#undef OP
 
#define OP -=
#define OP_NAME msb
#include "op_2t.h"
#include "op-2t.h"
#undef OP_NAME
#undef OP
 
#undef OP_FILE
 
#define OP_FILE "op_lwhb_op.h"
#define OP_FILE "op-lwhb-op.h"
 
#define LS_OP_NAME lbz
#define LS_OP_CAST
#define LS_OP_FUNC eval_mem8
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
799,8 → 799,8
#define LS_OP_NAME lbs
#define LS_OP_CAST (int8_t)
#define LS_OP_FUNC eval_mem8
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
808,8 → 808,8
#define LS_OP_NAME lhz
#define LS_OP_CAST
#define LS_OP_FUNC eval_mem16
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
817,8 → 817,8
#define LS_OP_NAME lhs
#define LS_OP_CAST (int16_t)
#define LS_OP_FUNC eval_mem16
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
826,8 → 826,8
#define LS_OP_NAME lwz
#define LS_OP_CAST
#define LS_OP_FUNC eval_mem32
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
835,8 → 835,8
#define LS_OP_NAME lws
#define LS_OP_CAST (int32_t)
#define LS_OP_FUNC eval_mem32
#include "op_2t.h"
#include "op_1t.h"
#include "op-2t.h"
#include "op-1t.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
843,29 → 843,29
 
#undef OP_FILE
 
#define OP_FILE "op_swhb_op.h"
#define OP_FILE "op-swhb-op.h"
 
#define S_OP_NAME sb
#define S_FUNC set_mem8
#include "op_swhb_op.h"
#include "op_2t.h"
#include "op_1t.h"
#include "op-swhb-op.h"
#include "op-2t.h"
#include "op-1t.h"
#undef S_FUNC
#undef S_OP_NAME
 
#define S_OP_NAME sh
#define S_FUNC set_mem16
#include "op_swhb_op.h"
#include "op_2t.h"
#include "op_1t.h"
#include "op-swhb-op.h"
#include "op-2t.h"
#include "op-1t.h"
#undef S_FUNC
#undef S_OP_NAME
 
#define S_OP_NAME sw
#define S_FUNC set_mem32
#include "op_swhb_op.h"
#include "op_2t.h"
#include "op_1t.h"
#include "op-swhb-op.h"
#include "op-2t.h"
#include "op-1t.h"
#undef S_FUNC
#undef S_OP_NAME
 
/trunk/or1ksim/cpu/or32/dyn32-defs.h
1,23 → 1,37
/* dyn32-defs.h -- Definitions for the dynamic execution model
 
 
Copyright (C) 2008 Embecosm Limited
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
This file is part of OpenRISC 1000 Architectural Simulator.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>. */
 
This file is part of OpenRISC 1000 Architectural Simulator.
/* This program is commented throughout in a fashion suitable for processing
with Doxygen. */
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
#ifndef DYN32_DEFS__H
#define DYN32_DEFS__H
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* Package includes */
#include "arch.h"
 
 
struct op_queue {
unsigned int num_ops;
unsigned int ops_len;
121,3 → 135,5
void gen_lf_sub_s PARAMS((struct op_queue *, int *, int));
void l_none(struct op_queue *opq, int *param_t, int delay_slot);
 
#endif /* DYN32_DEFS__H */
 
/trunk/or1ksim/cpu/or32/op-support.c
36,12 → 36,12
#include "abstract.h"
#include "execute.h"
#include "sched.h"
 
#include "i386-regs.h"
 
#include "dyn-rec.h"
#include "op-support.h"
#include "simprintf.h"
 
 
/* Stuff that is really a `micro' operation but is rather big (or for some other
* reason like calling exit()) */
 
/trunk/or1ksim/cpu/or32/op-swhb-op.h
26,9 → 26,6
/* FIXME: Do something with breakpoint */
 
 
#ifndef OP_SWHB_OP__H
#define OP_SWHB_OP__H
 
#ifdef OP_2T
__or_dynop void glue (glue (op_, S_OP_NAME), T) (void)
{
58,5 → 55,3
S_FUNC (OP_PARAM1, 0, &breakpoint);
}
#endif
 
#endif /* OP_SWHB_OP__H */
/trunk/or1ksim/cpu/or32/dyn-rec.c
42,15 → 42,14
#include "spr-defs.h"
#include "sim-config.h"
#include "sched.h"
 
#include "i386-regs.h"
 
#include "def-op-t.h"
#include "dyn-rec.h"
#include "gen-ops.h"
 
#include "op-support.h"
#include "toplevel-support.h"
 
 
/* NOTE: All openrisc (or) addresses in this file are *PHYSICAL* addresses */
 
/* FIXME: Optimise sorted list adding */
1073,7 → 1072,9
return;
}
 
if((opq->param[0] == opq->param[1] == opq->param[2]) && (param_t[2] != T_NONE))
if((opq->param[0] == opq->param[1]) &&
(opq->param[0] == opq->param[2]) &&
(param_t[2] != T_NONE))
return;
 
if(param_t[2] == T_NONE)
1728,7 → 1729,9
if(!opq->param[0])
return;
 
if((opq->param[0] == opq->param[1] == opq->param[2]) && (param_t[2] != T_NONE))
if((opq->param[0] == opq->param[1]) &&
(opq->param[0] == opq->param[2]) &&
(param_t[2] != T_NONE))
return;
 
if(!opq->param[1] && !opq->param[2]) {
/trunk/or1ksim/cpu/or32/execute.c
54,28 → 54,23
#include "branch-predict.h"
#include "support/simprintf.h"
#include "sprs.h"
#include "rsp-server.h"
 
 
/* Sets a new SPR_SR_OV value, based on next register value */
#if SET_OV_FLAG
#define SET_OV_FLAG_FN(value) \
if((value) & 0x80000000) \
cpu_state.sprs[SPR_SR] |= SPR_SR_OV; \
else \
cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV
#else
#define SET_OV_FLAG_FN(value)
#endif
/* Includes and macros for simple execution */
#if SIMPLE_EXECUTION
 
/* Macros for simple execution */
#if SIMPLE_EXECUTION
#define SET_PARAM0(val) set_operand(0, val, current->insn_index, current->insn)
 
#define PARAM0 eval_operand(0, current->insn_index, current->insn)
#define PARAM1 eval_operand(1, current->insn_index, current->insn)
#define PARAM2 eval_operand(2, current->insn_index, current->insn)
#endif
 
#define INSTRUCTION(name) void name (struct iqueue_entry *current)
 
#endif /* SIMPLE_EXECUTION */
 
 
/*! Current cpu state. Globally available. */
struct cpu_state cpu_state;
 
103,16 → 98,20
static int sbuf_head = 0;
static int sbuf_tail = 0;
static int sbuf_count = 0;
#if !(DYNAMIC_EXECUTION)
static int sbuf_buf[MAX_SBUF_LEN] = { 0 };
#endif
 
static int sbuf_prev_cycles = 0;
 
/* Local data needed for execution. */
static int next_delay_insn;
static int breakpoint;
/* Variables used throughout this file to share information */
static int breakpoint;
static int next_delay_insn;
 
/* Forward declaration of static functions */
#if !(DYNAMIC_EXECUTION)
static void decode_execute (struct iqueue_entry *current);
#endif
 
/*---------------------------------------------------------------------------*/
/*!Get an actual value of a specific register
132,7 → 131,7
#if RAW_RANGE_STATS
int delta = (runtime.sim.cycles - raw_stats.reg[regno]);
 
if ((unsigned long) delta < (unsigned long) MAX_RAW_RANGE)
if ((unsigned long) delta < (unsigned long) RAW_RANGE)
{
raw_stats.range[delta]++;
}
484,6 → 483,9
 
} /* analysis() */
 
 
#if !(DYNAMIC_EXECUTION)
 
/*---------------------------------------------------------------------------*/
/*!Store buffer analysis for store instructions
 
565,7 → 567,9
}
} /* sbuf_load() */
 
#endif /* !DYNAMIC_EXECUTION */
 
 
/*---------------------------------------------------------------------------*/
/*!Outputs dissasembled instruction */
/*---------------------------------------------------------------------------*/
683,7 → 687,7
}
if (or32_opcodes[cpu_state.iqueue.insn_index].flags & OR32_R_FLAG)
{
fprintf (runtime.sim.fexe_log, "SR =%08x ",
fprintf (runtime.sim.fexe_log, "SR =%" PRIxREG " ",
cpu_state.sprs[SPR_SR]);
j++;
}
952,17 → 956,21
{
while (runtime.cpu.stalled)
{
if (config.debug.gdb_enabled)
if (config.debug.rsp_enabled)
{
handle_rsp ();
}
else if (config.debug.gdb_enabled)
{
block_jtag ();
handle_server_socket (FALSE);
}
else
{
fprintf (stderr,
"WARNING: CPU stalled and gdb connection not enabled.\n");
/* Dump the user into interactive mode. From there he can decide what
* to do. */
fprintf (stderr, "ERROR: CPU stalled and GDB connection not "
"enabled: Invoking CLI and terminating.\n");
/* Dump the user into interactive mode. From there he or
she can decide what to do. */
handle_sim_command ();
sim_done ();
}
1002,6 → 1010,11
if (cpu_state.sprs[SPR_DMR1] & SPR_DMR1_ST)
{
set_stall_state (1);
 
if (config.debug.rsp_enabled)
{
rsp_exception (EXCEPT_TRAP);
}
}
}
 
1023,8 → 1036,6
#elif SIMPLE_EXECUTION
 
 
#define INSTRUCTION(name) void name (struct iqueue_entry *current)
 
/*---------------------------------------------------------------------------*/
/*!Evaluates source operand
 
/trunk/or1ksim/cpu/or32/op-arith-op.h
20,7 → 20,7
#ifdef OP_3T
__or_dynop void glue(glue(op_, OP_NAME), T)(void)
{
OP_CAST(T0) = OP_CAST(T1) OP OP_CAST(T2) OP_EXTRA;
T0 = OP_CAST(T1) OP OP_CAST(T2) OP_EXTRA;
}
#endif
 
27,7 → 27,7
#ifdef OP_2T
__or_dynop void glue(glue(glue(op_, OP_NAME), _imm), T)(void)
{
OP_CAST(T0) = OP_CAST(T1) OP OP_CAST(OP_PARAM1) OP_EXTRA;
T0 = OP_CAST(T1) OP OP_CAST(OP_PARAM1) OP_EXTRA;
}
#endif
 
/trunk/or1ksim/cpu/or32/dyn-rec.h
1,26 → 1,32
/* dyn-rec.h -- Recompiler specific definitions
 
 
Copyright (C) 2008 Embecosm Limited
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
This file is part of OpenRISC 1000 Architectural Simulator.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>. */
 
This file is part of OpenRISC 1000 Architectural Simulator.
/* This program is commented throughout in a fashion suitable for processing
with Doxygen. */
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
#ifndef DYN_REC__H
#define DYN_REC__H
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
#ifndef DYN_REC_H
#define DYN_REC_H
 
typedef void (*gen_code_ent)(void);
 
/* Each dynamically recompiled page has one of these */
37,19 → 43,21
unsigned int *insn_indexs; /* Decoded instructions on this page */
};
 
void recompile_page(struct dyn_page *dyn);
struct dyn_page *new_dp(oraddr_t page);
void add_to_opq(struct op_queue *opq, int end, int op);
void add_to_op_params(struct op_queue *opq, int end, unsigned long param);
void *enough_host_page(struct dyn_page *dp, void *cur, unsigned int *len,
/* Function prototypes for external use */
extern void recompile_page(struct dyn_page *dyn);
extern struct dyn_page *new_dp(oraddr_t page);
extern void add_to_opq(struct op_queue *opq, int end, int op);
extern void add_to_op_params(struct op_queue *opq, int end, unsigned long param);
extern void *enough_host_page(struct dyn_page *dp, void *cur, unsigned int *len,
unsigned int amount);
void init_dyn_recomp(void);
void run_sched_out_of_line(void);
void recheck_immu(int got_en_dis);
void enter_dyn_code(oraddr_t addr, struct dyn_page *dp);
void dyn_checkwrite(oraddr_t addr);
void dyn_main(void);
extern void init_dyn_recomp(void);
extern void run_sched_out_of_line(void);
extern void recheck_immu(int got_en_dis);
extern void enter_dyn_code(oraddr_t addr, struct dyn_page *dp);
extern void dyn_checkwrite(oraddr_t addr);
extern void dyn_main(void);
 
/* Global variables for external use */
extern void *rec_stack_base;
 
#define IMMU_GOT_ENABLED 1
58,4 → 66,5
#define xglue(x, y) x ## y
#define glue(x, y) xglue(x, y)
 
#endif
#endif /* DYN_REC__H */
 
/trunk/or1ksim/cpu/or32/simpl32-defs.h
1,22 → 1,38
/* simpl32-defs.h -- Definitions for the simple execution model
 
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
Copyright (C) 2008 Embecosm Limited
 
This file is part of OpenRISC 1000 Architectural Simulator.
Contributed by Damjan Lampret (lampret@opencores.org).
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
This file is also part of or1k_gen_isa, GDB and GAS.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
 
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>. */
 
/* This program is commented throughout in a fashion suitable for processing
with Doxygen. */
 
 
#ifndef SIMPLE32_DEFS__H
#define SIMPLE32_DEFS__H
 
/* Package includes */
#include "abstract.h"
 
 
extern void l_invalid PARAMS((struct iqueue_entry *));
extern void l_sfne PARAMS((struct iqueue_entry *));
extern void l_bf PARAMS((struct iqueue_entry *));
93,3 → 109,4
extern void lf_sub_s PARAMS((struct iqueue_entry *));
extern void l_none PARAMS((struct iqueue_entry *));
 
#endif /* SIMPLE32_DEFS__H */
/trunk/or1ksim/cpu/or32/def-op-t.h
0,0 → 1,138
/* def_op_t.h -- Operation-generation strucutre definitions helpers
 
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
#define GPR_T(op_name, temp) \
{ NULL, \
glue(glue(op_name, 1), temp), \
glue(glue(op_name, 2), temp), \
glue(glue(op_name, 3), temp), \
glue(glue(op_name, 4), temp), \
glue(glue(op_name, 5), temp), \
glue(glue(op_name, 6), temp), \
glue(glue(op_name, 7), temp), \
glue(glue(op_name, 8), temp), \
glue(glue(op_name, 9), temp), \
glue(glue(op_name, 10), temp), \
glue(glue(op_name, 11), temp), \
glue(glue(op_name, 12), temp), \
glue(glue(op_name, 13), temp), \
glue(glue(op_name, 14), temp), \
glue(glue(op_name, 15), temp), \
glue(glue(op_name, 16), temp), \
glue(glue(op_name, 17), temp), \
glue(glue(op_name, 18), temp), \
glue(glue(op_name, 19), temp), \
glue(glue(op_name, 20), temp), \
glue(glue(op_name, 21), temp), \
glue(glue(op_name, 22), temp), \
glue(glue(op_name, 23), temp), \
glue(glue(op_name, 24), temp), \
glue(glue(op_name, 25), temp), \
glue(glue(op_name, 26), temp), \
glue(glue(op_name, 27), temp), \
glue(glue(op_name, 28), temp), \
glue(glue(op_name, 29), temp), \
glue(glue(op_name, 30), temp), \
glue(glue(op_name, 31), temp) }
 
#if NUM_T_REGS == 3
 
#define OP_ROW(op_name) \
{ glue(op_name, _t0), glue(op_name, _t1), glue(op_name, _t2) }
 
#define OP_ROW_NEQ0(op_name) \
{ NULL, glue(op_name, _t1), glue(op_name, _t2) }
 
#define OP_ROW_NEQ1(op_name) \
{ glue(op_name, _t0), NULL, glue(op_name, _t2) }
 
#define OP_ROW_NEQ2(op_name) \
{ glue(op_name, _t0), glue(op_name, _t1), NULL }
 
#define OP_ROW_COL(op_name) { \
OP_ROW(glue(op_name, _t0)), \
OP_ROW(glue(op_name, _t1)), \
OP_ROW(glue(op_name, _t2)), }
 
/* In 3D space: row, column, ??? */
#define OP_ROW_COL_3D(op_name) { \
OP_ROW_COL(glue(op_name, _t0)), \
OP_ROW_COL(glue(op_name, _t1)), \
OP_ROW_COL(glue(op_name, _t2)) }
 
#define OP_ROW_COL_NEQ(op_name) { \
OP_ROW_NEQ0(glue(op_name, _t0)), \
OP_ROW_NEQ1(glue(op_name, _t1)), \
OP_ROW_NEQ2(glue(op_name, _t2)) }
 
#define OP_ROW_COL_NEQ0(op_name) { \
OP_ROW_NEQ0(glue(op_name, _t0)), \
OP_ROW(glue(op_name, _t1)), \
OP_ROW(glue(op_name, _t2)) }
 
#define OP_ROW_COL_NEQ1(op_name) { \
OP_ROW(glue(op_name, _t0)), \
OP_ROW_NEQ1(glue(op_name, _t1)), \
OP_ROW(glue(op_name, _t2)) }
 
#define OP_ROW_COL_NEQ2(op_name) { \
OP_ROW(glue(op_name, _t0)), \
OP_ROW(glue(op_name, _t1)), \
OP_ROW_NEQ2(glue(op_name, _t2)) }
 
#define OP_ROW_COL_3D_NEQ(op_name) { \
OP_ROW_COL_NEQ0(glue(op_name, _t0)), \
OP_ROW_COL_NEQ1(glue(op_name, _t1)), \
OP_ROW_COL_NEQ2(glue(op_name, _t2)) }
 
#define GPR_ROW_COL(op_name) { \
GPR_T(op_name, _t0), \
GPR_T(op_name, _t1), \
GPR_T(op_name, _t2) }
 
#else
#error Update def_op_t.h for NUM_T_REGS temporaries
#endif
 
#define DEF_1T_OP(type, name, op_name) \
static const type name[NUM_T_REGS] = \
OP_ROW(op_name)
 
#define DEF_2T_OP(type, name, op_name) \
static const type name[NUM_T_REGS][NUM_T_REGS] = \
OP_ROW_COL(op_name)
 
#define DEF_3T_OP(type, name, op_name) \
static const type name[NUM_T_REGS][NUM_T_REGS][NUM_T_REGS] = \
OP_ROW_COL_3D(op_name)
 
/* Same as above but put NULL in places where T0 == T1 */
#define DEF_2T_OP_NEQ(type, name, op_name) \
static const type name[NUM_T_REGS][NUM_T_REGS] = \
OP_ROW_COL_NEQ(op_name)
 
/* Same as above but put NULL in places where T0 == T1 == T2 */
#define DEF_3T_OP_NEQ(type, name, op_name) \
static const type name[NUM_T_REGS][NUM_T_REGS][NUM_T_REGS] = \
OP_ROW_COL_3D_NEQ(op_name)
 
#define DEF_GPR_OP(type, name, op_name) \
static const generic_gen_op name[NUM_T_REGS][32] = \
GPR_ROW_COL(op_name)
 
/trunk/or1ksim/cpu/or32/insnset.c
1,4 → 1,4
/* execute.c -- Instruction specific functions.
/* insnset.c -- Instruction specific functions.
 
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
2000-2002 Marko Mlinar, markom@opencores.org
343,7 → 343,7
simprintf(stackaddr, evalsim_reg(3));
break;
case NOP_PUTC: /*JPB */
printf( "%c", evalsim_reg( 3 ));
printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
fflush( stdout );
break;
case NOP_REPORT:
350,7 → 350,7
PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
default:
if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
PRINTF("report %i (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
PRINTF("report %" PRIdREG " (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
evalsim_reg(3));
break;
}
/trunk/or1ksim/cpu/or32/dyngen.c
36,11 → 36,11
"\n"
"#include \"arch.h\"\n"
"#include \"opcode/or32.h\"\n"
"#include \"spr_defs.h\"\n"
"#include \"i386_regs.h\"\n"
"#include \"spr-defs.h\"\n"
"#include \"i386-regs.h\"\n"
"#include \"abstract.h\"\n"
"\n"
"#include \"dyn_rec.h\"\n"
"#include \"dyn-rec.h\"\n"
"#include \"%s\"\n"
"\n";
 
59,10 → 59,10
"\n"
"#include \"arch.h\"\n"
"#include \"opcode/or32.h\"\n"
"#include \"spr_defs.h\"\n"
"#include \"i386_regs.h\"\n"
"#include \"spr-defs.h\"\n"
"#include \"i386-regs.h\"\n"
"#include \"abstract.h\"\n"
"#include \"dyn_rec.h\"\n"
"#include \"dyn-rec.h\"\n"
"#include \"%s\"\n"
"\n"
"void gen_code(struct op_queue *opq, struct dyn_page *dp)\n"
103,15 → 103,15
"#include <inttypes.h>\n"
"\n"
"#include \"arch.h\"\n"
"#include \"spr_defs.h\"\n"
"#include \"i386_regs.h\"\n"
"#include \"spr-defs.h\"\n"
"#include \"i386-regs.h\"\n"
"#include \"opcode/or32.h\"\n"
"#include \"abstract.h\"\n"
"#include \"tick.h\"\n"
"#include \"execute.h\"\n"
"#include \"sprs.h\"\n"
"#include \"dyn_rec.h\"\n"
"#include \"op_support.h\"\n"
"#include \"dyn-rec.h\"\n"
"#include \"op-support.h\"\n"
"#include \"%s\"\n"
"\n"
"void do_scheduler(void); /* FIXME: Remove */\n"
/trunk/or1ksim/cpu/or32/Makefile.am
23,18 → 23,20
 
if DYNAMIC_EXECUTION
 
noinst_LTLIBRARIES = libarch.la libop.la
noinst_LTLIBRARIES = libarch.la
 
noinst_PROGRAMS = dyngen
 
dyngen_SOURCES = dyngen.c \
dyngen-i386.c \
dyngen-elf.c \
libarch_la_SOURCES = execute.c \
or32.c \
op.c \
dyn-rec.c \
op-support.c \
common-i386.h \
dyn32-defs.h \
dyngen.h \
dyn-rec.h \
i386-regs.h \
i386-regs.h \
op-arith-op.h \
op-comp-op.h \
op-extend-op.h \
49,18 → 51,25
rec-i386.h \
sched-i386.h \
simpl32-defs.h
dyngen_CFLAGS = $(AM_CFLAGS)
 
libarch_la_SOURCES = execute.c \
or32.c \
op.c \
dyn-rec.c \
op-support.c \
nodist_libarch_la_SOURCES = gen-ops.h \
gen-ops.c \
gen-ops-gen.c \
gen-ops-rel.c
 
BUILT_SOURCES = gen-ops.h \
gen-ops.c \
gen-ops-gen.c \
gen-ops-rel.c
 
dyngen_SOURCES = dyngen.c \
dyngen-i386.c \
dyngen-elf.c \
common-i386.h \
dyn32-defs.h \
dyngen.h \
dyn-rec.h \
i386-regs.h \
i386-regs.h \
op-arith-op.h \
op-comp-op.h \
op-extend-op.h \
75,32 → 84,17
rec-i386.h \
sched-i386.h \
simpl32-defs.h
dyngen_CFLAGS = $(AM_CFLAGS)
 
nodist_libarch_la_SOURCES = gen-ops.h \
gen-ops.c \
gen-ops-gen.c \
gen-ops-rel.c
gen-ops.h gen-ops.c gen-ops-gen.c gen-ops-rel.c: dyngen$(EXEEXT) op-tmp.o
./dyngen$(EXEEXT) op-tmp.o gen-ops.c gen-ops-gen.c gen-ops-rel.c gen-ops.h
 
BUILT_SOURCES = gen-ops.h \
gen-ops.c \
gen-ops-gen.c \
gen-ops-rel.c
OP_CFLAGS = -Wall -fomit-frame-pointer -fno-reorder-blocks -O2
 
libop_la_SOURCES = op.c \
op-t-reg-mov-op.h \
op-i386.h op-arith-op.h \
op-comp-op.h \
op-extend-op.h \
op-mac-op.h \
op-mftspr-op.h \
op-lwhb-op.h \
op-swhb-op.h
 
libop_la_CFLAGS = -Wall -fomit-frame-pointer -fno-reorder-blocks -O2
 
gen-ops.h gen-ops.c gen-ops-gen.c gen-ops-rel.c: dyngen$(EXEEXT) op.lo
./dyngen$(EXEEXT) op.lo gen-ops.c gen-ops-gen.c gen-ops-rel.c gen-ops.h
 
op-tmp.o: op.c op-t-reg-mov-op.h op-i386.h op-arith-op.h op-comp-op.h \
op-extend-op.h op-ff1-op.h op-mac-op.h op-mftspr-op.h op-lwhb-op.h \
op-swhb-op.h
$(CC) $(INCLUDES) -I$(top_builddir) $(OP_CFLAGS) -o $@ -c $<
else
 
noinst_LTLIBRARIES = libarch.la
165,7 → 159,6
else
 
libarch_la_SOURCES = execute.c \
insnset.c \
or32.c \
common-i386.h \
dyn32-defs.h \
187,6 → 180,8
sched-i386.h \
simpl32-defs.h
 
dist_EXTRA_libarch_la_SOURCES = insnset.c
 
endif
endif
 
/trunk/or1ksim/cpu/or32/dyngen-elf.c
86,7 → 86,7
if((obj->e_hdr.e_ident[EI_VERSION] != 1) ||
(obj->e_hdr.e_version != 1)) {
fprintf(stderr, "Unexpected elf version found: %i (%li)\n",
obj->e_hdr.e_ident[EI_VERSION], obj->e_hdr.e_version);
obj->e_hdr.e_ident[EI_VERSION], (long int)obj->e_hdr.e_version);
goto error_load;
}
 
/trunk/or1ksim/cpu/common/stats.c
39,7 → 39,6
#define DSTATS_LEN 3000
#define SSTATS_LEN 300
#define FSTATS_LEN 200
#define RAW_RANGE 1000
 
/* Used by safe division - increment divisor by one if it is zero */
#define SD(X) (X != 0 ? X : 1)
92,12 → 91,6
int depend;
}; /*!< functional units stats */
 
struct raw_stats
{
int reg[64];
int range[RAW_RANGE];
}; /*!< RAW hazard stats */
 
/* Globally visible statistics data. Renamed mstats to or1k_mstats because Mac
OS X has a lib function called mstats */
struct mstats_entry or1k_mstats = { 0 }; /*!< misc units stats */
105,12 → 98,12
struct cachestats_entry dc_stats = { 0 }; /*!< data cache stats */
struct immustats_entry immu_stats = { 0 }; /*!< insn MMU stats */
struct dmmustats_entry dmmu_stats = { 0 }; /*!< data MMU stats */
struct raw_stats raw_stats; /*!< RAW hazard stats */
 
/* Statistics data strutures used just here */
static struct dstats_entry dstats[DSTATS_LEN]; /*!< dependency stats */
static struct sstats_entry sstats[SSTATS_LEN]; /*!< single stats */
static struct fstats_entry fstats[FSTATS_LEN]; /*!< func units stats */
static struct raw_stats raw_stats; /*!< RAW hazard stats */
 
 
void
268,7 → 261,7
else
PRINTF ("BTIC simulation disabled. Enabled it to see BTIC analysis\n");
 
if (ic_state->enabled)
if ((NULL != ic_state) && ic_state->enabled)
{
PRINTF ("IC read: hit %d(%d%%), miss %d\n", ic_stats.readhit,
(ic_stats.readhit * 100) / SD (ic_stats.readhit +
399,7 → 392,7
case 5:
PRINTF ("stats 5: Raw register usage over time\n");
#if RAW_RANGE_STATS
for (i = 0; (i < MAX_RANGE); i++)
for (i = 0; (i < RAW_RANGE); i++)
PRINTF (" Register set and reused in %d. cycle: %d cases\n", i,
raw_stats.range[i]);
#endif
/trunk/or1ksim/cpu/common/abstract.c
48,7 → 48,7
#include "immu.h"
 
#if DYNAMIC_EXECUTION
#include "dyn_rec.h"
#include "dyn-rec.h"
#endif
 
 
549,7 → 549,7
if (config.debug.enabled)
*breakpoint += check_debug_unit (DebugInstructionFetch, memaddr);
 
if (ic_state->enabled)
if ((NULL != ic_state) && ic_state->enabled)
temp = ic_simulate_fetch (phys_memaddr, memaddr);
else
temp = evalsim_mem32 (phys_memaddr, memaddr);
/trunk/or1ksim/cpu/common/stats.h
30,6 → 30,7
/* Package includes */
#include "opcode/or32.h"
 
#define RAW_RANGE 1000
 
struct bpbstat
{
79,12 → 80,19
int stores_pagefaults;
}; /*!< DMMU stats */
 
struct raw_stats
{
int reg[64];
int range[RAW_RANGE];
}; /*!< RAW hazard stats */
 
/* Globally visible data structures */
extern struct mstats_entry or1k_mstats;
extern struct cachestats_entry ic_stats;
extern struct cachestats_entry dc_stats;
extern struct immustats_entry immu_stats;
extern struct dmmustats_entry dmmu_stats;
extern struct mstats_entry or1k_mstats;
extern struct cachestats_entry ic_stats;
extern struct cachestats_entry dc_stats;
extern struct immustats_entry immu_stats;
extern struct dmmustats_entry dmmu_stats;
extern struct raw_stats raw_stats;
 
/* Function prototypes for external use */
extern void addsstats (int item, int cnt_dynamic);
/trunk/or1ksim/cpu/common/execute.h
33,12 → 33,23
 
#if DYNAMIC_EXECUTION
#include "setjmp.h"
#include "dyn_rec.h"
#include "dyn-rec.h"
#endif
 
 
#define CURINSN(INSN) (strcmp(cur->insn, (INSN)) == 0)
 
/*! Sets a new SPR_SR_OV value, based on next register value */
#if SET_OV_FLAG
#define SET_OV_FLAG_FN(value) \
if((value) & 0x80000000) \
cpu_state.sprs[SPR_SR] |= SPR_SR_OV; \
else \
cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV
#else
#define SET_OV_FLAG_FN(value)
#endif
 
/*!The main structure holding the current execution state of the CPU
 
Not to be confused with @c runtime, which holds the state of the
103,5 → 114,4
extern void exec_main ();
extern int depend_operands (struct iqueue_entry *prev,
struct iqueue_entry *next);
 
#endif /* EXECUTE__H */
/trunk/or1ksim/cpu/common/parse.c
374,7 → 374,6
 
/* loading section */
freemem = COFF_LONG_H (coffscnhdr.s_paddr);
TRACE_ (coff) ("Starting to load at 0x%x\n", freemem);
if (fseek (inputfs, COFF_LONG_H (coffscnhdr.s_scnptr), SEEK_SET) == -1)
{
fclose (inputfs);
389,12 → 388,8
if (len == 2)
{
fseek (inputfs, -2, SEEK_CUR);
TRACE_ (coff) ("readfile_coff: %" PRIx32 " 0x%x \n", sectsize,
insn >> 16);
}
else
TRACE_ (coff) ("readfile_coff: %" PRIx32 " 0x%x \n", sectsize,
insn);
 
addprogram (freemem, insn, &breakpoint);
sectsize -= len;
}
463,8 → 458,6
&& strlen (coffsymhdr.e.e_name) < 9)
add_label (COFF_LONG_H (coffsymhdr.e_value),
coffsymhdr.e.e_name);
TRACE_ (coff) ("[%i] Symbol: %s,", count++,
coffsymhdr.e.e_name);
}
else
{
481,15 → 474,9
break;
tmp[32] = 0;
add_label (COFF_LONG_H (coffsymhdr.e_value), &tmp[0]);
TRACE_ (coff) ("[%i] Symbol: %s,", count++, &tmp[0]);
}
fseek (inputfs, fpos, SEEK_SET);
}
 
TRACE_ (coff) (" val: 0x%.8lx,", COFF_LONG_H (coffsymhdr.e_value));
TRACE_ (coff) (" type: %x, %x, auxs: %i\n",
COFF_SHORT_H (coffsymhdr.e_type),
*((unsigned short *) coffsymhdr.e_type), n);
}
 
for (i = 0; i < n; i++)
854,7 → 841,7
Loads file to memory starting at address startaddr and returns freemem.
 
@param[in] filename File to load
@param[in[ startaddr Start address at which to load
@param[in] startaddr Start address at which to load
@param[in] virtphy_transl Virtual to physical transation table if
required. Only used for microkernel simulation,
and not used in Ork1sim at present (set to NULL)
/trunk/or1ksim/cpu/or1k/spr-dump.c
38,8 → 38,6
#include "misc.h"
 
 
DEFAULT_DEBUG_CHANNEL(spr);
 
struct spr_bit_def {
const char *name;
uorreg_t mask;
536,7 → 534,7
for(tmp = spr_bit_def->mask, i = 0; !(tmp & 1); i++)
tmp >>= 1;
 
sprintf(ret_spr, "%s%s = %x", ret_spr, spr_bit_def->name,
sprintf(ret_spr, "%s%s = %" PRIxREG, ret_spr, spr_bit_def->name,
(spr_val >> i) & tmp);
}
return ret_spr;
/trunk/or1ksim/cpu/or1k/sprs.c
48,7 → 48,6
#include "pic.h"
 
 
DEFAULT_DEBUG_CHANNEL(spr);
DECLARE_DEBUG_CHANNEL(immu);
 
static int audio_cnt = 0;
63,8 → 62,6
prev_val = cpu_state.sprs[regno];
cpu_state.sprs[regno] = value;
 
TRACE("%s\n", dump_spr(regno, value));
/* MM: Register hooks. */
switch (regno) {
case SPR_TTCR:
188,8 → 185,6
 
/* Mask reseved bits in ITLBMR and ITLBMR registers */
if ( (regno >= SPR_ITLBMR_BASE(0)) && (regno < SPR_ITLBTR_LAST(3))) {
TRACE_(immu)("Writting to an mmu way (reg: %"PRIx16", value: %"PRIx32")\n",
regno, value);
if((regno & 0xff) < 0x80)
cpu_state.sprs[regno] = IADDR_PAGE(value) |
(value & (SPR_ITLBMR_V | SPR_ITLBMR_PL1 | SPR_ITLBMR_CID | SPR_ITLBMR_LRU));
237,8 → 232,6
ret = cpu_state.reg[regno - 0x0400];
}
 
TRACE("%s\n", dump_spr(regno, ret));
 
return ret;
}
 
/trunk/or1ksim/cpu/or1k/except.c
38,40 → 38,17
 
#if DYNAMIC_EXECUTION
#include "sched.h"
#include "op_support.h"
#include "op-support.h"
#endif
 
extern void op_join_mem_cycles(void);
 
DEFAULT_DEBUG_CHANNEL (except);
 
 
int except_pending = 0;
 
static const char *except_names[] = {
NULL,
"Reset",
"Bus Error",
"Data Page Fault",
"Insn Page Fault",
"Tick timer",
"Alignment",
"Illegal instruction",
"Interrupt",
"Data TLB Miss",
"Insn TLB Miss",
"Range",
"System Call",
"Floating Point",
"Trap"
};
 
static const char *
except_name (oraddr_t except)
{
return except_names[except >> 8];
}
 
/* Asserts OR1K exception. */
/* WARNING: Don't excpect except_handle to return. Sometimes it _may_ return at
/* WARNING: Don't expect except_handle to return. Sometimes it _may_ return at
* other times it may not. */
void
except_handle (oraddr_t except, oraddr_t ea)
88,11 → 65,6
except_pending = 1;
#endif
 
TRACE ("Exception 0x%" PRIxADDR " (%s) at 0x%" PRIxADDR ", EA: 0x%" PRIxADDR
", cycles %lld, #%lld\n",
except, except_name (except), cpu_state.pc, ea, runtime.sim.cycles,
runtime.cpu.instructions);
 
except_vector =
except + (cpu_state.sprs[SPR_SR] & SPR_SR_EPH ? 0xf0000000 : 0x00000000);
 
/trunk/or1ksim/cpu/or1k/opcode/or32.h
54,9 → 54,9
 
#if defined(HAVE_EXECUTION)
# if SIMPLE_EXECUTION
# include "simpl32_defs.h"
# include "simpl32-defs.h"
# elif DYNAMIC_EXECUTION
# include "dyn32_defs.h"
# include "dyn32-defs.h"
# else
extern void l_none PARAMS((void));
# endif
/trunk/or1ksim/cpu/or1k/except.h
32,6 → 32,7
#include "arch.h"
 
/* Definition of OR1K exceptions */
#define EXCEPT_NONE 0x0000
#define EXCEPT_RESET 0x0100
#define EXCEPT_BUSERR 0x0200
#define EXCEPT_DPF 0x0300
44,6 → 45,7
#define EXCEPT_ITLBMISS 0x0a00
#define EXCEPT_RANGE 0x0b00
#define EXCEPT_SYSCALL 0x0c00
#define EXCEPT_FPE 0x0d00
#define EXCEPT_TRAP 0x0e00
 
/* Function prototypes for external use */
/trunk/or1ksim/tick/tick.c
46,11 → 46,8
#include "sprs.h"
#include "sim-config.h"
#include "sched.h"
#include "debug.h"
 
 
DEFAULT_DEBUG_CHANNEL (tick);
 
/*! When did the timer start to count */
static long long cycles_start = 0;
 
95,8 → 92,6
{
cpu_state.sprs[SPR_TTCR] = 0;
cycles_start = runtime.sim.cycles;
TRACE ("Scheduleing timer restart job for %" PRIdREG "\n",
cpu_state.sprs[SPR_TTMR] & SPR_TTMR_PERIOD);
SCHED_ADD (tick_restart, NULL, cpu_state.sprs[SPR_TTMR] & SPR_TTMR_PERIOD);
}
 
104,7 → 99,6
static void
tick_one_shot (void *dat)
{
TRACE ("Stopping one-shot timer\n");
cpu_state.sprs[SPR_TTCR] = cpu_state.sprs[SPR_TTMR] & SPR_TTMR_PERIOD;
tick_count = 0;
}
143,19 → 137,14
match_time += (0xfffffffu - ttcr_period) + 1;
}
 
TRACE ("Cycles to go until match: %" PRIu32 " (0x%" PRIx32 ")\n",
match_time, match_time);
 
switch (ttmr & SPR_TTMR_M)
{
case 0: /* Disabled timer */
TRACE ("Scheduleing exception when timer match (in disabled mode).\n");
if (!match_time && (ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
SCHED_ADD (tick_raise_except, NULL, 0);
break;
 
case SPR_TTMR_RT: /* Auto-restart timer */
TRACE ("Scheduleing auto-restarting timer.\n");
SCHED_ADD (tick_restart, NULL, match_time);
if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
SCHED_ADD (tick_raise_except, NULL, match_time);
162,7 → 151,6
break;
 
case SPR_TTMR_SR: /* One-shot timer */
TRACE ("Scheduleing one-shot timer.\n");
if (tick_count)
{
SCHED_ADD (tick_one_shot, NULL, match_time);
172,7 → 160,6
break;
 
case SPR_TTMR_CR: /* Continuos timer */
TRACE ("Scheduleing exception when timer match (in cont. mode).\n");
if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
SCHED_ADD (tick_raise_except, NULL, match_time);
}
183,7 → 170,6
void
spr_write_ttcr (uorreg_t value)
{
TRACE ("set ttcr = %" PRIxREG "\n", value);
cycles_start = runtime.sim.cycles - value;
 
sched_timer_job (cpu_state.sprs[SPR_TTMR]);
196,9 → 182,6
{
uorreg_t value = cpu_state.sprs[SPR_TTMR];
 
TRACE ("set ttmr = %" PRIxREG " (previous: %" PRIxREG ")\n", value,
prev_val);
 
/* Code running on or1k can't set SPR_TTMR_IP so make sure it isn't */
cpu_state.sprs[SPR_TTMR] &= ~SPR_TTMR_IP;
 
237,6 → 220,5
ret = runtime.sim.cycles - cycles_start;
}
 
TRACE ("read ttcr %" PRIdREG " (0x%" PRIxREG ")\n", ret, ret);
return ret;
}
/trunk/or1ksim/libtoplevel.c
262,7 → 262,7
int
or1ksim_is_le ()
{
#ifdef WORDS_BIGENDIAN
#ifdef OR32_BIG_ENDIAN
return 0;
#else
return 1;
/trunk/or1ksim/rsp.cfg
0,0 → 1,967
/* sim.cfg -- Simulator configuration script file
Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
It contains the default configuration and help about configuring
the simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
/* INTRODUCTION
 
The ork1sim has various parameters, that are set in configuration files
like this one. The user can switch between configurations at startup by
specifying the required configuration file with the -f <filename.cfg> option.
If no configuration file is specified or1ksim searches for the default
configuration file sim.cfg. First it searches for './sim.cfg'. If this
file is not found, it searches for '~/or1k/sim.cfg'. If this file is
not found too, it reverts to the built-in default configuration.
NOTE: Users should not rely on the built-in configuration, since the
default configuration may differ between version.
Rather create a configuration file that sets all critical values.
 
This file may contain (standard C) comments only - no // support.
Configure files may be be included, using:
include "file_name_to_include"
 
Like normal configuration files, the included file is divided into
sections. Each section is described in detail also.
 
Some section have subsections. One example of such a subsection is:
 
device <index>
instance specific parameters...
enddevice
 
which creates a device instance.
*/
 
 
/* MEMORY SECTION
 
This section specifies how the memory is generated and the blocks
it consists of.
 
type = random/unknown/pattern
Specifies the initial memory values.
'random' generates random memory using seed 'random_seed'.
'pattern' fills memory with 'pattern'.
'unknown' does not specify how memory should be generated,
leaving the memory in a undefined state. This is the fastest
option.
 
random_seed = <value>
random seed for randomizer, used if type = 'random'.
 
pattern = <value>
pattern to fill memory, used if type = 'pattern'.
 
baseaddr = <hex_value>
memory start address
 
size = <hex_value>
memory size
 
name = "<string>"
memory block name
 
ce = <value>
chip enable index of the memory instance
 
mc = <value>
memory controller this memory is connected to
 
delayr = <value>
cycles, required for read access, -1 if instance does not support reading
 
delayw = <value>
cycles, required for write access, -1 if instance does not support
writing
 
log = "<filename>"
filename, where to log memory accesses to. If log command is not
specified, accesses are not logged.
*/
 
 
section memory
name = "RAM"
random_seed = 12345
type = random
ce = 0
mc = 0
baseaddr = 0x00000000
size = 0x00400000
delayr = 1
delayw = 2
end
 
/* IMMU SECTION
 
This section configures the Instruction Memory Manangement Unit
 
enabled = 0/1
'0': disabled
'1': enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of ITLB sets; must be power of two
 
nways = <value>
number of ITLB ways
 
pagesize = <value>
instruction page size; must be power of two
 
entrysize = <value>
instruction entry size in bytes
 
ustates = <value>
number of ITLB usage states (2, 3, 4 etc., max is 4)
hitdelay = <value>
number of cycles immu hit costs
missdelay = <value>
number of cycles immu miss costs
*/
 
section immu
enabled = 0
nsets = 64
nways = 1
pagesize = 8192
hitdelay = 0
missdelay = 0
end
 
 
/* DMMU SECTION
 
This section configures the Data Memory Manangement Unit
 
enabled = 0/1
'0': disabled
'1': enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of DTLB sets; must be power of two
 
nways = <value>
number of DTLB ways
 
pagesize = <value>
data page size; must be power of two
 
entrysize = <value>
data entry size in bytes
 
ustates = <value>
number of DTLB usage states (2, 3, 4 etc., max is 4)
 
hitdelay = <value>
number of cycles dmmu hit costs
 
missdelay = <value>
number of cycles dmmu miss costs
*/
 
section dmmu
enabled = 0
nsets = 64
nways = 1
pagesize = 8192
hitdelay = 0
missdelay = 0
end
 
 
/* IC SECTION
 
This section configures the Instruction Cache
 
enabled = 0/1
'0': disabled
'1': enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of IC sets; must be power of two
 
nways = <value>
number of IC ways
 
blocksize = <value>
IC block size in bytes; must be power of two
 
ustates = <value>
number of IC usage states (2, 3, 4 etc., max is 4)
 
hitdelay = <value>
number of cycles ic hit costs
missdelay = <value>
number of cycles ic miss costs
*/
 
section ic
enabled = 0
nsets = 256
nways = 1
blocksize = 16
hitdelay = 0
missdelay = 0
end
 
 
/* DC SECTION
 
This section configures the Data Cache
 
enabled = 0/1
'0': disabled
'1': enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of DC sets; must be power of two
 
nways = <value>
number of DC ways
 
blocksize = <value>
DC block size in bytes; must be power of two
 
ustates = <value>
number of DC usage states (2, 3, 4 etc., max is 4)
 
load_hitdelay = <value>
number of cycles dc load hit costs
load_missdelay = <value>
number of cycles dc load miss costs
store_hitdelay = <value>
number of cycles dc store hit costs
store_missdelay = <value>
number of cycles dc store miss costs
*/
 
section dc
enabled = 0
nsets = 256
nways = 1
blocksize = 16
load_hitdelay = 0
load_missdelay = 0
store_hitdelay = 0
store_missdelay = 0
end
 
 
/* PIC SECTION
 
This section specifies how the pic should behave
 
enabled = 0/1
'0': PIC is disabled
'1': PIC is enabled
 
edge_trigger = 0/1
'0': Level triggered PIC
'1': Edge triggered PIC
*/
 
section pic
enabled = 1
edge_trigger = 1
end
 
 
/* SIM SECTION
 
This section specifies how or1ksim should behave.
 
verbose = 0/1
'0': don't print extra messages
'1': print extra messages
 
debug = 0-9
0 : no debug messages
1-9: debug message level.
higher numbers produce more messages
 
profile = 0/1
'0': don't generate profiling file 'sim.profile'
'1': don't generate profiling file 'sim.profile'
 
prof_file = "<filename>"
optional filename for the profiling file.
valid only if 'profile' is set
mprofile = 0/1
'0': don't generate memory profiling file 'sim.mprofile'
'1': generate memory profiling file 'sim.mprofile'
 
mprof_file = "<filename>"
optional filename for the memory profiling file.
valid only if 'mprofile' is set
 
history = 0/1
'0': don't track execution flow
'1': track execution flow
Execution flow can be tracked for the simulator's
'hist' command. Useful for back-trace debugging.
 
iprompt = 0/1
'0': start in <not interactive prompt> (so what do we start in ???)
'1': start in interactive prompt.
 
exe_log = 0/1
'0': don't generate execution log.
'1': generate execution log.
exe_log_type = default/hardware/simple/software
type of execution log, default is used when not specified
exe_log_start = <value>
index of first instruction to start logging, default = 0
exe_log_end = <value>
index of last instruction to end logging; not limited, if omitted
exe_log_marker = <value>
<value> specifies number of instructions before horizontal marker is
printed; if zero, markers are disabled (default)
 
exe_log_file = "<filename>"
filename for the exection log file.
valid only if 'exe_log' is set
 
clkcycle = <value>[ps|ns|us|ms]
specifies time measurement for one cycle
*/
 
section sim
/* verbose = 1 */
debug = 0
profile = 0
prof_file = "sim.profile"
 
history = 0
/* iprompt = 0 */
exe_log = 0
exe_log_type = software
exe_log_start = 0
/* exe_log_end = 20000000*/
exe_log_marker = 10000
exe_log_file = "executed.log"
 
clkcycle = 100ns
end
 
 
/* SECTION VAPI
 
This section configures the Verification API, used for Advanced
Core Verification.
 
enabled = 0/1
'0': disbable VAPI server
'1': enable/start VAPI server
 
server_port = <value>
TCP/IP port to start VAPI server on
 
log_enabled = 0/1
'0': disable VAPI requests logging
'1': enable VAPI requests logging
 
hide_device_id = 0/1
'1': don't log device id (for compatability with old version)
'0': log device id
 
vapi_log_file = <filename>
filename for the log file.
valid only if log_enabled is set
*/
 
section VAPI
enabled = 0
server_port = 50000
log_enabled = 0
vapi_log_file = "vapi.log"
end
 
 
/* CPU SECTION
 
This section specifies various CPU parameters.
 
ver = <value>
cfg = <value>
rev = <value>
specifies version, configuration and revision fields of the CPU version
register.
 
upr = <value>
changes the upr register
cfgr = <value>
changes the CPU configuration register
 
sr = <value>
sets the initial Supervision Register value
 
superscalar = 0/1
'0': CPU is scalar
'1': CPU is superscalar
(modify cpu/or32/execute.c to tune superscalar model)
 
hazards = 0/1
'0': don't track data hazards in superscalar CPU
'1': track data hazards in superscalar CPU
If tracked, data hazards can be displayed using the
simulator's 'r' command.
 
dependstats = 0/1
'0': don't calculate inter-instruction dependencies.
'1': calculate inter-instruction dependencies.
If calculated, inter-instruction dependencies can be
displayed using the simulator's 'stat' command.
 
sbuf_len = <value>
length of store buffer (<= 256), 0 = disabled
*/
 
section cpu
ver = 0x12
cfg = 0x00
rev = 0x0001
superscalar = 0
hazards = 0
dependstats = 0
sbuf_len = 0
end
 
 
/* PM SECTION
 
This section specifies Power Management parameters
 
enabled = 0/1
'0': disable power management
'1': enable power management
*/
 
section pm
enabled = 1
end
 
 
/* BPB SECTION
 
This section specifies how branch prediction should behave.
enabled = 0/1
'0': disable branch prediction
'1': enable branch prediction
btic = 0/1
'0': disable branch target instruction cache model
'1': enable branch target instruction cache model
 
sbp_bf_fwd = 0/1
Static branch prediction for 'l.bf'
'0': don't use forward prediction
'1': use forward prediction
sbp_bnf_fwd = 0/1
Static branch prediction for 'l.bnf'
'0': don't use forward prediction
'1': use forward prediction
 
hitdelay = <value>
number of cycles bpb hit costs
missdelay = <value>
number of cycles bpb miss costs
*/
 
section bpb
enabled = 1
btic = 0
sbp_bf_fwd = 0
sbp_bnf_fwd = 0
hitdelay = 0
missdelay = 0
end
 
 
/* DEBUG SECTION
 
This sections specifies how the debug unit should behave.
 
enabled = 0/1
'0': disable debug unit
'1': enable debug unit
 
gdb_enabled = 0/1
'0': don't start gdb server
'1': start gdb server at port 'server_port'
 
server_port = <value>
TCP/IP port to start gdb server on
valid only if gdb_enabled is set
 
vapi_id = <hex_value>
Used to create "fake" vapi log file containing the JTAG proxy messages.
*/
 
section debug
enabled = 1
gdb_enabled = 0
rsp_enabled = 1
rsp_port = 51000
end
 
 
/* MC SECTION
 
This section configures the memory controller
 
enabled = 0/1
'0': disable memory controller
'1': enable memory controller
 
baseaddr = <hex_value>
address of first MC register
 
POC = <hex_value>
Power On Configuration register
 
index = <value>
Index of this memory controller amongst all the memory controllers
*/
 
section mc
enabled = 1
baseaddr = 0x93000000
POC = 0x0000000a /* 32 bit SSRAM */
index = 0
end
 
 
/* UART SECTION
 
This section configures the UARTs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first UART register for this device
 
channel = <channeltype>:<args>
The channel parameter indicates the source of received UART characters
and the sink for transmitted UART characters.
 
The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty"
(without quotes).
 
A) To send/receive characters from a pair of files, use a file
channel:
 
channel=file:<rxfile>,<txfile>
 
B) To create an interactive terminal window, use an xterm channel:
 
channel=xterm:[<xterm_arg>]*
 
C) To create a bidirectional tcp socket which one could, for example,
access via telnet, use a tcp channel:
 
channel=tcp:<port number>
 
D) To cause the UART to read/write from existing numeric file
descriptors, use an fd channel:
 
channel=fd:<rx file descriptor num>,<tx file descriptor num>
 
E) To connect the UART to a physical serial port, create a tty
channel:
 
channel=tty:device=/dev/ttyS0,baud=9600
 
irq = <value>
irq number for this device
 
16550 = 0/1
'0': this device is a UART16450
'1': this device is a UART16550
 
jitter = <value>
in msecs... time to block, -1 to disable it
 
vapi_id = <hex_value>
VAPI id of this instance
*/
 
section uart
enabled = 1
baseaddr = 0x90000000
irq = 2
channel = "file:uart0.rx,uart0.tx"
jitter = -1 /* async behaviour */
16550 = 1
end
 
 
/* DMA SECTION
 
This section configures the DMAs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first DMA register for this device
 
irq = <value>
irq number for this device
 
vapi_id = <hex_value>
VAPI id of this instance
*/
 
section dma
enabled = 1
baseaddr = 0x9a000000
irq = 11
end
 
 
/* ETHERNET SECTION
 
This section configures the ETHERNETs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first ethernet register for this device
 
dma = <value>
which controller is this ethernet "connected" to
 
irq = <value>
ethernet mac IRQ level
 
rtx_type = <value>
use 0 - file interface, 1 - socket interface. Note the socket
interface must be configured at build time.
 
rx_channel = <value>
DMA channel used for RX
 
tx_channel = <value>
DMA channel used for TX
 
rxfile = "<filename>"
filename, where to read data from
 
txfile = "<filename>"
filename, where to write data to
 
sockif = "<ifacename>"
interface name of ethernet socket
 
vapi_id = <hex_value>
VAPI id of this instance
*/
 
section ethernet
enabled = 1
baseaddr = 0x92000000
irq = 4
rtx_type = 0
rxfile = "eth0.rx"
txfile = "eth0.tx"
sockif = "eth0"
end
 
 
/* GPIO SECTION
 
This section configures the GPIOs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first GPIO register for this device
 
irq = <value>
irq number for this device
 
base_vapi_id = <hex_value>
first VAPI id of this instance
GPIO uses 8 consecutive VAPI IDs
*/
 
section gpio
enabled = 1
baseaddr = 0x91000000
irq = 3
base_vapi_id = 0x0200
end
 
/* VGA SECTION
This section configures the VGA/LCD controller
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first VGA register
irq = <value>
irq number for this device
refresh_rate = <value>
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
 
section vga
enabled = 1
baseaddr = 0x97100000
irq = 8
refresh_rate = 100000
filename = "primary"
end
 
 
/* FB SECTION
This section configures the frame buffer
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
base address of frame buffer
refresh_rate = <value>
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
 
section fb
enabled = 1
baseaddr = 0x97000000
refresh_rate = 1000000
filename = "primary"
end
 
 
/* KBD SECTION
 
This section configures the PS/2 compatible keyboard
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
base address of the keyboard device
irq = <value>
irq number for this device
 
rxfile = "<filename>"
filename, where to read data from
*/
 
section kbd
enabled = 1
baseaddr = 0x94000000
irq = 5
rxfile = "kbd.rx"
end
 
 
/* ATA SECTION
This section configures the ATA/ATAPI host controller
enabled = <0|1>
Enable/disable the peripheral. By default it is enabled.
 
baseaddr = <hex_value>
address of first ATA register
irq = <value>
irq number for this device
 
dev_id = 1/2/3
Which OCIDEC version to imitate
 
rev = <value>
Revision of OCIDEC
 
pio_mode0_t1 = <0-255>
PIO T1 reset value
 
pio_mode0_t2 = <0-255>
PIO T2 reset value
 
pio_mode0_t4 = <0-255>
PIO T4 reset value
 
pio_mode0_teoc = <0-255>
PIO Teoc reset value
 
dma_mode0_tm = <0-255>
DMA Tm reset value
 
dma_mode0_td = <0-255>
DMA Td reset value
 
dma_mode0_teoc = <0-255>
DMA Teoc reset value
 
Device specific
 
type = <value>
ata device 0 type
0: NO_CONNECT: none (not connected)
1: FILE : simulated harddisk
2: LOCAL : local system harddisk
 
file = "<filename>"
filename for simulated ATA device
valid only if dev_type0 == 1
 
size = <value>
size of simulated hard-disk (in MBytes)
valid only if dev_type0 == 1
 
packet = <value>
0: simulated ATA device does NOT implement PACKET command feature set
1: simulated ATA device does implement PACKET command feature set
 
firmware = <string>
Firmware to report in `Identify device command'
 
heads = <value>
Number of default heads (-1)
 
sectors = <value>
Number of default sectors per track
 
mwdma = <value>
The highest multiword DMA mode; 2, 1, 0, -1 (No DMA)
 
pio = <value>
The highest supported pio mode; 4, 3, 2, 1, 0
 
FIXME: irq number
*/
 
section ata
enabled = 1
baseaddr = 0x9e000000
irq = 15
dev_id = 1
rev = 0
 
pio_mode0_t1 = 6
pio_mode0_t2 = 28
pio_mode0_t4 = 2
pio_mode0_teoc = 23
 
dma_mode0_tm = 4
dma_mode0_td = 21
dma_mode0_teoc = 21
 
device 0
type = 1
file = "/tmp/sim_atadev0"
size = 1
packet = 0
 
heads = 7
sectors = 32
 
firmware = "02207031"
mwdma = 2
pio = 4
enddevice
 
device 1
type = 0
file = ""
size = 0
packet = 0
enddevice
end
 
 
/* CUC SECTION
 
This section configures the OpenRISC Custom Unit Compiler
 
memory_order = none/weak/strong/exact
none different memory ordering, even if there are dependencies,
burst can be made, width can change
weak different memory ordering, if there cannot be dependencies
burst can be made, width can change
strong same memory ordering, burst can be made, width can change
exact exacltly the same memory ordering and widths
 
calling_convention = 0/1
whether programs follow OpenRISC calling conventions
 
enable_bursts = 0/1
whether burst are detected
 
no_multicycle = 0/1
if selected no multicycle logic paths will be generated
 
timings_fn = "<filename>"
*/
 
section cuc
memory_order = weak
calling_convention = 1
enable_bursts = 1
no_multicycle = 1
timings_fn = "virtex.tim"
end
 
/trunk/or1ksim/configure.ac
26,7 → 26,7
# Process this file with autoconf to produce a configure script.
 
 
AC_INIT([or1ksim], [0.3.0rc1], [openrisc@opencores.org])
AC_INIT([or1ksim], [0.3.0rc2], [openrisc@opencores.org])
AC_CONFIG_SRCDIR([cpu/or32/execute.c])
AC_CANONICAL_TARGET([])
AC_PROG_LIBTOOL
33,12 → 33,12
AM_INIT_AUTOMAKE
AC_CONFIG_HEADERS([config.h])
 
AC_REVISION([$Id: configure.ac,v 1.1 2008-10-12 17:27:52 jeremybennett Exp $ using automake version] AC_ACVERSION)
AC_REVISION([$Id: configure.ac,v 1.2 2008-11-11 13:24:02 jeremybennett Exp $ using automake version] AC_ACVERSION)
 
# make sure we are using a recent autoconf version
AC_PREREQ(2.59)
 
# yuck
# yuck.
case "$target_cpu" in
or32*) CPU_ARCH=or32;
ARCH_ISA=OR32;
51,6 → 51,13
AC_DEFINE(OR32_TYPES, 1, "The compiler uses the OR32 ELF types");;
esac
 
# determine endianism from target CPU name. If it has "little" in the name,
# then its litte endian, otherwise its big endian (default for OR1K)
case "$target_cpu" in
*little*) AC_DEFINE(OR32_LITTLE_ENDIAN, 1, "The OR32 is little endian");;
*) AC_DEFINE(OR32_BIG_ENDIAN, 1, "The OR32 is big endian");;
esac
 
AC_SUBST(CPU_ARCH)
 
# We want these before the checks, so the checks can modify their values.
91,6 → 98,7
sys/ptem.h sys/pte.h sys/stream.h sys/stropts.h sys/select.h \
termcap.h termios.h termio.h sys/file.h locale.h getopt.h \
net/ethernet.h sys/ethernet.h malloc.h inttypes.h libintl.h)
AC_CHECK_DECLS([I_PUSH])
AC_C_BIGENDIAN
 
# Checks for typedefs, structures, and compiler characteristics (for argtable2)
124,6 → 132,9
AC_CHECK_SIZEOF(int, 1)
AC_CHECK_SIZEOF(long, 1)
 
#Check for compare function type for qsort (needed by some Linuxes)
AC_CHECK_TYPES([__compar_fn_t])
 
# check for GNU readline
AC_CHECK_LIB(readline, add_history)
 
150,7 → 161,7
AC_ARG_ENABLE(profiling,
[ --enable-profiling generate profiling code], [
case "$enableval" in
yes) profile="-pg -a" ;;
yes) profile="-pg" ;;
esac
])
AC_MSG_RESULT(${enable_profiling-no})
215,8 → 226,8
AC_ARG_ENABLE(ov_flag,
[ --enable-ov-flag Whether instructions set overflow flag.], [
case "$enableval" in
no) set_ov_flag="0" ;;
yes) set_ov_flag="1" ;;
no) set_ov_flag="0" ;;
yes) set_ov_flag="1" ;;
esac
])
AC_MSG_RESULT(${enable_ov_flag-no})
238,8 → 249,8
AC_HELP_STRING([--enable-debug],[enable library debugging symbols]),
[
case $enableval in
yes) echo "enabling debugging symbols" & DEBUGFLAGS="-g -UNDEBUG";;
no) echo "disabling debugging symbols" & DEBUGFLAGS="-DNDEBUG";;
yes) echo "enabling argtable2 debugging symbols" & DEBUGFLAGS="-g -UNDEBUG";;
no) echo "disabling argtable2 debugging symbols" & DEBUGFLAGS="-DNDEBUG";;
*) echo "illegal argument to --enable-debug" & exit 1;;
esac
],
/trunk/or1ksim/argtable2/Makefile.in
90,16 → 90,20
am__libargtable2_la_SOURCES_DIST = argtable2.c arg_end.c arg_rem.c \
arg_lit.c arg_int.c arg_dbl.c arg_str.c arg_file.c getopt.c \
getopt1.c getopt.h arg_rex.c arg_date.c
@USE_SYS_GETOPTLONG_FALSE@am__objects_1 = getopt.lo getopt1.lo
@USE_ARGREX_TRUE@am__objects_2 = arg_rex.lo
@USE_ARGDATE_TRUE@am__objects_3 = arg_date.lo
am_libargtable2_la_OBJECTS = argtable2.lo arg_end.lo arg_rem.lo \
arg_lit.lo arg_int.lo arg_dbl.lo arg_str.lo arg_file.lo \
$(am__objects_1) $(am__objects_2) $(am__objects_3)
@USE_SYS_GETOPTLONG_FALSE@am__objects_1 = libargtable2_la-getopt.lo \
@USE_SYS_GETOPTLONG_FALSE@ libargtable2_la-getopt1.lo
@USE_ARGREX_TRUE@am__objects_2 = libargtable2_la-arg_rex.lo
@USE_ARGDATE_TRUE@am__objects_3 = libargtable2_la-arg_date.lo
am_libargtable2_la_OBJECTS = libargtable2_la-argtable2.lo \
libargtable2_la-arg_end.lo libargtable2_la-arg_rem.lo \
libargtable2_la-arg_lit.lo libargtable2_la-arg_int.lo \
libargtable2_la-arg_dbl.lo libargtable2_la-arg_str.lo \
libargtable2_la-arg_file.lo $(am__objects_1) $(am__objects_2) \
$(am__objects_3)
libargtable2_la_OBJECTS = $(am_libargtable2_la_OBJECTS)
libargtable2_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \
$(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
$(libargtable2_la_LDFLAGS) $(LDFLAGS) -o $@
$(LIBTOOLFLAGS) --mode=link $(CCLD) $(libargtable2_la_CFLAGS) \
$(CFLAGS) $(libargtable2_la_LDFLAGS) $(LDFLAGS) -o $@
DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
depcomp = $(SHELL) $(top_srcdir)/depcomp
am__depfiles_maybe = depfiles
244,6 → 248,7
libargtable2_la_SOURCES = argtable2.c arg_end.c arg_rem.c arg_lit.c \
arg_int.c arg_dbl.c arg_str.c arg_file.c $(am__append_1) \
$(am__append_2) $(am__append_3)
libargtable2_la_CFLAGS = $(DEBUGFLAGS)
 
#libtool library versioning uses current:revision:age where
# current = most recent interface number
309,18 → 314,18
distclean-compile:
-rm -f *.tab.c
 
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arg_date.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arg_dbl.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arg_end.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arg_file.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arg_int.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arg_lit.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arg_rem.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arg_rex.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arg_str.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/argtable2.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getopt.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getopt1.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libargtable2_la-arg_date.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libargtable2_la-arg_dbl.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libargtable2_la-arg_end.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libargtable2_la-arg_file.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libargtable2_la-arg_int.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libargtable2_la-arg_lit.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libargtable2_la-arg_rem.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libargtable2_la-arg_rex.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libargtable2_la-arg_str.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libargtable2_la-argtable2.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libargtable2_la-getopt.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libargtable2_la-getopt1.Plo@am__quote@
 
.c.o:
@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
343,6 → 348,90
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(LTCOMPILE) -c -o $@ $<
 
libargtable2_la-argtable2.lo: argtable2.c
@am__fastdepCC_TRUE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libargtable2_la_CFLAGS) $(CFLAGS) -MT libargtable2_la-argtable2.lo -MD -MP -MF $(DEPDIR)/libargtable2_la-argtable2.Tpo -c -o libargtable2_la-argtable2.lo `test -f 'argtable2.c' || echo '$(srcdir)/'`argtable2.c
@am__fastdepCC_TRUE@ mv -f $(DEPDIR)/libargtable2_la-argtable2.Tpo $(DEPDIR)/libargtable2_la-argtable2.Plo
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='argtable2.c' object='libargtable2_la-argtable2.lo' libtool=yes @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libargtable2_la_CFLAGS) $(CFLAGS) -c -o libargtable2_la-argtable2.lo `test -f 'argtable2.c' || echo '$(srcdir)/'`argtable2.c
 
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mostlyclean-libtool:
-rm -f *.lo
 
/trunk/or1ksim/argtable2/argtable2.c
24,12 → 24,10
#include "config.h"
#endif
 
#ifdef STDC_HEADERS
#include <stdlib.h>
#include <string.h>
#include <stdlib.h>
#include <ctype.h>
#endif
 
#ifdef HAVE_STRINGS_H
#include <strings.h>
93,6 → 91,7
};
 
#ifndef NDEBUG
/* Commented out by JPB for GCC compliance
static
void dump_longoptions(struct longoptions* longoptions)
{
107,6 → 106,7
printf("options[%d].val = %d\n", i, longoptions->options[i].val);
}
}
*/
#endif
 
static
942,10 → 942,10
* will result in the following output:
*
* Some
* _ text
* _ that
* _ doesn'
* _ t fit.
*   text
*   that
*   doesn'
*   t fit.
*
* As you see, the first line is not indented. This enables output of
* lines, which start in a line where output already happened.
968,7 → 968,7
{
/* Eat leading whitespaces. This is essential because while
wrapping lines, there will often be a whitespace at beginning
of line _*/
of line  */
while ( isspace(*(text+line_start)) )
{ line_start++; }
 
1014,9 → 1014,9
/**
* Prints the glossary in strict GNU format.
* Differences to arg_print_glossary() are:
* _- wraps lines after 80 chars
* _- indents lines without shortops
* _- does not accept formatstrings
*  - wraps lines after 80 chars
*  - indents lines without shortops
*  - does not accept formatstrings
*
* Contributed by Uli Fouquet
*/
/trunk/or1ksim/argtable2/Makefile.am
32,6 → 32,8
libargtable2_la_SOURCES = argtable2.c arg_end.c arg_rem.c arg_lit.c arg_int.c arg_dbl.c \
arg_str.c arg_file.c
 
libargtable2_la_CFLAGS = $(DEBUGFLAGS)
 
#libtool library versioning uses current:revision:age where
# current = most recent interface number
# revision = minor version of current interface
/trunk/or1ksim/doc/or1ksim.info
46,32 → 46,160
1 Installation
**************
 
Installation follows standard GNU protocols. Unpack the software and
create a _separate_ directory in which to build it:
Installation follows standard GNU protocols.
 
tar jxf or1ksim-0.3.0rc1.tar.bz2
* Menu:
 
* Preparation::
* Configuring the Build::
* Build and Install::
 

File: or1ksim.info, Node: Preparation, Next: Configuring the Build, Up: Installation
 
1.1 Preparation
===============
 
Unpack the software and create a _separate_ directory in which to build
it:
 
tar jxf or1ksim-0.3.0rc2.tar.bz2
mkdir builddir_or1ksim
cd builddir_or1ksim
 
Configure the software. The only critical argument is `--target', which
must specify the OpenRISC 1000 architecture.

File: or1ksim.info, Node: Configuring the Build, Next: Build and Install, Prev: Preparation, Up: Installation
 
../or1ksim-0.3.0rc1/configure --target=or32-uclinux ...
1.2 Configuring the Build
=========================
 
See `configure --help' for other options. The most useful is `--prefix'
to specify a directory for installation of the tools.
Configure the software using the `configure' script in the main
directory.
 
A number of features in the simulator do require enabling at
The most significant argument is `--target', which should specify the
OpenRISC 1000 32-bit architecture. If this argument is omitted, it will
default to OpenRISC 1000 32-bit with a warning
 
../or1ksim-0.3.0rc2/configure --target=or32-uclinux ...
 
There are several other options available, many of which are standard
to GNU `configure' scripts. Use `configure --help' to see all the
options. The most useful is `--prefix' to specify a directory for
installation of the tools.
 
A number of Or1ksim features in the simulator do require enabling at
configuration. These include
 
`--enable-profiling'
`--disable-profiling'
If enabled, Or1ksim is compiled for profiling with `gprof'. This
is disabled by default. Only really of value for developers of
Or1ksim.
 
`--enable-execution=simple'
`--enable-execution=complex'
`--enable-execution=dynamic'
Or1ksim has developed to improve functionality and performance.
This feature allows three versions of Or1ksim to be built
 
`--enable-execution=simple'
Build the original simple interpreting simulator
 
`--enable-execution=complex'
Build a more complex interpreting simulator. Experiments
suggest this is 50% faster than the simple simulator. This is
the default.
 
`--enable-execution=dynamic'
Build a dynamically compiling simulator. This is the way many
modern ISS are built. This represents a work in progress.
Currently Or1ksim will compile, but segfaults if configured
with this option.
 
 
The default is `--enable-execution=complex'.
 
`--enable-ethphy'
Allow the Ethernet to be simulated by connecting via a socket (the
alternative reads and writes, from and to files). This must then be
configured using the relevant fields in the `ethernet' section of
the configuration file. *Note Ethernet Configuration: Ethernet
Configuration.
`--disable-ethphy'
If enabled, this option allows the Ethernet to be simulated by
connecting via a socket (the alternative reads and writes, from
and to files). This must then be configured using the relevant
fields in the `ethernet' section of the configuration file. *Note
Ethernet Configuration: Ethernet Configuration.
 
The default is for this to be disabled.
 
`--enable-range-stats'
`--disable-range-stats'
If enabled, this option allows statistics to be collected to
analyse register access over time. The default is for this to be
disabled.
 
`--enable-ov-flag'
`--disable-ov-flag'
If enabled, this option causes instructions to set the overflow
flag. The instructions affected by this are `l.add', `l.addc',
`l.addi', `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli',
`l.or', `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra',
`l.srai', `l.sub', `l.xor' and `l.xori'.
 
The default is for this to be disabled.
 
Caution: This appears a very dangerous option, to the extent
of arguably being a bug. Whether or not flags are set is part
of the OpenRISC 1000 architectural specification. Within the
above list, the arithmetic instructions (`l.add', `l.addc',
`l.addi', `l.div', `l.divu', `l.mul', `l.muli' and `l.sub'),
together with `l.addic' which is missed out, set the overflow
flag. All the others (`l.and', `l.andi', `l.or', `l.ori',
`l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
`l.xor' and `l.xori') do not.
 
Thus it is impossible to get correct behavior whichever way
this option is set.
 
`--enable-arith-flag'
`--disable-arith-flag'
If enabled, this option causes instructions to set the flag (`F'
bit) in the supervision register. The instructions affected by
this are `l.add', `l.addc', `l.addi', `l.and' and `l.andi'.
 
The default is for this to be disabled.
 
Caution: As with `--enable-ov-flag', this appears another
very dangerous option, to the extent of arguably being a bug.
It also appears to be only partially implemented--why only
the instructions early in the alphabet?
 
Whether or not flags are set is part of the OpenRISC 1000
architectural specification. The only flags which should set
this are the "set flag" instructions: `l.sfeq', `l.sfeqi',
`l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui', `l.sfgts',
`l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles', `l.sflesi',
`l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi', `l.sfltu',
`l.sfltui', `l.sfne' and `l.sfnei'.
 
The flags are correctly set (irrespective of
`--enable-arith_flag').
 
Correct behavior is thus achieved if this flag is not set.
`--enable-arith-flag' should never be used.
 
 
`--enable-debug'
`--disable-debug'
This is a feature of the Argtable2 package used to process
arguments. If enabled, some debugging features are turned on in
Argtable2. It is provided for completeness, but there is no reason
why this feature should ever be needed by any Or1ksim user.
 
 

File: or1ksim.info, Node: Build and Install, Prev: Configuring the Build, Up: Installation
 
1.3 Building and Installing
===========================
 
The tool is then built with:
 
make all
1195,8 → 1323,35
Note: This enables the functionality of the debug unit (its
registers etc) within the mode. It does not provide any
external interface to the debug unit. For that, see
`gdb_enabled' below.
`gdb_enabled' and `rsp_enabled' below.
 
`rsp_enabled = 0|1'
If 1 (true), the GDB "Remote Serial Protocol" server is started,
provding an interface to an external GNU debugger, using the port
specified in the `rsp_port' field (see below), or the
`or1ksim-rsp' TCP/IP service. If 0 (the default), the server is
not started, and no external interface is provided.
 
For more detailed information on the interface to the GNU Debugger
see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
Practical Experience with the OpenRISC 1000 Architecture', by
Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
 
Note: `rsp_enabled' may not be enabled with `gdb_enabled'
(see below). If both are enabled, a warning is issued and
only the "Remote Serial Protocol" interface is enabled.
 
`rsp_port = VALUE'
VALUE specifies the port to be used for the GDB "Remote Serial
Protocol" interface to the GNU Debugger (GDB). Default value
51000. If the value 0 is specified, Or1ksim will instead look for
a TCP/IP service named `or1ksim-rsp'.
 
Tip: There is no registered port for Or1ksim "Remote Serial
Protocol" service `or1ksim-rsp'. Good practice suggests users
should adopt port values in the "Dynamic" or "Private" port
range, i.e. 49152-65535.
 
`gdb_enabled = 0|1'
If 1 (true), the OpenRISC Remote JTAG protocol server is started,
provding an interface to an external GNU debugger, using the port
1210,16 → 1365,20
Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
 
Note: The OpenRISC Remote JTAG protocol is unique to
OpenRISC, and is hard to justify maintaining long term. In
the future it will be replaced by an interface to the
standard GDB "Remote Serial Protocol", providing access to a
wider range of GDB functionality and easier ongoing
maintenance.
OpenRISC, and remains only for backward compatibility. New
users should adopt the standard GDB "Remote Serial Protocol"
interface (see `rsp_enabled' above) providing access to a
wider range of GDB functionality.
 
Note: `gdb_enabled' may not be enabled with `rsp_enabled'. If
both are enabled, a warning is issued and only the "Remote
Serial Protocol" interface is enabled.
 
`server_port = VALUE'
VALUE specifies the port to be used for the interface to the GNU
Debugger (GDB). Default value 51000. If the value 0 is specified,
Or1ksim will instead look for a TCP/IP service named `or1ksim'.
VALUE specifies the port to be used for the OpenRISC Rmote JTAG
protocol interface to the GNU Debugger (GDB). Default value 51000.
If the value 0 is specified, Or1ksim will instead look for a TCP/IP
service named `or1ksim'.
 
Tip: There is no registered port for Or1ksim Remote JTAG
Interface or service `or1ksim'. Good practice suggests users
2009,16 → 2168,11
command is useful when debugging the JTAG interface, used by
debuggers such as GDB.
 
Caution: There is no command to "unstall" the processor (this
would appear to be a bug). Once the processor has been
stalled, it can only be unstalled by using the `reset'
command, or a debugger sending the correct command to the
JTAG interface (using the OpenRISC 1000 Remote JTAG protocol).
`unstall'
Unstall the processor, so that normal execution can continue. This
command is useful when debugging the JTAG interface, used by
debuggers such as GDB.
 
In particular it is possible to stall a processor which does
not have the debugger enabled, and so cannot be unstalled by
any method other than a reset.
 
`stats CATEGORY | clear'
Print the statistics for the given CATEGORY, if available, or
clear if `clear' is specified. The categories are:
2939,11 → 3093,36
* --cumulative: Profiling Utility. (line 26)
* --debug-config: Standalone Simulator.
(line 48)
* --enable-ethphy: Installation. (line 25)
* --disable-arith-flag: Configuring the Build.
(line 93)
* --disable-debug: Configuring the Build.
(line 121)
* --disable-ethphy: Configuring the Build.
(line 54)
* --disable-ov-flag: Configuring the Build.
(line 70)
* --disable-profiling: Configuring the Build.
(line 25)
* --disable-range-stats: Configuring the Build.
(line 64)
* --enable-arith-flag: Configuring the Build.
(line 92)
* --enable-debug: Configuring the Build.
(line 120)
* --enable-ethphy: Configuring the Build.
(line 53)
* --enable-execution: Configuring the Build.
(line 32)
* --enable-mprofile: Standalone Simulator.
(line 60)
* --enable-ov-flag: Configuring the Build.
(line 69)
* --enable-profile: Standalone Simulator.
(line 57)
* --enable-profiling: Configuring the Build.
(line 24)
* --enable-range-stats: Configuring the Build.
(line 63)
* --file: Standalone Simulator.
(line 24)
* --filename: Memory Profiling Utility.
3006,6 → 3185,8
* 0x04 UART VAPI sub-command (UART verification): Verification API.
(line 66)
* 16550 (UART configuration): UART Configuration. (line 73)
* Argtable2 debugging: Configuring the Build.
(line 121)
* ATA/ATAPI configuration: Disc Interface Configuration.
(line 6)
* ATA/ATAPI device configuration: Disc Interface Configuration.
3061,6 → 3242,8
(line 54)
* command line for Or1ksim standalone use: Standalone Simulator.
(line 6)
* complex model: Configuring the Build.
(line 32)
* config: Global Data Structures.
(line 7)
* config.bpb: Global Data Structures.
3088,11 → 3271,11
* configuration global structure: Global Data Structures.
(line 7)
* configuration info (Interactive CLI): Interactive Command Line.
(line 124)
(line 119)
* configuration of generic peripherals: Generic Peripheral Configuration.
(line 6)
* configuration parameter setting (Interactive CLI): Interactive Command Line.
(line 151)
(line 146)
* configuring branch prediction: Branch Prediction Configuration.
(line 6)
* configuring data & instruction caches: Cache Configuration. (line 6)
3136,7 → 3319,7
* CPU configuration: CPU Configuration. (line 6)
* CUC configuration: CUC Configuration. (line 6)
* Custom Unit Compiler (Interactive CLI): Interactive Command Line.
(line 167)
(line 162)
* Custom Unit Compiler Configuration: CUC Configuration. (line 6)
* data cache configuration: Cache Configuration. (line 6)
* data MMU configuration: Memory Management Configuration.
3144,17 → 3327,19
* DCGE (power management register): Power Management Configuration.
(line 21)
* debug (Interactive CLI): Interactive Command Line.
(line 156)
(line 151)
* debug (simulator configuration): Simulator Behavior. (line 13)
* debug channel toggle (Interactive CLI): Interactive Command Line.
(line 146)
(line 141)
* debug interface configuration: Debug Interface Configuration.
(line 6)
* debug mode toggle (Interactive CLI): Interactive Command Line.
(line 156)
(line 151)
* debug unit configuration: Debug Interface Configuration.
(line 6)
* Debug Unit verification (VAPI): Verification API. (line 34)
* debugging enabled (Argtable2): Configuring the Build.
(line 121)
* delayr (memory configuration): Memory Configuration.
(line 109)
* delayw (memory configuration): Memory Configuration.
3193,9 → 3378,11
* doze mode (power management register): Power Management Configuration.
(line 15)
* dv (Interactive CLI): Interactive Command Line.
(line 129)
(line 124)
* dynamic clock gating (power management register): Power Management Configuration.
(line 21)
* dynamic model: Configuring the Build.
(line 32)
* dynamic ports, use of: Verification API Configuration.
(line 23)
* edge_trigger (interrupt controller): Interrupt Configuration.
3231,7 → 3418,8
(line 15)
* enabled (VGA configuration): Display Interface Configuration.
(line 22)
* enabling Ethernet via socket: Installation. (line 25)
* enabling Ethernet via socket: Configuring the Build.
(line 54)
* entrysize (MMU configuration): Memory Management Configuration.
(line 32)
* ETH_VAPI_CTRL (Ethernet verification): Verification API. (line 86)
3239,7 → 3427,8
* Ethernet configuration: Ethernet Configuration.
(line 6)
* Ethernet verification (VAPI): Verification API. (line 78)
* Ethernet via socket, enabling: Installation. (line 25)
* Ethernet via socket, enabling: Configuring the Build.
(line 54)
* exe_log (simulator configuration): Simulator Behavior. (line 48)
* exe_log_end (simulator configuration): Simulator Behavior. (line 88)
* exe_log_file (simulator configuration): Simulator Behavior. (line 96)
3272,10 → 3461,12
(line 47)
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
(line 117)
* flag setting by instructions: Configuring the Build.
(line 93)
* frame buffer configuration: Frame Buffer Configuration.
(line 6)
* gdb_enabled (debug interface configuration): Debug Interface Configuration.
(line 20)
(line 47)
* generic peripheral configuration: Generic Peripheral Configuration.
(line 6)
* GPIO configuration: GPIO Configuration. (line 6)
3291,9 → 3482,9
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
(line 121)
* help (Interactive CLI): Interactive Command Line.
(line 175)
(line 170)
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
(line 138)
(line 133)
* hide_device_id (verification API configuration): Verification API Configuration.
(line 36)
* hist (Interactive CLI): Interactive Command Line.
3314,7 → 3505,7
* index (memory controller configuration): Memory Controller Configuration.
(line 50)
* info (Interactive CLI): Interactive Command Line.
(line 124)
(line 119)
* installing Or1ksim: Installation. (line 6)
* instruction cache configuration: Cache Configuration. (line 6)
* instruction MMU configuration: Memory Management Configuration.
3321,7 → 3512,7
(line 6)
* instruction profiling for Or1ksim: Profiling Utility. (line 6)
* instruction profiling utility (Interactive CLI): Interactive Command Line.
(line 183)
(line 178)
* internal debugging: Internal Debugging. (line 6)
* interrupt controller configuration: Interrupt Configuration.
(line 6)
3362,9 → 3553,9
* memory display (Interactive CLI): Interactive Command Line.
(line 31)
* memory dump, hexadecimal (Interactive CLI): Interactive Command Line.
(line 138)
(line 133)
* memory dump, Verilog (Interactive CLI): Interactive Command Line.
(line 129)
(line 124)
* memory patching (Interactive CLI): Interactive Command Line.
(line 48)
* memory profiling end address: Memory Profiling Utility.
3372,7 → 3563,7
* memory profiling start address: Memory Profiling Utility.
(line 56)
* memory profiling utility (Interactive CLI): Interactive Command Line.
(line 178)
(line 173)
* memory profiling version of Or1ksim: Memory Profiling Utility.
(line 6)
* memory_order (CUC configuration): CUC Configuration. (line 15)
3392,7 → 3583,7
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
(line 33)
* mprofile (Interactive CLI): Interactive Command Line.
(line 178)
(line 173)
* mprofile (simulator configuration): Simulator Behavior. (line 28)
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
(line 128)
3415,6 → 3606,8
* or1ksim_run: Simulator Library. (line 35)
* or1ksim_set_time_point: Simulator Library. (line 51)
* output rediretion: Concepts. (line 7)
* overflow flag setting by instructions: Configuring the Build.
(line 70)
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
(line 113)
* pagesize (MMU configuration): Memory Management Configuration.
3478,6 → 3671,8
* processor configuration: CPU Configuration. (line 6)
* processor stall (Interactive CLI): Interactive Command Line.
(line 72)
* processor unstall (Interactive CLI): Interactive Command Line.
(line 78)
* prof_file (simulator configuration): Simulator Behavior. (line 23)
* prof_fn (simulator configuration - deprecated): Simulator Behavior.
(line 23)
3484,7 → 3679,7
* profile (simulator configuration): Simulator Behavior. (line 19)
* profiling for Or1ksim: Profiling Utility. (line 6)
* profiling utility (Interactive CLI): Interactive Command Line.
(line 183)
(line 178)
* program counter patching (Interactive CLI): Interactive Command Line.
(line 51)
* programmable interrupt controller configuration: Interrupt Configuration.
3506,8 → 3701,12
* reg_sim_reset: Concepts. (line 13)
* register display (Interactive CLI): Interactive Command Line.
(line 14)
* register over time statistics: Configuring the Build.
(line 64)
* register patching (Interactive CLI): Interactive Command Line.
(line 28)
* Remote Serial Protocol: Debug Interface Configuration.
(line 20)
* reset (Interactive CLI): Interactive Command Line.
(line 63)
* reset hooks: Concepts. (line 13)
3516,6 → 3715,10
* rev (ATA/ATAPI configuration): Disc Interface Configuration.
(line 44)
* rev (CPU configuration): CPU Configuration. (line 15)
* rsp_enabled (debug interface configuration): Debug Interface Configuration.
(line 20)
* rsp_port (debug interface configuration): Debug Interface Configuration.
(line 36)
* rtx_type (Ethernet configuration): Ethernet Configuration.
(line 46)
* run (Interactive CLI): Interactive Command Line.
3588,22 → 3791,24
* sectors (ATA/ATAPI device configuration): Disc Interface Configuration.
(line 125)
* server_port (debug interface configuration): Debug Interface Configuration.
(line 39)
(line 69)
* server_port (verification API configuration): Verification API Configuration.
(line 19)
* set (Interactive CLI): Interactive Command Line.
(line 151)
(line 146)
* set breakpoint (Interactive CLI): Interactive Command Line.
(line 57)
* setdbch (Interactive CLI): Interactive Command Line.
(line 146)
(line 141)
* simple model: Configuring the Build.
(line 32)
* simulator configuration: Simulator Behavior. (line 6)
* simulator configuration info (Interactive CLI): Interactive Command Line.
(line 124)
(line 119)
* simulator reset (Interactive CLI): Interactive Command Line.
(line 63)
* simulator statistics (Interactive CLI): Interactive Command Line.
(line 88)
(line 83)
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
(line 109)
* size (generic peripheral configuration): Generic Peripheral Configuration.
3623,10 → 3828,12
(line 72)
* stall the processor (Interactive CLI): Interactive Command Line.
(line 72)
* statistics, register over time: Configuring the Build.
(line 64)
* statistics, simulation (Interactive CLI): Interactive Command Line.
(line 88)
(line 83)
* stats (Interactive CLI): Interactive Command Line.
(line 88)
(line 83)
* stepping code (Interactive CLI): Interactive Command Line.
(line 19)
* store_hitdelay (data cache configuration): Cache Configuration.
3643,7 → 3850,9
* TCP/IP port range: Verification API Configuration.
(line 23)
* TCP/IP port range for or1ksim service: Debug Interface Configuration.
(line 43)
(line 74)
* TCP/IP port range for or1ksim-rsp service: Debug Interface Configuration.
(line 41)
* timings_file (CUC configuration): CUC Configuration. (line 46)
* timings_fn (CUC configuration - deprecated): CUC Configuration.
(line 46)
3650,9 → 3859,9
* toggle breakpoint (Interactive CLI): Interactive Command Line.
(line 57)
* toggle debug channels (Interactive CLI): Interactive Command Line.
(line 146)
(line 141)
* toggle debug mode (Interactive CLI): Interactive Command Line.
(line 156)
(line 151)
* tx_channel (Ethernet configuration): Ethernet Configuration.
(line 60)
* txfile (Ethernet configuration): Ethernet Configuration.
3681,6 → 3890,10
* UART I/O from/to open file descriptors: UART Configuration. (line 58)
* UART I/O from/to TCP/IP: UART Configuration. (line 45)
* UART verification (VAPI): Verification API. (line 41)
* unstall (Interactive CLI): Interactive Command Line.
(line 78)
* unstall the processor (Interactive CLI): Interactive Command Line.
(line 78)
* upr (CPU configuration): CPU Configuration. (line 21)
* ustates (cache configuration): Cache Configuration. (line 33)
* ustates (MMU configuration): Memory Management Configuration.
3693,7 → 3906,7
* VAPI for GPIO: Verification API. (line 88)
* VAPI for UART: Verification API. (line 41)
* vapi_id (debug interface configuration): Debug Interface Configuration.
(line 49)
(line 80)
* vapi_id (DMA configuration) <1>: Ethernet Configuration.
(line 88)
* vapi_id (DMA configuration): DMA Configuration. (line 38)
3708,7 → 3921,7
* Verification API configuration: Verification API Configuration.
(line 6)
* Verilog memory dump (Interactive CLI): Interactive Command Line.
(line 129)
(line 124)
* VGA configuration: Display Interface Configuration.
(line 6)
* word_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3719,48 → 3932,51
Tag Table:
Node: Top808
Node: Installation1218
Node: Usage2778
Node: Standalone Simulator2992
Node: Profiling Utility5012
Node: Memory Profiling Utility5920
Node: Simulator Library7279
Node: Configuration11225
Node: Configuration File Format11831
Node: Configuration File Preprocessing12123
Node: Configuration File Syntax12493
Node: Simulator Configuration15271
Node: Simulator Behavior15562
Node: Verification API Configuration19578
Node: CUC Configuration21507
Node: Core OpenRISC Configuration23412
Node: CPU Configuration23914
Node: Memory Configuration27704
Node: Memory Management Configuration32980
Node: Cache Configuration35341
Node: Interrupt Configuration37707
Node: Power Management Configuration38439
Node: Branch Prediction Configuration39711
Node: Debug Interface Configuration41064
Node: Peripheral Configuration43708
Node: Memory Controller Configuration44333
Node: UART Configuration46930
Node: DMA Configuration50436
Node: Ethernet Configuration52291
Node: GPIO Configuration56247
Node: Display Interface Configuration57870
Node: Frame Buffer Configuration60170
Node: Keyboard Configuration62020
Node: Disc Interface Configuration64246
Node: Generic Peripheral Configuration69161
Node: Interactive Command Line71445
Node: Verification API78744
Node: Code Internals83162
Node: Coding Conventions83719
Node: Global Data Structures88134
Node: Concepts90786
Ref: Output Redirection90931
Node: Internal Debugging91468
Node: GNU Free Documentation License91964
Node: Index114371
Node: Preparation1448
Node: Configuring the Build1741
Node: Build and Install6855
Node: Usage7523
Node: Standalone Simulator7737
Node: Profiling Utility9757
Node: Memory Profiling Utility10665
Node: Simulator Library12024
Node: Configuration15970
Node: Configuration File Format16576
Node: Configuration File Preprocessing16868
Node: Configuration File Syntax17238
Node: Simulator Configuration20016
Node: Simulator Behavior20307
Node: Verification API Configuration24323
Node: CUC Configuration26252
Node: Core OpenRISC Configuration28157
Node: CPU Configuration28659
Node: Memory Configuration32449
Node: Memory Management Configuration37725
Node: Cache Configuration40086
Node: Interrupt Configuration42452
Node: Power Management Configuration43184
Node: Branch Prediction Configuration44456
Node: Debug Interface Configuration45809
Node: Peripheral Configuration50009
Node: Memory Controller Configuration50634
Node: UART Configuration53231
Node: DMA Configuration56737
Node: Ethernet Configuration58592
Node: GPIO Configuration62548
Node: Display Interface Configuration64171
Node: Frame Buffer Configuration66471
Node: Keyboard Configuration68321
Node: Disc Interface Configuration70547
Node: Generic Peripheral Configuration75462
Node: Interactive Command Line77746
Node: Verification API84694
Node: Code Internals89112
Node: Coding Conventions89669
Node: Global Data Structures94084
Node: Concepts96736
Ref: Output Redirection96881
Node: Internal Debugging97418
Node: GNU Free Documentation License97914
Node: Index120321

End Tag Table
/trunk/or1ksim/doc/stamp-vti
1,4 → 1,4
@set UPDATED 12 October 2008
@set UPDATED-MONTH October 2008
@set EDITION 0.3.0rc1
@set VERSION 0.3.0rc1
@set UPDATED 11 November 2008
@set UPDATED-MONTH November 2008
@set EDITION 0.3.0rc2
@set VERSION 0.3.0rc2
/trunk/or1ksim/doc/or1ksim.texi
70,9 → 70,20
@chapter Installation
@cindex installing @value{OR1KSIM}
 
Installation follows standard GNU protocols. Unpack the software and
create a @emph{separate} directory in which to build it:
Installation follows standard GNU protocols.
 
@menu
* Preparation::
* Configuring the Build::
* Build and Install::
@end menu
 
@node Preparation
@section Preparation
 
Unpack the software and create a @emph{separate} directory in which to
build it:
 
@example
@kbd{tar jxf or1ksim-@value{VERSION}.tar.bz2}
@kbd{mkdir builddir_or1ksim}
79,32 → 90,165
@kbd{cd builddir_or1ksim}
@end example
 
Configure the software. The only critical argument is @code{--target},
which must specify the OpenRISC 1000 architecture.
@node Configuring the Build
@section Configuring the Build
 
Configure the software using the @command{configure} script in the
main directory.
 
The most significant argument is @code{--target}, which should specify
the OpenRISC 1000 32-bit architecture. If this argument is omitted, it will
default to OpenRISC 1000 32-bit with a warning
 
@example
@kbd{../or1ksim-@value{VERSION}/configure --target=or32-uclinux ...}
@end example
 
See @kbd{configure --help} for other options. The most useful is
@code{--prefix} to specify a directory for installation of the tools.
There are several other options available, many of which are standard
to GNU @command{configure} scripts. Use @kbd{configure --help} to see
all the options. The most useful is @code{--prefix} to specify a
directory for installation of the tools.
 
A number of features in the simulator do require enabling at
A number of @value{OR1KSIM} features in the simulator do require enabling at
configuration. These include
 
@table @code
@item --enable-profiling
@cindex @code{--enable-profiling}
@itemx --disable-profiling
@cindex @code{--disable-profiling}
If enabled, Or1ksim is compiled for profiling with
@command{gprof}. This is disabled by default. Only really of value for
developers of @value{OR1KSIM}.
 
@item --enable-execution=simple
@itemx --enable-execution=complex
@itemx --enable-execution=dynamic
@cindex @code{--enable-execution}
@cindex simple model
@cindex complex model
@cindex dynamic model
@value{OR1KSIM} has developed to improve functionality and
performance. This feature allows three versions of Or1ksim to be built
 
@table @code
 
@item --enable-execution=simple
Build the original simple interpreting simulator
 
@item --enable-execution=complex
Build a more complex interpreting simulator. Experiments suggest this
is 50% faster than the simple simulator. This is the default.
 
@item --enable-execution=dynamic
Build a dynamically compiling simulator. This is the way many modern ISS are
built. This represents a work in progress. Currently @value{OR1KSIM} will
compile, but segfaults if configured with this option.
 
@end table
 
The default is @code{--enable-execution=complex}.
 
@item --enable-ethphy
@cindex @code{--enable-ethphy}
@itemx --disable-ethphy
@cindex @code{--disable-ethphy}
@cindex Ethernet via socket, enabling
@cindex enabling Ethernet via socket
Allow the Ethernet to be simulated by connecting via a socket (the
alternative reads and writes, from and to files). This must then be
configured using the relevant fields in the @code{ethernet} section of
the configuration file. @xref{Ethernet Configuration, , Ethernet
Configuration}.
If enabled, this option allows the Ethernet to be simulated by connecting via a
socket (the alternative reads and writes, from and to files). This
must then be configured using the relevant fields in the
@code{ethernet} section of the configuration file. @xref{Ethernet
Configuration, , Ethernet Configuration}.
 
The default is for this to be disabled.
 
@item --enable-range-stats
@cindex @code{--enable-range-stats}
@itemx --disable-range-stats
@cindex @code{--disable-range-stats}
@cindex statistics, register over time
@cindex register over time statistics
If enabled, this option allows statistics to be collected to analyse
register access over time. The default is for this to be disabled.
 
@item --enable-ov-flag
@cindex @code{--enable-ov-flag}
@itemx --disable-ov-flag
@cindex @code{--disable-ov-flag}
@cindex overflow flag setting by instructions
If enabled, this option causes instructions to set the overflow
flag. The instructions affected by this are @code{l.add},
@code{l.addc}, @code{l.addi}, @code{l.and}, @code{l.andi},
@code{l.div}, @code{l.divu}, @code{l.mul}, @code{l.muli}, @code{l.or},
@code{l.ori}, @code{l.sll}, @code{l.slli}, @code{l.srl},
@code{l.srli}, @code{l.sra}, @code{l.srai}, @code{l.sub}, @code{l.xor}
and @code{l.xori}.
 
The default is for this to be disabled.
 
@quotation Caution
This appears a very dangerous option, to the extent of arguably being
a bug. Whether or not flags are set is part of the OpenRISC 1000
architectural specification. Within the above list, the arithmetic
instructions (@code{l.add}, @code{l.addc}, @code{l.addi},
@code{l.div}, @code{l.divu}, @code{l.mul}, @code{l.muli} and
@code{l.sub}), together with @code{l.addic} which is missed out, set
the overflow flag. All the others (@code{l.and}, @code{l.andi},
@code{l.or}, @code{l.ori}, @code{l.sll}, @code{l.slli}, @code{l.srl},
@code{l.srli}, @code{l.sra}, @code{l.srai}, @code{l.xor} and
@code{l.xori}) do not.
 
Thus it is impossible to get correct behavior whichever way this option is
set.
@end quotation
 
@item --enable-arith-flag
@cindex @code{--enable-arith-flag}
@itemx --disable-arith-flag
@cindex @code{--disable-arith-flag}
@cindex flag setting by instructions
If enabled, this option causes instructions to set the flag (@code{F} bit) in
the supervision register. The instructions affected by this are @code{l.add},
@code{l.addc}, @code{l.addi}, @code{l.and} and @code{l.andi}.
 
The default is for this to be disabled.
 
@quotation Caution
As with @code{--enable-ov-flag}, this appears another very dangerous option,
to the extent of arguably being a bug. It also appears to be only partially
implemented---why only the instructions early in the alphabet?
 
Whether or not flags are set is part of the OpenRISC 1000 architectural
specification. The only flags which should set this are the ``set flag''
instructions: @code{l.sfeq}, @code{l.sfeqi}, @code{l.sfges}, @code{l.sfgesi},
@code{l.sfgeu}, @code{l.sfgeui}, @code{l.sfgts}, @code{l.sfgtsi},
@code{l.sfgtu}, @code{l.sfgtui}, @code{l.sfles}, @code{l.sflesi},
@code{l.sfleu}, @code{l.sfleui}, @code{l.sflts}, @code{l.sfltsi},
@code{l.sfltu}, @code{l.sfltui}, @code{l.sfne} and @code{l.sfnei}.
 
The flags are correctly set (irrespective of @code{--enable-arith_flag}).
 
Correct behavior is thus achieved if this flag is not set.
@code{--enable-arith-flag} should never be used.
 
@end quotation
 
@item --enable-debug
@cindex @code{--enable-debug}
@itemx --disable-debug
@cindex @code{--disable-debug}
@cindex debugging enabled (Argtable2)
@cindex Argtable2 debugging
This is a feature of the Argtable2 package used to process arguments. If
enabled, some debugging features are turned on in Argtable2. It is provided for
completeness, but there is no reason why this feature should ever be needed by
any @value{OR1KSIM} user.
 
@end table
 
@node Build and Install
@section Building and Installing
The tool is then built with:
 
@example
1481,42 → 1625,80
 
@item enabled = 0|1
@cindex @code{enabled} (debug interface configuration)
If 1 (true), the debug unit is enabled. If 0 (the default), it is
disabled.
If 1 (true), the debug unit is enabled. If 0 (the default), it is disabled.
 
@quotation Note
This enables the functionality of the debug unit (its registers etc)
within the mode. It does not provide any external interface to the
debug unit. For that, see @code{gdb_enabled} below.
This enables the functionality of the debug unit (its registers etc) within
the mode. It does not provide any external interface to the debug unit. For
that, see @code{gdb_enabled} and @code{rsp_enabled} below.
@end quotation
 
@item rsp_enabled = 0|1
@cindex @code{rsp_enabled} (debug interface configuration)
@cindex Remote Serial Protocol
If 1 (true), the GDB @dfn{Remote Serial Protocol} server is started, provding
an interface to an external GNU debugger, using the port specified in the
@code{rsp_port} field (see below), or the @code{or1ksim-rsp} TCP/IP
service. If 0 (the default), the server is not started, and no external
interface is provided.
 
For more detailed information on the interface to the GNU Debugger see
Embecosm Application Note 2, @cite{Howto: Porting the GNU Debugger Practical
Experience with the OpenRISC 1000 Architecture}, by Jeremy Bennett, published
by Embecosm Limited (@url{www.embecosm.com}).
 
@quotation Note
@code{rsp_enabled} may not be enabled with @code{gdb_enabled} (see below). If
both are enabled, a warning is issued and only the @dfn{Remote Serial
Protocol} interface is enabled.
@end quotation
 
@item rsp_port = @var{value}
@cindex @code{rsp_port} (debug interface configuration)
@var{value} specifies the port to be used for the GDB @dfn{Remote Serial
Protocol} interface to the GNU Debugger (GDB). Default value 51000. If
the value 0 is specified, @value{OR1KSIM} will instead look for a TCP/IP
service named @code{or1ksim-rsp}.
 
@quotation Tip
@cindex TCP/IP port range for @code{or1ksim-rsp} service
There is no registered port for @value{OR1KSIM} @dfn{Remote Serial Protocol}
service @code{or1ksim-rsp}. Good practice suggests users should adopt port
values in the @dfn{Dynamic} or @dfn{Private} port range, i.e. 49152-65535.
@end quotation
 
@item gdb_enabled = 0|1
@cindex @code{gdb_enabled} (debug interface configuration)
If 1 (true), the OpenRISC Remote JTAG protocol server is started,
provding an interface to an external GNU debugger, using the port
specified in the @code{server_port} field (see below), or the
@code{or1ksim} TCP/IP service. If 0 (the default), the server is not
started, and no external interface is provided.
If 1 (true), the OpenRISC Remote JTAG protocol server is started, provding an
interface to an external GNU debugger, using the port specified in the
@code{server_port} field (see below), or the @code{or1ksim} TCP/IP service. If
0 (the default), the server is not started, and no external interface is
provided.
 
For more detailed information on the interface to the GNU Debugger see
Embecosm Application Note 2, @cite{Howto: Porting the GNU Debugger
Practical Experience with the OpenRISC 1000 Architecture}, by Jeremy
Bennett, published by Embecosm Limited (@url{www.embecosm.com}).
Embecosm Application Note 2, @cite{Howto: Porting the GNU Debugger Practical
Experience with the OpenRISC 1000 Architecture}, by Jeremy Bennett, published
by Embecosm Limited (@url{www.embecosm.com}).
 
@quotation Note
The OpenRISC Remote JTAG protocol is unique to OpenRISC, and is hard
to justify maintaining long term. In the future it will be replaced by
an interface to the standard GDB @dfn{Remote Serial Protocol},
providing access to a wider range of GDB functionality and easier
ongoing maintenance.
The OpenRISC Remote JTAG protocol is unique to OpenRISC, and remains only for
backward compatibility. New users should adopt the standard GDB @dfn{Remote
Serial Protocol} interface (see @code{rsp_enabled} above) providing access to
a wider range of GDB functionality.
@end quotation
 
@quotation Note
@code{gdb_enabled} may not be enabled with @code{rsp_enabled}. If both are
enabled, a warning is issued and only the @dfn{Remote Serial Protocol}
interface is enabled.
@end quotation
 
@item server_port = @var{value}
@cindex @code{server_port} (debug interface configuration)
@var{value} specifies the port to be used for the interface to the GNU
Debugger (GDB). Default value 51000. If the value 0 is specified,
@value{OR1KSIM} will instead look for a TCP/IP service named
@code{or1ksim}.
@var{value} specifies the port to be used for the OpenRISC Rmote JTAG
protocol interface to the GNU Debugger (GDB). Default value 51000. If
the value 0 is specified, @value{OR1KSIM} will instead look for a TCP/IP
service named @code{or1ksim}.
 
@quotation Tip
@cindex TCP/IP port range for @code{or1ksim} service
2489,18 → 2671,13
useful when debugging the JTAG interface, used by debuggers such as
GDB.
 
@quotation Caution
There is no command to ``unstall'' the processor (this would appear to
be a bug). Once the processor has been stalled, it can only be
unstalled by using the @code{reset} command, or a debugger sending the
correct command to the JTAG interface (using the OpenRISC 1000 Remote
JTAG protocol).
@item unstall
@cindex @code{unstall} (Interactive CLI)
@cindex processor unstall (Interactive CLI)
@cindex unstall the processor (Interactive CLI)
Unstall the processor, so that normal execution can continue. This command is
useful when debugging the JTAG interface, used by debuggers such as GDB.
 
In particular it is possible to stall a processor which does not have
the debugger enabled, and so cannot be unstalled by any method other
than a reset.
@end quotation
 
@item stats @var{category} | clear
@cindex @code{stats} (Interactive CLI)
@cindex simulator statistics (Interactive CLI)
/trunk/or1ksim/doc/version.texi
1,4 → 1,4
@set UPDATED 12 October 2008
@set UPDATED-MONTH October 2008
@set EDITION 0.3.0rc1
@set VERSION 0.3.0rc1
@set UPDATED 11 November 2008
@set UPDATED-MONTH November 2008
@set EDITION 0.3.0rc2
@set VERSION 0.3.0rc2
/trunk/or1ksim/cuc/adv.c
195,6 → 195,7
else if (f->INSN(ref).opt[o] & OPT_CONST) return f->INSN(ref).op[o];
else if (f->INSN(ref).opt[o] & OPT_REGISTER) return 0xffffffff;
else assert (0);
return 0;
}
 
/* Returns maximum value, based on inputs */
/trunk/or1ksim/cuc/cuc.c
202,6 → 202,7
return timings;
}
 
 
/* Simple comparison function */
int
tim_comp (cuc_timings * a, cuc_timings * b)
334,8 → 335,13
t[i].b, t[i].preroll, t[i].unroll, t[i].new_time);
#endif
 
#if HAVE___COMPAR_FN_T
qsort (t, nt, sizeof (cuc_timings),
(int (*)(const void *, const void *)) tim_comp);
(__compar_fn_t) tim_comp);
#else
qsort (t, nt, sizeof (cuc_timings),
(int (*) (const void *, const void *)) tim_comp);
#endif
 
/* Delete timings, that have worst time and bigger size than other */
j = 1;
378,8 → 384,13
t[i].size);
 
/* Sort again with new timings added */
#if HAVE___COMPAR_FN_T
qsort (t, nt, sizeof (cuc_timings),
(__compar_fn_t) tim_comp);
#else
qsort (t, nt, sizeof (cuc_timings),
(int (*)(const void *, const void *)) tim_comp);
#endif
 
/* Delete timings, that have worst time and bigger size than other */
j = 1;
/trunk/or1ksim/sim-cmd.c
57,6 → 57,7
#include "branch-predict.h"
#include "debug.h"
#include "cuc.h"
#include "rsp-server.h"
 
 
/* The number of instructions to execute before droping into interactive mode */
693,6 → 694,9
cur_arg = readline ("(sim) ");
#else
PRINTF ("(sim) ");
 
/* RSP does not get involved during CLI, so only check legacy interface
here. */
if (config.debug.gdb_enabled)
{
fflush (stdout);
808,7 → 812,13
int
check_gdb_comm (void)
{
handle_server_socket (TRUE); /* block & check_stdin = true */
/* Only do anything for legacy debug interface. RSP does not get involved
when the CLI is active */
if (config.debug.gdb_enabled)
{
handle_server_socket (TRUE); /* block & check_stdin = true */
}
 
return 0;
}
 
/trunk/or1ksim/pic/pic.c
43,9 → 43,7
#include "sprs.h"
#include "sim-config.h"
#include "sched.h"
#include "debug.h"
 
DEFAULT_DEBUG_CHANNEL (pic);
 
/* FIXME: This ugly hack will be removed once the bus architecture gets written
*/
69,7 → 67,6
{
if (cpu_state.sprs[SPR_PICSR])
{
TRACE ("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
}
}
94,9 → 91,6
/* Disable doze and sleep mode */
cpu_state.sprs[SPR_PMR] &= ~(SPR_PMR_DME | SPR_PMR_SME);
 
TRACE ("Asserting interrupt %d (%s).\n", line,
(cpu_state.sprs[SPR_PICMR] & lmask) ? "Unmasked" : "Masked");
 
/* If PIC is disabled, don't set any register, just raise EXCEPT_INT */
if (!config.pic.enabled)
{
108,7 → 102,7
if (cpu_state.pic_lines & lmask)
{
/* No edge occured, warn about performance penalty and exit */
WARN ("Int line %d did not change state\n", line);
fprintf (stderr, "Warning: Int line %d did not change state\n", line);
return;
}
 
124,7 → 118,6
void
clear_interrupt (int line)
{
TRACE ("Clearing interrupt %d\n", line);
cpu_state.pic_lines &= ~(1 << line);
 
if (!config.pic.edge_trigger)
/trunk/or1ksim/ChangeLog
1,3 → 1,41
2008-11-17 Jeremy Bennett <jeremy.bennett@embecosm.com>
* sim-config.c: MERROR deleted (not used). WARNING replaced by
explicit fprintf calls.
* sim-config.h, sim-config.c, peripheral/16450.c: CONFIG_ERROR
replaced by fprintf.
 
2008-11-16 Jeremy Bennett <jeremy.bennett@embecosm.com>
* debug/gdbcomm.c (get_server_socket): server_ip flag getting by
fcntl corrected (wrong syntax used for GETFL).
2008-11-16 Jeremy Bennett <jeremy.bennett@embecosm.com>
* doc/or1ksim.texi: Documentation of the various configuration
options added.
2008-11-16 Jeremy Bennett <jeremy.bennett@embecosm.com>
* cpu/or32/op-mftspr-op.h, cpu/or32/op.c, cpu/or32/dyn32-defs.h,
cpu/or32/def_op_t.h, cpu/or32/op-support.c, cpu/or32/op-swhb-op.h,
cpu/or32/dyn-rec.c, cpu/or32/execute.c, cpu/or32/op-arith-op.h,
cpu/or32/dyn-rec.h, cpu/or32/simpl32-defs.h, cpu/or32/insnset.c,
cpu/or32/dyngen.c, cpu/or32/dyngen-elf.c, cpu/or32/Makefile.am:
Numerous changes to ensure compilation succeeds with
DYNAMIC_EXECUTION.
 
2008-11-16 Jeremy Bennett <jeremy.bennett@embecosm.com>
* cpu/or1k/opcode/or32.h: Change include of simple32_defs.h to
simple32-defs.h and dyn32_defs.h to dyn32-defs.h
* cpu/or32/simple32-defs.h: Made conditional and added include of
* cpu/or32/Makefile.am: For simple execution removed insnset.c
from the sources and added it to EXTRA sources.
2008-10-15 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure.ac: Corrected gcc args for --enabled-profiling
* cpu/common/stats.h, cpu/common/stats.c: Moved definition of
RAW_RANGE to stats.h from stats.c. Made declaration of raw_stats
non-static and added extern declaration to stats.h
* cpu/common/stats.c (printstats): Changed MAX_RANGE to RAW_RANGE
* cpu/or32/execute.c (evalsim_reg): Changed MAX_RAW_RANGE to RAW_RANGE
2008-10-11 Jeremy Bennett <jeremy.bennett@embecosm.com>
* all: Removed redundant headers added missing GPL statements,
formatted to GNU standard. Made all non-global functions and top
/trunk/or1ksim/peripheral/gpio.c
34,7 → 34,6
/* Package includes */
#include "sim-config.h"
#include "arch.h"
#include "debug.h"
#include "vapi.h"
#include "sched.h"
#include "pic.h"
62,9 → 61,7
#define RGPIO_CTRL_INTE 0x00000004
#define RGPIO_CTRL_INTS 0x00000008
 
DEFAULT_DEBUG_CHANNEL (gpio);
 
 
/*
* The various VAPI IDs each GPIO device has
*/
204,7 → 201,6
switch (addr)
{
case RGPIO_IN:
TRACE ("GPIO: Cannot write to RGPIO_IN\n");
break;
case RGPIO_OUT:
gpio->next.out = value;
240,15 → 236,11
unsigned which;
struct gpio_device *gpio = dat;
 
TRACE ("GPIO: id %08lx, data %08lx\n", id, data);
 
which = id - gpio->base_vapi_id;
 
switch (which)
{
case GPIO_VAPI_DATA:
TRACE ("GPIO: Next input from VAPI = 0x%08lx (RGPIO_OE = 0x%08lx)\n",
data, gpio->next.oe);
gpio->next.in = data;
break;
case GPIO_VAPI_AUX:
332,8 → 324,6
/* If any outputs changed, notify the world (i.e. vapi) */
if (gpio->next.out != gpio->curr.out)
{
TRACE ("GPIO: New output 0x%08lx, RGPIO_OE = 0x%08lx\n", gpio->next.out,
gpio->next.oe);
if (gpio->base_vapi_id)
vapi_send (gpio->base_vapi_id + GPIO_VAPI_DATA, gpio->next.out);
}
341,8 → 331,6
/* If any inputs changed and interrupt enabled, generate interrupt */
if (gpio->next.in != gpio->curr.in)
{
TRACE ("GPIO: New input 0x%08lx\n", gpio->next.in);
 
if (gpio->next.ctrl & RGPIO_CTRL_INTE)
{
unsigned changed_bits = gpio->next.in ^ gpio->curr.in; /* inputs that have changed */
354,7 → 342,6
 
if (relevant_bits & gpio->next.inte)
{
TRACE ("GPIO: Reporting interrupt %d\n", gpio->irq);
gpio->next.ctrl |= RGPIO_CTRL_INTS;
gpio->next.ints |= relevant_bits & gpio->next.inte;
/* Since we can't report an interrupt during a readmem/writemem
/trunk/or1ksim/peripheral/mc.c
46,7 → 46,6
#include "arch.h"
#include "abstract.h"
#include "sim-config.h"
#include "debug.h"
#include "toplevel-support.h"
#include "sim-cmd.h"
 
137,7 → 136,6
#define MC_TMS_SYNC_TRDV_OFFSET 0
#define MC_TMS_SYNC_TRDV_WIDTH 8
 
DEFAULT_DEBUG_CHANNEL (mc);
 
struct mc_area
{
182,12 → 180,6
{
/* FIXME: No peripheral should _ever_ acess a dev_memarea structure
* directly */
TRACE ("Remapping %" PRIxADDR "-%" PRIxADDR " to %" PRIxADDR "-%"
PRIxADDR "\n", cur->mem->addr_compare,
cur->mem->addr_compare | cur->mem->size_mask,
(csc >> MC_CSC_SEL_OFFSET) << 22,
((csc >> MC_CSC_SEL_OFFSET) << 22) | cur->mem->size_mask);
 
cur->mem->addr_mask = mc->ba_mask << 22;
cur->mem->addr_compare =
((csc >> MC_CSC_SEL_OFFSET) /* & 0xff */ ) << 22;
228,8 → 220,6
struct mc *mc = dat;
int chipsel;
 
TRACE ("mc_write_word(%" PRIxADDR ",%08" PRIx32 ")\n", addr, value);
 
switch (addr)
{
case MC_CSR:
236,7 → 226,7
mc->csr = value;
break;
case MC_POC:
WARN ("warning: write to MC's POC register!");
fprintf (stderr, "Warning: write to MC's POC register!");
break;
case MC_BA_MASK:
mc->ba_mask = value & MC_BA_MASK_VALID;
255,9 → 245,6
set_csc_tms (addr >> 3, mc->csc[addr >> 3], mc->tms[addr >> 3], mc);
break;
}
else
TRACE ("write out of range (addr %" PRIxADDR ")\n",
addr + mc->baseaddr);
}
}
 
268,8 → 255,6
struct mc *mc = dat;
uint32_t value = 0;
 
TRACE ("mc_read_word(%" PRIxADDR ")", addr);
 
switch (addr)
{
case MC_CSR:
290,12 → 275,9
else
value = mc->csc[addr >> 3];
}
else
TRACE (" read out of range (addr %" PRIxADDR ")\n",
addr + mc->baseaddr);
 
break;
}
TRACE (" value(%" PRIx32 ")\n", value);
return value;
}
 
/trunk/or1ksim/peripheral/atadevice-cmdi.c
34,12 → 34,9
#include "atadevice-cmdi.h"
#include "atahost.h"
#include "atacmd.h"
#include "debug.h"
#include "sched.h"
 
 
DEFAULT_DEBUG_CHANNEL (ata);
 
/* FIXME: If device0 is not selected and then an interrupt occurs and
* then it is selected, the interrupt should be delivered, but I just drop it
* (same goes for device 1). */
48,9 → 45,6
{
struct ata_device *dev = dat;
 
TRACE ("Cmd completed intrq: %i, dev: %i\n", dev->sigs.intrq,
dev->internals.dev ? 1 : 0);
 
dev->regs.status &= ~ATA_SR_BSY;
 
if (dev->regs.device_control & ATA_DCR_IEN)
125,8 → 119,6
if (!dev->internals.nr_sect)
return;
 
TRACE ("Reading sector from %" PRId32 "\n", dev->internals.lba);
 
/* set the file-positon pointer to the start of the sector */
fseek (dev->conf.stream, dev->internals.lba, SEEK_SET);
 
156,8 → 148,6
return;
}
 
TRACE ("Writeing sector to %" PRId32 "\n", dev->internals.lba);
 
/* set the file-positon pointer to the start of the sector */
fseek (dev->conf.stream, dev->internals.lba, SEEK_SET);
 
213,9 → 203,6
void
ata_execute_device_diagnostics_cmd (struct ata_device *device)
{
/* print debug information */
TRACE ("executing command 'execute_device_diagnostics'\n");
 
/* clear SRST bit, if set */
device->regs.device_control &= ~ATA_DCR_RST;
 
266,11 → 253,11
static void
ata_device_reset_cmd (struct ata_device *device)
{
/* print debug information */
TRACE ("executing command 'device reset'\n");
 
if (!device->conf.packet)
WARN ("executing DEVICE_RESET on non-packet device.");
{
fprintf( stderr, "Warning: executing DEVICE_RESET on non-packet "
"device\n");
}
 
ata_execute_device_diagnostics_cmd (device);
}
287,9 → 274,6
int n;
unsigned int tmp;
 
/* print debug information */
TRACE ("ata_device executing command 'identify device'\n");
 
/* reset databuffer */
device->internals.dbuf_cnt = 256;
device->internals.dbuf_ptr = device->internals.dbuf;
362,7 → 346,6
Respond by placing PACKET Command feature set signature in block registers.
Abort command.
*/
TRACE ("'identify_device' command: This is a PACKET device\n");
 
ata_set_device_signature (device, 1);
device->regs.status = ATA_SR_ERR;
930,9 → 913,6
static void
ata_initialize_device_parameters_cmd (struct ata_device *device)
{
/* print debug information */
TRACE ("executing command 'initialize device parameters'\n");
 
device->internals.sectors_per_track = device->regs.sector_count;
device->internals.heads_per_cylinder = device->regs.device_head & ATA_DHR_H;
 
950,9 → 930,6
size_t sector_count;
uint32_t lba;
 
/* print debug information */
TRACE ("executing command 'read sectors'\n");
 
/* check if this is a NON-PACKET device */
if (device->conf.packet)
{
961,8 → 938,6
Respond by placing PACKET Command feature set signature in block registers.
Abort command.
*/
TRACE ("'identify_device' command: This is a PACKET device\n");
 
ata_set_device_signature (device, 1);
device->regs.status = ATA_SR_ERR | ATA_SR_DRDY;
device->regs.error = ATA_ERR_ABT;
977,15 → 952,11
 
lba = ata_calc_lba (device);
 
TRACE ("Reading from lba %i, %i sectors\n", lba, sector_count);
 
/* check if sector within bounds */
if (lba >= device->conf.size_sect)
{
/* invalid sector address */
/* set the status & error registers */
TRACE ("Sector read out-of-bounds: %i >= %i\n", lba,
device->conf.size_sect);
device->regs.status = ATA_SR_DRDY | ATA_SR_ERR;
device->regs.error = ATA_ERR_IDNF;
return;
1009,7 → 980,6
static void
ata_read_native_max_addr (struct ata_device *dev)
{
TRACE ("executing command 'read native max addr'\n");
// FIXME: Left shift????
ata_set_sect (dev, dev->conf.size << 11);
 
1025,8 → 995,6
size_t sector_count;
uint32_t lba;
 
TRACE ("executing command 'write sectors'\n");
 
if (dev->conf.packet)
{
ata_set_device_signature (dev, 1);
1043,15 → 1011,11
 
lba = ata_calc_lba (dev);
 
TRACE ("Writeing to lba %i, %i sectors\n", lba, sector_count);
 
/* check if sector within bounds */
if (lba >= dev->conf.size_sect)
{
/* invalid sector address */
/* set the status & error registers */
TRACE ("Sector read out-of-bounds: %i >= %i\n", lba,
dev->conf.size_sect);
dev->regs.status = ATA_SR_DRDY | ATA_SR_ERR;
dev->regs.error = ATA_ERR_IDNF;
return;
1082,14 → 1046,16
case 0: /* Set default */
break;
case 1: /* Set PIO mode */
TRACE ("Setting device pio mode %d\n",
dev->regs.sector_count & 0x7);
break;
case 4: /* Set DMA mode */
FIXME ("Set DMA mode to %d\n", dev->regs.sector_count & 0x7);
/* FIXME */
fprintf (stderr, "Fixme: Set DMA mode to %d\n",
dev->regs.sector_count & 0x7);
break;
case 8: /* Set UDMA mode */
FIXME ("Set UDMA mode to %d\n", dev->regs.sector_count & 0x7);
/* FIXME */
fprintf (stderr, "Fixme: Set UDMA mode to %d\n",
dev->regs.sector_count & 0x7);
break;
}
dev->regs.status = ATA_SR_DSC | ATA_SR_DRDY | ATA_SR_BSY;
1097,7 → 1063,9
default:
dev->regs.error = ATA_ERR_ABT;
dev->regs.status = ATA_SR_ERR | ATA_SR_BSY | ATA_SR_DRDY;
FIXME ("Unknown set features sub-command %x\n", dev->regs.features);
/* FIXME */
fprintf (stderr, "Fixme: Unknown set features sub-command %x\n",
dev->regs.features);
}
}
 
1105,9 → 1073,6
int
ata_device_execute_cmd (struct ata_device *device)
{
/*display debug information */
TRACE ("command: 0x%02X\n", device->regs.command);
 
/* execute the commands */
switch (device->regs.command)
{
1156,7 → 1121,8
default:
device->regs.error = ATA_ERR_ABT;
device->regs.status = ATA_SR_ERR | ATA_SR_BSY | ATA_SR_DRDY;
FIXME ("Unknown command %x\n", device->regs.command);
/* FIXME */
fprintf (stderr, "Fixme: Unknown command %x\n", device->regs.command);
SCHED_ADD (ata_cmd_complete, device, 40000);
return -1;
}
/trunk/or1ksim/peripheral/channels/xterm.c
207,7 → 207,7
if (xt->fds.fdout < 0)
goto closemastererror;
 
#if HAVE_SYS_STROPTS_H
#if HAVE_DECL_I_PUSH
/* These modules must be pushed onto the stream for some non-Linux and
non-Cygwin operating systems. */
retval = ioctl (xt->fds.fdin, I_PUSH, "ptem");
/trunk/or1ksim/peripheral/channels/fd.c
31,6 → 31,8
 
/* System includes */
#include <stdlib.h>
#include <sys/types.h>
#include <sys/time.h>
#include <unistd.h>
#include <errno.h>
#include <stdio.h>
/trunk/or1ksim/peripheral/generic.c
123,7 → 123,7
unsigned long wordaddr = fulladdr & 0xfffffffc;
unsigned long bitoff = (fulladdr & 0x00000003) << 3;
 
#ifdef WORDS_BIGENDIAN
#ifdef OR32_BIG_ENDIAN
unsigned long mask = 0x000000ff << (24 - bitoff);
unsigned long res = ext_read (wordaddr, mask);
 
158,7 → 158,7
unsigned long wordaddr = fulladdr & 0xfffffffc;
unsigned long bitoff = (fulladdr & 0x00000003) << 3;
 
#ifdef WORDS_BIGENDIAN
#ifdef OR32_BIG_ENDIAN
unsigned long mask = 0x000000ff << (24 - bitoff);
unsigned long wordval = ((unsigned long int) value) << (24 - bitoff);
#else
200,7 → 200,7
unsigned long wordaddr = fulladdr & 0xfffffffc;
unsigned long bitoff = (fulladdr & 0x00000003) << 3;
 
#ifdef WORDS_BIGENDIAN
#ifdef OR32_BIG_ENDIAN
unsigned long mask = 0x0000ffff << (16 - bitoff);
unsigned long res = ext_read (wordaddr, mask);
 
240,7 → 240,7
unsigned long wordaddr = fulladdr & 0xfffffffc;
unsigned long bitoff = (fulladdr & 0x00000003) << 3;
 
#ifdef WORDS_BIGENDIAN
#ifdef OR32_BIG_ENDIAN
unsigned long mask = 0x0000ffff << (16 - bitoff);
unsigned long wordval = ((unsigned long int) value) << (16 - bitoff);
#else
/trunk/or1ksim/peripheral/eth.c
44,11 → 44,11
#include <sys/socket.h>
#include <net/if.h>
 
#ifdef HAVE_ETH_PHY
#if HAVE_ETH_PHY
#include <netpacket/packet.h>
#endif /* HAVE_ETH_PHY */
 
#ifdef HAVE_NET_ETHERNET_H
#if HAVE_NET_ETHERNET_H
# include <net/ethernet.h>
#elif defined(HAVE_SYS_ETHERNET_H)
# include <sys/ethernet.h>
68,7 → 68,6
#include "vapi.h"
#include "pic.h"
#include "sched.h"
#include "debug.h"
#include "toplevel-support.h"
#include "sim-cmd.h"
 
404,8 → 403,6
};
 
 
DEFAULT_DEBUG_CHANNEL (eth);
 
/* simulator interface */
static void eth_vapi_read (unsigned long id, unsigned long data, void *dat);
/* register interface */
441,7 → 438,6
switch (eth->tx.state)
{
case ETH_TXSTATE_IDLE:
TRACE ("TX - entering state WAIT4BD (%ld)\n", eth->tx.bd_index);
eth->tx.state = ETH_TXSTATE_WAIT4BD;
break;
case ETH_TXSTATE_WAIT4BD:
494,10 → 490,6
eth->tx.crc_dly = 0;
/* XXX - For now we skip CRC calculation */
 
TRACE ("Ethernet: Starting TX of %lu bytes (min. %u, max. %u)\n",
eth->tx.packet_length, eth->tx.minimum_length,
eth->tx.maximum_length);
 
if (eth->rtx_type == ETH_RTX_FILE)
{
/* write packet length to file */
508,7 → 500,6
 
/************************************************/
/* start transmit with reading packet into FIFO */
TRACE ("TX - entering state READFIFO\n");
eth->tx.state = ETH_TXSTATE_READFIFO;
}
 
539,7 → 530,6
#endif
else
{
TRACE ("TX - entering state TRANSMIT\n");
eth->tx.state = ETH_TXSTATE_TRANSMIT;
}
break;
565,11 → 555,8
{
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
TRACE ("ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
 
TRACE ("TX - entering state WAIT4BD\n");
eth->tx.state = ETH_TXSTATE_WAIT4BD;
TRACE ("send (%ld)bytes OK\n", nwritten);
}
else
{
577,11 → 564,8
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
TRACE ("ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
 
TRACE ("TX - entering state WAIT4BD\n");
eth->tx.state = ETH_TXSTATE_WAIT4BD;
TRACE ("send FAILED!\n");
}
 
eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
633,7 → 617,6
switch (eth->rx.state)
{
case ETH_RXSTATE_IDLE:
TRACE ("RX - entering state WAIT4BD (%ld)\n", eth->rx.bd_index);
eth->rx.state = ETH_RXSTATE_WAIT4BD;
break;
 
653,8 → 636,6
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, TOOBIG);
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, TOOSHORT);
 
TRACE ("Ethernet: Starting RX\n");
 
/* Setup file to read from */
if (TEST_FLAG (eth->regs.moder, ETH_MODER, LOOPBCK))
{
666,12 → 647,10
eth->rx.fd = eth->rxfd;
eth->rx.offset = 0;
}
TRACE ("RX - entering state RECV\n");
eth->rx.state = ETH_RXSTATE_RECV;
}
else if (!TEST_FLAG (eth->regs.moder, ETH_MODER, RXEN))
{
TRACE ("RX - entering state IDLE\n");
eth->rx.state = ETH_RXSTATE_IDLE;
}
else
699,9 → 678,6
sizeof (eth->rx.packet_length))
{
/* TODO: just do what real ethernet would do (some kind of error state) */
TRACE
("eth_start_rx(): File does not have a packet ready for RX (len = %ld)\n",
eth->rx.packet_length);
sim_done ();
break;
}
709,10 → 685,8
/* Packet must be big enough to hold a header */
if (eth->rx.packet_length < ETHER_HDR_LEN)
{
TRACE ("eth_start_rx(): Packet too small\n");
eth_rx_next_packet (eth);
 
TRACE ("RX - entering state WAIT4BD\n");
eth->rx.state = ETH_RXSTATE_WAIT4BD;
break;
}
724,8 → 698,6
nread = eth_read_rx_file (eth, eth->rx_buff, eth->rx.bytes_left);
if (nread < eth->rx.bytes_left)
{
TRACE ("Read %ld from %ld. Error!\n", nread,
eth->rx.bytes_left);
eth->rx.error = 1;
break;
}
734,7 → 706,6
eth->rx.bytes_left = nread;
eth->rx.bytes_read = 0;
 
TRACE ("RX - entering state WRITEFIFO\n");
eth->rx.state = ETH_RXSTATE_WRITEFIFO;
 
break;
744,7 → 715,6
 
if (nread == 0)
{
TRACE ("No data read\n");
break;
}
else if (nread < 0)
751,7 → 721,6
{
if (errno != EAGAIN)
{
TRACE ("recv() FAILED!\n");
break;
}
else
779,7 → 748,6
eth->rx.bytes_left = nread;
eth->rx.bytes_read = 0;
 
TRACE ("RX - entering state WRITEFIFO\n");
eth->rx.state = ETH_RXSTATE_WRITEFIFO;
 
break;
796,8 → 764,6
((unsigned long) eth->rx_buff[eth->rx.bytes_read + 3]);
set_direct32 (eth->rx.bd_addr + eth->rx.bytes_read, send_word, 0, 0);
/* update counters */
TRACE ("Write %ld, left %ld - %08lXd\n", eth->rx.bytes_read,
eth->rx.bytes_left, send_word);
eth->rx.bytes_left -= 4;
eth->rx.bytes_read += 4;
#else
813,7 → 779,6
SET_FIELD (eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length);
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, READY);
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, RXB);
TRACE ("ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
 
if (eth->rx.packet_length <
(GET_FIELD (eth->regs.packetlen, ETH_PACKETLEN, MINFL) - 4))
838,7 → 803,6
}
 
/* ready to receive next packet */
TRACE ("RX - entering state IDLE\n");
eth->rx.state = ETH_RXSTATE_IDLE;
}
break;
876,7 → 840,6
 
if (eth->rx.fd <= 0)
{
TRACE ("Ethernet: No RX file\n");
return 0;
}
 
883,12 → 846,10
if (eth->rx.offset)
if (lseek (eth->rx.fd, *(eth->rx.offset), SEEK_SET) == (off_t) - 1)
{
TRACE ("Ethernet: Error seeking RX file\n");
return 0;
}
 
result = read (eth->rx.fd, buf, count);
TRACE ("Ethernet: read result = %d \n", result);
if (eth->rx.offset && result >= 0)
*(eth->rx.offset) += result;
 
942,7 → 903,6
if (eth->rtx_sock != 0)
break;
 
TRACE ("RTX opening socket...\n");
eth->rtx_sock = socket (PF_PACKET, SOCK_RAW, htons (ETH_P_ALL));
if (eth->rtx_sock == -1)
{
951,7 → 911,6
}
 
/* get interface index number */
TRACE ("RTX getting interface...\n");
memset (&(eth->ifr), 0, sizeof (eth->ifr));
strncpy (eth->ifr.ifr_name, eth->sockif, IFNAMSIZ);
if (ioctl (eth->rtx_sock, SIOCGIFINDEX, &(eth->ifr)) == -1)
959,11 → 918,8
fprintf (stderr, "SIOCGIFINDEX failed!\n");
return;
}
TRACE ("RTX Socket Interface : %d\n", eth->ifr.ifr_ifindex);
 
/* Bind to interface... */
TRACE ("Binding to the interface ifindex=%d\n",
eth->ifr.ifr_ifindex);
memset (&sll, 0xff, sizeof (sll));
sll.sll_family = AF_PACKET; /* allways AF_PACKET */
sll.sll_protocol = htons (ETH_P_ALL);
976,13 → 932,11
}
 
/* first, flush all received packets. */
TRACE ("Flush");
do
{
fd_set fds;
struct timeval t;
 
TRACE (".");
FD_ZERO (&fds);
FD_SET (eth->rtx_sock, &fds);
memset (&t, 0, sizeof (t));
991,7 → 945,6
recv (eth->rtx_sock, eth->rx_buff, j, 0);
}
while (j);
TRACE ("\n");
 
break;
#else /* HAVE_ETH_PHY */
1255,11 → 1208,8
 
which = id - eth->base_vapi_id;
 
TRACE ("ETH: id %08lx, data %08lx\n", id, data);
 
if (!eth)
{
TRACE ("ETH: VAPI ID %08lx is not ours!\n", id);
return;
}
 
/trunk/or1ksim/peripheral/ps2kbd.c
459,7 → 459,7
if (kbd->ccmd == KBD_CCMD_EKI)
kbd->ccmdbyte &= ~KBD_CCMDBYTE_EN;
if (config.sim.verbose)
PRINTF ("kbd_write8(%" PRIxADDR ") %" PRIx32 "\n", addr, value);
PRINTF ("kbd_write8(%" PRIxADDR ") %02x\n", addr, value);
break;
case KBD_DATA:
if (kbd->ccmd == KBD_CCMD_WCB)
476,7 → 476,7
kbd->kresp = 0x1;
kbd->ccmd = 0x00;
if (config.sim.verbose)
PRINTF ("kbd_write8(%" PRIxADDR ") %" PRIx32 "\n", addr, value);
PRINTF ("kbd_write8(%" PRIxADDR ") %02x\n", addr, value);
break;
default:
fprintf (stderr, "Write out of keyboard space (0x%" PRIxADDR ")!\n",
/trunk/or1ksim/peripheral/atadevice.c
36,12 → 36,9
#include "atadevice.h"
#include "atadevice-cmdi.h"
#include "atacmd.h"
#include "debug.h"
#include "abstract.h"
 
 
DEFAULT_DEBUG_CHANNEL (ata);
 
/*
mandatory commands:
- execute device diagnostics (done)
85,7 → 82,8
if (!(fp = fopen (filename, "rb+")))
if (!(fp = fopen (filename, "wb+")))
{
ERR ("ata_open_file, cannot open hd-file %s\n", filename);
fprintf (stderr, "Warning: ata_open_file, cannot open hd-file %s\n",
filename);
return NULL;
}
else
92,8 → 90,6
{
/* TODO create a file 'size' large */
/* create a file 'size' large */
TRACE ("ata_device; generating a new hard disk file.\n");
TRACE ("This may take a while, depending on the requested size.\n");
for (n = 0; n < *size; n++)
fputc (0, fp);
}
101,14 → 97,10
fprintf (stderr, "file %s already exists. Using existing file.\n",
filename);
 
TRACE ("requested filesize was: %d (MBytes).\n", *size);
 
/* get the size of the file. This is also the size of the harddisk */
fseek (fp, 0, SEEK_END);
*size = ftell (fp);
 
TRACE ("actual filesize is: %d (MBytes).\n", *size >> 20);
 
return fp;
}
 
118,8 → 110,8
open_local (void)
{
// TODO:
FIXME
("Device type LOCAL is not yet supported. Defaulting to device type NO_CONNECT.");
fprintf (stderr, "Warning: Device type LOCAL is not yet supported: "
"Defaulting to device type NO_CONNECT.");
return NULL;
}
 
133,22 → 125,20
switch (device->conf.type)
{
case TYPE_NO_CONNECT:
TRACE ("ata_device, using type NO_CONNECT.\n");
device->conf.stream = NULL;
break;
 
case TYPE_FILE:
TRACE ("ata_device, using device type FILE.\n");
device->conf.stream = open_file (&device->conf.size, device->conf.file);
break;
 
case TYPE_LOCAL:
TRACE ("ata_device, using device type LOCAL.\n");
device->conf.stream = open_local ();
break;
 
default:
ERR ("Illegal device-type. Defaulting to type NO_CONNECT.\n");
fprintf (stderr, "Warning: Illegal device-type %d: "
"Defaulting to type NO_CONNECT.\n", device->conf.type);
device->conf.stream = NULL;
break;
}
228,9 → 218,6
void
ata_devices_hw_reset (struct ata_devices * devices, int reset_signal)
{
/* display debug information */
TRACE (reset_signal ? "Starting reset\n" : "Finishing reset\n");
 
/* find device 0 */
if ((devices->device[0].conf.stream) && (devices->device[1].conf.stream))
{
261,11 → 248,6
0, /* negate pdiag input, there's no device1 */
0); /* negate dasp input, there's no device1 */
}
else
{
/* no devices connected */
TRACE ("ata_device_hw_reset, no devices connected.\n");
}
}
 
 
297,9 → 279,6
 
/* set new state */
device->internals.state = ATA_STATE_SW_RST;
 
/* display debug information */
TRACE ("ata_device_sw_reset initiated.\n");
}
}
else if (device->internals.state == ATA_STATE_SW_RST)
318,9 → 297,6
 
/* set new state */
device->internals.state = ATA_STATE_IDLE;
 
/* display debug information */
TRACE ("ata_device_sw_reset done.\n");
}
/*
<else> We are doing a hardware reset (or similar)
338,9 → 314,13
/* check BSY & DRQ */
if ((device->regs.status & ATA_SR_BSY)
|| (device->regs.status & ATA_SR_DRQ))
if (device->regs.command != DEVICE_RESET)
WARN
("ata_device_write, writing a command while BSY or DRQ asserted.\n");
{
if (device->regs.command != DEVICE_RESET)
{
fprintf (stderr, "Warning: ata_device_write, writing a command "
"while BSY or DRQ asserted.\n");
}
}
 
/* check if device selected */
if ((device->regs.device_head & ATA_DHR_DEV) == device->internals.dev)
354,32 → 334,6
}
 
 
/* Return contents of status register in pretty for */
static const char *
ata_pretty_status (uint8_t status)
{
static char str[50];
 
str[0] = '\0';
if (status & ATA_SR_BSY)
strcat (str, "BUSY");
if (status & ATA_SR_DRDY)
strcat (str, "| READY");
if (status & ATA_SR_DF)
strcat (str, "| FAULT");
if (status & ATA_SR_DSC)
strcat (str, "| SEEKC");
if (status & ATA_SR_DRQ)
strcat (str, "| DRQ");
if (status & ATA_SR_COR)
strcat (str, "| COR");
if (status & ATA_SR_IDX)
strcat (str, "| IDX");
if (status & ATA_SR_ERR)
strcat (str, "| ERROR");
return str;
}
 
/*
D E V I C E S _ R E A D
*/
391,7 → 345,10
 
/* check for no connected devices */
if ((!devices->device[0].conf.stream) && (!devices->device[1].conf.stream))
ERR ("ata_devices_read, no ata devices connected.\n");
{
fprintf (stderr, "Warning: ata_devices_read, no ata devices "
"connected.\n");
}
else
{
/* check if both device0 and device1 are connected */
417,38 → 374,28
switch (adr)
{
case ATA_ASR:
TRACE ("read alternate status register: %s\n",
ata_pretty_status (device->regs.status));
if ((device->regs.device_head & ATA_DHR_DEV) ==
device->internals.dev)
return device->regs.status;
else
{
TRACE ("device0 responds for device1, asr = 0x00\n");
return 0; // return 0 when device0 responds for device1
}
 
case ATA_CHR:
TRACE ("cylinder_high register read, value = 0x%02X\n",
device->regs.cylinder_high);
return device->regs.cylinder_high;
 
case ATA_CLR:
TRACE ("cylinder_low register read, value = 0x%02X\n",
device->regs.cylinder_low);
return device->regs.cylinder_low;
 
case ATA_DR:
if (!device->regs.status & ATA_SR_DRQ)
{
TRACE ("data register read, while DRQ bit negated\n");
return 0;
}
else
{
uint16_t val = LE16 (*device->internals.dbuf_ptr++);
TRACE ("data register read, value = 0x%04X, cnt = %3d\n", val,
device->internals.dbuf_cnt);
if (!--device->internals.dbuf_cnt)
{
device->regs.status &= ~ATA_SR_DRQ;
459,27 → 406,18
}
 
case ATA_DHR:
TRACE ("device_head register read, value = 0x%02X\n",
device->regs.device_head);
return device->regs.device_head;
 
case ATA_ERR:
TRACE ("error register read, value = 0x%02X\n", device->regs.error);
return device->regs.error;
 
case ATA_SCR:
TRACE ("sectorcount register read, value = 0x%02X\n",
device->regs.sector_count);
return device->regs.sector_count;
 
case ATA_SNR:
TRACE ("sectornumber register read, value = 0x%02X\n",
device->regs.sector_number);
return device->regs.sector_number;
 
case ATA_SR:
TRACE ("read status register: %s\n",
ata_pretty_status (device->regs.status));
if ((device->regs.device_head & ATA_DHR_DEV) ==
device->internals.dev)
{
487,7 → 425,6
return device->regs.status;
}
 
TRACE ("device0 responds for device1, sr = 0x00\n");
return 0; // return 0 when device0 responds for device1
 
// case ATA_DA :
508,9 → 445,6
switch (adr)
{
case ATA_CR:
/*display debug information */
TRACE ("command register written, value = 0x%02X\n", value);
 
device->regs.command = value;
 
/* check command register settings and execute command */
519,30 → 453,20
 
 
case ATA_CHR:
/*display debug information */
TRACE ("cylinder high register written, value = 0x%02X\n", value);
 
device->regs.cylinder_high = value;
break;
 
case ATA_CLR:
/*display debug information */
TRACE ("cylinder low register written, value = 0x%02X\n", value);
 
device->regs.cylinder_low = value;
break;
 
case ATA_DR:
/*display debug information */
if (!device->regs.status & ATA_SR_DRQ)
{
TRACE ("data register write, while DRQ bit negated\n");
break;
}
else
{
TRACE ("data register write, value = 0x%04X, cnt = %3d\n",
value, device->internals.dbuf_cnt);
*device->internals.dbuf_ptr++ = LE16 (value);
if (!--device->internals.dbuf_cnt)
{
555,38 → 479,23
break;
 
case ATA_DCR:
/*display debug information */
TRACE ("device control register written, value = 0x%02X\n", value);
 
device->regs.device_control = value;
ata_device_do_control_register (device);
break;
 
case ATA_DHR:
/*display debug information */
TRACE ("device head register written, value = 0x%02X\n", value);
 
device->regs.device_head = value;
break;
 
case ATA_FR:
/*display debug information */
TRACE ("features register written, value = 0x%02X\n", value);
 
device->regs.features = value;
break;
 
case ATA_SCR:
/*display debug information */
TRACE ("sectorcount register written, value = 0x%02X\n", value);
 
device->regs.sector_count = value;
break;
 
case ATA_SNR:
/*display debug information */
TRACE ("sectornumber register written, value = 0x%02X\n", value);
 
device->regs.sector_number = value;
break;
 
599,7 → 508,10
{
/* check for no connected devices */
if (!devices->device[0].conf.stream && !devices->device[1].conf.stream)
ERR ("ata_devices_write, no ata devices connected.\n");
{
fprintf (stderr, "Warning: ata_devices_write, no ata devices "
"connected.\n");
}
else
{
/* first device */
/trunk/or1ksim/peripheral/dma.c
37,7 → 37,6
 
/* Package includes */
#include "dma.h"
#include "debug.h"
#include "fields.h"
#include "abstract.h"
#include "sched.h"
45,7 → 44,6
#include "toplevel-support.h"
#include "sim-cmd.h"
 
DEFAULT_DEBUG_CHANNEL (dma);
 
/* We keep a copy of all our controllers because we have to export an interface
* to other peripherals eg. ethernet */
312,7 → 310,6
/* Do we need to abort? */
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, STOP))
{
TRACE ("DMA: STOP requested\n");
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, CH_EN);
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, BUSY);
SET_FLAG (channel->regs.csr, DMA_CH_CSR, ERR);
339,8 → 336,6
/* If this is the first cycle of the transfer, initialize our state */
if (!TEST_FLAG (channel->regs.csr, DMA_CH_CSR, BUSY))
{
TRACE ("DMA: Starting new transfer\n");
 
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, DONE);
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, ERR);
SET_FLAG (channel->regs.csr, DMA_CH_CSR, BUSY);
357,8 → 352,6
/* Might need to skip descriptor */
if (CHANNEL_ND_I (channel))
{
TRACE
("DMA: dma_nd_i asserted before dma_req_i, skipping descriptor\n");
dma_channel_terminate_transfer (channel, 0);
return;
}
380,7 → 373,6
/* When done with a chunk, check for dma_nd_i */
if (CHANNEL_ND_I (channel))
{
TRACE ("DMA: dma_nd_i asserted\n");
dma_channel_terminate_transfer (channel, 0);
return;
}
453,8 → 445,6
dma_channel_terminate_transfer (struct dma_channel *channel,
int generate_interrupt)
{
TRACE ("DMA: Terminating transfer\n");
 
/* Might be working in a linked list */
if (channel->load_next_descriptor_when_done)
{
/trunk/or1ksim/peripheral/atahost.c
34,7 → 34,6
/* Package includes */
#include "atahost.h"
#include "sim-config.h"
#include "debug.h"
#include "abstract.h"
#include "pic.h"
#include "toplevel-support.h"
51,7 → 50,6
#define DMA_MODE0_TD 21
#define DMA_MODE0_TEOC 21
 
DEFAULT_DEBUG_CHANNEL (ata);
 
/* reset and initialize ATA host core(s) */
static void
115,7 → 113,6
switch (addr)
{
case ATA_CTRL:
TRACE ("Read control register: %" PRIx32 "\n", ata->regs.ctrl);
return ata->regs.ctrl;
 
case ATA_STAT:
186,7 → 183,6
switch (addr)
{
case ATA_CTRL:
TRACE ("Writting control register: %" PRIx32 "\n", value);
ata->regs.ctrl = value;
 
/* check if reset bit set, if so reset ata-devices */
205,23 → 201,14
break;
 
case ATA_PCTR:
TRACE ("PCTR: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
value & 0xff);
ata->regs.pctr = value;
break;
 
case ATA_PFTR0:
TRACE ("PFTR0: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
value & 0xff);
ata->regs.pftr0 = value;
break;
 
case ATA_PFTR1:
TRACE ("PFTR1: Toec = %d, t4 = %d, t2 = %d, t1 = %d\n",
value >> 24, (value >> 16) & 0xff, (value >> 8) & 0xff,
value & 0xff);
ata->regs.pftr1 = value;
break;
 
288,22 → 275,22
return;
 
PRINTF ("\nOCIDEC-%1d at: 0x%" PRIxADDR "\n", ata->dev_id, ata->baseaddr);
PRINTF ("ATA CTRL : 0x%08X\n", ata->regs.ctrl);
PRINTF ("ATA STAT : 0x%08x\n", ata->regs.stat);
PRINTF ("ATA PCTR : 0x%08x\n", ata->regs.pctr);
PRINTF ("ATA CTRL : 0x%08" PRIx32 "\n", ata->regs.ctrl);
PRINTF ("ATA STAT : 0x%08" PRIx32 "\n", ata->regs.stat);
PRINTF ("ATA PCTR : 0x%08" PRIx32 "n", ata->regs.pctr);
 
if (ata->dev_id > 1)
{
PRINTF ("ATA FCTR0 : 0x%08x\n", ata->regs.pftr0);
PRINTF ("ATA FCTR1 : 0x%08x\n", ata->regs.pftr1);
PRINTF ("ATA FCTR0 : 0x%08" PRIx32 "\n", ata->regs.pftr0);
PRINTF ("ATA FCTR1 : 0x%08" PRIx32 "\n", ata->regs.pftr1);
}
 
if (ata->dev_id > 2)
{
PRINTF ("ATA DTR0 : 0x%08x\n", ata->regs.dtr0);
PRINTF ("ATA DTR1 : 0x%08x\n", ata->regs.dtr1);
PRINTF ("ATA TXD : 0x%08x\n", ata->regs.txb);
PRINTF ("ATA RXD : 0x%08x\n", ata->regs.rxb);
PRINTF ("ATA DTR0 : 0x%08" PRIx32 "\n", ata->regs.dtr0);
PRINTF ("ATA DTR1 : 0x%08" PRIx32 "\n", ata->regs.dtr1);
PRINTF ("ATA TXD : 0x%08" PRIx32 "\n", ata->regs.txb);
PRINTF ("ATA RXD : 0x%08" PRIx32 "\n", ata->regs.rxb);
}
}
 
/trunk/or1ksim/peripheral/memory.c
164,7 → 164,7
if (config.sim.verbose)
fprintf (stderr,
"WARNING: 16-bit memory write to 0x%" PRIxADDR ", non-write "
"memory area (value 0x%08" PRIx32 ").\n", addr, value);
"memory area (value 0x%08" PRIx16 ").\n", addr, value);
}
 
static void
173,7 → 173,7
if (config.sim.verbose)
fprintf (stderr,
"WARNING: 8-bit memory write to 0x%" PRIxADDR ", non-write "
"memory area (value 0x%08" PRIx32 ").\n", addr, value);
"memory area (value 0x%08" PRIx8 ").\n", addr, value);
}
 
static void
/trunk/or1ksim/peripheral/16450.c
42,7 → 42,6
 
/* Package includes */
#include "sim-config.h"
#include "debug.h"
#include "arch.h"
#include "pic.h"
#include "sched.h"
53,8 → 52,6
#include "sim-cmd.h"
 
 
DEFAULT_DEBUG_CHANNEL (uart);
 
#define MIN(a,b) ((a) < (b) ? (a) : (b))
/* Definitions */
#define UART_ADDR_SPACE 8 /*!< UART addr space size in bytes */
301,8 → 298,6
 
if ((uart->regs.iir & UART_IIR_NO_INT) || (uart->regs.iir == UART_IIR_MSI))
{
TRACE ("Raiseing modem status interrupt\n");
 
uart->regs.iir = UART_IIR_MSI;
report_interrupt (uart->irq);
}
321,8 → 316,6
if ((uart->regs.iir & UART_IIR_NO_INT) || (uart->regs.iir == UART_IIR_MSI)
|| (uart->regs.iir == UART_IIR_THRI))
{
TRACE ("Raiseing transmitter holding register interrupt\n");
 
uart->regs.iir = UART_IIR_THRI;
report_interrupt (uart->irq);
}
340,8 → 333,6
 
if ((uart->regs.iir != UART_IIR_RLSI) && (uart->regs.iir != UART_IIR_RDI))
{
TRACE ("Raiseing character timeout interrupt\n");
 
uart->regs.iir = UART_IIR_CTI;
report_interrupt (uart->irq);
}
359,8 → 350,6
 
if (uart->regs.iir != UART_IIR_RLSI)
{
TRACE ("Raiseing receiver data interrupt\n");
 
uart->regs.iir = UART_IIR_RDI;
report_interrupt (uart->irq);
}
376,8 → 365,6
if (!(uart->regs.ier & UART_IER_RLSI))
return;
 
TRACE ("Raiseing receiver line status interrupt\n");
 
/* Highest priority interrupt */
uart->regs.iir = UART_IIR_RLSI;
report_interrupt (uart->irq);
402,8 → 389,6
 
if (uart->istat.rxbuf_full >= UART_FIFO_TRIGGER (uart->regs.fcr >> 6))
{
TRACE ("FIFO trigger level reached %i\n",
UART_FIFO_TRIGGER (uart->regs.fcr >> 6));
uart_int_rdi (uart);
}
}
441,8 → 426,6
{
uart->istat.ints &= ~(1 << intr);
 
TRACE ("Interrupt pending was %x\n", uart->regs.iir);
 
/* Some stuff schedule uart_int_cti, therefore remove it here */
if (intr == UART_IIR_CTI)
SCHED_FIND_REMOVE (uart_int_cti, uart);
450,8 → 433,6
if (intr != uart->regs.iir)
return;
 
TRACE ("Clearing interrupt 0x%x\n", intr);
 
uart_next_int (uart);
}
 
496,8 → 477,6
send_char (struct dev_16450 *uart, int bits_send)
{
PRINTF ("%c", (char) uart->iregs.txser);
TRACE ("TX \'%c\' via UART at %" PRIxADDR "\n", (char) uart->iregs.txser,
uart->baseaddr);
if (uart->regs.mcr & UART_MCR_LOOP)
uart->iregs.loopback = uart->iregs.txser;
else
566,12 → 545,9
if (uart->vapi.lcr & UART_LCR_STOP)
fe |= ((packet >> (nbits++)) & 1) ^ 1;
 
TRACE ("lcr vapi %02x, uart %02x\n", uart->vapi.lcr,
uart->regs.lcr);
data |=
(uart->vapi.lcr << 8) | (pe << 16) | (fe << 17) | (uart->vapi.
lcr << 8);
TRACE ("vapi_send (%08lx, %08x)\n", uart->vapi_id, data);
vapi_send (uart->vapi_id, data);
}
else
588,7 → 564,6
{
struct dev_16450 *uart = dat;
 
TRACE ("Sending data in shift reg: 0x%02" PRIx8 "\n", uart->iregs.txser);
/* We've sent all bits */
send_char (uart, (uart->regs.lcr & UART_LCR_WLEN8) + 5);
 
604,14 → 579,6
{
struct dev_16450 *uart = dat;
 
TRACE ("Sending break\n");
#if 0
/* Send broken frame */
int nbits_sent =
((uart->regs.lcr & UART_LCR_WLEN8) + 5) * (uart->istat.txser_clks -
1) / uart->char_clks;
send_char (i, nbits_sent);
#endif
/* Send one break signal */
vapi_send (uart->vapi_id, UART_LCR_SBC << 8);
 
634,9 → 601,6
uart->istat.txbuf_full--;
uart->regs.lsr &= ~UART_LSR_TXSERE;
 
TRACE ("Moveing head of TX fifo (fill: %i) to shift reg 0x%02" PRIx8 "\n",
uart->istat.txbuf_full, uart->iregs.txser);
 
/* Schedules a char_clock to run in the correct amount of time */
if (!(uart->regs.lcr & UART_LCR_SBC))
{
644,7 → 608,6
}
else
{
TRACE ("Sending break not char\n");
SCHED_ADD (uart_send_break, uart, 0);
}
 
675,7 → 638,6
}
else
{
TRACE ("add %02x\n", ch);
uart->regs.rxbuf[uart->istat.rxbuf_head] = ch;
uart->istat.rxbuf_head = (uart->istat.rxbuf_head + 1) % uart->fifo_len;
if (!uart->istat.rxbuf_full++)
737,8 → 699,6
char_to_add =
uart->iregs.rxser & (((1 << ((uart->regs.lcr & 3) + 5)) - 1) | 0xff00);
 
TRACE ("Receiving 0x%02" PRIx16 "'%c' via UART at %" PRIxADDR "\n",
char_to_add, (char) char_to_add, uart->baseaddr);
PRINTF ("%c", (char) char_to_add);
 
if (uart->regs.mcr & UART_MCR_LOOP)
771,8 → 731,6
retval = channel_read (uart->channel, (char *) &buffer, 1);
if (retval > 0)
{
TRACE ("Shifting 0x%02" PRIx8 " (`%c') into shift reg\n", buffer,
buffer);
uart->iregs.rxser = buffer;
uart->istat.receiveing = 1;
SCHED_ADD (uart_recv_char, uart, uart->char_clks * UART_CLOCK_DIVIDER);
813,12 → 771,8
uart->regs.dll = value;
uart->char_clks =
char_clks (uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
TRACE ("\tSetting char_clks to %li (%02x, %02x, %02x)\n",
uart->char_clks, uart->regs.dll, uart->regs.dlh,
uart->regs.lcr);
return;
case UART_DLH:
TRACE ("Setting dlh with %" PRIx8 "\n", value);
uart->regs.dlh = value;
return;
}
827,8 → 781,6
switch (addr)
{
case UART_TXBUF:
TRACE ("Adding %" PRIx8 " to TX FIFO (fill %i)\n", value,
uart->istat.txbuf_full);
uart->regs.lsr &= ~UART_LSR_TXBUFE;
if (uart->istat.txbuf_full < uart->fifo_len)
{
844,7 → 796,6
uart_clear_int (uart, UART_IIR_THRI);
break;
case UART_FCR:
TRACE ("Setting FCR reg with %" PRIx8 "\n", value);
uart->regs.fcr = value & UART_VALID_FCR;
if ((uart->fifo_len == 1 && (value & UART_FCR_FIE))
|| (uart->fifo_len != 1 && !(value & UART_FCR_FIE)))
874,12 → 825,9
break;
case UART_IER:
uart->regs.ier = value & UART_VALID_IER;
TRACE ("Enabling 0x%02x interrupts with 0x%x interrupts pending\n",
value, uart->istat.ints);
uart_next_int (uart);
break;
case UART_LCR:
TRACE ("Setting LCR reg with %" PRIx8 "\n", value);
if ((uart->regs.lcr & UART_LCR_SBC) != (value & UART_LCR_SBC))
{
if ((value & UART_LCR_SBC) && !(uart->regs.lsr & UART_LSR_TXSERE))
901,16 → 849,12
char_clks (uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
break;
case UART_MCR:
TRACE ("Setting MCR reg with %" PRIx8 "\n", value);
uart->regs.mcr = value & UART_VALID_MCR;
uart_loopback (uart);
break;
case UART_SCR:
TRACE ("Setting SCR reg with %" PRIx8 "\n", value);
uart->regs.scr = value;
break;
default:
TRACE ("write out of range (addr %" PRIxADDR ")\n", addr);
}
}
 
927,11 → 871,9
{
case UART_DLL:
value = uart->regs.dll;
TRACE ("reading DLL = %" PRIx8 "\n", value);
return value;
case UART_DLH:
value = uart->regs.dlh;
TRACE ("reading DLH = %" PRIx8 "\n", value);
return value;
}
}
939,16 → 881,6
switch (addr)
{
case UART_RXBUF:
{ /* Print out FIFO for debugging */
int i;
TRACE ("(%i/%i, %i, %i:", uart->istat.rxbuf_full, uart->fifo_len,
uart->istat.rxbuf_head, uart->istat.rxbuf_tail);
for (i = 0; i < uart->istat.rxbuf_full; i++)
TRACE ("%02x ",
uart->regs.rxbuf[(uart->istat.rxbuf_tail + i) %
uart->fifo_len]);
TRACE (")\n");
}
if (uart->istat.rxbuf_full)
{
value = uart->regs.rxbuf[uart->istat.rxbuf_tail];
955,10 → 887,7
uart->istat.rxbuf_tail =
(uart->istat.rxbuf_tail + 1) % uart->fifo_len;
uart->istat.rxbuf_full--;
TRACE ("Reading %" PRIx8 " out of RX FIFO\n", value);
}
else
TRACE ("Trying to read out of RX FIFO but it's empty!\n");
 
uart_clear_int (uart, UART_IIR_RDI);
uart_clear_int (uart, UART_IIR_CTI);
980,7 → 909,6
break;
case UART_IER:
value = uart->regs.ier & UART_VALID_IER;
TRACE ("reading IER = %" PRIx8 "\n", value);
break;
case UART_IIR:
value = (uart->regs.iir & UART_VALID_IIR) | 0xc0;
987,15 → 915,12
/* Only clear the thri interrupt if it is the one we are repporting */
if (uart->regs.iir == UART_IIR_THRI)
uart_clear_int (uart, UART_IIR_THRI);
TRACE ("reading IIR = %" PRIx8 "\n", value);
break;
case UART_LCR:
value = uart->regs.lcr & UART_VALID_LCR;
TRACE ("reading LCR = %" PRIx8 "\n", value);
break;
case UART_MCR:
value = 0;
TRACE ("reading MCR = %" PRIx8 "\n", value);
break;
case UART_LSR:
value = uart->regs.lsr & UART_VALID_LSR;
1004,7 → 929,6
| UART_LSR_FRAME | UART_LSR_RXERR);
/* Clear potentially pending RLSI interrupt */
uart_clear_int (uart, UART_IIR_RLSI);
TRACE ("reading LSR = %" PRIx8 "\n", value);
break;
case UART_MSR:
value = uart->regs.msr & UART_VALID_MSR;
1011,14 → 935,10
uart->regs.msr = 0;
uart_clear_int (uart, UART_IIR_MSI);
uart_loopback (uart);
TRACE ("reading MSR = %" PRIx8 "\n", value);
break;
case UART_SCR:
value = uart->regs.scr;
TRACE ("reading SCR = %" PRIx8 "\n", value);
break;
default:
TRACE ("read out of range (addr %" PRIxADDR ")\n", addr);
}
return value;
}
1036,8 → 956,6
if (uart->vapi_buf_head_ptr != uart->vapi_buf_tail_ptr)
{
unsigned long data = uart->vapi_buf[uart->vapi_buf_tail_ptr];
TRACE ("\tHandling: %08lx (%i,%i)\n", data, uart->vapi_buf_head_ptr,
uart->vapi_buf_tail_ptr);
uart->vapi_buf_tail_ptr =
(uart->vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
switch (data >> 24)
1056,24 → 974,28
{
if ((uart->vapi.lcr & ~UART_LCR_SBC) !=
(uart->regs.lcr & ~UART_LCR_SBC))
WARN ("unmatched VAPI (%02" PRIx8 ") and uart (%02" PRIx8
") modes.\n", uart->vapi.lcr & ~UART_LCR_SBC,
uart->regs.lcr & ~UART_LCR_SBC);
fprintf (stderr, "Warning: Unmatched VAPI (%02" PRIx8
") and uart (%02" PRIx8
") modes.\n", uart->vapi.lcr & ~UART_LCR_SBC,
uart->regs.lcr & ~UART_LCR_SBC);
if (uart->vapi.char_clks != uart->char_clks)
{
WARN
("unmatched VAPI (%li) and uart (%li) char clocks.\n",
uart->vapi.char_clks, uart->char_clks);
WARN ("VAPI: lcr: %02" PRIx8 ", dll: %02" PRIx8
", dlh: %02" PRIx8 "\n", uart->vapi.lcr,
uart->vapi.dll, uart->vapi.dlh);
WARN ("UART: lcr: %02" PRIx8 ", dll: %02" PRIx8
", dlh: %02" PRIx8 "\n", uart->regs.lcr,
uart->regs.dll, uart->vapi.dlh);
fprintf (stderr, "Warning: Unmatched VAPI (%li) and "
"UART (%li) char clocks.\n",
uart->vapi.char_clks, uart->char_clks);
fprintf (stderr, "VAPI: lcr: %02" PRIx8 ", dll: %02"
PRIx8 ", dlh: %02" PRIx8 "\n", uart->vapi.lcr,
uart->vapi.dll, uart->vapi.dlh);
fprintf (stderr, "UART: lcr: %02" PRIx8 ", dll: %02"
PRIx8 ", dlh: %02" PRIx8 "\n", uart->regs.lcr,
uart->regs.dll, uart->vapi.dlh);
}
if (uart->vapi.skew < -MAX_SKEW
|| uart->vapi.skew > MAX_SKEW)
WARN ("VAPI skew is beyond max: %i\n", uart->vapi.skew);
{
fprintf(stderr, "VAPI skew is beyond max: %i\n",
uart->vapi.skew);
}
/* Set error bits */
uart->iregs.rxser |= (UART_LSR_FRAME | UART_LSR_RXERR) << 8;
if (uart->regs.lcr & UART_LCR_PARITY)
1122,7 → 1044,8
}
break;
default:
WARN ("WARNING: Invalid vapi command %02lx\n", data >> 24);
fprintf (stderr, "WARNING: Invalid vapi command %02lx\n",
data >> 24);
break;
}
}
1136,7 → 1059,6
uart_vapi_read (unsigned long id, unsigned long data, void *dat)
{
struct dev_16450 *uart = dat;
TRACE ("UART: id %08lx, data %08lx\n", id, data);
uart->vapi_buf[uart->vapi_buf_head_ptr] = data;
uart->vapi_buf_head_ptr = (uart->vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;
if (uart->vapi_buf_tail_ptr == uart->vapi_buf_head_ptr)
1169,8 → 1091,8
uart->channel = channel_init (uart->channel_str);
if (channel_open (uart->channel) < 0)
{
WARN ("WARNING: problem with channel \"%s\" detected.\n",
uart->channel_str);
fprintf (stderr, "Warning: problem with channel \"%s\" detected.\n",
uart->channel_str);
}
else if (config.sim.verbose)
PRINTF ("UART at 0x%" PRIxADDR "\n", uart->baseaddr);
1177,8 → 1099,8
}
else
{
WARN ("WARNING: UART at %" PRIxADDR
" has no vapi nor channel specified\n", uart->baseaddr);
fprintf (stderr, "Warning: UART at %" PRIxADDR
" has no vapi nor channel specified\n", uart->baseaddr);
}
 
if (uart->uart16550)
1327,9 → 1249,8
static void
uart_newway (union param_val val, void *dat)
{
CONFIG_ERROR
(" txfile and rxfile and now obsolete.\n\tUse 'channel = \"file:rxfile,txfile\"' instead.");
exit (1);
fprintf (stderr, "Warning: txfile and rxfile now obsolete and ignored. "
"Use 'channel = \"file:rxfile,txfile\"'.");
}
 
static void
/trunk/or1ksim/mmu/dmmu.c
37,7 → 37,6
#include "dmmu.h"
#include "sim-config.h"
#include "arch.h"
#include "debug.h"
#include "execute.h"
#include "spr-defs.h"
#include "stats.h"
47,8 → 46,6
#include "sim-cmd.h"
 
 
DEFAULT_DEBUG_CHANNEL (dmmu);
 
struct dmmu *dmmu_state;
 
/* Data MMU */
104,9 → 101,6
 
dtlbtr = dtlbmr + 128;
 
TRACE ("DTLB hit (virtaddr=%" PRIxADDR ") at %lli.\n", virtaddr,
runtime.sim.cycles);
 
/* Set LRUs */
for (i = 0; i < dmmu->nways; i++, dtlbmr_lru += (128 * 2))
{
140,9 → 134,6
except_handle (EXCEPT_DPF, virtaddr);
}
 
TRACE ("Returning physical address %" PRIxADDR "\n",
(*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
(dmmu->page_offset_mask)));
return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
(dmmu->page_offset_mask));
}
175,8 → 166,6
 
cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] |= SPR_DTLBMR_V;
#endif
TRACE ("DTLB miss (virtaddr=%" PRIxADDR ") at %lli.\n", virtaddr,
runtime.sim.cycles);
runtime.sim.mem_cycles += dmmu->missdelay;
/* if tlb refill implemented in HW */
/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * dmmu->pagesize + (virtaddr % dmmu->pagesize); */
227,9 → 216,6
 
dtlbtr = dtlbmr + 128;
 
TRACE ("DTLB hit (virtaddr=%" PRIxADDR ") at %lli.\n", virtaddr,
runtime.sim.cycles);
 
/* Test for page fault */
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
{
/trunk/or1ksim/mmu/immu.c
34,7 → 34,6
#include "immu.h"
#include "sim-config.h"
#include "execute.h"
#include "debug.h"
#include "stats.h"
#include "except.h"
#include "spr-dump.h"
42,8 → 41,6
#include "sim-cmd.h"
 
 
DEFAULT_DEBUG_CHANNEL (immu);
 
struct immu *immu_state;
 
/* Insn MMU */
97,8 → 94,6
if (itlbmr)
{ /* Yes, we did. */
immu_stats.fetch_tlbhit++;
TRACE ("ITLB hit (virtaddr=%" PRIxADDR ").\n", virtaddr);
 
itlbtr = itlbmr + 128;
 
/* Set LRUs */
132,9 → 127,6
except_handle (EXCEPT_IPF, virtaddr);
}
 
TRACE ("Returning physical address %" PRIxADDR "\n",
(*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->
page_offset_mask));
return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->page_offset_mask);
}
 
/trunk/or1ksim/vapi/vapi.c
34,6 → 34,8
#include <stdio.h>
#include <errno.h>
#include <sys/poll.h>
#include <sys/socket.h>
#include <netinet/in.h>
#include <fcntl.h>
#include <netdb.h>
#include <netinet/tcp.h>
41,9 → 43,7
/* Package includes */
#include "sim-config.h"
#include "vapi.h"
#include "debug.h"
 
DEFAULT_DEBUG_CHANNEL (vapi);
 
static unsigned int serverIP = 0;
 
487,7 → 487,6
}
 
vapi_write_log_file (VAPI_COMMAND_REQUEST, id, data);
TRACE ("[%08lx, %08lx]\n", id, data);
 
/* This packet may be for another handler */
if (!handler_fits_id (t, id))
511,8 → 510,6
exit (1);
}
 
TRACE (".");
 
/* Handle everything in queue. */
while (1)
{
636,8 → 633,6
{
struct vapi_handler *tt;
 
TRACE ("vapi_install_handler %08lx, %lu, %p\n", base_id, num_ids,
read_func);
if (read_func == NULL)
{
struct vapi_handler **t = &vapi_handler;
700,7 → 695,6
void
vapi_send (unsigned long id, unsigned long data)
{
TRACE ("vapi_send [%08lx %08lx]\n", id, data);
vapi_write_log_file (VAPI_COMMAND_SEND, id, data);
write_packet (id, data);
}
/trunk/or1ksim/config.h.in
18,6 → 18,10
/* Define to 1 if you have the `bzero' function. */
#undef HAVE_BZERO
 
/* Define to 1 if you have the declaration of `I_PUSH', and to 0 if you don't.
*/
#undef HAVE_DECL_I_PUSH
 
/* Define to 1 if you have the <dirent.h> header file, and it defines `DIR'.
*/
#undef HAVE_DIRENT_H
204,9 → 208,18
/* Define to 1 if you have the <varargs.h> header file. */
#undef HAVE_VARARGS_H
 
/* Define to 1 if the system has the type `__compar_fn_t'. */
#undef HAVE___COMPAR_FN_T
 
/* Define to 1 if your C compiler doesn't accept -c and -o together. */
#undef NO_MINUS_C_MINUS_O
 
/* "The OR32 is big endian" */
#undef OR32_BIG_ENDIAN
 
/* "The OR32 is little endian" */
#undef OR32_LITTLE_ENDIAN
 
/* "The compiler uses the OR32 ELF types" */
#undef OR32_TYPES
 
/trunk/or1ksim/sim-config.c
65,11 → 65,6
#include "argtable2.h"
 
 
DEFAULT_DEBUG_CHANNEL (config);
 
#define WARNING(s) fprintf (stderr, "Warning: config.%s: %s\n", cur_section->name, (s))
#define MERROR(s) {fprintf (stderr, "ERROR: %s\n", s); if (runtime.sim.init) exit (1);}
 
struct config config;
struct runtime runtime;
 
217,7 → 212,9
/* Debug */
config.debug.enabled = 0;
config.debug.gdb_enabled = 0;
config.debug.rsp_enabled = 0;
config.debug.server_port = 51000;
config.debug.rsp_port = 51000;
config.debug.vapi_id = 0;
 
cpu_state.sprs[SPR_DCFGR] = SPR_DCFGR_WPCI |
240,7 → 237,6
runtime.sim.iprompt = 0;
runtime.sim.fprof = NULL;
runtime.sim.fmprof = NULL;
runtime.sim.init = 1;
runtime.sim.fout = stdout;
 
/* VAPI */
346,7 → 342,7
if (0 == cfg_file->count)
{
fprintf (stderr,
"WARNING: No config file given, default configuration used\n");
"Warning: No config file given, default configuration used\n");
}
 
read_script_file (cfg_file->filename[0]);
485,12 → 481,14
{
if (val.int_val < 0)
{
WARNING ("Debug value negative: 0 used instead");
fprintf (stderr,
"Warning: Config debug value negative: 0 substituted\n");
config.sim.debug = 0;
}
else if (val.int_val > 9)
{
WARNING ("Debug value too large: 9 used instead");
fprintf (stderr,
"Warning: Config debug value too large: 9 substituted\n");
config.sim.debug = 9;
}
else
577,7 → 575,8
}
else
{
WARNING ("Execution log type invalid. Ignored");
fprintf (stderr, "Warning: Execution log type %s invalid. Ignored",
val.str_val);
}
} /* sim_exe_log_type() */
 
628,18 → 627,13
int len = strlen (val.str_val);
int pos = len - 1;
long time;
if (len < 2)
if ((len < 2) || (val.str_val[pos--] != 's'))
{
WARNING ("Clock cycle time invalid: unchanged\n");
fprintf (stderr, "Warning: Clock cycle time %s invalid: ignored\n",
val.str_val);
return;
}
 
if (val.str_val[pos--] != 's')
{
WARNING ("Clock cycle time invalid: unchanged\n");
return;
}
 
switch (val.str_val[pos--])
{
case 'p':
655,7 → 649,8
time = 1000000000;
break;
default:
WARNING ("Clock cycle time invalid: unchanged\n");
fprintf (stderr, "Warning: Clock cycle time %s invalid: ignored\n",
val.str_val);
return;
}
 
664,7 → 659,7
 
if (0 == time)
{
WARNING ("Clock cycle time of zero invalid: unchanged\n");
fprintf (stderr, "Warning: Clock cycle time of zero invalid: ignored\n");
return;
}
 
742,28 → 737,6
reg_cuc_sec ();
}
 
/* Returns a user friendly string of type */
static char *
get_paramt_str (enum param_t type)
{
switch (type)
{
case paramt_int:
return "integer";
case paramt_longlong:
return "longlong";
case paramt_addr:
return "address";
case paramt_str:
return "string";
case paramt_word:
return "word";
case paramt_none:
return "none";
}
return "";
}
 
void
reg_config_param (struct config_section *sec, const char *param,
enum param_t type,
771,9 → 744,6
{
struct config_param *new = malloc (sizeof (struct config_param));
 
TRACE ("Registering config param `%s' to section `%s', type %s\n", param,
sec->name, get_paramt_str (type));
 
if (!new)
{
fprintf (stderr, "Out-of-memory\n");
799,8 → 769,6
{
struct config_section *new = malloc (sizeof (struct config_section));
 
TRACE ("Registering config section `%s'\n", section);
 
if (!new)
{
fprintf (stderr, "Out-of-memory\n");
851,7 → 819,8
case paramt_str:
if (*param != '"')
{
CONFIG_ERROR ("String value expected\n");
fprintf (stderr,
"Warning: String value for parameter expected: ignored\n");
return;
}
 
925,7 → 894,6
local ? filename : ctmp);
exit (1);
}
TRACE ("Came across section `%s'\n", param);
for (cur = sections; cur; cur = cur->next)
if (strcmp (cur->name, param) == 0)
{
935,7 → 903,7
if (!cur)
{
fprintf (stderr,
"WARNING: config: Unknown section: %s; ignoring.\n",
"Warning: Unknown config section: %s; ignoring.\n",
param);
/* just skip section */
while (fscanf (f, "%s\n", param) == 1
973,8 → 941,6
{
struct config_param *cur_param;
char *cur_p;
TRACE ("Came across parameter `%s' in section `%s'\n", param,
cur_section->name);
for (cur_param = cur_section->params; cur_param;
cur_param = cur_param->next)
if (strcmp (cur_param->name, param) == 0)
983,9 → 949,8
}
if (!cur_param)
{
char tmp[200];
sprintf (tmp, "Invalid parameter: %s; ignoring.\n", param);
WARNING (tmp);
fprintf (stderr, "Warning: Invalid parameter: %s; ignored\n",
param);
while (fgetc (f) != '\n' || feof (f));
continue;
}
1006,7 → 971,7
}
else if (config.sim.verbose)
fprintf (stderr,
"WARNING: Cannot read script file from '%s',\nneither '%s'.\n",
"Warning: Cannot read script file from '%s' of '%s'.\n",
filename, ctmp);
}
 
/trunk/or1ksim/support/sched.c
39,7 → 39,6
#include "sim-config.h"
 
 
DEFAULT_DEBUG_CHANNEL(sched);
DECLARE_DEBUG_CHANNEL(sched_jobs);
 
#define SCHED_HEAP_SIZE 128
114,15 → 113,6
} while(scheduler.job_queue->time <= 0);
}
 
static void sched_print_jobs(void)
{
struct sched_entry *cur;
int i;
 
for (cur = scheduler.job_queue, i = 0; cur; cur = cur->next, i++)
TRACE("\t%i: %p $%p @ %"PRIi32"\n", i, cur->func, cur->param, cur->time);
}
 
/* Adds new job to the queue */
void sched_add(void (*job_func)(void *), void *job_param, int32_t job_time,
const char *func)
130,13 → 120,6
struct sched_entry *cur, *prev, *new_job;
int32_t alltime;
 
TRACE("%s@%lli:SCHED_ADD(time %"PRIi32")\n", func, runtime.sim.cycles,
job_time);
if(TRACE_ON(sched_jobs)) {
sched_print_jobs();
TRACE("--------\n");
}
 
cur = scheduler.job_queue;
prev = NULL;
alltime = cur->time;
157,30 → 140,22
if(prev) {
new_job->time = job_time - (alltime - (cur ? cur->time : 0));
prev->next = new_job;
TRACE("Scheduled job not going to head of queue, relative time: %"
PRIi32"\n", new_job->time);
} else {
scheduler.job_queue = new_job;
new_job->time = job_time >= 0 ? job_time : cur->time;
TRACE("Setting to-go cycles to %"PRIi32" at %lli\n", job_time,
runtime.sim.cycles);
}
 
if(cur)
cur->time -= new_job->time;
 
if(TRACE_ON(sched_jobs))
sched_print_jobs();
}
 
/* Returns a job with specified function and param, NULL if not found */
void sched_find_remove(void (*job_func)(void *), void *dat, const char *func)
void sched_find_remove(void (*job_func)(void *), void *dat)
{
struct sched_entry *cur;
struct sched_entry *prev = NULL;
 
TRACE("%s@%lli:SCHED_REMOVE()\n", func, runtime.sim.cycles);
 
for (cur = scheduler.job_queue; cur; prev = cur, cur = cur->next) {
if ((cur->func == job_func) && (cur->param == dat)) {
if(cur->next)
/trunk/or1ksim/support/sched.h
32,7 → 32,7
#define SCHED_ADD(job_func, job_param, job_time) sched_add(job_func, job_param, job_time, #job_func)
 
/*! Macro to remove a job from the scheduler */
#define SCHED_FIND_REMOVE(f, p) sched_find_remove(f, p, __FUNCTION__)
#define SCHED_FIND_REMOVE(f, p) sched_find_remove(f, p)
 
/*! Structure for holding one job entry */
struct sched_entry
59,8 → 59,7
extern void sched_next_insn (void (*func) (void *),
void *dat);
extern void sched_find_remove (void (*job_func) (void *),
void *dat,
const char *func);
void *dat);
extern void sched_add (void (*job_func) (void *),
void *job_param,
int32_t job_time,
/trunk/or1ksim/support/simprintf.c
44,8 → 44,6
#include "execute.h"
 
 
DEFAULT_DEBUG_CHANNEL(simprintf);
 
/* Should args be passed on stack for simprintf
*
* FIXME: do not enable this since it causes problems
105,8 → 103,6
 
simgetstr (stackaddr, regparam);
 
TRACE ("simprintf: stackaddr: 0x%" PRIxADDR "\n", stackaddr);
 
#if STACK_ARGS
argaddr = stackaddr;
#else
121,18 → 117,14
 
if (tee_exe_log)
fprintf (runtime.sim.fexe_log, "SIMPRINTF: ");
TRACE ("simprintf: %s\n", fmtstrpart);
while (strlen (fmtstrpart))
{
TRACE ("simprintf(): 1");
if ((fmtstrend = strstr (fmtstrpart + 1, "%")))
*fmtstrend = '\0';
TRACE (" 2");
if (strstr (fmtstrpart, "%"))
{
char *tmp;
int string = 0;
TRACE (" 3");
#if STACK_ARGS
arg = eval_direct32 (argaddr, 1, 0);
argaddr += 4;
150,8 → 142,6
arg = evalsim_reg (++argaddr);
}
#endif
TRACE (" 4: fmtstrpart=%p fmtstrpart=%s arg=0x%08" PRIx32 "\n",
fmtstrpart, fmtstrpart, arg);
tmp = fmtstrpart;
if (*tmp == '%')
{
173,8 → 163,6
for (; eval_direct8 (arg, 1, 0); len++)
*(str + len) = eval_direct8 (arg++, 1, 0);
*(str + len) = eval_direct8 (arg, 1, 0); /* null ch */
TRACE ("4a: len=%d str=%s\n", len, str);
TRACE ("4b:");
printf (fmtstrpart, str);
if (tee_exe_log)
fprintf (runtime.sim.fexe_log, fmtstrpart, str);
189,20 → 177,13
}
else
{
TRACE (" 5");
printf (fmtstrpart);
if (tee_exe_log)
fprintf (runtime.sim.fexe_log, fmtstrpart);
TRACE (fmtstrpart);
}
if (!fmtstrend)
break;
TRACE (" 6");
fmtstrpart = fmtstrend;
*fmtstrpart = '%';
TRACE (" 7");
}
 
TRACE (" 8\n");
 
}
/trunk/or1ksim/support/dumpverilog.c
53,8 → 53,8
"// There are still some bugs in generated output (dump word aligned regions)\n\n"\
"module %s(clk, data, addr, ce, we, disout);\n\n"\
"parameter dw = 32;\n"\
"parameter amin = %d;\n\n"\
"parameter amax = %d;\n\n"\
"parameter amin = %" PRIdREG ";\n\n"\
"parameter amax = %" PRIdREG ";\n\n"\
"input clk;\n"\
"inout [dw-1:0] data;\n"\
"input [31:0] addr;\n"\
/trunk/gdb-5.0/include/opcode/or32.h
54,9 → 54,9
 
#if defined(HAVE_EXECUTION)
# if SIMPLE_EXECUTION
# include "simpl32_defs.h"
# include "simpl32-defs.h"
# elif DYNAMIC_EXECUTION
# include "dyn32_defs.h"
# include "dyn32-defs.h"
# else
extern void l_none PARAMS((void));
# endif
/trunk/gdb-5.0/opcodes/or32.h
54,9 → 54,9
 
#if defined(HAVE_EXECUTION)
# if SIMPLE_EXECUTION
# include "simpl32_defs.h"
# include "simpl32-defs.h"
# elif DYNAMIC_EXECUTION
# include "dyn32_defs.h"
# include "dyn32-defs.h"
# else
extern void l_none PARAMS((void));
# endif
/trunk/insight/include/opcode/or32.h
54,9 → 54,9
 
#if defined(HAVE_EXECUTION)
# if SIMPLE_EXECUTION
# include "simpl32_defs.h"
# include "simpl32-defs.h"
# elif DYNAMIC_EXECUTION
# include "dyn32_defs.h"
# include "dyn32-defs.h"
# else
extern void l_none PARAMS((void));
# endif

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