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/trunk/xess/xsv_cpld/syn/xilinx_pr/xsv_cpld.ucf
1,82 → 1,82
#
# pin assignments for the XC95108 CPLD chip on the XSV Board
#
 
# set all the bits in the initial state of the power-on
# counter so we get the maximum timeout interval
#INST poweron_cnt_reg[*] INIT = S;
 
# Virtex FPGA
NET "V_dout" LOC = "p6";
NET "V_wrb" LOC = "p7";
NET "V_csb" LOC = "p8";
NET "V_initb" LOC = "p9";
NET "V_done" LOC = "p10";
NET "V_progb" LOC = "p11";
NET "V_cclk" LOC = "p12";
NET "V_m[0]" LOC = "p13";
NET "V_m[1]" LOC = "p14";
NET "V_m[2]" LOC = "p15";
 
# Flash RAM
NET "resetb" LOC = "p3";
NET "ceb" LOC = "P46";
NET "oeb" LOC = "p42";
NET "web" LOC = "p43";
NET "a[0]" LOC = "p16";
NET "a[1]" LOC = "p17";
NET "a[2]" LOC = "p18";
NET "a[3]" LOC = "p19";
NET "a[4]" LOC = "p20";
NET "a[5]" LOC = "p23";
NET "a[6]" LOC = "p24";
NET "a[7]" LOC = "p25";
NET "a[8]" LOC = "p27";
NET "a[9]" LOC = "p28";
NET "a[10]" LOC = "p29";
NET "a[11]" LOC = "p30";
NET "a[12]" LOC = "p49";
NET "a[13]" LOC = "p50";
NET "a[14]" LOC = "p52";
NET "a[15]" LOC = "p53";
NET "a[16]" LOC = "p54";
NET "a[17]" LOC = "p55";
NET "a[18]" LOC = "p56";
NET "a[19]" LOC = "p58";
NET "a[20]" LOC = "p59";
 
# programmable oscillator
NET "clk" LOC = "p22";
 
# parallel port
#NET "ppd[0]" LOC = "p77";
#NET "ppd[1]" LOC = "p74";
NET "ppd[2]" LOC = "p72";
NET "ppd[3]" LOC = "p70";
NET "ppd[4]" LOC = "p68";
NET "ppd[5]" LOC = "p67";
#NET "ppd[6]" LOC = "p66";
#NET "ppd[7]" LOC = "p65";
#NET "ppc[0]" LOC = "p79";
#NET "ppc[1]" LOC = "p78";
#NET "ppc[3]" LOC = "p71";
#NET "pps[3]" LOC = "p76";
#NET "pps[4]" LOC = "p60";
NET "pps[5]" LOC = "p61";
#NET "pps[6]" LOC = "p64";
 
# UART
NET "rxd" LOC = "p80"; # Connected to RS232
NET "txd" LOC = "p81"; # Connected to RS232
#NET "TXD1" LOC = "p9"; # INIT on Virtex = I/O after configuration
#NET "RXD1" LOC = "p8"; # CS on Virtex = I/O after configuration unless the SelectMAP port is retained.
#
# pin assignments for the XC95108 CPLD chip on the XSV Board
#
 
# set all the bits in the initial state of the power-on
# counter so we get the maximum timeout interval
#INST poweron_cnt_reg[*] INIT = S;
 
# Virtex FPGA
NET "V_dout" LOC = "p6";
NET "V_wrb" LOC = "p7";
NET "V_csb" LOC = "p8";
NET "V_initb" LOC = "p9";
NET "V_done" LOC = "p10";
NET "V_progb" LOC = "p11";
NET "V_cclk" LOC = "p12";
NET "V_m[0]" LOC = "p13";
NET "V_m[1]" LOC = "p14";
NET "V_m[2]" LOC = "p15";
 
# Flash RAM
NET "resetb" LOC = "p3";
NET "ceb" LOC = "P46";
NET "oeb" LOC = "p42";
NET "web" LOC = "p43";
NET "a[0]" LOC = "p16";
NET "a[1]" LOC = "p17";
NET "a[2]" LOC = "p18";
NET "a[3]" LOC = "p19";
NET "a[4]" LOC = "p20";
NET "a[5]" LOC = "p23";
NET "a[6]" LOC = "p24";
NET "a[7]" LOC = "p25";
NET "a[8]" LOC = "p27";
NET "a[9]" LOC = "p28";
NET "a[10]" LOC = "p29";
NET "a[11]" LOC = "p30";
NET "a[12]" LOC = "p49";
NET "a[13]" LOC = "p50";
NET "a[14]" LOC = "p52";
NET "a[15]" LOC = "p53";
NET "a[16]" LOC = "p54";
NET "a[17]" LOC = "p55";
NET "a[18]" LOC = "p56";
NET "a[19]" LOC = "p58";
NET "a[20]" LOC = "p59";
 
# programmable oscillator
NET "clk" LOC = "p22";
 
# parallel port
#NET "ppd[0]" LOC = "p77";
#NET "ppd[1]" LOC = "p74";
NET "ppd[2]" LOC = "p72";
NET "ppd[3]" LOC = "p70";
NET "ppd[4]" LOC = "p68";
NET "ppd[5]" LOC = "p67";
#NET "ppd[6]" LOC = "p66";
#NET "ppd[7]" LOC = "p65";
#NET "ppc[0]" LOC = "p79";
#NET "ppc[1]" LOC = "p78";
#NET "ppc[3]" LOC = "p71";
#NET "pps[3]" LOC = "p76";
#NET "pps[4]" LOC = "p60";
NET "pps[5]" LOC = "p61";
#NET "pps[6]" LOC = "p64";
 
# UART
NET "rxd" LOC = "p80"; # Connected to RS232
NET "txd" LOC = "p81"; # Connected to RS232
#NET "TXD1" LOC = "p9"; # INIT on Virtex = I/O after configuration
#NET "RXD1" LOC = "p8"; # CS on Virtex = I/O after configuration unless the SelectMAP port is retained.
 
# Ethernet
NET "eth_leds" LOC = "p1";
NET "eth_ledr" LOC = "p95";
NET "eth_ledt" LOC = "p96";
NET "eth_ledl" LOC = "p97";
NET "eth_ledc" LOC = "p98";
NET "eth_ledc" LOC = "p99";
NET "eth_mf[0]" LOC = "p91";
NET "eth_mf[1]" LOC = "p90";
NET "eth_mf[2]" LOC = "p89";

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