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/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18 2002/08/15 06:04:11 lampret
// Fixed Xilinx trace buffer address. REported by Taylor Su.
//
// Revision 1.17 2002/08/12 05:31:44 lampret
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
//
311,6 → 314,28
//`define OR1200_WB_RETRY 7
 
//
// Store buffer
//
// It will improve performance by "caching" CPU stores
// using store buffer. This is most important for function
// prologues because DC can only work in write though mode
// and all stores would have to complete external WB writes
// to memory.
// Store buffer is between DC and data BIU.
// All stores will be stored into store buffer and immediately
// completed by the CPU, even though actual external writes
// will be performed later. As a consequence store buffer masks
// all data bus errors related to stores (data bus errors
// related to loads are delivered normally).
// All pending CPU loads will wait until store buffer is empty to
// ensure strict memory model. Right now this is necessary because
// we don't make destinction between cached and cache inhibited
// address space, so we simply empty store buffer until loads
// can begin.
//
`define OR1200_SB_IMPLEMENTED
 
//
// Enable additional synthesis directives if using
// _Synopsys_ synthesis tool
//
/trunk/or1200/rtl/verilog/or1200_immu_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/08/14 06:23:50 lampret
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
//
// Revision 1.7 2002/08/12 05:31:30 lampret
// Delayed external access at page crossing.
//
260,7 → 263,7
// icpu_rty_o
//
// assign icpu_rty_o = !icpu_err_o & icimmu_rty_i;
assign icpu_rty_o = icimmu_rty_i | itlb_spr_access;
assign icpu_rty_o = icimmu_rty_i | itlb_spr_access & immu_en;
 
//
// icpu_err_o
286,7 → 289,8
// Cut transfer if something goes wrong with translation. If IC is disabled,
// use delayed signals.
//
assign icimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross;
// assign icimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
assign icimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
 
//
// Cache Inhibit
314,7 → 318,7
// Physical address is either translated virtual address or
// simply equal when IMMU is disabled
//
assign icimmu_adr_o = immu_en ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]};
assign icimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
 
//
// Output to SPRS unit
/trunk/or1200/rtl/verilog/or1200_sb.v
0,0 → 1,190
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implements store buffer. ////
//// ////
//// To Do: ////
//// - byte combining ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_sb(
// RISC clock, reset
clk, rst,
 
// Internal RISC bus (DC<->SB)
dcsb_dat_i, dcsb_adr_i, dcsb_cyc_i, dcsb_stb_i, dcsb_we_i, dcsb_sel_i, dcsb_cab_i,
dcsb_dat_o, dcsb_ack_o, dcsb_err_o,
 
// BIU bus
sbbiu_dat_o, sbbiu_adr_o, sbbiu_cyc_o, sbbiu_stb_o, sbbiu_we_o, sbbiu_sel_o, sbbiu_cab_o,
sbbiu_dat_i, sbbiu_ack_i, sbbiu_err_i
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// RISC clock, reset
//
input clk; // RISC clock
input rst; // RISC reset
 
//
// Internal RISC bus (DC<->SB)
//
input [dw-1:0] dcsb_dat_i; // input data bus
input [aw-1:0] dcsb_adr_i; // address bus
input dcsb_cyc_i; // WB cycle
input dcsb_stb_i; // WB strobe
input dcsb_we_i; // WB write enable
input dcsb_cab_i; // CAB input
input [3:0] dcsb_sel_i; // byte selects
output [dw-1:0] dcsb_dat_o; // output data bus
output dcsb_ack_o; // ack output
output dcsb_err_o; // err output
 
//
// BIU bus
//
output [dw-1:0] sbbiu_dat_o; // output data bus
output [aw-1:0] sbbiu_adr_o; // address bus
output sbbiu_cyc_o; // WB cycle
output sbbiu_stb_o; // WB strobe
output sbbiu_we_o; // WB write enable
output sbbiu_cab_o; // CAB input
output [3:0] sbbiu_sel_o; // byte selects
input [dw-1:0] sbbiu_dat_i; // input data bus
input sbbiu_ack_i; // ack output
input sbbiu_err_i; // err output
 
`ifdef OR1200_SB_IMPLEMENTED
 
//
// Internal wires and regs
//
wire [4+dw+aw-1:0] fifo_dat_i; // FIFO data in
wire [4+dw+aw-1:0] fifo_dat_o; // FIFO data out
wire fifo_wr;
wire fifo_rd;
wire fifo_full;
wire fifo_empty;
wire sel_sb;
reg outstanding_store;
reg fifo_wr_ack;
 
//
// FIFO data in/out
//
assign fifo_dat_i = {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
assign {sbbiu_sel_o, sbbiu_dat_o, sbbiu_adr_o} = sel_sb ? fifo_dat_o : {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
 
//
// Control
//
assign fifo_wr = dcsb_cyc_i & dcsb_stb_i & dcsb_we_i & ~fifo_full & ~fifo_wr_ack;
assign fifo_rd = ~outstanding_store;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sel_sb ? fifo_wr_ack : sbbiu_ack_i;
assign dcsb_err_o = sel_sb ? 1'b0 : sbbiu_err_i; // SB never returns error
assign sbbiu_cyc_o = sel_sb ? outstanding_store : dcsb_cyc_i;
assign sbbiu_stb_o = sel_sb ? outstanding_store : dcsb_stb_i;
assign sbbiu_we_o = sel_sb ? 1'b1 : dcsb_we_i;
assign sbbiu_cab_o = sel_sb ? 1'b0 : dcsb_cab_i;
assign sel_sb = ~fifo_empty | (fifo_empty & outstanding_store); // | fifo_wr;
 
//
// Store buffer FIFO instantiation
//
or1200_sb_fifo #(68, 2, 4) or1200_sb_fifo (
.clk_i(clk),
.rst_i(rst),
.dat_i(fifo_dat_i),
.wr_i(fifo_wr),
.rd_i(fifo_rd),
.dat_o(fifo_dat_o),
.full_o(fifo_full),
.empty_o(fifo_empty)
);
 
//
// fifo_rd
//
always @(posedge clk or posedge rst)
if (rst)
outstanding_store <= #1 1'b0;
else if (sbbiu_ack_i)
outstanding_store <= #1 1'b0;
else if (sel_sb | fifo_wr)
outstanding_store <= #1 1'b1;
 
//
// fifo_wr_ack
//
always @(posedge clk or posedge rst)
if (rst)
fifo_wr_ack <= #1 1'b0;
else if (fifo_wr)
fifo_wr_ack <= #1 1'b1;
else
fifo_wr_ack <= #1 1'b0;
 
`else // !OR1200_SB_IMPLEMENTED
 
assign sbbiu_dat_o = dcsb_dat_i;
assign sbbiu_adr_o = dcsb_adr_i;
assign sbbiu_cyc_o = dcsb_cyc_i;
assign sbbiu_stb_o = dcsb_stb_i;
assign sbbiu_we_o = dcsb_we_i;
assign sbbiu_cab_o = dcsb_cab_i;
assign sbbiu_sel_o = dcsb_sel_i;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sbbiu_ack_i;
assign dcsb_err_o = sbbiu_err_i;
 
`endif
 
endmodule
/trunk/or1200/rtl/verilog/or1200_sb_fifo.v
0,0 → 1,137
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer FIFO ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implementation of store buffer FIFO. ////
//// ////
//// To Do: ////
//// - N/A ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_sb_fifo(
clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o
);
 
parameter dw = 32;
parameter fw = 2;
parameter fl = 4;
 
//
// FIFO signals
//
input clk_i; // Clock
input rst_i; // Reset
input [dw-1:0] dat_i; // Input data bus
input wr_i; // Write request
input rd_i; // Read request
output dat_o; // Output data bus
output full_o; // FIFO full
output empty_o;// FIFO empty
 
//
// Internal regs
//
reg [dw:0] mem [fl-1:0];
reg [dw-1:0] dat_o;
reg [fw+1:0] cntr;
reg [fw-1:0] wr_pntr;
reg [fw-1:0] rd_pntr;
reg empty_o;
reg full_o;
 
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
full_o <= #1 1'b0;
empty_o <= #1 1'b1;
wr_pntr <= #1 {fw{1'b0}};
rd_pntr <= #1 {fw{1'b0}};
cntr <= #1 {fw+2{1'b0}};
dat_o <= #1 {dw{1'b0}};
end
// else if ((wr_i && !full_o) && (rd_i && !empty_o)) begin // FIFO Read and Write
else if (wr_i && rd_i) begin // FIFO Read and Write
mem[wr_pntr] <= #1 dat_i;
if (wr_pntr >= fl-1)
wr_pntr <= #1 {fw{1'b0}};
else
wr_pntr <= #1 wr_pntr + 1'b1;
if (empty_o)
dat_o <= #1 dat_i;
else
dat_o <= #1 mem[rd_pntr];
if (rd_pntr >= fl-1)
rd_pntr <= #1 {fw{1'b0}};
else
rd_pntr <= #1 rd_pntr + 1'b1;
end
else if (wr_i && !full_o) begin // FIFO Write
mem[wr_pntr] <= #1 dat_i;
cntr <= #1 cntr + 1'b1;
empty_o <= #1 1'b0;
if (cntr >= fl) begin
full_o <= #1 1'b1;
cntr <= #1 fl;
end
if (wr_pntr >= fl-1)
wr_pntr <= #1 {fw{1'b0}};
else
wr_pntr <= #1 wr_pntr + 1'b1;
end
else if (rd_i && !empty_o) begin // FIFO Read
dat_o <= #1 mem[rd_pntr];
cntr <= #1 cntr - 1'b1;
full_o <= #1 1'b0;
if (cntr <= 0) begin
empty_o <= #1 1'b1;
cntr <= #1 {fw+2{1'b0}};
end
if (rd_pntr >= fl-1)
rd_pntr <= #1 {fw{1'b0}};
else
rd_pntr <= #1 rd_pntr + 1'b1;
end
 
endmodule
/trunk/or1200/rtl/verilog/or1200_dc_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
89,8 → 92,8
clk, rst,
 
// External i/f
dcbiu_dat_o, dcbiu_adr_o, dcbiu_cyc_o, dcbiu_stb_o, dcbiu_we_o, dcbiu_sel_o, dcbiu_cab_o,
dcbiu_dat_i, dcbiu_ack_i, dcbiu_err_i,
dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o, dcsb_cab_o,
dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
 
// Internal i/f
dc_en,
117,16 → 120,16
//
// External I/F
//
output [dw-1:0] dcbiu_dat_o;
output [31:0] dcbiu_adr_o;
output dcbiu_cyc_o;
output dcbiu_stb_o;
output dcbiu_we_o;
output [3:0] dcbiu_sel_o;
output dcbiu_cab_o;
input [dw-1:0] dcbiu_dat_i;
input dcbiu_ack_i;
input dcbiu_err_i;
output [dw-1:0] dcsb_dat_o;
output [31:0] dcsb_adr_o;
output dcsb_cyc_o;
output dcsb_stb_o;
output dcsb_we_o;
output [3:0] dcsb_sel_o;
output dcsb_cab_o;
input [dw-1:0] dcsb_dat_i;
input dcsb_ack_i;
input dcsb_err_i;
 
//
// Internal I/F
179,7 → 182,7
//
// Simple assignments
//
assign dcbiu_adr_o = dc_addr;
assign dcsb_adr_o = dc_addr;
assign dc_inv = spr_cs & spr_write;
assign dctag_we = dcfsm_tag_we | dc_inv;
assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
190,16 → 193,16
// Data to BIU is from DCRAM when DC is enabled or from LSU when
// DC is disabled
//
assign dcbiu_dat_o = dcpu_dat_i;
assign dcsb_dat_o = dcpu_dat_i;
 
//
// Bypases of the DC when DC is disabled
//
assign dcbiu_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
assign dcbiu_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
assign dcbiu_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
assign dcbiu_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcdmmu_ci_i) ? 4'b1111 : dcpu_sel_i;
assign dcbiu_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcdmmu_ci_i) ? 4'b1111 : dcpu_sel_i;
assign dcsb_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
assign dcpu_rty_o = ~dcpu_ack_o;
assign dcdmmu_tag_o = dcdmmu_err_o ? `OR1200_DTAG_BE : dcpu_tag_i;
 
206,8 → 209,8
//
// DC/LSU normal and error termination
//
assign dcpu_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcbiu_ack_i;
assign dcdmmu_err_o = dc_en ? dcfsm_first_miss_err : dcbiu_err_i;
assign dcpu_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
assign dcdmmu_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
 
//
// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
217,12 → 220,12
//
// Select between input data generated by LSU or by BIU
//
assign to_dcram = (dcfsm_biu_read) ? dcbiu_dat_i : dcpu_dat_i;
assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcpu_dat_i;
 
//
// Select between data generated by DCRAM or passed by BIU
//
assign dcpu_dat_o = dcfsm_first_miss_ack | !dc_en ? dcbiu_dat_i : from_dcram;
assign dcpu_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
 
//
// Tag comparison
246,8 → 249,8
.dcpu_we_i(dcpu_we_i),
.dcpu_sel_i(dcpu_sel_i),
.tagcomp_miss(tagcomp_miss),
.biudata_valid(dcbiu_ack_i),
.biudata_error(dcbiu_err_i),
.biudata_valid(dcsb_ack_i),
.biudata_error(dcsb_err_i),
.start_addr(dcdmmu_adr_i),
.saved_addr(saved_addr),
.dcram_we(dcram_we),
/trunk/or1200/rtl/verilog/or1200_except.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.9 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
443,12 → 446,18
end
13'b0_01xx_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
//
// itlb miss exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?)
// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
13'b0_001x_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_IPF;
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
//
// ipf exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?)
// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
13'b0_0001_xxxx_xxxx: begin
/trunk/or1200/rtl/verilog/or1200_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.6 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
206,21 → 209,34
//
 
//
// DC to BIU
// DC to SB
//
wire [dw-1:0] dcbiu_dat_dc;
wire [aw-1:0] dcbiu_adr_dc;
wire dcbiu_cyc_dc;
wire dcbiu_stb_dc;
wire dcbiu_we_dc;
wire [3:0] dcbiu_sel_dc;
wire [3:0] dcbiu_tag_dc;
wire [dw-1:0] dcbiu_dat_biu;
wire dcbiu_ack_biu;
wire dcbiu_err_biu;
wire [3:0] dcbiu_tag_biu;
wire [dw-1:0] dcsb_dat_dc;
wire [aw-1:0] dcsb_adr_dc;
wire dcsb_cyc_dc;
wire dcsb_stb_dc;
wire dcsb_we_dc;
wire [3:0] dcsb_sel_dc;
wire dcsb_cab_dc;
wire [dw-1:0] dcsb_dat_sb;
wire dcsb_ack_sb;
wire dcsb_err_sb;
 
//
// SB to BIU
//
wire [dw-1:0] sbbiu_dat_sb;
wire [aw-1:0] sbbiu_adr_sb;
wire sbbiu_cyc_sb;
wire sbbiu_stb_sb;
wire sbbiu_we_sb;
wire [3:0] sbbiu_sel_sb;
wire sbbiu_cab_sb;
wire [dw-1:0] sbbiu_dat_biu;
wire sbbiu_ack_biu;
wire sbbiu_err_biu;
 
//
// IC to BIU
//
wire [dw-1:0] icbiu_dat_ic;
404,16 → 420,16
.wb_dat_o(dwb_dat_o),
 
// Internal RISC bus
.biu_dat_i(dcbiu_dat_dc),
.biu_adr_i(dcbiu_adr_dc),
.biu_cyc_i(dcbiu_cyc_dc),
.biu_stb_i(dcbiu_stb_dc),
.biu_we_i(dcbiu_we_dc),
.biu_sel_i(dcbiu_sel_dc),
.biu_cab_i(dcbiu_cab_dc),
.biu_dat_o(dcbiu_dat_biu),
.biu_ack_o(dcbiu_ack_biu),
.biu_err_o(dcbiu_err_biu)
.biu_dat_i(sbbiu_dat_sb),
.biu_adr_i(sbbiu_adr_sb),
.biu_cyc_i(sbbiu_cyc_sb),
.biu_stb_i(sbbiu_stb_sb),
.biu_we_i(sbbiu_we_sb),
.biu_sel_i(sbbiu_sel_sb),
.biu_cab_i(sbbiu_cab_sb),
.biu_dat_o(sbbiu_dat_biu),
.biu_ack_o(sbbiu_ack_biu),
.biu_err_o(sbbiu_err_biu)
);
 
//
624,19 → 640,52
.spr_dat_i(spr_dat_cpu),
 
// DC and BIU
.dcbiu_dat_o(dcbiu_dat_dc),
.dcbiu_adr_o(dcbiu_adr_dc),
.dcbiu_cyc_o(dcbiu_cyc_dc),
.dcbiu_stb_o(dcbiu_stb_dc),
.dcbiu_we_o(dcbiu_we_dc),
.dcbiu_sel_o(dcbiu_sel_dc),
.dcbiu_cab_o(dcbiu_cab_dc),
.dcbiu_dat_i(dcbiu_dat_biu),
.dcbiu_ack_i(dcbiu_ack_biu),
.dcbiu_err_i(dcbiu_err_biu)
.dcsb_dat_o(dcsb_dat_dc),
.dcsb_adr_o(dcsb_adr_dc),
.dcsb_cyc_o(dcsb_cyc_dc),
.dcsb_stb_o(dcsb_stb_dc),
.dcsb_we_o(dcsb_we_dc),
.dcsb_sel_o(dcsb_sel_dc),
.dcsb_cab_o(dcsb_cab_dc),
.dcsb_dat_i(dcsb_dat_sb),
.dcsb_ack_i(dcsb_ack_sb),
.dcsb_err_i(dcsb_err_sb)
);
 
//
// Instantiation of Store Buffer
//
or1200_sb or1200_sb(
// RISC clock, reset
.clk(clk_i),
.rst(rst_i),
 
// Internal RISC bus (DC<->SB)
.dcsb_dat_i(dcsb_dat_dc),
.dcsb_adr_i(dcsb_adr_dc),
.dcsb_cyc_i(dcsb_cyc_dc),
.dcsb_stb_i(dcsb_stb_dc),
.dcsb_we_i(dcsb_we_dc),
.dcsb_sel_i(dcsb_sel_dc),
.dcsb_cab_i(dcsb_cab_dc),
.dcsb_dat_o(dcsb_dat_sb),
.dcsb_ack_o(dcsb_ack_sb),
.dcsb_err_o(dcsb_err_sb),
 
// SB and BIU
.sbbiu_dat_o(sbbiu_dat_sb),
.sbbiu_adr_o(sbbiu_adr_sb),
.sbbiu_cyc_o(sbbiu_cyc_sb),
.sbbiu_stb_o(sbbiu_stb_sb),
.sbbiu_we_o(sbbiu_we_sb),
.sbbiu_sel_o(sbbiu_sel_sb),
.sbbiu_cab_o(sbbiu_cab_sb),
.sbbiu_dat_i(sbbiu_dat_biu),
.sbbiu_ack_i(sbbiu_ack_biu),
.sbbiu_err_i(sbbiu_err_biu)
);
 
//
// Instantiation of Debug Unit
//
or1200_du or1200_du(

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