OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 985 to Rev 986
    ↔ Reverse comparison
  •

Rev 985 → Rev 986

/trunk/or1ksim/cuc/verilog.c
528,12 → 528,19
if (nstores) {
int cur_store = 0;
GEN ("\n/* Memory stores */\n");
GEN ("always @(posedge clk or posedge rst)\nbegin\n");
GEN (" if (rst) swb_dat_o <= #Tp 32'h0;\n");
GEN ("always @(");
for (i = 0; i < f->nmsched; i++)
if (f->mtype[i] & MT_STORE) {
char t[30];
GEN (" else if (s_stb[%i]) swb_dat_o <= #Tp %s;\n", cur_store++,
printf ("%s%s", cur_store++ ? ", " : "", print_op_v (f, t, f->msched[i], 0));
}
cur_store = 0;
GEN (")\nbegin\n");
for (i = 0; i < f->nmsched; i++)
if (f->mtype[i] & MT_STORE) {
char t[30];
GEN (" %sif (s_stb[%i]) swb_dat_o = %s;\n", i ? "else " : "", cur_store++,
print_op_v (f, t, f->msched[i], 0));
//printf ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
}
540,104 → 547,70
GEN ("end\n");
}
 
if (nloads) {
int cur_load = 0;
GEN ("\n/* Load state machine */\n");
GEN ("always @(posedge clk or posedge rst)\n");
GEN ("begin\n");
GEN (" if (rst) begin\n");
GEN (" l_stb <= #Tp %i'h0;\n", nloads);
GEN (" lwb_cycstb_o <= #Tp 1'b0;\n");
GEN (" lwb_sel_o[3:0] <= #Tp 4'b0000;\n");
GEN (" lwb_linbrst_o <= #Tp 1'b0;\n");
GEN (" lwb_adr_o <= #Tp 32'h0;\n");
GEN (" end else begin\n");
cucdebug (1, "loads \n");
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_LOAD) {
/* Generate load and store state machine */
for (j = 0; j < 2; j++) {
char c;
char *s;
switch (j) {
case 0: c = 'l'; s = "Load"; break;
case 1: c = 's'; s = "Store"; break;
case 2: c = 'c'; s = "Calls"; break;
}
if (j == 0 && nloads
|| j == 1 && nstores
|| j == 2 && ncalls) {
int cur = 0;
char t[30];
dep_list *dep = f->INSN(f->msched[i]).dep;
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
GEN (" if (");
GEN ("\n/* %s state machine */\n", s);
GEN ("always @(");
for (i = 0; i < f->nmsched; i++) {
print_op_v (f, t, f->msched[i], 1); break;
GEN (" or ");
GEN ("t%x_%x", REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
GEN (" or ");
}
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
GEN (") begin\n");
print_turn_off_dep (fo, f, dep);
GEN (" l_stb[%i] <= #Tp 1'b1;\n", cur_load++);
GEN (" lwb_cycstb_o <= #Tp 1'b1;\n");
GEN (" lwb_sel_o[3:0] <= #Tp 4'b");
switch (f->mtype[i] & MT_WIDTH) {
case 1: GEN ("0001 << (%s & 32'h3);\n",
print_op_v (f, t, f->msched[i], 1)); break;
case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
print_op_v (f, t, f->msched[i], 1)); break;
case 4: GEN ("1111;\n"); break;
default: assert (0);
}
GEN (" lwb_linbrst_o <= #Tp 1'b%i;\n",
GEN ("%c_end)\n", c);
GEN ("begin\n");
cucdebug (1, "%s\n", s);
for (i = 0; i < f->nmsched; i++)
if (j == 0 && f->mtype[i] & MT_LOAD
|| j == 1 && f->mtype[i] & MT_STORE
|| j == 2 && f->mtype[i] & MT_CALL) {
dep_list *dep = f->INSN(f->msched[i]).dep;
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
GEN (" if (");
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
GEN (") begin\n");
print_turn_off_dep (fo, f, dep);
GEN (" %c_stb[%i] <= #Tp 1'b1;\n", c, cur++);
GEN (" %cwb_cycstb_o <= #Tp 1'b1;\n", c);
GEN (" %cwb_sel_o[3:0] <= #Tp 4'b", c);
switch (f->mtype[i] & MT_WIDTH) {
case 1: GEN ("0001 << (%s & 32'h3);\n",
print_op_v (f, t, f->msched[i], 1)); break;
case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
print_op_v (f, t, f->msched[i], 1)); break;
case 4: GEN ("1111;\n"); break;
default: assert (0);
}
GEN (" %cwb_linbrst_o <= #Tp 1'b%i;\n", c,
(f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
GEN (" lwb_adr_o <= #Tp t%x_%x & ~32'h3;\n",
GEN (" %cwb_adr_o <= #Tp t%x_%x & ~32'h3;\n", c,
REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
GEN (" end\n");
}
GEN (" if (l_end[%i]) begin\n", nloads - 1);
GEN (" l_stb <= #Tp %i'h0;\n", nloads);
GEN (" lwb_cycstb_o <= #Tp 1'b0;\n");
GEN (" lwb_sel_o[3:0] <= #Tp 4'b0000;\n");
GEN (" lwb_linbrst_o <= #Tp 1'b0;\n");
GEN (" lwb_adr_o <= #Tp 32'h0;\n");
GEN (" end\n");
GEN (" end\n");
GEN ("end\n");
}
 
if (nstores) {
int cur_store = 0;
GEN ("\n/* Store state machine */\n");
GEN ("always @(posedge clk or posedge rst)\n");
GEN ("begin\n");
GEN (" if (rst) begin\n");
GEN (" s_stb <= #Tp %i'h0;\n", nstores);
GEN (" swb_cycstb_o <= #Tp 1'b0;\n");
GEN (" swb_sel_o[3:0] <= #Tp 4'b0000;\n");
GEN (" swb_linbrst_o <= #Tp 1'b0;\n");
GEN (" swb_adr_o <= #Tp 32'h0;\n");
GEN (" end else begin\n");
cucdebug (1, "stores \n");
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_STORE) {
char t[30];
dep_list *dep = f->INSN(f->msched[i]).dep;
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
GEN (" if (");
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
GEN (") begin\n");
print_turn_off_dep (fo, f, dep);
GEN (" s_stb[%i] <= #Tp 1'b1;\n", cur_store++);
GEN (" swb_cycstb_o <= #Tp 1'b1;\n");
GEN (" swb_sel_o[3:0] <= #Tp 4'b");
switch (f->mtype[i] & MT_WIDTH) {
case 1: GEN ("0001 << (%s & 32'h3);\n",
print_op_v (f, t, f->msched[i], 1)); break;
case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
print_op_v (f, t, f->msched[i], 1)); break;
case 4: GEN ("1111;\n"); break;
default: assert (0);
GEN (" end\n");
}
GEN (" swb_linbrst_o <= #Tp 1'b%i;\n",
(f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
GEN (" swb_adr_o <= #Tp t%x_%x & ~32'h3;\n",
REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
GEN (" end\n");
GEN (" if (%c_end[%i]) begin\n", c, cur - 1);
GEN (" %c_stb <= #Tp %i'h0;\n", c, cur);
GEN (" %cwb_cycstb_o <= #Tp 1'b0;\n", c);
GEN (" %cwb_sel_o[3:0] <= #Tp 4'b0000;\n", c);
GEN (" %cwb_linbrst_o <= #Tp 1'b0;\n", c);
GEN (" %cwb_adr_o <= #Tp 32'h0;\n", c);
GEN (" end\n");
GEN ("end\n");
}
GEN (" if (s_end[%i]) begin\n", nstores - 1);
GEN (" s_stb <= #Tp %i'h0;\n", nstores);
GEN (" swb_cycstb_o <= #Tp 1'b0;\n");
GEN (" swb_sel_o[3:0] <= #Tp 4'b0000;\n");
GEN (" swb_linbrst_o <= #Tp 1'b0;\n");
GEN (" swb_adr_o <= #Tp 32'h0;\n");
GEN (" end\n");
GEN (" end\n");
GEN ("end\n");
}
 
if (ncalls) {

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.