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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 986 to Rev 987
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  •

Rev 986 → Rev 987

/trunk/orpmon/reset.S
82,7 → 82,11
.org (0x500 - 0x100 + _reset)
.endif
 
l.j _tick
l.addi r1,r1,-128
l.sw 0x4(r1),r2
l.movhi r2,hi(_tick)
l.ori r2,r2,lo(_tick)
l.jr r2
l.nop
 
.if IN_FLASH
92,7 → 96,11
.org (0x600 - 0x100 + _reset)
.endif
 
l.j _align
l.addi r1,r1,-128
l.sw 0x08(r1),r2
l.movhi r2,hi(_align)
l.ori r2,r2,lo(_align)
l.jr r2
l.nop
 
.if IN_FLASH
101,7 → 109,11
.org (0x800 - 0x100 + _reset)
.endif
 
l.j _int_wrapper
l.addi r1,r1,-128
l.sw 0x4(r1),r2
l.movhi r2,hi(_int_wrapper)
l.ori r2,r2,lo(_int_wrapper)
l.jr r2
l.nop
 
.section .text
224,7 → 236,7
l.addi r4,r3,MC_CSC(0)
l.movhi r5,hi(FLASH_BASE_ADDR)
l.srai r5,r5,5
l.srai r5,r5,6
l.ori r5,r5,0x0025
l.sw 0(r4),r5
249,7 → 261,7
 
l.addi r4,r3,MC_CSC(1)
l.movhi r5,hi(SDRAM_BASE_ADDR)
l.srai r5,r5,5
l.srai r5,r5,6
l.ori r5,r5,0x0411
l.sw 0(r4),r5
256,7 → 268,7
#ifdef ETH_DATA_BASE
l.addi r4,r3,MC_CSC(2)
l.movhi r5,hi(ETH_DATA_BASE)
l.srai r5,r5,5
l.srai r5,r5,6
l.ori r5,r5,0x0005
l.sw 0(r4),r5
271,9 → 283,6
.endif
 
_tick:
l.addi r1,r1,-128
 
l.sw 0x4(r1),r2
l.sw 0x8(r1),r4
l.sw 0xc(r1),r5
l.sw 0x10(r1),r6
346,9 → 355,6
l.nop
 
_int_wrapper:
l.addi r1,r1,-128
 
l.sw 0x4(r1),r2
l.sw 0x8(r1),r4
l.sw 0xc(r1),r5
l.sw 0x10(r1),r6
422,8 → 428,6
l.nop
 
_align:
l.addi r1,r1,-128
l.sw 0x08(r1),r2
l.sw 0x0c(r1),r3
l.sw 0x10(r1),r4
l.sw 0x14(r1),r5
/trunk/orpmon/include/board.h
1,11 → 1,7
#ifndef _BOARD_H_
#define _BOARD_H_
 
#ifdef XESS
#define MC_ENABLED 0
#else
#define MC_ENABLED 1
#endif
 
#define IC_ENABLE 0
#define IC_SIZE 8192
12,47 → 8,36
#define DC_ENABLE 0
#define DC_SIZE 8192
 
#define MC_CSR_VAL 0x0B000300
#define MC_MASK_VAL 0x000000e0
#define FLASH_BASE_ADDR 0x04000000
#define FLASH_SIZE 0x02000000
#define FLASH_BLOCK_SIZE 0x20000
#define FLASH_TMS_VAL 0x00102102
#define SDRAM_BASE_ADDR 0x00000000
#define SDRAM_TMS_VAL 0x07248230
#define MC_CSR_VAL 0x0B000300
#define MC_MASK_VAL 0x000003f0
#define FLASH_BASE_ADDR 0xf0000000
#define FLASH_TMS_VAL 0x00000103
#define SDRAM_BASE_ADDR 0x00000000
#define SDRAM_TMS_VAL 0x19220057
 
#ifdef XESS
#define IN_CLK 10000000
#else
#define FLASH_BLOCK_SIZE 0x00020000
#define FLASH_SIZE 0x02000000
 
#define IN_CLK 25000000
#endif
 
#define UART_BAUD_RATE 9600
 
#define TICKS_PER_SEC 100
 
#define STACK_SIZE 0x10000
 
#ifdef XESS
#define UART_BAUD_RATE 19200
#else
#define UART_BAUD_RATE 9600 /* 115200 */
#endif
 
#define UART_BASE 0x90000000
#define UART_IRQ 19
#ifdef XESS
#define ETH_BASE 0x92000000
#else
#define ETH_BASE 0xD0000000
#endif
#define ETH_IRQ 15
#define MC_BASE_ADDR 0x60000000
#define SPI_BASE 0xa0000000
#define UART_IRQ 2
#define ETH_BASE 0x92000000
#define ETH_IRQ 4
#define MC_BASE_ADDR 0x93000000
#define SPI_BASE 0xb9000000
#define CRT_BASE_ADDR 0x97000000
#define ATA_BASE_ADDR 0x9e000000
#define KBD_BASE_ADD 0x94000000
#define KBD_IRQ 5
 
#ifdef XESS
#define ETH_DATA_BASE 0x00100000 /* Address for ETH_DATA */
#else
#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
#endif
#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
 
#define BOARD_DEF_IP 0x0a010185
#define BOARD_DEF_MASK 0xff000000
66,10 → 51,8
#define ETH_MACADDR5 0x9a
 
#define CRT_ENABLED 1
#define CRT_BASE_ADDR 0xc0000000
#define FB_BASE_ADDR 0xa8000000
 
#define ATA_BASE_ADDR 0xc8000000
 
/* Whether online help is available -- saves space */
#define HELP_ENABLED 1
80,11 → 63,6
/* Whether we have keyboard suppport */
#define KBD_ENABLED 1
 
/* Keyboard base address */
#define KBD_BASE_ADD 0x98000000
 
#define KBD_IRQ 12
 
/* Keyboard buffer size */
#define KBDBUF_SIZE 256
 
/trunk/orpmon/sim.cfg
109,7 → 109,7
device 0
name = "FLASH"
ce = 0
baseaddr = 0x04000000
baseaddr = 0xf0000000
size = 0x00800000
delayr = 10
delayw = -1
573,7 → 573,7
 
section mc
enabled = 1
baseaddr = 0x60000000
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
end
 
615,7 → 615,7
 
device 0
baseaddr = 0x90000000
irq = 19
irq = 2
rxfile = "uart0.rx"
txfile = "uart0.tx"
jitter = -1 /* async behaviour */
648,8 → 648,8
 
/*
device 0
baseaddr = 0xa0000000
irq = 4
baseaddr = 0x9a000000
irq = 11
enddevice
*/
end
699,9 → 699,9
nethernets = 1
 
device 0
baseaddr = 0xd0000000
baseaddr = 0x92000000
dma = 0
irq = 15
irq = 4
rtx_type = 1
tx_channel = 0
rx_channel = 1
736,8 → 736,8
ngpios = 1
 
device 0
baseaddr = 0xA1000000
irq = 23
baseaddr = 0x91000000
irq = 3
base_vapi_id = 0x0200
enddevice
end
767,8 → 767,8
nvgas = 1
device 0
baseaddr = 0xb0000000
irq = 20
baseaddr = 0x97100000
irq = 8
refresh_rate = 100000
filename = "primary"
enddevice
814,7 → 814,7
 
section fb
enabled = 1
baseaddr = 0xc0000000
baseaddr = 0x97000000
refresh_rate = 1000000
filename = "primary"
end
836,8 → 836,8
 
section kbd
enabled = 1
irq = 12
baseaddr = 0x98000000
irq = 5
baseaddr = 0x94000000
rxfile = "kbd.rx"
end
 
890,8 → 890,8
natas = 1
 
device 0
baseaddr = 0xc8000000
irq = 21
baseaddr = 0x9e000000
irq = 15
 
dev_type0 = 1
dev_file0 = "/tmp/sim_atadev0"
/trunk/orpmon/flash.ld
1,6 → 1,6
MEMORY
{
flash : ORIGIN = 0x04000000, LENGTH = 0x00100000
flash : ORIGIN = 0xf0000000, LENGTH = 0x00100000
vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
ram : ORIGIN = 0x00002000, LENGTH = 0x00200000 - 0x00002000
}
/trunk/orpmon/drivers/eth.c
87,7 → 87,7
REG32(ETH_REG_BASE + ETH_TX_BD_NUM) = ETH_TXBD_NUM << 1;
 
/* Set min/max packet length */
REG32(ETH_REG_BASE + ETH_PACKETLEN) = 0x003c0600;
REG32(ETH_REG_BASE + ETH_PACKETLEN) = 0x00640600;
 
/* Set IPGT register to recomended value */
REG32(ETH_REG_BASE + ETH_IPGT) = 0x00000012;

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