URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 989 to Rev 990
- ↔ Reverse comparison
Rev 989 → Rev 990
/trunk/orp/orp_soc/sw/except/except_test.c
10,7 → 10,7
#define FLASH_START 0x04000000 |
#define FLASH_SIZE 0x00200000 |
#define RAM_START 0x00000000 |
#define RAM_SIZE 0x00200000 |
#define RAM_SIZE 0x00400000 |
|
/* MMU page size */ |
#define PAGE_SIZE 8192 |
37,14 → 37,13
|
#define TLB_CODE_MASK 0xffffc000 |
#define TLB_PR_MASK 0x00003fff |
#define DTLB_PR_NOLIMIT ( SPR_DTLBTR_CI | \ |
SPR_DTLBTR_URE | \ |
|
#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE | \ |
SPR_DTLBTR_UWE | \ |
SPR_DTLBTR_SRE | \ |
SPR_DTLBTR_SWE ) |
|
#define ITLB_PR_NOLIMIT ( SPR_ITLBTR_CI | \ |
SPR_ITLBTR_SXE | \ |
#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE | \ |
SPR_ITLBTR_UXE ) |
|
/* fails if x is false */ |
90,6 → 89,7
extern int int_trigger (void); |
extern int int_loop (void); |
extern int jump_back (void); |
extern int ic_invalidate (void); |
|
/* Local functions prototypes */ |
void dmmu_disable (void); |
409,7 → 409,7
} |
|
/* Set dtlb no permisions */ |
itlb_val = SPR_ITLBTR_CI; |
itlb_val = 0; |
|
/* Reset except counter */ |
except_count = 0; |
432,7 → 432,7
ASSERT(ret == 0); |
|
/* Set dtlb no permisions */ |
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE; |
itlb_val = SPR_ITLBTR_SXE; |
|
/* Reset except counter */ |
except_count = 0; |
448,7 → 448,7
ASSERT(ret == 0); |
|
/* Set dtlb no permisions */ |
itlb_val = SPR_ITLBTR_CI; |
itlb_val = 0; |
|
/* Reset except counter */ |
except_count = 0; |
464,7 → 464,7
ASSERT(ret == 0); |
|
/* Set dtlb no permisions */ |
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE; |
itlb_val = SPR_ITLBTR_SXE; |
|
/* Reset except counter */ |
except_count = 0; |
518,7 → 518,7
} |
|
/* Set dtlb no permisions */ |
dtlb_val = SPR_DTLBTR_CI; |
dtlb_val = 0; |
|
/* Reset except counter */ |
except_count = 0; |
542,7 → 542,7
ASSERT(ret == 0x12345678); |
|
/* Set dtlb no permisions */ |
dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE; |
dtlb_val = SPR_DTLBTR_SRE; |
|
/* Reset except counter */ |
except_count = 0; |
620,7 → 620,7
|
/* Set IMMU translation */ |
ea = RAM_START + (RAM_SIZE) + ((TLB_TEXT_SET_NB)*PAGE_SIZE); |
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE; |
itlb_val = SPR_ITLBTR_SXE; |
mtspr (SPR_ITLBMR_BASE(0) + TLB_TEXT_SET_NB, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V); |
mtspr (SPR_ITLBTR_BASE(0) + TLB_TEXT_SET_NB, ((ea + PAGE_SIZE) & SPR_ITLBTR_PPN) | itlb_val); |
|
647,6 → 647,8
ea = RAM_START + RAM_SIZE - 8; |
memcpy((void *)ea, (void *)&jump_back, 8); |
|
// ic_invalidate (); |
|
/* Check if there was bus error exception */ |
ret = call (ea, 0); |
ASSERT(except_count == 1); |
662,7 → 664,7
|
/* Set DMMU translation */ |
ea = RAM_START + (RAM_SIZE) + ((TLB_DATA_SET_NB)*PAGE_SIZE); |
dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE; |
dtlb_val = SPR_DTLBTR_SRE; |
mtspr (SPR_DTLBMR_BASE(0) + TLB_DATA_SET_NB, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V); |
mtspr (SPR_DTLBTR_BASE(0) + TLB_DATA_SET_NB, ((ea + PAGE_SIZE) & SPR_DTLBTR_PPN) | dtlb_val); |
|
884,7 → 886,7
} |
|
/* Set dtlb no permisions */ |
itlb_val = SPR_ITLBTR_CI; |
itlb_val = 0; |
|
/* Invalidate all entries in DTLB */ |
for (i = 0; i < DTLB_WAYS; i++) { |
906,7 → 908,7
tick_init (1, 1); |
|
/* Set dtlb no permisions */ |
dtlb_val = SPR_DTLBTR_CI; |
dtlb_val = 0; |
|
/* Reset except counter */ |
except_count = 0; |
1127,10 → 1129,10
itlb_test (); // OK |
|
/* DTLB exception test */ |
// dtlb_test (); // OK [with enabled IC/DC it fails on or1ksim] |
dtlb_test (); // OK [with enabled IC/DC it fails on or1ksim] |
|
/* Bus error exception test */ |
// buserr_test (); // Doesn't work on or1ksim |
buserr_test (); // Doesn't work on or1ksim |
|
/* Illegal insn test */ |
illegal_insn_test (); // OK |
1145,7 → 1147,7
// range_test (); // Doesn't work on or1ksim |
|
/* Exception priority test */ |
// except_priority_test (); // Doesn't work on or1ksim |
except_priority_test (); // Doesn't work on or1ksim |
|
report (0xdeaddead); |
exit (0); |
/trunk/orp/orp_soc/sw/except/except_test_s.S
21,6 → 21,7
.global _int_trigger |
.global _int_loop |
.global _jump_back |
.global _ic_invalidate |
|
.section .vectors |
.extern _reset_support |
564,3 → 565,40
l.jr r9 |
l.addi r11,r11,1 |
|
_ic_invalidate: |
/* Disable IC */ |
l.mfspr r13,r0,SPR_SR |
|
l.andi r11,r13,SPR_SR_ICE |
l.sfeq r11,r0 |
l.bnf 1f |
l.nop |
l.jr r9 |
l.nop |
1: |
l.addi r11,r0,-1 |
l.xori r11,r11,SPR_SR_ICE |
l.and r11,r13,r11 |
l.mtspr r0,r11,SPR_SR |
|
/* Invalidate IC */ |
l.addi r13,r0,0 |
l.addi r11,r0,8192 |
1: |
l.mtspr r0,r13,SPR_ICBIR |
l.sfne r13,r11 |
l.bf 1b |
l.addi r13,r13,16 |
|
/* Enable IC */ |
l.mfspr r13,r0,SPR_SR |
l.ori r13,r13,SPR_SR_ICE |
l.mtspr r0,r13,SPR_SR |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
|
l.jr r9 |
l.nop |