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https://opencores.org/ocsvn/or1k/or1k/trunk
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- This comparison shows the changes necessary to convert path
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- from Rev 993 to Rev 994
- ↔ Reverse comparison
Rev 993 → Rev 994
/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.20 2002/08/18 21:59:45 lampret |
// Disable SB until it is tested |
// |
// Revision 1.19 2002/08/18 19:53:08 lampret |
// Added store buffer. |
// |
317,30 → 320,6
//`define OR1200_WB_RETRY 7 |
|
// |
// Store buffer |
// |
// It will improve performance by "caching" CPU stores |
// using store buffer. This is most important for function |
// prologues because DC can only work in write though mode |
// and all stores would have to complete external WB writes |
// to memory. |
// Store buffer is between DC and data BIU. |
// All stores will be stored into store buffer and immediately |
// completed by the CPU, even though actual external writes |
// will be performed later. As a consequence store buffer masks |
// all data bus errors related to stores (data bus errors |
// related to loads are delivered normally). |
// All pending CPU loads will wait until store buffer is empty to |
// ensure strict memory model. Right now this is necessary because |
// we don't make destinction between cached and cache inhibited |
// address space, so we simply empty store buffer until loads |
// can begin. |
// |
// [SB hasn't been tested yet, so don't enable it just yet!] |
// |
//`define OR1200_SB_IMPLEMENTED |
|
// |
// Enable additional synthesis directives if using |
// _Synopsys_ synthesis tool |
// |
1233,3 → 1212,46
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9 |
`define OR1200_DCTAG_W 20 |
`endif |
|
///////////////////////////////////////////////// |
// |
// Store buffer (SB) |
// |
|
// |
// Store buffer |
// |
// It will improve performance by "caching" CPU stores |
// using store buffer. This is most important for function |
// prologues because DC can only work in write though mode |
// and all stores would have to complete external WB writes |
// to memory. |
// Store buffer is between DC and data BIU. |
// All stores will be stored into store buffer and immediately |
// completed by the CPU, even though actual external writes |
// will be performed later. As a consequence store buffer masks |
// all data bus errors related to stores (data bus errors |
// related to loads are delivered normally). |
// All pending CPU loads will wait until store buffer is empty to |
// ensure strict memory model. Right now this is necessary because |
// we don't make destinction between cached and cache inhibited |
// address space, so we simply empty store buffer until loads |
// can begin. |
// |
// It makes design a bit bigger, depending what is the number of |
// entries in SB FIFO. Number of entries can be changed further |
// down. |
// |
//`define OR1200_SB_IMPLEMENTED |
|
// |
// Number of store buffer entries |
// |
// Verified number of entries are 4 and 8 entries |
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must |
// always match 2**OR1200_SB_LOG. |
// To disable store buffer, undefine |
// OR1200_SB_IMPLEMENTED. |
// |
`define OR1200_SB_LOG 2 // 2 or 3 |
`define OR1200_SB_ENTRIES 4 // 4 or 8 |
/trunk/or1200/rtl/verilog/or1200_sb.v
44,7 → 44,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2002/08/18 19:53:08 lampret |
// Added store buffer. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
139,7 → 142,7
// |
// Store buffer FIFO instantiation |
// |
or1200_sb_fifo #(68, 2, 4) or1200_sb_fifo ( |
or1200_sb_fifo or1200_sb_fifo ( |
.clk_i(clk), |
.rst_i(rst), |
.dat_i(fifo_dat_i), |
/trunk/or1200/rtl/verilog/or1200_sb_fifo.v
44,7 → 44,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2002/08/18 19:53:08 lampret |
// Added store buffer. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
55,9 → 58,9
clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o |
); |
|
parameter dw = 32; |
parameter fw = 2; |
parameter fl = 4; |
parameter dw = 68; |
parameter fw = `OR1200_SB_LOG; |
parameter fl = `OR1200_SB_ENTRIES; |
|
// |
// FIFO signals |
91,17 → 94,18
cntr <= #1 {fw+2{1'b0}}; |
dat_o <= #1 {dw{1'b0}}; |
end |
// else if ((wr_i && !full_o) && (rd_i && !empty_o)) begin // FIFO Read and Write |
else if (wr_i && rd_i) begin // FIFO Read and Write |
else if (wr_i && rd_i) begin // FIFO Read and Write |
mem[wr_pntr] <= #1 dat_i; |
if (wr_pntr >= fl-1) |
wr_pntr <= #1 {fw{1'b0}}; |
else |
wr_pntr <= #1 wr_pntr + 1'b1; |
if (empty_o) |
if (empty_o) begin |
dat_o <= #1 dat_i; |
else |
end |
else begin |
dat_o <= #1 mem[rd_pntr]; |
end |
if (rd_pntr >= fl-1) |
rd_pntr <= #1 {fw{1'b0}}; |
else |
111,7 → 115,7
mem[wr_pntr] <= #1 dat_i; |
cntr <= #1 cntr + 1'b1; |
empty_o <= #1 1'b0; |
if (cntr >= fl) begin |
if (cntr >= (fl-1)) begin |
full_o <= #1 1'b1; |
cntr <= #1 fl; |
end |
124,7 → 128,7
dat_o <= #1 mem[rd_pntr]; |
cntr <= #1 cntr - 1'b1; |
full_o <= #1 1'b0; |
if (cntr <= 0) begin |
if (cntr <= 1) begin |
empty_o <= #1 1'b1; |
cntr <= #1 {fw+2{1'b0}}; |
end |