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/tags/rel_3/docs/openrisc1200_spec.doc

tags/rel_3/docs/openrisc1200_spec.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/rel_3/docs/openrisc1200_spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/rel_3/docs/openrisc1200_spec.pdf =================================================================== --- tags/rel_3/docs/openrisc1200_spec.pdf (nonexistent) +++ tags/rel_3/docs/openrisc1200_spec.pdf (revision 995)

tags/rel_3/docs/openrisc1200_spec.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/rel_3/or1200/rtl/verilog/or1200_defines.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_defines.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_defines.v (revision 995) @@ -0,0 +1,1257 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's definitions //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Parameters of the OR1200 core //// +//// //// +//// To Do: //// +//// - add parameters that are missing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.20 2002/08/18 21:59:45 lampret +// Disable SB until it is tested +// +// Revision 1.19 2002/08/18 19:53:08 lampret +// Added store buffer. +// +// Revision 1.18 2002/08/15 06:04:11 lampret +// Fixed Xilinx trace buffer address. REported by Taylor Su. +// +// Revision 1.17 2002/08/12 05:31:44 lampret +// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. +// +// Revision 1.16 2002/07/14 22:17:17 lampret +// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. +// +// Revision 1.15 2002/06/08 16:20:21 lampret +// Added defines for enabling generic FF based memory macro for register file. +// +// Revision 1.14 2002/03/29 16:24:06 lampret +// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives +// +// Revision 1.13 2002/03/29 15:16:55 lampret +// Some of the warnings fixed. +// +// Revision 1.12 2002/03/28 19:25:42 lampret +// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. +// +// Revision 1.11 2002/03/28 19:13:17 lampret +// Updated defines. +// +// Revision 1.10 2002/03/14 00:30:24 lampret +// Added alternative for critical path in DU. +// +// Revision 1.9 2002/03/11 01:26:26 lampret +// Fixed async loop. Changed multiplier type for ASIC. +// +// Revision 1.8 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.7 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.6 2002/01/19 14:10:22 lampret +// Fixed OR1200_XILINX_RAM32X1D. +// +// Revision 1.5 2002/01/18 07:56:00 lampret +// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. +// +// Revision 1.4 2002/01/14 09:44:12 lampret +// Default ASIC configuration does not sample WB inputs. +// +// Revision 1.3 2002/01/08 00:51:08 lampret +// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. +// +// Revision 1.2 2002/01/03 21:23:03 lampret +// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.20 2001/12/04 05:02:36 lampret +// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 +// +// Revision 1.19 2001/11/27 19:46:57 lampret +// Now FPGA and ASIC target are separate. +// +// Revision 1.18 2001/11/23 21:42:31 simons +// Program counter divided to PPC and NPC. +// +// Revision 1.17 2001/11/23 08:38:51 lampret +// Changed DSR/DRR behavior and exception detection. +// +// Revision 1.16 2001/11/20 21:30:38 lampret +// Added OR1200_REGISTERED_INPUTS. +// +// Revision 1.15 2001/11/19 14:29:48 simons +// Cashes disabled. +// +// Revision 1.14 2001/11/13 10:02:21 lampret +// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) +// +// Revision 1.13 2001/11/12 01:45:40 lampret +// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. +// +// Revision 1.12 2001/11/10 03:43:57 lampret +// Fixed exceptions. +// +// Revision 1.11 2001/11/02 18:57:14 lampret +// Modified virtual silicon instantiations. +// +// Revision 1.10 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.9 2001/10/19 23:28:46 lampret +// Fixed some synthesis warnings. Configured with caches and MMUs. +// +// Revision 1.8 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.3 2001/08/17 08:01:19 lampret +// IC enable/disable. +// +// Revision 1.2 2001/08/13 03:36:20 lampret +// Added cfg regs. Moved all defines into one defines.v file. More cleanup. +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/22 03:31:54 lampret +// Fixed RAM's oen bug. Cache bypass under development. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// +// Dump VCD +// +//`define OR1200_VCD_DUMP + +// +// Generate debug messages during simulation +// +//`define OR1200_VERBOSE + +//`define OR1200_ASIC +//////////////////////////////////////////////////////// +// +// Typical configuration for an ASIC +// +`ifdef OR1200_ASIC + +// +// Target ASIC memories +// +//`define OR1200_ARTISAN_SSP +//`define OR1200_ARTISAN_SDP +//`define OR1200_ARTISAN_STP +`define OR1200_VIRTUALSILICON_SSP +`define OR1200_VIRTUALSILICON_STP_T1 +//`define OR1200_VIRTUALSILICON_STP_T2 + +// +// Do not implement Data cache +// +//`define OR1200_NO_DC + +// +// Do not implement Insn cache +// +//`define OR1200_NO_IC + +// +// Do not implement Data MMU +// +//`define OR1200_NO_DMMU + +// +// Do not implement Insn MMU +// +//`define OR1200_NO_IMMU + +// +// Select between ASIC optimized and generic multiplier +// +// (Generic seems to trigger a bug in the Cadence Ncsim simulator) +// +//`define OR1200_ASIC_MULTP2_32X32 +`define OR1200_GENERIC_MULTP2_32X32 + +// +// Size/type of insn/data cache if implemented +// +// `define OR1200_IC_1W_4KB +`define OR1200_IC_1W_8KB +// `define OR1200_DC_1W_4KB +`define OR1200_DC_1W_8KB + +`else + + +///////////////////////////////////////////////////////// +// +// Typical configuration for an FPGA +// + +// +// Target FPGA memories +// +`define OR1200_XILINX_RAMB4 +//`define OR1200_XILINX_RAM32X1D +//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D + +// +// Do not implement Data cache +// +//`define OR1200_NO_DC + +// +// Do not implement Insn cache +// +//`define OR1200_NO_IC + +// +// Do not implement Data MMU +// +//`define OR1200_NO_DMMU + +// +// Do not implement Insn MMU +// +//`define OR1200_NO_IMMU + +// +// Select between ASIC and generic multiplier +// +// (Generic seems to trigger a bug in the Cadence Ncsim simulator) +// +//`define OR1200_ASIC_MULTP2_32X32 +`define OR1200_GENERIC_MULTP2_32X32 + +// +// Size/type of insn/data cache if implemented +// (consider available FPGA memory resources) +// +`define OR1200_IC_1W_4KB +//`define OR1200_IC_1W_8KB +`define OR1200_DC_1W_4KB +//`define OR1200_DC_1W_8KB + +`endif + + +////////////////////////////////////////////////////////// +// +// Do not change below unless you know what you are doing +// + +// +// Register OR1200 WISHBONE outputs +// (must be defined/enabled) +// +`define OR1200_REGISTERED_OUTPUTS + +// +// Register OR1200 WISHBONE inputs +// +// (must be undefined/disabled) +// +//`define OR1200_REGISTERED_INPUTS + +// +// Disable bursts if they are not supported by the +// memory subsystem (only affect cache line fill) +// +//`define OR1200_NO_BURSTS +// + +// +// WISHBONE retry counter range +// +// 2^value range for retry counter. Retry counter +// is activated whenever *wb_rty_i is asserted and +// until retry counter expires, corresponding +// WISHBONE interface is deactivated. +// +// To disable retry counters and *wb_rty_i all together, +// undefine this macro. +// +//`define OR1200_WB_RETRY 7 + +// +// Enable additional synthesis directives if using +// _Synopsys_ synthesis tool +// +//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + +// +// Operand width / register file address width +// +// (DO NOT CHANGE) +// +`define OR1200_OPERAND_WIDTH 32 +`define OR1200_REGFILE_ADDR_WIDTH 5 + +// +// Implement rotate in the ALU +// +//`define OR1200_IMPL_ALU_ROTATE + +// +// Type of ALU compare to implement +// +//`define OR1200_IMPL_ALU_COMP1 +`define OR1200_IMPL_ALU_COMP2 + +// +// Select between low-power (larger) multiplier or faster multiplier +// +//`define OR1200_LOWPWR_MULT + +// +// Clock synchronization for RISC clk and WB divided clocks +// +// If you plan to run WB:RISC clock 1:1, you can comment these two +// +`define OR1200_CLKDIV_2_SUPPORTED +//`define OR1200_CLKDIV_4_SUPPORTED + +// +// Type of register file RAM +// +// Memory macro w/ two ports (see or1200_hdtp_32x32.v) +// `define OR1200_RFRAM_TWOPORT +// +// Memory macro dual port (see or1200_hddp_32x32.v) +`define OR1200_RFRAM_DUALPORT +// +// ... otherwise generic (flip-flop based) register file + +// +// Type of mem2reg aligner to implement. +// +// Once OR1200_IMPL_MEM2REG2 yielded faster +// circuit, however with today tools it will +// most probably give you slower circuit. +// +`define OR1200_IMPL_MEM2REG1 +//`define OR1200_IMPL_MEM2REG2 + +// +// Simulate l.div and l.divu +// +// If commented, l.div/l.divu will produce undefined result. If enabled, +// div instructions will be simulated, but not synthesized ! OR1200 +// does not have a hardware divider. +// +`define OR1200_SIM_ALU_DIV +`define OR1200_SIM_ALU_DIVU + +// +// ALUOPs +// +`define OR1200_ALUOP_WIDTH 4 +`define OR1200_ALUOP_NOP 4'd4 +/* Order defined by arith insns that have two source operands both in regs + (see binutils/include/opcode/or32.h) */ +`define OR1200_ALUOP_ADD 4'd0 +`define OR1200_ALUOP_ADDC 4'd1 +`define OR1200_ALUOP_SUB 4'd2 +`define OR1200_ALUOP_AND 4'd3 +`define OR1200_ALUOP_OR 4'd4 +`define OR1200_ALUOP_XOR 4'd5 +`define OR1200_ALUOP_MUL 4'd6 +`define OR1200_ALUOP_SHROT 4'd8 +`define OR1200_ALUOP_DIV 4'd9 +`define OR1200_ALUOP_DIVU 4'd10 +/* Order not specifically defined. */ +`define OR1200_ALUOP_IMM 4'd11 +`define OR1200_ALUOP_MOVHI 4'd12 +`define OR1200_ALUOP_COMP 4'd13 +`define OR1200_ALUOP_MTSR 4'd14 +`define OR1200_ALUOP_MFSR 4'd15 + +// +// MACOPs +// +`define OR1200_MACOP_WIDTH 2 +`define OR1200_MACOP_NOP 2'b00 +`define OR1200_MACOP_MAC 2'b01 +`define OR1200_MACOP_MSB 2'b10 + +// +// Shift/rotate ops +// +`define OR1200_SHROTOP_WIDTH 2 +`define OR1200_SHROTOP_NOP 2'd0 +`define OR1200_SHROTOP_SLL 2'd0 +`define OR1200_SHROTOP_SRL 2'd1 +`define OR1200_SHROTOP_SRA 2'd2 +`define OR1200_SHROTOP_ROR 2'd3 + +// Execution cycles per instruction +`define OR1200_MULTICYCLE_WIDTH 2 +`define OR1200_ONE_CYCLE 2'd0 +`define OR1200_TWO_CYCLES 2'd1 + +// Operand MUX selects +`define OR1200_SEL_WIDTH 2 +`define OR1200_SEL_RF 2'd0 +`define OR1200_SEL_IMM 2'd1 +`define OR1200_SEL_EX_FORW 2'd2 +`define OR1200_SEL_WB_FORW 2'd3 + +// +// BRANCHOPs +// +`define OR1200_BRANCHOP_WIDTH 3 +`define OR1200_BRANCHOP_NOP 3'd0 +`define OR1200_BRANCHOP_J 3'd1 +`define OR1200_BRANCHOP_JR 3'd2 +`define OR1200_BRANCHOP_BAL 3'd3 +`define OR1200_BRANCHOP_BF 3'd4 +`define OR1200_BRANCHOP_BNF 3'd5 +`define OR1200_BRANCHOP_RFE 3'd6 + +// +// LSUOPs +// +// Bit 0: sign extend +// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword +// Bit 3: 0 load, 1 store +`define OR1200_LSUOP_WIDTH 4 +`define OR1200_LSUOP_NOP 4'b0000 +`define OR1200_LSUOP_LBZ 4'b0010 +`define OR1200_LSUOP_LBS 4'b0011 +`define OR1200_LSUOP_LHZ 4'b0100 +`define OR1200_LSUOP_LHS 4'b0101 +`define OR1200_LSUOP_LWZ 4'b0110 +`define OR1200_LSUOP_LWS 4'b0111 +`define OR1200_LSUOP_LD 4'b0001 +`define OR1200_LSUOP_SD 4'b1000 +`define OR1200_LSUOP_SB 4'b1010 +`define OR1200_LSUOP_SH 4'b1100 +`define OR1200_LSUOP_SW 4'b1110 + +// FETCHOPs +`define OR1200_FETCHOP_WIDTH 1 +`define OR1200_FETCHOP_NOP 1'b0 +`define OR1200_FETCHOP_LW 1'b1 + +// +// Register File Write-Back OPs +// +// Bit 0: register file write enable +// Bits 2-1: write-back mux selects +`define OR1200_RFWBOP_WIDTH 3 +`define OR1200_RFWBOP_NOP 3'b000 +`define OR1200_RFWBOP_ALU 3'b001 +`define OR1200_RFWBOP_LSU 3'b011 +`define OR1200_RFWBOP_SPRS 3'b101 +`define OR1200_RFWBOP_LR 3'b111 + +// Compare instructions +`define OR1200_COP_SFEQ 3'b000 +`define OR1200_COP_SFNE 3'b001 +`define OR1200_COP_SFGT 3'b010 +`define OR1200_COP_SFGE 3'b011 +`define OR1200_COP_SFLT 3'b100 +`define OR1200_COP_SFLE 3'b101 +`define OR1200_COP_X 3'b111 +`define OR1200_SIGNED_COMPARE 'd3 +`define OR1200_COMPOP_WIDTH 4 + +// +// TAGs for instruction bus +// +`define OR1200_ITAG_IDLE 4'h0 // idle bus +`define OR1200_ITAG_NI 4'h1 // normal insn +`define OR1200_ITAG_BE 4'hb // Bus error exception +`define OR1200_ITAG_PE 4'hc // Page fault exception +`define OR1200_ITAG_TE 4'hd // TLB miss exception + +// +// TAGs for data bus +// +`define OR1200_DTAG_IDLE 4'h0 // idle bus +`define OR1200_DTAG_ND 4'h1 // normal data +`define OR1200_DTAG_AE 4'ha // Alignment exception +`define OR1200_DTAG_BE 4'hb // Bus error exception +`define OR1200_DTAG_PE 4'hc // Page fault exception +`define OR1200_DTAG_TE 4'hd // TLB miss exception + + +////////////////////////////////////////////// +// +// ORBIS32 ISA specifics +// + +// SHROT_OP position in machine word +`define OR1200_SHROTOP_POS 7:6 + +// ALU instructions multicycle field in machine word +`define OR1200_ALUMCYC_POS 9:8 + +// +// Instruction opcode groups (basic) +// +`define OR1200_OR32_J 6'b000000 +`define OR1200_OR32_JAL 6'b000001 +`define OR1200_OR32_BNF 6'b000011 +`define OR1200_OR32_BF 6'b000100 +`define OR1200_OR32_NOP 6'b000101 +`define OR1200_OR32_MOVHI 6'b000110 +`define OR1200_OR32_XSYNC 6'b001000 +`define OR1200_OR32_RFE 6'b001001 +/* */ +`define OR1200_OR32_JR 6'b010001 +`define OR1200_OR32_JALR 6'b010010 +`define OR1200_OR32_MACI 6'b010011 +/* */ +`define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LBZ 6'b100011 +`define OR1200_OR32_LBS 6'b100100 +`define OR1200_OR32_LHZ 6'b100101 +`define OR1200_OR32_LHS 6'b100110 +`define OR1200_OR32_ADDI 6'b100111 +`define OR1200_OR32_ADDIC 6'b101000 +`define OR1200_OR32_ANDI 6'b101001 +`define OR1200_OR32_ORI 6'b101010 +`define OR1200_OR32_XORI 6'b101011 +`define OR1200_OR32_MULI 6'b101100 +`define OR1200_OR32_MFSPR 6'b101101 +`define OR1200_OR32_SH_ROTI 6'b101110 +`define OR1200_OR32_SFXXI 6'b101111 +/* */ +`define OR1200_OR32_MTSPR 6'b110000 +`define OR1200_OR32_MACMSB 6'b110001 +/* */ +`define OR1200_OR32_SW 6'b110101 +`define OR1200_OR32_SB 6'b110110 +`define OR1200_OR32_SH 6'b110111 +`define OR1200_OR32_ALU 6'b111000 +`define OR1200_OR32_SFXX 6'b111001 + + +///////////////////////////////////////////////////// +// +// Exceptions +// +`define OR1200_EXCEPT_WIDTH 4 +`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf +`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he +`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd +`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc +`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb +`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha +`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9 +`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8 +`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7 +`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6 +`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5 +`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4 +`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3 +`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2 +`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1 +`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0 + + +///////////////////////////////////////////////////// +// +// SPR groups +// + +// Bits that define the group +`define OR1200_SPR_GROUP_BITS 15:11 + +// Width of the group bits +`define OR1200_SPR_GROUP_WIDTH 5 + +// Bits that define offset inside the group +`define OR1200_SPR_OFS_BITS 10:0 + +// List of groups +`define OR1200_SPR_GROUP_SYS 5'd00 +`define OR1200_SPR_GROUP_DMMU 5'd01 +`define OR1200_SPR_GROUP_IMMU 5'd02 +`define OR1200_SPR_GROUP_DC 5'd03 +`define OR1200_SPR_GROUP_IC 5'd04 +`define OR1200_SPR_GROUP_MAC 5'd05 +`define OR1200_SPR_GROUP_DU 5'd06 +`define OR1200_SPR_GROUP_PM 5'd08 +`define OR1200_SPR_GROUP_PIC 5'd09 +`define OR1200_SPR_GROUP_TT 5'd10 + + +///////////////////////////////////////////////////// +// +// System group +// + +// +// System registers +// +`define OR1200_SPR_CFGR 7'd0 +`define OR1200_SPR_RF 6'd32 // 1024 >> 5 +`define OR1200_SPR_NPC 11'd16 +`define OR1200_SPR_SR 11'd17 +`define OR1200_SPR_PPC 11'd18 +`define OR1200_SPR_EPCR 11'd32 +`define OR1200_SPR_EEAR 11'd48 +`define OR1200_SPR_ESR 11'd64 + +// +// SR bits +// +`define OR1200_SR_WIDTH 16 +`define OR1200_SR_SM 0 +`define OR1200_SR_TEE 1 +`define OR1200_SR_IEE 2 +`define OR1200_SR_DCE 3 +`define OR1200_SR_ICE 4 +`define OR1200_SR_DME 5 +`define OR1200_SR_IME 6 +`define OR1200_SR_LEE 7 +`define OR1200_SR_CE 8 +`define OR1200_SR_F 9 +`define OR1200_SR_CY 10 // Unused +`define OR1200_SR_OV 11 // Unused +`define OR1200_SR_OVE 12 // Unused +`define OR1200_SR_DSX 13 // Unused +`define OR1200_SR_EPH 14 +`define OR1200_SR_FO 15 +`define OR1200_SR_CID 31:28 // Unimplemented + +// Bits that define offset inside the group +`define OR1200_SPROFS_BITS 10:0 + +// +// VR, UPR and Configuration Registers +// + +// Define if you want configuration registers implemented +`define OR1200_CFGR_IMPLEMENTED + +// Define if you want full address decode inside SYS group +`define OR1200_SYS_FULL_DECODE + +// Offsets of VR, UPR and CFGR registers +`define OR1200_SPRGRP_SYS_VR 4'h0 +`define OR1200_SPRGRP_SYS_UPR 4'h1 +`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2 +`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3 +`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4 +`define OR1200_SPRGRP_SYS_DCCFGR 4'h5 +`define OR1200_SPRGRP_SYS_ICCFGR 4'h6 +`define OR1200_SPRGRP_SYS_DCFGR 4'h7 + +// VR fields +`define OR1200_VR_REV_BITS 5:0 +`define OR1200_VR_RES1_BITS 15:6 +`define OR1200_VR_CFG_BITS 23:16 +`define OR1200_VR_VER_BITS 31:24 + +// VR values +`define OR1200_VR_REV 6'h00 +`define OR1200_VR_RES1 10'h000 +`define OR1200_VR_CFG 8'h00 +`define OR1200_VR_VER 8'h12 + +// UPR fields +`define OR1200_UPR_UP_BITS 0 +`define OR1200_UPR_DCP_BITS 1 +`define OR1200_UPR_ICP_BITS 2 +`define OR1200_UPR_DMP_BITS 3 +`define OR1200_UPR_IMP_BITS 4 +`define OR1200_UPR_MP_BITS 5 +`define OR1200_UPR_DUP_BITS 6 +`define OR1200_UPR_PCUP_BITS 7 +`define OR1200_UPR_PMP_BITS 8 +`define OR1200_UPR_PICP_BITS 9 +`define OR1200_UPR_TTP_BITS 10 +`define OR1200_UPR_RES1_BITS 23:11 +`define OR1200_UPR_CUP_BITS 31:24 + +// UPR values +`define OR1200_UPR_UP 1'b1 +`define OR1200_UPR_DCP 1'b1 +`define OR1200_UPR_ICP 1'b1 +`define OR1200_UPR_DMP 1'b1 +`define OR1200_UPR_IMP 1'b1 +`define OR1200_UPR_MP 1'b1 +`define OR1200_UPR_DUP 1'b1 +`define OR1200_UPR_PCUP 1'b0 +`define OR1200_UPR_PMP 1'b1 +`define OR1200_UPR_PICP 1'b1 +`define OR1200_UPR_TTP 1'b1 +`define OR1200_UPR_RES1 13'h0000 +`define OR1200_UPR_CUP 8'h00 + +// CPUCFGR fields +`define OR1200_CPUCFGR_NSGF_BITS 3:0 +`define OR1200_CPUCFGR_HGF_BITS 4 +`define OR1200_CPUCFGR_OB32S_BITS 5 +`define OR1200_CPUCFGR_OB64S_BITS 6 +`define OR1200_CPUCFGR_OF32S_BITS 7 +`define OR1200_CPUCFGR_OF64S_BITS 8 +`define OR1200_CPUCFGR_OV64S_BITS 9 +`define OR1200_CPUCFGR_RES1_BITS 31:10 + +// CPUCFGR values +`define OR1200_CPUCFGR_NSGF 4'h0 +`define OR1200_CPUCFGR_HGF 1'b0 +`define OR1200_CPUCFGR_OB32S 1'b1 +`define OR1200_CPUCFGR_OB64S 1'b0 +`define OR1200_CPUCFGR_OF32S 1'b0 +`define OR1200_CPUCFGR_OF64S 1'b0 +`define OR1200_CPUCFGR_OV64S 1'b0 +`define OR1200_CPUCFGR_RES1 22'h000000 + +// DMMUCFGR fields +`define OR1200_DMMUCFGR_NTW_BITS 1:0 +`define OR1200_DMMUCFGR_NTS_BITS 4:2 +`define OR1200_DMMUCFGR_NAE_BITS 7:5 +`define OR1200_DMMUCFGR_CRI_BITS 8 +`define OR1200_DMMUCFGR_PRI_BITS 9 +`define OR1200_DMMUCFGR_TEIRI_BITS 10 +`define OR1200_DMMUCFGR_HTR_BITS 11 +`define OR1200_DMMUCFGR_RES1_BITS 31:12 + +// DMMUCFGR values +`define OR1200_DMMUCFGR_NTW 2'h0 +`define OR1200_DMMUCFGR_NTS 3'h5 +`define OR1200_DMMUCFGR_NAE 3'h0 +`define OR1200_DMMUCFGR_CRI 1'b0 +`define OR1200_DMMUCFGR_PRI 1'b0 +`define OR1200_DMMUCFGR_TEIRI 1'b1 +`define OR1200_DMMUCFGR_HTR 1'b0 +`define OR1200_DMMUCFGR_RES1 20'h00000 + +// IMMUCFGR fields +`define OR1200_IMMUCFGR_NTW_BITS 1:0 +`define OR1200_IMMUCFGR_NTS_BITS 4:2 +`define OR1200_IMMUCFGR_NAE_BITS 7:5 +`define OR1200_IMMUCFGR_CRI_BITS 8 +`define OR1200_IMMUCFGR_PRI_BITS 9 +`define OR1200_IMMUCFGR_TEIRI_BITS 10 +`define OR1200_IMMUCFGR_HTR_BITS 11 +`define OR1200_IMMUCFGR_RES1_BITS 31:12 + +// IMMUCFGR values +`define OR1200_IMMUCFGR_NTW 2'h0 +`define OR1200_IMMUCFGR_NTS 3'h5 +`define OR1200_IMMUCFGR_NAE 3'h0 +`define OR1200_IMMUCFGR_CRI 1'b0 +`define OR1200_IMMUCFGR_PRI 1'b0 +`define OR1200_IMMUCFGR_TEIRI 1'b1 +`define OR1200_IMMUCFGR_HTR 1'b0 +`define OR1200_IMMUCFGR_RES1 20'h00000 + +// DCCFGR fields +`define OR1200_DCCFGR_NCW_BITS 2:0 +`define OR1200_DCCFGR_NCS_BITS 6:3 +`define OR1200_DCCFGR_CBS_BITS 7 +`define OR1200_DCCFGR_CWS_BITS 8 +`define OR1200_DCCFGR_CCRI_BITS 9 +`define OR1200_DCCFGR_CBIRI_BITS 10 +`define OR1200_DCCFGR_CBPRI_BITS 11 +`define OR1200_DCCFGR_CBLRI_BITS 12 +`define OR1200_DCCFGR_CBFRI_BITS 13 +`define OR1200_DCCFGR_CBWBRI_BITS 14 +`define OR1200_DCCFGR_RES1_BITS 31:15 + +// DCCFGR values +`define OR1200_DCCFGR_NCW 3'h0 +`define OR1200_DCCFGR_NCS 4'h5 +`define OR1200_DCCFGR_CBS 1'b0 +`define OR1200_DCCFGR_CWS 1'b0 +`define OR1200_DCCFGR_CCRI 1'b1 +`define OR1200_DCCFGR_CBIRI 1'b1 +`define OR1200_DCCFGR_CBPRI 1'b0 +`define OR1200_DCCFGR_CBLRI 1'b0 +`define OR1200_DCCFGR_CBFRI 1'b0 +`define OR1200_DCCFGR_CBWBRI 1'b1 +`define OR1200_DCCFGR_RES1 17'h00000 + +// ICCFGR fields +`define OR1200_ICCFGR_NCW_BITS 2:0 +`define OR1200_ICCFGR_NCS_BITS 6:3 +`define OR1200_ICCFGR_CBS_BITS 7 +`define OR1200_ICCFGR_CWS_BITS 8 +`define OR1200_ICCFGR_CCRI_BITS 9 +`define OR1200_ICCFGR_CBIRI_BITS 10 +`define OR1200_ICCFGR_CBPRI_BITS 11 +`define OR1200_ICCFGR_CBLRI_BITS 12 +`define OR1200_ICCFGR_CBFRI_BITS 13 +`define OR1200_ICCFGR_CBWBRI_BITS 14 +`define OR1200_ICCFGR_RES1_BITS 31:15 + +// ICCFGR values +`define OR1200_ICCFGR_NCW 3'h0 +`define OR1200_ICCFGR_NCS 4'h5 +`define OR1200_ICCFGR_CBS 1'b0 +`define OR1200_ICCFGR_CWS 1'b0 +`define OR1200_ICCFGR_CCRI 1'b1 +`define OR1200_ICCFGR_CBIRI 1'b1 +`define OR1200_ICCFGR_CBPRI 1'b0 +`define OR1200_ICCFGR_CBLRI 1'b0 +`define OR1200_ICCFGR_CBFRI 1'b0 +`define OR1200_ICCFGR_CBWBRI 1'b1 +`define OR1200_ICCFGR_RES1 17'h00000 + +// DCFGR fields +`define OR1200_DCFGR_NDP_BITS 2:0 +`define OR1200_DCFGR_WPCI_BITS 3 +`define OR1200_DCFGR_RES1_BITS 31:4 + +// DCFGR values +`define OR1200_DCFGR_NDP 3'h0 +`define OR1200_DCFGR_WPCI 1'b0 +`define OR1200_DCFGR_RES1 28'h0000000 + + +///////////////////////////////////////////////////// +// +// Power Management (PM) +// + +// Define it if you want PM implemented +`define OR1200_PM_IMPLEMENTED + +// Bit positions inside PMR (don't change) +`define OR1200_PM_PMR_SDF 3:0 +`define OR1200_PM_PMR_DME 4 +`define OR1200_PM_PMR_SME 5 +`define OR1200_PM_PMR_DCGE 6 +`define OR1200_PM_PMR_UNUSED 31:7 + +// PMR offset inside PM group of registers +`define OR1200_PM_OFS_PMR 11'b0 + +// PM group +`define OR1200_SPRGRP_PM 5'd8 + +// Define if PMR can be read/written at any address inside PM group +`define OR1200_PM_PARTIAL_DECODING + +// Define if reading PMR is allowed +`define OR1200_PM_READREGS + +// Define if unused PMR bits should be zero +`define OR1200_PM_UNUSED_ZERO + + +///////////////////////////////////////////////////// +// +// Debug Unit (DU) +// + +// Define it if you want DU implemented +`define OR1200_DU_IMPLEMENTED + +// Define if you want trace buffer +// (for now only available for Xilinx Virtex FPGAs) +`ifdef OR1200_ASIC +`else +`define OR1200_DU_TB_IMPLEMENTED +`endif + +// Address offsets of DU registers inside DU group +`define OR1200_DU_OFS_DMR1 11'd16 +`define OR1200_DU_OFS_DMR2 11'd17 +`define OR1200_DU_OFS_DSR 11'd20 +`define OR1200_DU_OFS_DRR 11'd21 +`define OR1200_DU_OFS_TBADR 11'h0ff +`define OR1200_DU_OFS_TBIA 11'h1xx +`define OR1200_DU_OFS_TBIM 11'h2xx +`define OR1200_DU_OFS_TBAR 11'h3xx +`define OR1200_DU_OFS_TBTS 11'h4xx + +// Position of offset bits inside SPR address +`define OR1200_DUOFS_BITS 10:0 + +// Define if you want these DU registers to be implemented +`define OR1200_DU_DMR1 +`define OR1200_DU_DMR2 +`define OR1200_DU_DSR +`define OR1200_DU_DRR + +// DMR1 bits +`define OR1200_DU_DMR1_ST 22 + +// DSR bits +`define OR1200_DU_DSR_WIDTH 14 +`define OR1200_DU_DSR_RSTE 0 +`define OR1200_DU_DSR_BUSEE 1 +`define OR1200_DU_DSR_DPFE 2 +`define OR1200_DU_DSR_IPFE 3 +`define OR1200_DU_DSR_TTE 4 +`define OR1200_DU_DSR_AE 5 +`define OR1200_DU_DSR_IIE 6 +`define OR1200_DU_DSR_IE 7 +`define OR1200_DU_DSR_DME 8 +`define OR1200_DU_DSR_IME 9 +`define OR1200_DU_DSR_RE 10 +`define OR1200_DU_DSR_SCE 11 +`define OR1200_DU_DSR_BE 12 +`define OR1200_DU_DSR_TE 13 + +// DRR bits +`define OR1200_DU_DRR_RSTE 0 +`define OR1200_DU_DRR_BUSEE 1 +`define OR1200_DU_DRR_DPFE 2 +`define OR1200_DU_DRR_IPFE 3 +`define OR1200_DU_DRR_TTE 4 +`define OR1200_DU_DRR_AE 5 +`define OR1200_DU_DRR_IIE 6 +`define OR1200_DU_DRR_IE 7 +`define OR1200_DU_DRR_DME 8 +`define OR1200_DU_DRR_IME 9 +`define OR1200_DU_DRR_RE 10 +`define OR1200_DU_DRR_SCE 11 +`define OR1200_DU_DRR_BE 12 +`define OR1200_DU_DRR_TE 13 + +// Define if reading DU regs is allowed +`define OR1200_DU_READREGS + +// Define if unused DU registers bits should be zero +`define OR1200_DU_UNUSED_ZERO + +// DU operation commands +`define OR1200_DU_OP_READSPR 3'd4 +`define OR1200_DU_OP_WRITESPR 3'd5 + +// Define if IF/LSU status is not needed by devel i/f +`define OR1200_DU_STATUS_UNIMPLEMENTED + +///////////////////////////////////////////////////// +// +// Programmable Interrupt Controller (PIC) +// + +// Define it if you want PIC implemented +`define OR1200_PIC_IMPLEMENTED + +// Define number of interrupt inputs (2-31) +`define OR1200_PIC_INTS 20 + +// Address offsets of PIC registers inside PIC group +`define OR1200_PIC_OFS_PICMR 2'd0 +`define OR1200_PIC_OFS_PICSR 2'd2 + +// Position of offset bits inside SPR address +`define OR1200_PICOFS_BITS 1:0 + +// Define if you want these PIC registers to be implemented +`define OR1200_PIC_PICMR +`define OR1200_PIC_PICSR + +// Define if reading PIC registers is allowed +`define OR1200_PIC_READREGS + +// Define if unused PIC register bits should be zero +`define OR1200_PIC_UNUSED_ZERO + + +///////////////////////////////////////////////////// +// +// Tick Timer (TT) +// + +// Define it if you want TT implemented +`define OR1200_TT_IMPLEMENTED + +// Address offsets of TT registers inside TT group +`define OR1200_TT_OFS_TTMR 1'd0 +`define OR1200_TT_OFS_TTCR 1'd1 + +// Position of offset bits inside SPR group +`define OR1200_TTOFS_BITS 0 + +// Define if you want these TT registers to be implemented +`define OR1200_TT_TTMR +`define OR1200_TT_TTCR + +// TTMR bits +`define OR1200_TT_TTMR_TP 27:0 +`define OR1200_TT_TTMR_IP 28 +`define OR1200_TT_TTMR_IE 29 +`define OR1200_TT_TTMR_M 31:30 + +// Define if reading TT registers is allowed +`define OR1200_TT_READREGS + + +////////////////////////////////////////////// +// +// MAC +// +`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0 +`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable + + +////////////////////////////////////////////// +// +// Data MMU (DMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_DTLB_TM_ADDR 7 + +// +// DTLBMR fields +// +`define OR1200_DTLBMR_V_BITS 0 +`define OR1200_DTLBMR_CID_BITS 4:1 +`define OR1200_DTLBMR_RES_BITS 11:5 +`define OR1200_DTLBMR_VPN_BITS 31:13 + +// +// DTLBTR fields +// +`define OR1200_DTLBTR_CC_BITS 0 +`define OR1200_DTLBTR_CI_BITS 1 +`define OR1200_DTLBTR_WBC_BITS 2 +`define OR1200_DTLBTR_WOM_BITS 3 +`define OR1200_DTLBTR_A_BITS 4 +`define OR1200_DTLBTR_D_BITS 5 +`define OR1200_DTLBTR_URE_BITS 6 +`define OR1200_DTLBTR_UWE_BITS 7 +`define OR1200_DTLBTR_SRE_BITS 8 +`define OR1200_DTLBTR_SWE_BITS 9 +`define OR1200_DTLBTR_RES_BITS 11:10 +`define OR1200_DTLBTR_PPN_BITS 31:13 + +// +// DTLB configuration +// +`define OR1200_DMMU_PS 13 // 13 for 8KB page size +`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries +`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13 +`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19 +`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13 +`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12 +`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20 +`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20 +`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit +`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI + +// +// Cache inhibit while DMMU is not enabled/implemented +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !dcpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30] +// cache inhibited 2GB-4GB (default) dcpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_DMMU_CI dcpu_adr_i[31] + + +////////////////////////////////////////////// +// +// Insn MMU (IMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_ITLB_TM_ADDR 7 + +// +// ITLBMR fields +// +`define OR1200_ITLBMR_V_BITS 0 +`define OR1200_ITLBMR_CID_BITS 4:1 +`define OR1200_ITLBMR_RES_BITS 11:5 +`define OR1200_ITLBMR_VPN_BITS 31:13 + +// +// ITLBTR fields +// +`define OR1200_ITLBTR_CC_BITS 0 +`define OR1200_ITLBTR_CI_BITS 1 +`define OR1200_ITLBTR_WBC_BITS 2 +`define OR1200_ITLBTR_WOM_BITS 3 +`define OR1200_ITLBTR_A_BITS 4 +`define OR1200_ITLBTR_D_BITS 5 +`define OR1200_ITLBTR_SXE_BITS 6 +`define OR1200_ITLBTR_UXE_BITS 7 +`define OR1200_ITLBTR_RES_BITS 11:8 +`define OR1200_ITLBTR_PPN_BITS 31:13 + +// +// ITLB configuration +// +`define OR1200_IMMU_PS 13 // 13 for 8KB page size +`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries +`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13 +`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19 +`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13 +`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12 +`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20 +`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20 +`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit +`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI + +// +// Cache inhibit while IMMU is not enabled/implemented +// Note: all combinations that use icpu_adr_i cause async loop +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !icpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30] +// cache inhibited 2GB-4GB (default) icpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_IMMU_CI 1'b0 + + +///////////////////////////////////////////////// +// +// Insn cache (IC) +// + +// 3 for 8 bytes, 4 for 16 bytes etc +`define OR1200_ICLS 4 + +// +// IC configurations +// +`ifdef OR1200_IC_1W_4KB +`define OR1200_ICSIZE 12 // 4096 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8 +`define OR1200_ICTAG_W 21 +`endif +`ifdef OR1200_IC_1W_8KB +`define OR1200_ICSIZE 13 // 8192 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9 +`define OR1200_ICTAG_W 20 +`endif + + +///////////////////////////////////////////////// +// +// Data cache (DC) +// + +// 3 for 8 bytes, 4 for 16 bytes etc +`define OR1200_DCLS 4 + +// Define to perform store refill (potential performance penalty) +// `define OR1200_DC_STORE_REFILL + +// +// DC configurations +// +`ifdef OR1200_DC_1W_4KB +`define OR1200_DCSIZE 12 // 4096 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8 +`define OR1200_DCTAG_W 21 +`endif +`ifdef OR1200_DC_1W_8KB +`define OR1200_DCSIZE 13 // 8192 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9 +`define OR1200_DCTAG_W 20 +`endif + +///////////////////////////////////////////////// +// +// Store buffer (SB) +// + +// +// Store buffer +// +// It will improve performance by "caching" CPU stores +// using store buffer. This is most important for function +// prologues because DC can only work in write though mode +// and all stores would have to complete external WB writes +// to memory. +// Store buffer is between DC and data BIU. +// All stores will be stored into store buffer and immediately +// completed by the CPU, even though actual external writes +// will be performed later. As a consequence store buffer masks +// all data bus errors related to stores (data bus errors +// related to loads are delivered normally). +// All pending CPU loads will wait until store buffer is empty to +// ensure strict memory model. Right now this is necessary because +// we don't make destinction between cached and cache inhibited +// address space, so we simply empty store buffer until loads +// can begin. +// +// It makes design a bit bigger, depending what is the number of +// entries in SB FIFO. Number of entries can be changed further +// down. +// +//`define OR1200_SB_IMPLEMENTED + +// +// Number of store buffer entries +// +// Verified number of entries are 4 and 8 entries +// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must +// always match 2**OR1200_SB_LOG. +// To disable store buffer, undefine +// OR1200_SB_IMPLEMENTED. +// +`define OR1200_SB_LOG 2 // 2 or 3 +`define OR1200_SB_ENTRIES 4 // 4 or 8 Index: tags/rel_3/or1200/rtl/verilog/or1200_sb.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_sb.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_sb.v (revision 995) @@ -0,0 +1,193 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Store Buffer //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Implements store buffer. //// +//// //// +//// To Do: //// +//// - byte combining //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2002/08/18 19:53:08 lampret +// Added store buffer. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_sb( + // RISC clock, reset + clk, rst, + + // Internal RISC bus (DC<->SB) + dcsb_dat_i, dcsb_adr_i, dcsb_cyc_i, dcsb_stb_i, dcsb_we_i, dcsb_sel_i, dcsb_cab_i, + dcsb_dat_o, dcsb_ack_o, dcsb_err_o, + + // BIU bus + sbbiu_dat_o, sbbiu_adr_o, sbbiu_cyc_o, sbbiu_stb_o, sbbiu_we_o, sbbiu_sel_o, sbbiu_cab_o, + sbbiu_dat_i, sbbiu_ack_i, sbbiu_err_i +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_OPERAND_WIDTH; + +// +// RISC clock, reset +// +input clk; // RISC clock +input rst; // RISC reset + +// +// Internal RISC bus (DC<->SB) +// +input [dw-1:0] dcsb_dat_i; // input data bus +input [aw-1:0] dcsb_adr_i; // address bus +input dcsb_cyc_i; // WB cycle +input dcsb_stb_i; // WB strobe +input dcsb_we_i; // WB write enable +input dcsb_cab_i; // CAB input +input [3:0] dcsb_sel_i; // byte selects +output [dw-1:0] dcsb_dat_o; // output data bus +output dcsb_ack_o; // ack output +output dcsb_err_o; // err output + +// +// BIU bus +// +output [dw-1:0] sbbiu_dat_o; // output data bus +output [aw-1:0] sbbiu_adr_o; // address bus +output sbbiu_cyc_o; // WB cycle +output sbbiu_stb_o; // WB strobe +output sbbiu_we_o; // WB write enable +output sbbiu_cab_o; // CAB input +output [3:0] sbbiu_sel_o; // byte selects +input [dw-1:0] sbbiu_dat_i; // input data bus +input sbbiu_ack_i; // ack output +input sbbiu_err_i; // err output + +`ifdef OR1200_SB_IMPLEMENTED + +// +// Internal wires and regs +// +wire [4+dw+aw-1:0] fifo_dat_i; // FIFO data in +wire [4+dw+aw-1:0] fifo_dat_o; // FIFO data out +wire fifo_wr; +wire fifo_rd; +wire fifo_full; +wire fifo_empty; +wire sel_sb; +reg outstanding_store; +reg fifo_wr_ack; + +// +// FIFO data in/out +// +assign fifo_dat_i = {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i}; +assign {sbbiu_sel_o, sbbiu_dat_o, sbbiu_adr_o} = sel_sb ? fifo_dat_o : {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i}; + +// +// Control +// +assign fifo_wr = dcsb_cyc_i & dcsb_stb_i & dcsb_we_i & ~fifo_full & ~fifo_wr_ack; +assign fifo_rd = ~outstanding_store; +assign dcsb_dat_o = sbbiu_dat_i; +assign dcsb_ack_o = sel_sb ? fifo_wr_ack : sbbiu_ack_i; +assign dcsb_err_o = sel_sb ? 1'b0 : sbbiu_err_i; // SB never returns error +assign sbbiu_cyc_o = sel_sb ? outstanding_store : dcsb_cyc_i; +assign sbbiu_stb_o = sel_sb ? outstanding_store : dcsb_stb_i; +assign sbbiu_we_o = sel_sb ? 1'b1 : dcsb_we_i; +assign sbbiu_cab_o = sel_sb ? 1'b0 : dcsb_cab_i; +assign sel_sb = ~fifo_empty | (fifo_empty & outstanding_store); // | fifo_wr; + +// +// Store buffer FIFO instantiation +// +or1200_sb_fifo or1200_sb_fifo ( + .clk_i(clk), + .rst_i(rst), + .dat_i(fifo_dat_i), + .wr_i(fifo_wr), + .rd_i(fifo_rd), + .dat_o(fifo_dat_o), + .full_o(fifo_full), + .empty_o(fifo_empty) +); + +// +// fifo_rd +// +always @(posedge clk or posedge rst) + if (rst) + outstanding_store <= #1 1'b0; + else if (sbbiu_ack_i) + outstanding_store <= #1 1'b0; + else if (sel_sb | fifo_wr) + outstanding_store <= #1 1'b1; + +// +// fifo_wr_ack +// +always @(posedge clk or posedge rst) + if (rst) + fifo_wr_ack <= #1 1'b0; + else if (fifo_wr) + fifo_wr_ack <= #1 1'b1; + else + fifo_wr_ack <= #1 1'b0; + +`else // !OR1200_SB_IMPLEMENTED + +assign sbbiu_dat_o = dcsb_dat_i; +assign sbbiu_adr_o = dcsb_adr_i; +assign sbbiu_cyc_o = dcsb_cyc_i; +assign sbbiu_stb_o = dcsb_stb_i; +assign sbbiu_we_o = dcsb_we_i; +assign sbbiu_cab_o = dcsb_cab_i; +assign sbbiu_sel_o = dcsb_sel_i; +assign dcsb_dat_o = sbbiu_dat_i; +assign dcsb_ack_o = sbbiu_ack_i; +assign dcsb_err_o = sbbiu_err_i; + +`endif + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_sb_fifo.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_sb_fifo.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_sb_fifo.v (revision 995) @@ -0,0 +1,141 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Store Buffer FIFO //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Implementation of store buffer FIFO. //// +//// //// +//// To Do: //// +//// - N/A //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2002/08/18 19:53:08 lampret +// Added store buffer. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_sb_fifo( + clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o +); + +parameter dw = 68; +parameter fw = `OR1200_SB_LOG; +parameter fl = `OR1200_SB_ENTRIES; + +// +// FIFO signals +// +input clk_i; // Clock +input rst_i; // Reset +input [dw-1:0] dat_i; // Input data bus +input wr_i; // Write request +input rd_i; // Read request +output dat_o; // Output data bus +output full_o; // FIFO full +output empty_o;// FIFO empty + +// +// Internal regs +// +reg [dw:0] mem [fl-1:0]; +reg [dw-1:0] dat_o; +reg [fw+1:0] cntr; +reg [fw-1:0] wr_pntr; +reg [fw-1:0] rd_pntr; +reg empty_o; +reg full_o; + +always @(posedge clk_i or posedge rst_i) + if (rst_i) begin + full_o <= #1 1'b0; + empty_o <= #1 1'b1; + wr_pntr <= #1 {fw{1'b0}}; + rd_pntr <= #1 {fw{1'b0}}; + cntr <= #1 {fw+2{1'b0}}; + dat_o <= #1 {dw{1'b0}}; + end + else if (wr_i && rd_i) begin // FIFO Read and Write + mem[wr_pntr] <= #1 dat_i; + if (wr_pntr >= fl-1) + wr_pntr <= #1 {fw{1'b0}}; + else + wr_pntr <= #1 wr_pntr + 1'b1; + if (empty_o) begin + dat_o <= #1 dat_i; + end + else begin + dat_o <= #1 mem[rd_pntr]; + end + if (rd_pntr >= fl-1) + rd_pntr <= #1 {fw{1'b0}}; + else + rd_pntr <= #1 rd_pntr + 1'b1; + end + else if (wr_i && !full_o) begin // FIFO Write + mem[wr_pntr] <= #1 dat_i; + cntr <= #1 cntr + 1'b1; + empty_o <= #1 1'b0; + if (cntr >= (fl-1)) begin + full_o <= #1 1'b1; + cntr <= #1 fl; + end + if (wr_pntr >= fl-1) + wr_pntr <= #1 {fw{1'b0}}; + else + wr_pntr <= #1 wr_pntr + 1'b1; + end + else if (rd_i && !empty_o) begin // FIFO Read + dat_o <= #1 mem[rd_pntr]; + cntr <= #1 cntr - 1'b1; + full_o <= #1 1'b0; + if (cntr <= 1) begin + empty_o <= #1 1'b1; + cntr <= #1 {fw+2{1'b0}}; + end + if (rd_pntr >= fl-1) + rd_pntr <= #1 {fw{1'b0}}; + else + rd_pntr <= #1 rd_pntr + 1'b1; + end + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_except.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_except.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_except.v (revision 995) @@ -0,0 +1,574 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Exception logic //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Handles all OR1K exceptions inside CPU block. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.11 2002/08/18 19:54:28 lampret +// Added store buffer. +// +// Revision 1.10 2002/07/14 22:17:17 lampret +// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. +// +// Revision 1.9 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.8 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.7 2002/01/23 07:52:36 lampret +// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. +// +// Revision 1.6 2002/01/18 14:21:43 lampret +// Fixed 'the NPC single-step fix'. +// +// Revision 1.5 2002/01/18 07:56:00 lampret +// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. +// +// Revision 1.4 2002/01/14 21:11:50 lampret +// Changed alignment exception EPCR. Not tested yet. +// +// Revision 1.3 2002/01/14 19:09:57 lampret +// Fixed order of syscall and range exceptions. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.15 2001/11/27 23:13:11 lampret +// Fixed except_stop width and fixed EX PC for 1400444f no-ops. +// +// Revision 1.14 2001/11/23 08:38:51 lampret +// Changed DSR/DRR behavior and exception detection. +// +// Revision 1.13 2001/11/20 18:46:15 simons +// Break point bug fixed +// +// Revision 1.12 2001/11/18 09:58:28 lampret +// Fixed some l.trap typos. +// +// Revision 1.11 2001/11/18 08:36:28 lampret +// For GDB changed single stepping and disabled trap exception. +// +// Revision 1.10 2001/11/13 10:02:21 lampret +// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) +// +// Revision 1.9 2001/11/10 03:43:57 lampret +// Fixed exceptions. +// +// Revision 1.8 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.7 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +`define OR1200_EXCEPTFSM_WIDTH 3 +`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0 +`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1 +`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2 +`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3 +`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4 +`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5 + +// +// Exception recognition and sequencing +// + +module or1200_except( + // Clock and reset + clk, rst, + + // Internal i/f + sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault, + sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick, + branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall, + if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start, + except_started, except_stop, ex_void, + spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear, + esr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i +); + +// +// I/O +// +input clk; +input rst; +input sig_ibuserr; +input sig_dbuserr; +input sig_illegal; +input sig_align; +input sig_range; +input sig_dtlbmiss; +input sig_dmmufault; +input sig_int; +input sig_syscall; +input sig_trap; +input sig_itlbmiss; +input sig_immufault; +input sig_tick; +input branch_taken; +input genpc_freeze; +input id_freeze; +input ex_freeze; +input wb_freeze; +input if_stall; +input [31:0] if_pc; +output [31:2] lr_sav; +input [31:0] datain; +input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; +input epcr_we; +input eear_we; +input esr_we; +input pc_we; +output [31:0] epcr; +output [31:0] eear; +output [`OR1200_SR_WIDTH-1:0] esr; +input [`OR1200_SR_WIDTH-1:0] sr; +input [31:0] lsu_addr; +output flushpipe; +output extend_flush; +output [`OR1200_EXCEPT_WIDTH-1:0] except_type; +output except_start; +output except_started; +output [12:0] except_stop; +input ex_void; +output [31:0] spr_dat_ppc; +output [31:0] spr_dat_npc; +output abort_ex; +input icpu_ack_i; +input icpu_err_i; +input dcpu_ack_i; +input dcpu_err_i; + +// +// Internal regs and wires +// +reg [`OR1200_EXCEPT_WIDTH-1:0] except_type; +reg [31:0] id_pc; +reg [31:0] ex_pc; +reg [31:0] wb_pc; +reg [31:0] epcr; +reg [31:0] eear; +reg [`OR1200_SR_WIDTH-1:0] esr; +reg [2:0] id_exceptflags; +reg [2:0] ex_exceptflags; +reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state; +reg extend_flush; +reg extend_flush_last; +reg ex_dslot; +reg delayed1_ex_dslot; +reg delayed2_ex_dslot; +wire except_started; +wire [12:0] except_trig; +wire except_flushpipe; +reg [2:0] delayed_iee; +reg [2:0] delayed_tee; +wire int_pending; +wire tick_pending; + +// +// Simple combinatorial logic +// +assign except_started = extend_flush & except_start; +assign lr_sav = ex_pc[31:2]; +assign spr_dat_ppc = wb_pc; +assign spr_dat_npc = ex_void ? id_pc : ex_pc; +//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan +assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush; +assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot; +//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot; // works with uclinux. except_test fails +//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot; // works with uclinux, except_tets almost works (priority fails) +assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot; +assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal; // Abort write into RF by load & other instructions + +// +// Order defines exception detection priority +// +assign except_trig = { + tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE], + int_pending & ~du_dsr[`OR1200_DU_DSR_IE], + ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME], + ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE], + ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE], + sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE], + sig_align & ~du_dsr[`OR1200_DU_DSR_AE], + sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME], + sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE], + sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE], + sig_range & ~du_dsr[`OR1200_DU_DSR_RE], + sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze, + sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze + }; +assign except_stop = { + tick_pending & du_dsr[`OR1200_DU_DSR_TTE], + int_pending & du_dsr[`OR1200_DU_DSR_IE], + ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME], + ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE], + ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE], + sig_illegal & du_dsr[`OR1200_DU_DSR_IIE], + sig_align & du_dsr[`OR1200_DU_DSR_AE], + sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME], + sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE], + sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE], + sig_range & du_dsr[`OR1200_DU_DSR_RE], + sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze, + sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze + }; + +// +// PC and Exception flags pipelines +// +always @(posedge clk or posedge rst) begin + if (rst) begin + id_pc <= #1 32'd0; + id_exceptflags <= #1 3'b000; + end + else if (flushpipe) begin + id_pc <= #1 32'h0000_0000; + id_exceptflags <= #1 3'b000; + end + else if (!id_freeze) begin + id_pc <= #1 if_pc; + id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault }; + end +end + +// +// delayed_iee +// +// SR[IEE] should not enable interrupts right away +// when it is restored with l.rfe. Instead delayed_iee +// together with SR[IEE] enables interrupts once +// pipeline is again ready. +// +always @(posedge rst or posedge clk) + if (rst) + delayed_iee <= #1 3'b000; + else if (!sr[`OR1200_SR_IEE]) + delayed_iee <= #1 3'b000; + else + delayed_iee <= #1 {delayed_iee[1:0], 1'b1}; + +// +// delayed_tee +// +// SR[TEE] should not enable tick exceptions right away +// when it is restored with l.rfe. Instead delayed_tee +// together with SR[TEE] enables tick exceptions once +// pipeline is again ready. +// +always @(posedge rst or posedge clk) + if (rst) + delayed_tee <= #1 3'b000; + else if (!sr[`OR1200_SR_TEE]) + delayed_tee <= #1 3'b000; + else + delayed_tee <= #1 {delayed_tee[1:0], 1'b1}; + +// +// PC and Exception flags pipelines +// +always @(posedge clk or posedge rst) begin + if (rst) begin + ex_dslot <= #1 1'b0; + ex_pc <= #1 32'd0; + ex_exceptflags <= #1 3'b000; + delayed1_ex_dslot <= #1 1'b0; + delayed2_ex_dslot <= #1 1'b0; + end + else if (flushpipe) begin + ex_dslot <= #1 1'b0; + ex_pc <= #1 32'h0000_0000; + ex_exceptflags <= #1 3'b000; + delayed1_ex_dslot <= #1 1'b0; + delayed2_ex_dslot <= #1 1'b0; + end + else if (!ex_freeze & id_freeze) begin + ex_dslot <= #1 1'b0; + ex_pc <= #1 id_pc; + ex_exceptflags <= #1 3'b000; + delayed1_ex_dslot <= #1 ex_dslot; + delayed2_ex_dslot <= #1 delayed1_ex_dslot; + end + else if (!ex_freeze) begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("%t: ex_pc <= %h", $time, id_pc); +// synopsys translate_on +`endif + ex_dslot <= #1 branch_taken; + ex_pc <= #1 id_pc; + ex_exceptflags <= #1 id_exceptflags; + delayed1_ex_dslot <= #1 ex_dslot; + delayed2_ex_dslot <= #1 delayed1_ex_dslot; + end +end + +// +// PC and Exception flags pipelines +// +always @(posedge clk or posedge rst) begin + if (rst) begin + wb_pc <= #1 32'd0; + end + else if (!wb_freeze) begin + wb_pc <= #1 ex_pc; + end +end + +// +// Flush pipeline +// +assign flushpipe = except_flushpipe | pc_we | extend_flush; + +// +// We have started execution of exception handler: +// 1. Asserted for 3 clock cycles +// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler +// +assign except_flushpipe = |except_trig & !state; + +// +// Exception FSM that sequences execution of exception handler +// +// except_type signals which exception handler we start fetching in: +// 1. Asserted in next clock cycle after exception is recognized +// +always @(posedge clk or posedge rst) begin + if (rst) begin + state <= #1 `OR1200_EXCEPTFSM_IDLE; + except_type <= #1 `OR1200_EXCEPT_NONE; + extend_flush <= #1 1'b0; + epcr <= #1 32'b0; + eear <= #1 32'b0; + esr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1}; + extend_flush_last <= #1 1'b0; + end + else begin + case (state) // synopsys full_case parallel_case + `OR1200_EXCEPTFSM_IDLE: + if (except_flushpipe) begin + state <= #1 `OR1200_EXCEPTFSM_FLU1; + extend_flush <= #1 1'b1; + if (ex_dslot) begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display(" INFO: Exception during first delay slot instruction."); +// synopsys translate_on +`endif + end + else if (delayed1_ex_dslot) begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display(" INFO: Exception during second (NOP) delay slot instruction."); +// synopsys translate_on +`endif + end + else if (delayed2_ex_dslot) begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN)."); +// synopsys translate_on +`endif + end + else begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display(" INFO: Exception during normal (no delay slot) instruction."); +// synopsys translate_on +`endif + end + + esr <= #1 sr; + casex (except_trig) + 13'b1_xxxx_xxxx_xxxx: begin + except_type <= #1 `OR1200_EXCEPT_TICK; + epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + end + 13'b0_1xxx_xxxx_xxxx: begin + except_type <= #1 `OR1200_EXCEPT_INT; + epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + end + 13'b0_01xx_xxxx_xxxx: begin + except_type <= #1 `OR1200_EXCEPT_ITLBMISS; +// +// itlb miss exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?) +// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; +// mmu-icdc-O2 ex_pc only OK when no ex_dslot eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; +// mmu-icdc-O2 ex_pc only OK when no ex_dslot epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + eear <= #1 ex_dslot ? ex_pc : ex_pc; + epcr <= #1 ex_dslot ? wb_pc : ex_pc; +// eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; +// epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + end + 13'b0_001x_xxxx_xxxx: begin + except_type <= #1 `OR1200_EXCEPT_IPF; +// +// ipf exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?) +// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + end + 13'b0_0001_xxxx_xxxx: begin + except_type <= #1 `OR1200_EXCEPT_BUSERR; + eear <= #1 ex_dslot ? wb_pc : ex_pc; + epcr <= #1 ex_dslot ? wb_pc : ex_pc; + end + 13'b0_0000_1xxx_xxxx: begin + except_type <= #1 `OR1200_EXCEPT_ILLEGAL; + eear <= #1 ex_pc; + epcr <= #1 ex_dslot ? wb_pc : ex_pc; + end + 13'b0_0000_01xx_xxxx: begin + except_type <= #1 `OR1200_EXCEPT_ALIGN; + eear <= #1 lsu_addr; + epcr <= #1 ex_dslot ? wb_pc : ex_pc; + end + 13'b0_0000_001x_xxxx: begin + except_type <= #1 `OR1200_EXCEPT_DTLBMISS; + eear <= #1 lsu_addr; + epcr <= #1 ex_dslot ? wb_pc : ex_pc; + end + 13'b0_0000_0001_xxxx: begin + except_type <= #1 `OR1200_EXCEPT_DPF; + eear <= #1 lsu_addr; + epcr <= #1 ex_dslot ? wb_pc : ex_pc; + end + 13'b0_0000_0000_1xxx: begin // Data Bus Error + except_type <= #1 `OR1200_EXCEPT_BUSERR; + eear <= #1 lsu_addr; + epcr <= #1 ex_dslot ? wb_pc : ex_pc; + end + 13'b0_0000_0000_01xx: begin + except_type <= #1 `OR1200_EXCEPT_RANGE; + epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + end + 13'b0_0000_0000_001x: begin + except_type <= #1 `OR1200_EXCEPT_TRAP; + epcr <= #1 ex_dslot ? wb_pc : ex_pc; + end + 13'b0_0000_0000_0001: begin + except_type <= #1 `OR1200_EXCEPT_SYSCALL; + epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + end + default: + except_type <= #1 `OR1200_EXCEPT_NONE; + endcase + end + else if (pc_we) begin + state <= #1 `OR1200_EXCEPTFSM_FLU1; + extend_flush <= #1 1'b1; + end + else begin + if (epcr_we) + epcr <= #1 datain; + if (eear_we) + eear <= #1 datain; + if (esr_we) + esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]}; + end + `OR1200_EXCEPTFSM_FLU1: + if (icpu_ack_i | icpu_err_i | genpc_freeze) +// if (!if_stall | genpc_freeze) + state <= #1 `OR1200_EXCEPTFSM_FLU2; + `OR1200_EXCEPTFSM_FLU2: + if (except_type == `OR1200_EXCEPT_TRAP) begin + state <= #1 `OR1200_EXCEPTFSM_IDLE; + extend_flush <= #1 1'b0; + extend_flush_last <= #1 1'b0; + except_type <= #1 `OR1200_EXCEPT_NONE; + end + else +// if (!if_stall & !id_freeze) + state <= #1 `OR1200_EXCEPTFSM_FLU3; + `OR1200_EXCEPTFSM_FLU3: +// if (!if_stall && !id_freeze) + begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + if (except_flushpipe) + $display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr); +// synopsys translate_on +`endif + state <= #1 `OR1200_EXCEPTFSM_FLU4; + end + `OR1200_EXCEPTFSM_FLU4: begin + state <= #1 `OR1200_EXCEPTFSM_FLU5; + extend_flush <= #1 1'b0; + extend_flush_last <= #1 1'b0; // damjan + end + `OR1200_EXCEPTFSM_FLU5: begin + if (!if_stall && !id_freeze) begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display(" INFO: Just finished flushing pipeline."); +// synopsys translate_on +`endif + state <= #1 `OR1200_EXCEPTFSM_IDLE; + except_type <= #1 `OR1200_EXCEPT_NONE; + extend_flush_last <= #1 1'b0; + end + end + endcase + end +end + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_immu_top.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_immu_top.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_immu_top.v (revision 995) @@ -0,0 +1,372 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Instruction MMU top level //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instantiation of all IMMU blocks. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.8 2002/08/14 06:23:50 lampret +// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. +// +// Revision 1.7 2002/08/12 05:31:30 lampret +// Delayed external access at page crossing. +// +// Revision 1.6 2002/03/29 15:16:56 lampret +// Some of the warnings fixed. +// +// Revision 1.5 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.4 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.3 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.6 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.5 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.1 2001/08/17 08:03:35 lampret +// *** empty log message *** +// +// Revision 1.2 2001/07/22 03:31:53 lampret +// Fixed RAM's oen bug. Cache bypass under development. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +// +// Insn MMU +// + +module or1200_immu_top( + // Rst and clk + clk, rst, + + // CPU i/f + ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i, + icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o, + + // SPR access + spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, + + // IC i/f + icimmu_rty_i, icimmu_err_i, icimmu_tag_i, icimmu_adr_o, icimmu_cycstb_o, icimmu_ci_o +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_OPERAND_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// CPU I/F +// +input ic_en; +input immu_en; +input supv; +input [aw-1:0] icpu_adr_i; +input icpu_cycstb_i; +output [aw-1:0] icpu_adr_o; +output [3:0] icpu_tag_o; +output icpu_rty_o; +output icpu_err_o; + +// +// SPR access +// +input spr_cs; +input spr_write; +input [aw-1:0] spr_addr; +input [31:0] spr_dat_i; +output [31:0] spr_dat_o; + +// +// IC I/F +// +input icimmu_rty_i; +input icimmu_err_i; +input [3:0] icimmu_tag_i; +output [aw-1:0] icimmu_adr_o; +output icimmu_cycstb_o; +output icimmu_ci_o; + +// +// Internal wires and regs +// +wire itlb_spr_access; +wire [31:`OR1200_IMMU_PS] itlb_ppn; +wire itlb_hit; +wire itlb_uxe; +wire itlb_sxe; +wire [31:0] itlb_dat_o; +wire itlb_en; +wire itlb_ci; +wire itlb_done; +wire fault; +wire miss; +wire page_cross; +reg [31:0] icpu_adr_o; +`ifdef OR1200_NO_IMMU +`else +reg itlb_en_r; +reg dis_spr_access; +reg [31:`OR1200_IMMU_PS] icpu_vpn_r; +`endif + +// +// Implemented bits inside match and translate registers +// +// itlbwYmrX: vpn 31-10 v 0 +// itlbwYtrX: ppn 31-10 uxe 7 sxe 6 +// +// itlb memory width: +// 19 bits for ppn +// 13 bits for vpn +// 1 bit for valid +// 2 bits for protection +// 1 bit for cache inhibit + +// +// icpu_adr_o +// +`ifdef OR1200_REGISTERED_OUTPUTS +always @(posedge rst or posedge clk) + if (rst) + icpu_adr_o <= #1 32'h0000_0100; + else + icpu_adr_o <= #1 icpu_adr_i; +`else +Unsupported !!! +`endif + +`ifdef OR1200_NO_IMMU + +// +// Put all outputs in inactive state +// +assign spr_dat_o = 32'h00000000; +assign icimmu_adr_o = icpu_adr_i; +assign icpu_tag_o = icimmu_tag_i; +assign icimmu_cycstb_o = icpu_cycstb_i; +assign icpu_rty_o = icimmu_rty_i; +assign icpu_err_o = icimmu_err_i; +assign icimmu_ci_o = `OR1200_IMMU_CI; + +`else + +// +// ITLB SPR access +// +// 1200 - 12FF itlbmr w0 +// 1200 - 123F itlbmr w0 [63:0] +// +// 1300 - 13FF itlbtr w0 +// 1300 - 133F itlbtr w0 [63:0] +// +assign itlb_spr_access = spr_cs & ~dis_spr_access; + +// +// Disable ITLB SPR access +// +// This flop is used to mask ITLB miss/fault exception +// during first clock cycle of accessing ITLB SPR. In +// subsequent clock cycles it is assumed that ITLB SPR +// access was accomplished and that normal instruction fetching +// can proceed. +// +// spr_cs sets dis_spr_access and icpu_rty_o clears it. +// +always @(posedge clk or posedge rst) + if (rst) + dis_spr_access <= #1 1'b0; + else if (!icpu_rty_o) + dis_spr_access <= #1 1'b0; + else if (spr_cs) + dis_spr_access <= #1 1'b1; + +// +// Tags: +// +// OR1200_DTAG_TE - TLB miss Exception +// OR1200_DTAG_PE - Page fault Exception +// +assign icpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : icimmu_tag_i; + +// +// icpu_rty_o +// +// assign icpu_rty_o = !icpu_err_o & icimmu_rty_i; +assign icpu_rty_o = icimmu_rty_i | itlb_spr_access & immu_en; + +// +// icpu_err_o +// +assign icpu_err_o = miss | fault | icimmu_err_i; + +// +// Assert itlb_en_r after one clock cycle and when there is no +// ITLB SPR access +// +always @(posedge clk or posedge rst) + if (rst) + itlb_en_r <= #1 1'b0; + else + itlb_en_r <= #1 itlb_en & ~itlb_spr_access; + +// +// ITLB lookup successful +// +assign itlb_done = itlb_en_r & ~page_cross; + +// +// Cut transfer if something goes wrong with translation. If IC is disabled, +// use delayed signals. +// +// assign icimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL +assign icimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross; + +// +// Cache Inhibit +// +assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI; + +// +// Page cross +// +// Asserted when CPU address crosses page boundary. Most of the time it is zero. +// +assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r; + +// +// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come +// one clock cycle after offset part. +// +always @(posedge clk or posedge rst) + if (rst) + icpu_vpn_r <= #1 {31-`OR1200_IMMU_PS{1'b0}}; + else + icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS]; + +// +// Physical address is either translated virtual address or +// simply equal when IMMU is disabled +// +assign icimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en + +// +// Output to SPRS unit +// +assign spr_dat_o = spr_cs ? itlb_dat_o : 32'h00000000; + +// +// Page fault exception logic +// +assign fault = itlb_done & + ( (!supv & !itlb_uxe) // Execute in user mode not enabled + || (supv & !itlb_sxe)); // Execute in supv mode not enabled + +// +// TLB Miss exception logic +// +assign miss = itlb_done & !itlb_hit; + +// +// ITLB Enable +// +assign itlb_en = immu_en & icpu_cycstb_i; + +// +// Instantiation of ITLB +// +or1200_immu_tlb or1200_immu_tlb( + // Rst and clk + .clk(clk), + .rst(rst), + + // I/F for translation + .tlb_en(itlb_en), + .vaddr(icpu_adr_i), + .hit(itlb_hit), + .ppn(itlb_ppn), + .uxe(itlb_uxe), + .sxe(itlb_sxe), + .ci(itlb_ci), + + // SPR access + .spr_cs(itlb_spr_access), + .spr_write(spr_write), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_i), + .spr_dat_o(itlb_dat_o) +); + +`endif + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_dc_top.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_dc_top.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_dc_top.v (revision 995) @@ -0,0 +1,294 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Data Cache top level //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instantiation of all DC blocks. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.4 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.3 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.10 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.9 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:35 igorm +// no message +// +// Revision 1.4 2001/08/13 03:36:20 lampret +// Added cfg regs. Moved all defines into one defines.v file. More cleanup. +// +// Revision 1.3 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/22 03:31:53 lampret +// Fixed RAM's oen bug. Cache bypass under development. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +// +// Data cache +// +module or1200_dc_top( + // Rst, clk and clock control + clk, rst, + + // External i/f + dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o, dcsb_cab_o, + dcsb_dat_i, dcsb_ack_i, dcsb_err_i, + + // Internal i/f + dc_en, + dcdmmu_adr_i, dcdmmu_cycstb_i, dcdmmu_ci_i, + dcpu_we_i, dcpu_sel_i, dcpu_tag_i, dcpu_dat_i, + dcpu_dat_o, dcpu_ack_o, dcpu_rty_o, dcdmmu_err_o, dcdmmu_tag_o, + + // SPRs + spr_cs, spr_write, spr_dat_i +); + +parameter dw = `OR1200_OPERAND_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// External I/F +// +output [dw-1:0] dcsb_dat_o; +output [31:0] dcsb_adr_o; +output dcsb_cyc_o; +output dcsb_stb_o; +output dcsb_we_o; +output [3:0] dcsb_sel_o; +output dcsb_cab_o; +input [dw-1:0] dcsb_dat_i; +input dcsb_ack_i; +input dcsb_err_i; + +// +// Internal I/F +// +input dc_en; +input [31:0] dcdmmu_adr_i; +input dcdmmu_cycstb_i; +input dcdmmu_ci_i; +input dcpu_we_i; +input [3:0] dcpu_sel_i; +input [3:0] dcpu_tag_i; +input [dw-1:0] dcpu_dat_i; +output [dw-1:0] dcpu_dat_o; +output dcpu_ack_o; +output dcpu_rty_o; +output dcdmmu_err_o; +output [3:0] dcdmmu_tag_o; + +// +// SPR access +// +input spr_cs; +input spr_write; +input [31:0] spr_dat_i; + +// +// Internal wires and regs +// +wire tag_v; +wire [`OR1200_DCTAG_W-2:0] tag; +wire [dw-1:0] to_dcram; +wire [dw-1:0] from_dcram; +wire [31:0] saved_addr; +wire [3:0] dcram_we; +wire dctag_we; +wire [31:0] dc_addr; +wire dcfsm_biu_read; +wire dcfsm_biu_write; +reg tagcomp_miss; +wire [`OR1200_DCINDXH:`OR1200_DCLS] dctag_addr; +wire dctag_en; +wire dctag_v; +wire dc_inv; +wire dcfsm_first_hit_ack; +wire dcfsm_first_miss_ack; +wire dcfsm_first_miss_err; +wire dcfsm_burst; +wire dcfsm_tag_we; + +// +// Simple assignments +// +assign dcsb_adr_o = dc_addr; +assign dc_inv = spr_cs & spr_write; +assign dctag_we = dcfsm_tag_we | dc_inv; +assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS]; +assign dctag_en = dc_inv | dc_en; +assign dctag_v = ~dc_inv; + +// +// Data to BIU is from DCRAM when DC is enabled or from LSU when +// DC is disabled +// +assign dcsb_dat_o = dcpu_dat_i; + +// +// Bypases of the DC when DC is disabled +// +assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i; +assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i; +assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i; +assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcdmmu_ci_i) ? 4'b1111 : dcpu_sel_i; +assign dcsb_cab_o = (dc_en) ? dcfsm_burst : 1'b0; +assign dcpu_rty_o = ~dcpu_ack_o; +assign dcdmmu_tag_o = dcdmmu_err_o ? `OR1200_DTAG_BE : dcpu_tag_i; + +// +// DC/LSU normal and error termination +// +assign dcpu_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i; +assign dcdmmu_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i; + +// +// Select between claddr generated by DC FSM and addr[3:2] generated by LSU +// +//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcdmmu_adr_i; + +// +// Select between input data generated by LSU or by BIU +// +assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcpu_dat_i; + +// +// Select between data generated by DCRAM or passed by BIU +// +assign dcpu_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram; + +// +// Tag comparison +// +always @(tag or saved_addr or tag_v) begin + if ((tag != saved_addr[31:`OR1200_DCTAGL]) || !tag_v) + tagcomp_miss = 1'b1; + else + tagcomp_miss = 1'b0; +end + +// +// Instantiation of DC Finite State Machine +// +or1200_dc_fsm or1200_dc_fsm( + .clk(clk), + .rst(rst), + .dc_en(dc_en), + .dcdmmu_cycstb_i(dcdmmu_cycstb_i), + .dcdmmu_ci_i(dcdmmu_ci_i), + .dcpu_we_i(dcpu_we_i), + .dcpu_sel_i(dcpu_sel_i), + .tagcomp_miss(tagcomp_miss), + .biudata_valid(dcsb_ack_i), + .biudata_error(dcsb_err_i), + .start_addr(dcdmmu_adr_i), + .saved_addr(saved_addr), + .dcram_we(dcram_we), + .biu_read(dcfsm_biu_read), + .biu_write(dcfsm_biu_write), + .first_hit_ack(dcfsm_first_hit_ack), + .first_miss_ack(dcfsm_first_miss_ack), + .first_miss_err(dcfsm_first_miss_err), + .burst(dcfsm_burst), + .tag_we(dcfsm_tag_we), + .dc_addr(dc_addr) +); + +// +// Instantiation of DC main memory +// +or1200_dc_ram or1200_dc_ram( + .clk(clk), + .rst(rst), + .addr(dc_addr[`OR1200_DCINDXH:2]), + .en(dc_en), + .we(dcram_we), + .datain(to_dcram), + .dataout(from_dcram) +); + +// +// Instantiation of DC TAG memory +// +or1200_dc_tag or1200_dc_tag( + .clk(clk), + .rst(rst), + .addr(dctag_addr), + .en(dctag_en), + .we(dctag_we), + .datain({dc_addr[31:`OR1200_DCTAGL], dctag_v}), + .tag_v(tag_v), + .tag(tag) +); + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_top.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_top.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_top.v (revision 995) @@ -0,0 +1,798 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200 Top Level //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// OR1200 Top Level //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.7 2002/07/14 22:17:17 lampret +// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. +// +// Revision 1.6 2002/03/29 15:16:56 lampret +// Some of the warnings fixed. +// +// Revision 1.5 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.4 2002/02/01 19:56:55 lampret +// Fixed combinational loops. +// +// Revision 1.3 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.2 2002/01/18 07:56:00 lampret +// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.13 2001/11/23 08:38:51 lampret +// Changed DSR/DRR behavior and exception detection. +// +// Revision 1.12 2001/11/20 00:57:22 lampret +// Fixed width of du_except. +// +// Revision 1.11 2001/11/18 08:36:28 lampret +// For GDB changed single stepping and disabled trap exception. +// +// Revision 1.10 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.9 2001/10/14 13:12:10 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:35 igorm +// no message +// +// Revision 1.4 2001/08/13 03:36:20 lampret +// Added cfg regs. Moved all defines into one defines.v file. More cleanup. +// +// Revision 1.3 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/22 03:31:54 lampret +// Fixed RAM's oen bug. Cache bypass under development. +// +// Revision 1.1 2001/07/20 00:46:21 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_top( + // System + clk_i, rst_i, pic_ints_i, clmode_i, + + // Instruction WISHBONE INTERFACE + iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i, + iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_cab_o, iwb_dat_o, + + // Data WISHBONE INTERFACE + dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i, + dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_cab_o, dwb_dat_o, + + // External Debug Interface + dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i, + dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o, + + // Power Management + pm_cpustall_i, + pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o, + pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o + +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_OPERAND_WIDTH; +parameter ppic_ints = `OR1200_PIC_INTS; + +// +// I/O +// + +// +// System +// +input clk_i; +input rst_i; +input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4 +input [ppic_ints-1:0] pic_ints_i; + +// +// Instruction WISHBONE interface +// +input iwb_clk_i; // clock input +input iwb_rst_i; // reset input +input iwb_ack_i; // normal termination +input iwb_err_i; // termination w/ error +input iwb_rty_i; // termination w/ retry +input [dw-1:0] iwb_dat_i; // input data bus +output iwb_cyc_o; // cycle valid output +output [aw-1:0] iwb_adr_o; // address bus outputs +output iwb_stb_o; // strobe output +output iwb_we_o; // indicates write transfer +output [3:0] iwb_sel_o; // byte select outputs +output iwb_cab_o; // indicates consecutive address burst +output [dw-1:0] iwb_dat_o; // output data bus + +// +// Data WISHBONE interface +// +input dwb_clk_i; // clock input +input dwb_rst_i; // reset input +input dwb_ack_i; // normal termination +input dwb_err_i; // termination w/ error +input dwb_rty_i; // termination w/ retry +input [dw-1:0] dwb_dat_i; // input data bus +output dwb_cyc_o; // cycle valid output +output [aw-1:0] dwb_adr_o; // address bus outputs +output dwb_stb_o; // strobe output +output dwb_we_o; // indicates write transfer +output [3:0] dwb_sel_o; // byte select outputs +output dwb_cab_o; // indicates consecutive address burst +output [dw-1:0] dwb_dat_o; // output data bus + +// +// External Debug Interface +// +input dbg_stall_i; // External Stall Input +input [dw-1:0] dbg_dat_i; // External Data Input +input [aw-1:0] dbg_adr_i; // External Address Input +input [2:0] dbg_op_i; // External Operation Select Input +input dbg_ewt_i; // External Watchpoint Trigger Input +output [3:0] dbg_lss_o; // External Load/Store Unit Status +output [1:0] dbg_is_o; // External Insn Fetch Status +output [10:0] dbg_wp_o; // Watchpoints Outputs +output dbg_bp_o; // Breakpoint Output +output [dw-1:0] dbg_dat_o; // External Data Output + +// +// Power Management +// +input pm_cpustall_i; +output [3:0] pm_clksd_o; +output pm_dc_gate_o; +output pm_ic_gate_o; +output pm_dmmu_gate_o; +output pm_immu_gate_o; +output pm_tt_gate_o; +output pm_cpu_gate_o; +output pm_wakeup_o; +output pm_lvolt_o; + + +// +// Internal wires and regs +// + +// +// DC to SB +// +wire [dw-1:0] dcsb_dat_dc; +wire [aw-1:0] dcsb_adr_dc; +wire dcsb_cyc_dc; +wire dcsb_stb_dc; +wire dcsb_we_dc; +wire [3:0] dcsb_sel_dc; +wire dcsb_cab_dc; +wire [dw-1:0] dcsb_dat_sb; +wire dcsb_ack_sb; +wire dcsb_err_sb; + +// +// SB to BIU +// +wire [dw-1:0] sbbiu_dat_sb; +wire [aw-1:0] sbbiu_adr_sb; +wire sbbiu_cyc_sb; +wire sbbiu_stb_sb; +wire sbbiu_we_sb; +wire [3:0] sbbiu_sel_sb; +wire sbbiu_cab_sb; +wire [dw-1:0] sbbiu_dat_biu; +wire sbbiu_ack_biu; +wire sbbiu_err_biu; + +// +// IC to BIU +// +wire [dw-1:0] icbiu_dat_ic; +wire [aw-1:0] icbiu_adr_ic; +wire icbiu_cyc_ic; +wire icbiu_stb_ic; +wire icbiu_we_ic; +wire [3:0] icbiu_sel_ic; +wire [3:0] icbiu_tag_ic; +wire [dw-1:0] icbiu_dat_biu; +wire icbiu_ack_biu; +wire icbiu_err_biu; +wire [3:0] icbiu_tag_biu; + +// +// CPU's SPR access to various RISC units (shared wires) +// +wire supv; +wire [aw-1:0] spr_addr; +wire [dw-1:0] spr_dat_cpu; +wire [31:0] spr_cs; +wire spr_we; + +// +// DMMU and CPU +// +wire dmmu_en; +wire [31:0] spr_dat_dmmu; + +// +// DMMU and DC +// +wire dcdmmu_err_dc; +wire [3:0] dcdmmu_tag_dc; +wire [aw-1:0] dcdmmu_adr_dmmu; +wire dcdmmu_cycstb_dmmu; +wire dcdmmu_ci_dmmu; + +// +// CPU and data memory subsystem +// +wire dc_en; +wire [31:0] dcpu_adr_cpu; +wire dcpu_we_cpu; +wire [3:0] dcpu_sel_cpu; +wire [3:0] dcpu_tag_cpu; +wire [31:0] dcpu_dat_cpu; +wire [31:0] dcpu_dat_dc; +wire dcpu_ack_dc; +wire dcpu_rty_dc; +wire dcpu_err_dmmu; +wire [3:0] dcpu_tag_dmmu; + +// +// IMMU and CPU +// +wire immu_en; +wire [31:0] spr_dat_immu; + +// +// CPU and insn memory subsystem +// +wire ic_en; +wire [31:0] icpu_adr_cpu; +wire icpu_cycstb_cpu; +wire [3:0] icpu_sel_cpu; +wire [3:0] icpu_tag_cpu; +wire [31:0] icpu_dat_ic; +wire icpu_ack_ic; +wire [31:0] icpu_adr_immu; +wire icpu_err_immu; +wire [3:0] icpu_tag_immu; + +// +// IMMU and IC +// +wire [aw-1:0] icimmu_adr_immu; +wire icimmu_rty_ic; +wire icimmu_err_ic; +wire [3:0] icimmu_tag_ic; +wire icimmu_cycstb_immu; +wire icimmu_ci_immu; + +// +// Connection between CPU and PIC +// +wire [dw-1:0] spr_dat_pic; +wire pic_wakeup; +wire sig_int; + +// +// Connection between CPU and PM +// +wire [dw-1:0] spr_dat_pm; + +// +// CPU and TT +// +wire [dw-1:0] spr_dat_tt; +wire sig_tick; + +// +// Debug port and caches/MMUs +// +wire [dw-1:0] spr_dat_du; +wire du_stall; +wire [dw-1:0] du_addr; +wire [dw-1:0] du_dat_du; +wire du_read; +wire du_write; +wire [12:0] du_except; +wire [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; +wire [dw-1:0] du_dat_cpu; + +wire ex_freeze; +wire [31:0] ex_insn; +wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +wire [31:0] spr_dat_npc; +wire [31:0] rf_dataw; + + +// +// Instantiation of Instruction WISHBONE BIU +// +or1200_wb_biu iwb_biu( + // RISC clk, rst and clock control + .clk(clk_i), + .rst(rst_i), + .clmode(clmode_i), + + // WISHBONE interface + .wb_clk_i(iwb_clk_i), + .wb_rst_i(iwb_rst_i), + .wb_ack_i(iwb_ack_i), + .wb_err_i(iwb_err_i), + .wb_rty_i(iwb_rty_i), + .wb_dat_i(iwb_dat_i), + .wb_cyc_o(iwb_cyc_o), + .wb_adr_o(iwb_adr_o), + .wb_stb_o(iwb_stb_o), + .wb_we_o(iwb_we_o), + .wb_sel_o(iwb_sel_o), + .wb_cab_o(iwb_cab_o), + .wb_dat_o(iwb_dat_o), + + // Internal RISC bus + .biu_dat_i(icbiu_dat_ic), + .biu_adr_i(icbiu_adr_ic), + .biu_cyc_i(icbiu_cyc_ic), + .biu_stb_i(icbiu_stb_ic), + .biu_we_i(icbiu_we_ic), + .biu_sel_i(icbiu_sel_ic), + .biu_cab_i(icbiu_cab_ic), + .biu_dat_o(icbiu_dat_biu), + .biu_ack_o(icbiu_ack_biu), + .biu_err_o(icbiu_err_biu) +); + +// +// Instantiation of Data WISHBONE BIU +// +or1200_wb_biu dwb_biu( + // RISC clk, rst and clock control + .clk(clk_i), + .rst(rst_i), + .clmode(clmode_i), + + // WISHBONE interface + .wb_clk_i(dwb_clk_i), + .wb_rst_i(dwb_rst_i), + .wb_ack_i(dwb_ack_i), + .wb_err_i(dwb_err_i), + .wb_rty_i(dwb_rty_i), + .wb_dat_i(dwb_dat_i), + .wb_cyc_o(dwb_cyc_o), + .wb_adr_o(dwb_adr_o), + .wb_stb_o(dwb_stb_o), + .wb_we_o(dwb_we_o), + .wb_sel_o(dwb_sel_o), + .wb_cab_o(dwb_cab_o), + .wb_dat_o(dwb_dat_o), + + // Internal RISC bus + .biu_dat_i(sbbiu_dat_sb), + .biu_adr_i(sbbiu_adr_sb), + .biu_cyc_i(sbbiu_cyc_sb), + .biu_stb_i(sbbiu_stb_sb), + .biu_we_i(sbbiu_we_sb), + .biu_sel_i(sbbiu_sel_sb), + .biu_cab_i(sbbiu_cab_sb), + .biu_dat_o(sbbiu_dat_biu), + .biu_ack_o(sbbiu_ack_biu), + .biu_err_o(sbbiu_err_biu) +); + +// +// Instantiation of IMMU +// +or1200_immu_top or1200_immu_top( + // Rst and clk + .clk(clk_i), + .rst(rst_i), + + // CPU i/f + .ic_en(ic_en), + .immu_en(immu_en), + .supv(supv), + .icpu_adr_i(icpu_adr_cpu), + .icpu_cycstb_i(icpu_cycstb_cpu), + .icpu_adr_o(icpu_adr_immu), + .icpu_tag_o(icpu_tag_immu), + .icpu_rty_o(icpu_rty_immu), + .icpu_err_o(icpu_err_immu), + + // SPR access + .spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]), + .spr_write(spr_we), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_cpu), + .spr_dat_o(spr_dat_immu), + + // IC i/f + .icimmu_rty_i(icimmu_rty_ic), + .icimmu_err_i(icimmu_err_ic), + .icimmu_tag_i(icimmu_tag_ic), + .icimmu_adr_o(icimmu_adr_immu), + .icimmu_cycstb_o(icimmu_cycstb_immu), + .icimmu_ci_o(icimmu_ci_immu) +); + +// +// Instantiation of Instruction Cache +// +or1200_ic_top or1200_ic_top( + .clk(clk_i), + .rst(rst_i), + + // IC and CPU/IMMU + .ic_en(ic_en), + .icimmu_adr_i(icimmu_adr_immu), + .icimmu_cycstb_i(icimmu_cycstb_immu), + .icimmu_ci_i(icimmu_ci_immu), + .icpu_sel_i(icpu_sel_cpu), + .icpu_tag_i(icpu_tag_cpu), + .icpu_dat_o(icpu_dat_ic), + .icpu_ack_o(icpu_ack_ic), + .icimmu_rty_o(icimmu_rty_ic), + .icimmu_err_o(icimmu_err_ic), + .icimmu_tag_o(icimmu_tag_ic), + + // SPR access + .spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]), + .spr_write(spr_we), + .spr_dat_i(spr_dat_cpu), + + // IC and BIU + .icbiu_dat_o(icbiu_dat_ic), + .icbiu_adr_o(icbiu_adr_ic), + .icbiu_cyc_o(icbiu_cyc_ic), + .icbiu_stb_o(icbiu_stb_ic), + .icbiu_we_o(icbiu_we_ic), + .icbiu_sel_o(icbiu_sel_ic), + .icbiu_cab_o(icbiu_cab_ic), + .icbiu_dat_i(icbiu_dat_biu), + .icbiu_ack_i(icbiu_ack_biu), + .icbiu_err_i(icbiu_err_biu) +); + +// +// Instantiation of Instruction Cache +// +or1200_cpu or1200_cpu( + .clk(clk_i), + .rst(rst_i), + + // Connection IC and IFETCHER inside CPU + .ic_en(ic_en), + .icpu_adr_o(icpu_adr_cpu), + .icpu_cycstb_o(icpu_cycstb_cpu), + .icpu_sel_o(icpu_sel_cpu), + .icpu_tag_o(icpu_tag_cpu), + .icpu_dat_i(icpu_dat_ic), + .icpu_ack_i(icpu_ack_ic), + .icpu_rty_i(icpu_rty_immu), + .icpu_adr_i(icpu_adr_immu), + .icpu_err_i(icpu_err_immu), + .icpu_tag_i(icpu_tag_immu), + + // Connection CPU to external Debug port + .ex_freeze(ex_freeze), + .ex_insn(ex_insn), + .branch_op(branch_op), + .du_stall(du_stall), + .du_addr(du_addr), + .du_dat_du(du_dat_du), + .du_read(du_read), + .du_write(du_write), + .du_dsr(du_dsr), + .du_except(du_except), + .du_dat_cpu(du_dat_cpu), + .rf_dataw(rf_dataw), + + + // Connection IMMU and CPU internally + .immu_en(immu_en), + + // Connection DC and CPU + .dc_en(dc_en), + .dcpu_adr_o(dcpu_adr_cpu), + .dcpu_cycstb_o(dcpu_cycstb_cpu), + .dcpu_we_o(dcpu_we_cpu), + .dcpu_sel_o(dcpu_sel_cpu), + .dcpu_tag_o(dcpu_tag_cpu), + .dcpu_dat_o(dcpu_dat_cpu), + .dcpu_dat_i(dcpu_dat_dc), + .dcpu_ack_i(dcpu_ack_dc), + .dcpu_rty_i(dcpu_rty_dc), + .dcpu_err_i(dcpu_err_dmmu), + .dcpu_tag_i(dcpu_tag_dmmu), + + // Connection DMMU and CPU internally + .dmmu_en(dmmu_en), + + // Connection PIC and CPU's EXCEPT + .sig_int(sig_int), + .sig_tick(sig_tick), + + // SPRs + .supv(supv), + .spr_addr(spr_addr), + .spr_dat_cpu(spr_dat_cpu), + .spr_dat_pic(spr_dat_pic), + .spr_dat_tt(spr_dat_tt), + .spr_dat_pm(spr_dat_pm), + .spr_dat_dmmu(spr_dat_dmmu), + .spr_dat_immu(spr_dat_immu), + .spr_dat_du(spr_dat_du), + .spr_dat_npc(spr_dat_npc), + .spr_cs(spr_cs), + .spr_we(spr_we) +); + +// +// Instantiation of DMMU +// +or1200_dmmu_top or1200_dmmu_top( + // Rst and clk + .clk(clk_i), + .rst(rst_i), + + // CPU i/f + .dc_en(dc_en), + .dmmu_en(dmmu_en), + .supv(supv), + .dcpu_adr_i(dcpu_adr_cpu), + .dcpu_cycstb_i(dcpu_cycstb_cpu), + .dcpu_we_i(dcpu_we_cpu), + .dcpu_tag_o(dcpu_tag_dmmu), + .dcpu_err_o(dcpu_err_dmmu), + + // SPR access + .spr_cs(spr_cs[`OR1200_SPR_GROUP_DMMU]), + .spr_write(spr_we), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_cpu), + .spr_dat_o(spr_dat_dmmu), + + // DC i/f + .dcdmmu_err_i(dcdmmu_err_dc), + .dcdmmu_tag_i(dcdmmu_tag_dc), + .dcdmmu_adr_o(dcdmmu_adr_dmmu), + .dcdmmu_cycstb_o(dcdmmu_cycstb_dmmu), + .dcdmmu_ci_o(dcdmmu_ci_dmmu) +); + +// +// Instantiation of Data Cache +// +or1200_dc_top or1200_dc_top( + .clk(clk_i), + .rst(rst_i), + + // DC and CPU/DMMU + .dc_en(dc_en), + .dcdmmu_adr_i(dcdmmu_adr_dmmu), + .dcdmmu_cycstb_i(dcdmmu_cycstb_dmmu), + .dcdmmu_ci_i(dcdmmu_ci_dmmu), + .dcpu_we_i(dcpu_we_cpu), + .dcpu_sel_i(dcpu_sel_cpu), + .dcpu_tag_i(dcpu_tag_cpu), + .dcpu_dat_i(dcpu_dat_cpu), + .dcpu_dat_o(dcpu_dat_dc), + .dcpu_ack_o(dcpu_ack_dc), + .dcpu_rty_o(dcpu_rty_dc), + .dcdmmu_err_o(dcdmmu_err_dc), + .dcdmmu_tag_o(dcdmmu_tag_dc), + + // SPR access + .spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]), + .spr_write(spr_we), + .spr_dat_i(spr_dat_cpu), + + // DC and BIU + .dcsb_dat_o(dcsb_dat_dc), + .dcsb_adr_o(dcsb_adr_dc), + .dcsb_cyc_o(dcsb_cyc_dc), + .dcsb_stb_o(dcsb_stb_dc), + .dcsb_we_o(dcsb_we_dc), + .dcsb_sel_o(dcsb_sel_dc), + .dcsb_cab_o(dcsb_cab_dc), + .dcsb_dat_i(dcsb_dat_sb), + .dcsb_ack_i(dcsb_ack_sb), + .dcsb_err_i(dcsb_err_sb) +); + +// +// Instantiation of Store Buffer +// +or1200_sb or1200_sb( + // RISC clock, reset + .clk(clk_i), + .rst(rst_i), + + // Internal RISC bus (DC<->SB) + .dcsb_dat_i(dcsb_dat_dc), + .dcsb_adr_i(dcsb_adr_dc), + .dcsb_cyc_i(dcsb_cyc_dc), + .dcsb_stb_i(dcsb_stb_dc), + .dcsb_we_i(dcsb_we_dc), + .dcsb_sel_i(dcsb_sel_dc), + .dcsb_cab_i(dcsb_cab_dc), + .dcsb_dat_o(dcsb_dat_sb), + .dcsb_ack_o(dcsb_ack_sb), + .dcsb_err_o(dcsb_err_sb), + + // SB and BIU + .sbbiu_dat_o(sbbiu_dat_sb), + .sbbiu_adr_o(sbbiu_adr_sb), + .sbbiu_cyc_o(sbbiu_cyc_sb), + .sbbiu_stb_o(sbbiu_stb_sb), + .sbbiu_we_o(sbbiu_we_sb), + .sbbiu_sel_o(sbbiu_sel_sb), + .sbbiu_cab_o(sbbiu_cab_sb), + .sbbiu_dat_i(sbbiu_dat_biu), + .sbbiu_ack_i(sbbiu_ack_biu), + .sbbiu_err_i(sbbiu_err_biu) +); + +// +// Instantiation of Debug Unit +// +or1200_du or1200_du( + // RISC Internal Interface + .clk(clk_i), + .rst(rst_i), + .dcpu_cycstb_i(dcpu_cycstb_cpu), + .dcpu_we_i(dcpu_we_cpu), + .icpu_cycstb_i(icpu_cycstb_cpu), + .ex_freeze(ex_freeze), + .branch_op(branch_op), + .ex_insn(ex_insn), + .du_dsr(du_dsr), + + // For Trace buffer + .spr_dat_npc(spr_dat_npc), + .rf_dataw(rf_dataw), + + // DU's access to SPR unit + .du_stall(du_stall), + .du_addr(du_addr), + .du_dat_i(du_dat_cpu), + .du_dat_o(du_dat_du), + .du_read(du_read), + .du_write(du_write), + .du_except(du_except), + + // Access to DU's SPRs + .spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]), + .spr_write(spr_we), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_cpu), + .spr_dat_o(spr_dat_du), + + // External Debug Interface + .dbg_stall_i(dbg_stall_i), + .dbg_dat_i(dbg_dat_i), + .dbg_adr_i(dbg_adr_i), + .dbg_op_i(dbg_op_i), + .dbg_ewt_i(dbg_ewt_i), + .dbg_lss_o(dbg_lss_o), + .dbg_is_o(dbg_is_o), + .dbg_wp_o(dbg_wp_o), + .dbg_bp_o(dbg_bp_o), + .dbg_dat_o(dbg_dat_o) +); + +// +// Programmable interrupt controller +// +or1200_pic or1200_pic( + // RISC Internal Interface + .clk(clk_i), + .rst(rst_i), + .spr_cs(spr_cs[`OR1200_SPR_GROUP_PIC]), + .spr_write(spr_we), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_cpu), + .spr_dat_o(spr_dat_pic), + .pic_wakeup(pic_wakeup), + .int(sig_int), + + // PIC Interface + .pic_int(pic_ints_i) +); + +// +// Instantiation of Tick timer +// +or1200_tt or1200_tt( + // RISC Internal Interface + .clk(clk_i), + .rst(rst_i), + .du_stall(du_stall), + .spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]), + .spr_write(spr_we), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_cpu), + .spr_dat_o(spr_dat_tt), + .int(sig_tick) +); + +// +// Instantiation of Power Management +// +or1200_pm or1200_pm( + // RISC Internal Interface + .clk(clk_i), + .rst(rst_i), + .pic_wakeup(pic_wakeup), + .spr_write(spr_we), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_cpu), + .spr_dat_o(spr_dat_pm), + + // Power Management Interface + .pm_cpustall(pm_cpustall_i), + .pm_clksd(pm_clksd_o), + .pm_dc_gate(pm_dc_gate_o), + .pm_ic_gate(pm_ic_gate_o), + .pm_dmmu_gate(pm_dmmu_gate_o), + .pm_immu_gate(pm_immu_gate_o), + .pm_tt_gate(pm_tt_gate_o), + .pm_cpu_gate(pm_cpu_gate_o), + .pm_wakeup(pm_wakeup_o), + .pm_lvolt(pm_lvolt_o) +); + + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_immu_tlb.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_immu_tlb.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_immu_tlb.v (revision 995) @@ -0,0 +1,239 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Instruction TLB //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instantiation of ITLB. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.2 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.8 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.7 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +// +// Insn TLB +// + +module or1200_immu_tlb( + // Rst and clk + clk, rst, + + // I/F for translation + tlb_en, vaddr, hit, ppn, uxe, sxe, ci, + + // SPR access + spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_OPERAND_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// I/F for translation +// +input tlb_en; +input [aw-1:0] vaddr; +output hit; +output [31:`OR1200_IMMU_PS] ppn; +output uxe; +output sxe; +output ci; + +// +// SPR access +// +input spr_cs; +input spr_write; +input [31:0] spr_addr; +input [31:0] spr_dat_i; +output [31:0] spr_dat_o; + +// +// Internal wires and regs +// +wire [`OR1200_ITLB_TAG] vpn; +wire v; +wire [`OR1200_ITLB_INDXW-1:0] tlb_index; +wire tlb_mr_en; +wire tlb_mr_we; +wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in; +wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out; +wire tlb_tr_en; +wire tlb_tr_we; +wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in; +wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out; + +// +// Implemented bits inside match and translate registers +// +// itlbwYmrX: vpn 31-19 v 0 +// itlbwYtrX: ppn 31-13 uxe 7 sxe 6 +// +// itlb memory width: +// 19 bits for ppn +// 13 bits for vpn +// 1 bit for valid +// 2 bits for protection +// 1 bit for cache inhibit + +// +// Enable for Match registers +// +assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]); + +// +// Write enable for Match registers +// +assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]; + +// +// Enable for Translate registers +// +assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]); + +// +// Write enable for Translate registers +// +assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]; + +// +// Output to SPRS unit +// +assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ? + {vpn, tlb_index & {`OR1200_ITLB_INDXW{v}}, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} : + (!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ? + {ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} : + 32'h00000000; + +// +// Assign outputs from Match registers +// +assign {vpn, v} = tlb_mr_ram_out; + +// +// Assign to Match registers inputs +// +assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]}; + +// +// Assign outputs from Translate registers +// +assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out; + +// +// Assign to Translate registers inputs +// +assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS], + spr_dat_i[`OR1200_ITLBTR_UXE_BITS], + spr_dat_i[`OR1200_ITLBTR_SXE_BITS], + spr_dat_i[`OR1200_ITLBTR_CI_BITS]}; + +// +// Generate hit +// +assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v; + +// +// TLB index is normally vaddr[18:13]. If it is SPR access then index is +// spr_addr[5:0]. +// +assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX]; + +// +// Instantiation of ITLB Match Registers +// +or1200_spram_64x14 itlb_mr_ram( + .clk(clk), + .rst(rst), + .ce(tlb_mr_en), + .we(tlb_mr_we), + .oe(1'b1), + .addr(tlb_index), + .di(tlb_mr_ram_in), + .do(tlb_mr_ram_out) +); + +// +// Instantiation of ITLB Translate Registers +// +or1200_spram_64x22 itlb_tr_ram( + .clk(clk), + .rst(rst), + .ce(tlb_tr_en), + .we(tlb_tr_we), + .oe(1'b1), + .addr(tlb_index), + .di(tlb_tr_ram_in), + .do(tlb_tr_ram_out) +); + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_wb_biu.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_wb_biu.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_wb_biu.v (revision 995) @@ -0,0 +1,400 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's WISHBONE BIU //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Implements WISHBONE interface //// +//// //// +//// To Do: //// +//// - add support for wb_err_i //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/07/14 22:17:17 lampret +// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.12 2001/11/22 13:42:51 lampret +// Added wb_cyc_o assignment after it was removed by accident. +// +// Revision 1.11 2001/11/20 21:28:10 lampret +// Added optional sampling of inputs. +// +// Revision 1.10 2001/11/18 11:32:00 lampret +// OR1200_REGISTERED_OUTPUTS can now be enabled. +// +// Revision 1.9 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.8 2001/10/14 13:12:10 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:35 igorm +// no message +// +// Revision 1.3 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/22 03:31:54 lampret +// Fixed RAM's oen bug. Cache bypass under development. +// +// Revision 1.1 2001/07/20 00:46:23 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_wb_biu( + // RISC clock, reset and clock control + clk, rst, clmode, + + // WISHBONE interface + wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i, + wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_cab_o, wb_dat_o, + + // Internal RISC bus + biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i, + biu_dat_o, biu_ack_o, biu_err_o +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_OPERAND_WIDTH; + +// +// RISC clock, reset and clock control +// +input clk; // RISC clock +input rst; // RISC reset +input [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4 + +// +// WISHBONE interface +// +input wb_clk_i; // clock input +input wb_rst_i; // reset input +input wb_ack_i; // normal termination +input wb_err_i; // termination w/ error +input wb_rty_i; // termination w/ retry +input [dw-1:0] wb_dat_i; // input data bus +output wb_cyc_o; // cycle valid output +output [aw-1:0] wb_adr_o; // address bus outputs +output wb_stb_o; // strobe output +output wb_we_o; // indicates write transfer +output [3:0] wb_sel_o; // byte select outputs +output wb_cab_o; // consecutive address burst +output [dw-1:0] wb_dat_o; // output data bus + +// +// Internal RISC interface +// +input [dw-1:0] biu_dat_i; // input data bus +input [aw-1:0] biu_adr_i; // address bus +input biu_cyc_i; // WB cycle +input biu_stb_i; // WB strobe +input biu_we_i; // WB write enable +input biu_cab_i; // CAB input +input [3:0] biu_sel_i; // byte selects +output [31:0] biu_dat_o; // output data bus +output biu_ack_o; // ack output +output biu_err_o; // err output + +// +// Registers +// +reg [1:0] valid_div; // Used for synchronization +`ifdef OR1200_REGISTERED_OUTPUTS +reg [aw-1:0] wb_adr_o; // address bus outputs +reg wb_cyc_o; // cycle output +reg wb_stb_o; // strobe output +reg wb_we_o; // indicates write transfer +reg [3:0] wb_sel_o; // byte select outputs +reg wb_cab_o; // CAB output +reg [dw-1:0] wb_dat_o; // output data bus +`endif +`ifdef OR1200_REGISTERED_INPUTS +reg long_ack_o; // normal termination +reg long_err_o; // error termination +reg [dw-1:0] biu_dat_o; // output data bus +`else +wire long_ack_o; // normal termination +wire long_err_o; // error termination +`endif +wire aborted; // Graceful abort +reg aborted_r; // Graceful abort +wire retry; // Retry +`ifdef OR1200_WB_RETRY +reg [`OR1200_WB_RETRY-1:0] retry_cntr; // Retry counter +`endif + +// +// WISHBONE I/F <-> Internal RISC I/F conversion +// + +// +// Address bus +// +`ifdef OR1200_REGISTERED_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_adr_o <= #1 {aw{1'b0}}; + else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i)) + wb_adr_o <= #1 biu_adr_i; +`else +assign wb_adr_o = biu_adr_i; +`endif + +// +// Input data bus +// +`ifdef OR1200_REGISTERED_INPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + biu_dat_o <= #1 32'h0000_0000; + else if (wb_ack_i) + biu_dat_o <= #1 wb_dat_i; +`else +assign biu_dat_o = wb_dat_i; +`endif + +// +// Output data bus +// +`ifdef OR1200_REGISTERED_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_dat_o <= #1 {dw{1'b0}}; + else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted) + wb_dat_o <= #1 biu_dat_i; +`else +assign wb_dat_o = biu_dat_i; +`endif + +// +// Valid_div counts RISC clock cycles by modulo 4 +// and is used to synchronize external WB i/f to +// RISC clock +// +always @(posedge clk or posedge rst) + if (rst) + valid_div <= #1 2'b0; + else + valid_div <= #1 valid_div + 'd1; + +// +// biu_ack_o is one RISC clock cycle long long_ack_o. +// long_ack_o is one, two or four RISC clock cycles long because +// WISHBONE can work at 1, 1/2 or 1/4 RISC clock. +// +assign biu_ack_o = long_ack_o +`ifdef OR1200_CLKDIV_4_SUPPORTED + & (valid_div[1] | ~clmode[1]) +`ifdef OR1200_CLKDIV_2_SUPPORTED + & (valid_div[0] | ~clmode[0]) +`endif +`endif + ; + +// +// Acknowledgment of the data to the RISC +// +// long_ack_o +// +`ifdef OR1200_REGISTERED_INPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + long_ack_o <= #1 1'b0; + else + long_ack_o <= #1 wb_ack_i & ~aborted; +`else +assign long_ack_o = wb_ack_i & ~aborted; +`endif + +// +// biu_err_o is one RISC clock cycle long long_err_o. +// long_err_o is one, two or four RISC clock cycles long because +// WISHBONE can work at 1, 1/2 or 1/4 RISC clock. +// +assign biu_err_o = long_err_o +`ifdef OR1200_CLKDIV_4_SUPPORTED + & (valid_div[1] | ~clmode[1]) +`ifdef OR1200_CLKDIV_2_SUPPORTED + & (valid_div[0] | ~clmode[0]) +`endif +`endif + ; + +// +// Error termination +// +// long_err_o +// +`ifdef OR1200_REGISTERED_INPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + long_err_o <= #1 1'b0; + else + long_err_o <= #1 wb_err_i & ~aborted; +`else +assign long_err_o = wb_err_i & ~aborted; +`endif + +// +// Retry counter +// +// Assert 'retry' when 'wb_rty_i' is sampled high and keep it high +// until retry counter doesn't expire +// +`ifdef OR1200_WB_RETRY +assign retry = wb_rty_i | (|retry_cntr); +`else +assign retry = 1'b0; +`endif +`ifdef OR1200_WB_RETRY +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + retry_cntr <= #1 1'b0; + else if (wb_rty_i) + retry_cntr <= #1 {`OR1200_WB_RETRY{1'b1}}; + else if (retry_cntr) + retry_cntr <= #1 retry_cntr - 7'd1; +`endif + +// +// Graceful completion of aborted transfers +// +// Assert 'aborted' when 1) current transfer is in progress (wb_stb_o; which +// we know is only asserted together with wb_cyc_o) 2) and in next WB clock cycle +// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and +// there is no termination of current transfer in this WB clock cycle (wb_ack_i +// and wb_err_i are low). +// Extend 'aborted' signal with 'aborted_r' until this "aborted" transfer +// is properly terminated with wb_ack_i/wb_err_i. +// +// +assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i) | aborted_r; +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + aborted_r <= #1 1'b0; + else if (wb_ack_i | wb_err_i) + aborted_r <= #1 1'b0; + else if (aborted) + aborted_r <= #1 1'b1; + +// +// WB cyc_o +// +// Either 1) normal transfer initiated by biu_cyc_i (and biu_cab_i if +// bursts are enabled) and possibly suspended by 'retry' +// or 2) extended "aborted" transfer +// +`ifdef OR1200_REGISTERED_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_cyc_o <= #1 1'b0; + else +`ifdef OR1200_NO_BURSTS + wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry | aborted & ~wb_ack_i; +`else + wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry | biu_cab_i | aborted & ~wb_ack_i; +`endif +`else +`ifdef OR1200_NO_BURSTS +assign wb_cyc_o = biu_cyc_i & ~retry; +`else +assign wb_cyc_o = biu_cyc_i | biu_cab_i & ~retry; +`endif +`endif + +// +// WB stb_o +// +`ifdef OR1200_REGISTERED_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_stb_o <= #1 1'b0; + else + wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry | aborted & ~wb_ack_i; +`else +assign wb_stb_o = biu_cyc_i & biu_stb_i; +`endif + +// +// WB we_o +// +`ifdef OR1200_REGISTERED_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_we_o <= #1 1'b0; + else + wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i | aborted & wb_we_o; +`else +assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i; +`endif + +// +// WB sel_o +// +`ifdef OR1200_REGISTERED_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_sel_o <= #1 4'b0000; + else + wb_sel_o <= #1 biu_sel_i; +`else +assign wb_sel_o = biu_sel_i; +`endif + +// +// WB cab_o +// +`ifdef OR1200_REGISTERED_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_cab_o <= #1 1'b0; + else + wb_cab_o <= #1 biu_cab_i; +`else +assign wb_cab_o = biu_cab_i; +`endif + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_freeze.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_freeze.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_freeze.v (revision 995) @@ -0,0 +1,190 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Freeze logic //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Generates all freezes and stalls inside RISC //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.5 2002/07/14 22:17:17 lampret +// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. +// +// Revision 1.4 2002/03/29 15:16:55 lampret +// Some of the warnings fixed. +// +// Revision 1.3 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.10 2001/11/13 10:02:21 lampret +// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) +// +// Revision 1.9 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.8 2001/10/19 23:28:46 lampret +// Fixed some synthesis warnings. Configured with caches and MMUs. +// +// Revision 1.7 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +`define OR1200_NO_FREEZE 3'd0 +`define OR1200_FREEZE_BYDC 3'd1 +`define OR1200_FREEZE_BYMULTICYCLE 3'd2 +`define OR1200_WAIT_LSU_TO_FINISH 3'd3 +`define OR1200_WAIT_IC 3'd4 + +// +// Freeze logic (stalls CPU pipeline, ifetcher etc.) +// +module or1200_freeze( + // Clock and reset + clk, rst, + + // Internal i/f + multicycle, flushpipe, extend_flush, lsu_stall, if_stall, + lsu_unstall, du_stall, mac_stall, + force_dslot_fetch, abort_ex, + genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze, + icpu_ack_i, icpu_err_i +); + +// +// I/O +// +input clk; +input rst; +input [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; +input flushpipe; +input extend_flush; +input lsu_stall; +input if_stall; +input lsu_unstall; +input force_dslot_fetch; +input abort_ex; +input du_stall; +input mac_stall; +output genpc_freeze; +output if_freeze; +output id_freeze; +output ex_freeze; +output wb_freeze; +input icpu_ack_i; +input icpu_err_i; + +// +// Internal wires and regs +// +wire multicycle_freeze; +reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt; +reg flushpipe_r; + +// +// Pipeline freeze +// +// Rules how to create freeze signals: +// 1. Not overwriting pipeline stages: +// Freze signals at the beginning of pipeline (such as if_freeze) can be asserted more +// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never +// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc. +// +// 2. Inserting NOPs in the middle of pipeline only if supported: +// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted. +// This way NOP is asserted from stage ID into EX stage. +// +assign genpc_freeze = du_stall | flushpipe_r; +assign if_freeze = id_freeze | extend_flush; +//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall; +assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall | mac_stall; +assign ex_freeze = wb_freeze; +//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall; +assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex; + +// +// registered flushpipe +// +always @(posedge clk or posedge rst) + if (rst) + flushpipe_r <= #1 1'b0; + else if (icpu_ack_i | icpu_err_i) +// else if (!if_stall) + flushpipe_r <= #1 flushpipe; + else if (!flushpipe) + flushpipe_r <= #1 1'b0; + +// +// Multicycle freeze +// +assign multicycle_freeze = |multicycle_cnt; + +// +// Multicycle counter +// +always @(posedge clk or posedge rst) + if (rst) + multicycle_cnt <= #1 3'b0; + else if (multicycle_cnt) + multicycle_cnt <= #1 multicycle_cnt - 'd1; + else if (multicycle & !ex_freeze) + multicycle_cnt <= #1 multicycle; + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_gmultp2_32x32.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_gmultp2_32x32.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_gmultp2_32x32.v (revision 995) @@ -0,0 +1,131 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic 32x32 multiplier //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Generic 32x32 multiplier with pipeline stages. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.4 2001/12/04 05:02:35 lampret +// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 +// +// Revision 1.3 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.2 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +// 32x32 multiplier, no input/output registers +// Registers inside Wallace trees every 8 full adder levels, +// with first pipeline after level 4 + +`ifdef OR1200_GENERIC_MULTP2_32X32 + +`define OR1200_W 32 +`define OR1200_WW 64 + +module or1200_gmultp2_32x32 ( X, Y, CLK, RST, P ); + +input [`OR1200_W-1:0] X; +input [`OR1200_W-1:0] Y; +input CLK; +input RST; +output [`OR1200_WW-1:0] P; + +reg [`OR1200_WW-1:0] p0; +reg [`OR1200_WW-1:0] p1; +integer xi; +integer yi; + +// +// Conversion unsigned to signed +// +always @(X) + xi <= X; + +// +// Conversion unsigned to signed +// +always @(Y) + yi <= Y; + +// +// First multiply stage +// +always @(posedge CLK or posedge RST) + if (RST) + p0 <= `OR1200_WW'b0; + else + p0 <= #1 xi * yi; + +// +// Second multiply stage +// +always @(posedge CLK or posedge RST) + if (RST) + p1 <= `OR1200_WW'b0; + else + p1 <= #1 p0; + +assign P = p1; + +endmodule + +`endif Index: tags/rel_3/or1200/rtl/verilog/or1200_du.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_du.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_du.v (revision 995) @@ -0,0 +1,632 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Debug Unit //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Basic OR1200 debug unit. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.6 2002/03/14 00:30:24 lampret +// Added alternative for critical path in DU. +// +// Revision 1.5 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.4 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.3 2002/01/18 07:56:00 lampret +// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.12 2001/11/30 18:58:00 simons +// Trap insn couses break after exits ex_insn. +// +// Revision 1.11 2001/11/23 08:38:51 lampret +// Changed DSR/DRR behavior and exception detection. +// +// Revision 1.10 2001/11/20 21:25:44 lampret +// Fixed dbg_is_o assignment width. +// +// Revision 1.9 2001/11/20 18:46:14 simons +// Break point bug fixed +// +// Revision 1.8 2001/11/18 08:36:28 lampret +// For GDB changed single stepping and disabled trap exception. +// +// Revision 1.7 2001/10/21 18:09:53 lampret +// Fixed sensitivity list. +// +// Revision 1.6 2001/10/14 13:12:09 lampret +// MP3 version. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +// +// Debug unit +// + +module or1200_du( + // RISC Internal Interface + clk, rst, + dcpu_cycstb_i, dcpu_we_i, icpu_cycstb_i, + ex_freeze, branch_op, ex_insn, + spr_dat_npc, rf_dataw, + du_dsr, du_stall, du_addr, du_dat_i, du_dat_o, + du_read, du_write, du_except, + spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, + + // External Debug Interface + dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i, + dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_OPERAND_WIDTH; + +// +// I/O +// + +// +// RISC Internal Interface +// +input clk; // Clock +input rst; // Reset +input dcpu_cycstb_i; // LSU status +input dcpu_we_i; // LSU status +input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status +input ex_freeze; // EX stage freeze +input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op +input [dw-1:0] ex_insn; // EX insn +input [31:0] spr_dat_npc; // Next PC (for trace) +input [31:0] rf_dataw; // ALU result (for trace) +output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR +output du_stall; // Debug Unit Stall +output [aw-1:0] du_addr; // Debug Unit Address +input [dw-1:0] du_dat_i; // Debug Unit Data In +output [dw-1:0] du_dat_o; // Debug Unit Data Out +output du_read; // Debug Unit Read Enable +output du_write; // Debug Unit Write Enable +input [12:0] du_except; // Exception masked by DSR +input spr_cs; // SPR Chip Select +input spr_write; // SPR Read/Write +input [aw-1:0] spr_addr; // SPR Address +input [dw-1:0] spr_dat_i; // SPR Data Input +output [dw-1:0] spr_dat_o; // SPR Data Output + +// +// External Debug Interface +// +input dbg_stall_i; // External Stall Input +input [dw-1:0] dbg_dat_i; // External Data Input +input [aw-1:0] dbg_adr_i; // External Address Input +input [2:0] dbg_op_i; // External Operation Select Input +input dbg_ewt_i; // External Watchpoint Trigger Input +output [3:0] dbg_lss_o; // External Load/Store Unit Status +output [1:0] dbg_is_o; // External Insn Fetch Status +output [10:0] dbg_wp_o; // Watchpoints Outputs +output dbg_bp_o; // Breakpoint Output +output [dw-1:0] dbg_dat_o; // External Data Output + + +// +// Some connections go directly from the CPU through DU to Debug I/F +// +`ifdef OR1200_DU_STATUS_UNIMPLEMENTED +assign dbg_lss_o = 4'b0000; + +reg [1:0] dbg_is_o; +// +// Show insn activity (temp, must be removed) +// +always @(posedge clk or posedge rst) + if (rst) + dbg_is_o <= #1 2'b00; + else if (!ex_freeze & + ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16])) + dbg_is_o <= #1 ~dbg_is_o; +`ifdef UNUSED +assign dbg_is_o = 2'b00; +`endif +`else +assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000; +assign dbg_is_o = {1'b0, icpu_cycstb_i}; +`endif +assign dbg_wp_o = 11'b000_0000_0000; +assign dbg_dat_o = du_dat_i; + +// +// Some connections go directly from Debug I/F through DU to the CPU +// +assign du_stall = dbg_stall_i; +assign du_addr = dbg_adr_i; +assign du_dat_o = dbg_dat_i; +assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR); +assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR); + +`ifdef OR1200_DU_IMPLEMENTED + +// +// Debug Mode Register 1 (only ST and BT implemented) +// +`ifdef OR1200_DU_DMR1 +reg [23:22] dmr1; // DMR1 implemented (ST & BT) +`else +wire [23:22] dmr1; // DMR1 not implemented +`endif + +// +// Debug Mode Register 2 (not implemented) +// +`ifdef OR1200_DU_DMR2 +wire [31:0] dmr2; // DMR not implemented +`endif + +// +// Debug Stop Register +// +`ifdef OR1200_DU_DSR +reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented +`else +wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented +`endif + +// +// Debug Reason Register +// +`ifdef OR1200_DU_DRR +reg [13:0] drr; // DRR implemented +`else +wire [13:0] drr; // DRR not implemented +`endif + +// +// Internal wires +// +wire dmr1_sel; // DMR1 select +wire dsr_sel; // DSR select +wire drr_sel; // DRR select +reg dbg_bp_r; +`ifdef OR1200_DU_READREGS +reg [31:0] spr_dat_o; +`endif +reg [13:0] except_stop; // Exceptions that stop because of DSR +`ifdef OR1200_DU_TB_IMPLEMENTED +wire tb_enw; +reg [7:0] tb_wadr; +reg [31:0] tb_timstmp; +`endif +wire [31:0] tbia_dat_o; +wire [31:0] tbim_dat_o; +wire [31:0] tbar_dat_o; +wire [31:0] tbts_dat_o; + +// +// DU registers address decoder +// +`ifdef OR1200_DU_DMR1 +assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DMR1)); +`endif +`ifdef OR1200_DU_DSR +assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DSR)); +`endif +`ifdef OR1200_DU_DRR +assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DRR)); +`endif + +// +// Decode started exception +// +always @(du_except) begin + except_stop = 14'b0000_0000_0000; + casex (du_except) + 13'b1_xxxx_xxxx_xxxx: + except_stop[`OR1200_DU_DRR_TTE] = 1'b1; + 13'b0_1xxx_xxxx_xxxx: begin + except_stop[`OR1200_DU_DRR_IE] = 1'b1; + end + 13'b0_01xx_xxxx_xxxx: begin + except_stop[`OR1200_DU_DRR_IME] = 1'b1; + end + 13'b0_001x_xxxx_xxxx: + except_stop[`OR1200_DU_DRR_IPFE] = 1'b1; + 13'b0_0001_xxxx_xxxx: begin + except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1; + end + 13'b0_0000_1xxx_xxxx: + except_stop[`OR1200_DU_DRR_IIE] = 1'b1; + 13'b0_0000_01xx_xxxx: begin + except_stop[`OR1200_DU_DRR_AE] = 1'b1; + end + 13'b0_0000_001x_xxxx: begin + except_stop[`OR1200_DU_DRR_DME] = 1'b1; + end + 13'b0_0000_0001_xxxx: + except_stop[`OR1200_DU_DRR_DPFE] = 1'b1; + 13'b0_0000_0000_1xxx: + except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1; + 13'b0_0000_0000_01xx: begin + except_stop[`OR1200_DU_DRR_RE] = 1'b1; + end + 13'b0_0000_0000_001x: begin + except_stop[`OR1200_DU_DRR_TE] = 1'b1; + end + 13'b0_0000_0000_0001: + except_stop[`OR1200_DU_DRR_SCE] = 1'b1; + default: + except_stop = 14'b0000_0000_0000; + endcase +end + +// +// dbg_bp_o is registered +// +assign dbg_bp_o = dbg_bp_r; + +// +// Breakpoint activation register +// +always @(posedge clk or posedge rst) + if (rst) + dbg_bp_r <= #1 1'b0; + else if (!ex_freeze) + dbg_bp_r <= #1 |except_stop +`ifdef OR1200_DU_DMR1_ST + | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST] +`endif +`ifdef OR1200_DU_DMR1_BT + | (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT] +`endif + ; + else + dbg_bp_r <= #1 |except_stop; + +// +// Write to DMR1 +// +`ifdef OR1200_DU_DMR1 +always @(posedge clk or posedge rst) + if (rst) + dmr1 <= 2'b00; + else if (dmr1_sel && spr_write) + dmr1 <= #1 spr_dat_i[23:22]; +`else +assign dmr1 = 2'b00; +`endif + +// +// DMR2 bits tied to zero +// +`ifdef OR1200_DU_DMR2 +assign dmr2 = 32'h0000_0000; +`endif + +// +// Write to DSR +// +`ifdef OR1200_DU_DSR +always @(posedge clk or posedge rst) + if (rst) + dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}}; + else if (dsr_sel && spr_write) + dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0]; +`else +assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}}; +`endif + +// +// Write to DRR +// +`ifdef OR1200_DU_DRR +always @(posedge clk or posedge rst) + if (rst) + drr <= 14'b0; + else if (drr_sel && spr_write) + drr <= #1 spr_dat_i[13:0]; + else + drr <= #1 drr | except_stop; +`else +assign drr = 14'b0; +`endif + +// +// Read DU registers +// +`ifdef OR1200_DU_READREGS +always @(spr_addr or dsr or drr or dmr1 or dmr2 or + tbia_dat_o or tbim_dat_o or tbar_dat_o or tb_wadr) + casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case +`ifdef OR1200_DU_DMR1 + `OR1200_DU_OFS_DMR1: + spr_dat_o = {8'b0, dmr1, 22'b0}; +`endif +`ifdef OR1200_DU_DMR2 + `OR1200_DU_OFS_DMR2: + spr_dat_o = dmr2; +`endif +`ifdef OR1200_DU_DSR + `OR1200_DU_OFS_DSR: + spr_dat_o = {18'b0, dsr}; +`endif +`ifdef OR1200_DU_DRR + `OR1200_DU_OFS_DRR: + spr_dat_o = {18'b0, drr}; +`endif +`ifdef OR1200_DU_TB_IMPLEMENTED + `OR1200_DU_OFS_TBADR: + spr_dat_o = {24'h000000, tb_wadr}; + `OR1200_DU_OFS_TBIA: + spr_dat_o = tbia_dat_o; + `OR1200_DU_OFS_TBIM: + spr_dat_o = tbim_dat_o; + `OR1200_DU_OFS_TBAR: + spr_dat_o = tbar_dat_o; + `OR1200_DU_OFS_TBTS: + spr_dat_o = tbts_dat_o; +`endif + default: + spr_dat_o = 32'h0000_0000; + endcase +`endif + +// +// DSR alias +// +assign du_dsr = dsr; + +`ifdef OR1200_DU_TB_IMPLEMENTED +// +// Simple trace buffer +// (right now hardcoded for Xilinx Virtex FPGAs) +// +// Stores last 256 instruction addresses, instruction +// machine words and ALU results +// + +// +// Trace buffer write enable +// +assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]); + +// +// Trace buffer write address pointer +// +always @(posedge clk or posedge rst) + if (rst) + tb_wadr <= #1 8'h00; + else if (tb_enw) + tb_wadr <= #1 tb_wadr + 8'd1; + +// +// Free running counter (time stamp) +// +always @(posedge clk or posedge rst) + if (rst) + tb_timstmp <= #1 32'h00000000; + else if (!dbg_bp_r) + tb_timstmp <= #1 tb_timstmp + 32'd1; + +// +// Trace buffer RAMs +// +RAMB4_S16_S16 tbia_ramb4_s16_0( + .CLKA(clk), + .RSTA(rst), + .ADDRA(tb_wadr), + .DIA(spr_dat_npc[15:0]), + .ENA(1'b1), + .WEA(tb_enw), + .DOA(), + + .CLKB(clk), + .RSTB(rst), + .ADDRB(spr_addr[7:0]), + .DIB(16'h0000), + .ENB(1'b1), + .WEB(1'b0), + .DOB(tbia_dat_o[15:0]) +); + +RAMB4_S16_S16 tbia_ramb4_s16_1( + .CLKA(clk), + .RSTA(rst), + .ADDRA(tb_wadr), + .DIA(spr_dat_npc[31:16]), + .ENA(1'b1), + .WEA(tb_enw), + .DOA(), + + .CLKB(clk), + .RSTB(rst), + .ADDRB(spr_addr[7:0]), + .DIB(16'h0000), + .ENB(1'b1), + .WEB(1'b0), + .DOB(tbia_dat_o[31:16]) +); + +RAMB4_S16_S16 tbim_ramb4_s16_0( + .CLKA(clk), + .RSTA(rst), + .ADDRA(tb_wadr), + .DIA(ex_insn[15:0]), + .ENA(1'b1), + .WEA(tb_enw), + .DOA(), + + .CLKB(clk), + .RSTB(rst), + .ADDRB(spr_addr[7:0]), + .DIB(16'h0000), + .ENB(1'b1), + .WEB(1'b0), + .DOB(tbim_dat_o[15:0]) +); + +RAMB4_S16_S16 tbim_ramb4_s16_1( + .CLKA(clk), + .RSTA(rst), + .ADDRA(tb_wadr), + .DIA(ex_insn[31:16]), + .ENA(1'b1), + .WEA(tb_enw), + .DOA(), + + .CLKB(clk), + .RSTB(rst), + .ADDRB(spr_addr[7:0]), + .DIB(16'h0000), + .ENB(1'b1), + .WEB(1'b0), + .DOB(tbim_dat_o[31:16]) +); + +RAMB4_S16_S16 tbar_ramb4_s16_0( + .CLKA(clk), + .RSTA(rst), + .ADDRA(tb_wadr), + .DIA(rf_dataw[15:0]), + .ENA(1'b1), + .WEA(tb_enw), + .DOA(), + + .CLKB(clk), + .RSTB(rst), + .ADDRB(spr_addr[7:0]), + .DIB(16'h0000), + .ENB(1'b1), + .WEB(1'b0), + .DOB(tbar_dat_o[15:0]) +); + +RAMB4_S16_S16 tbar_ramb4_s16_1( + .CLKA(clk), + .RSTA(rst), + .ADDRA(tb_wadr), + .DIA(rf_dataw[31:16]), + .ENA(1'b1), + .WEA(tb_enw), + .DOA(), + + .CLKB(clk), + .RSTB(rst), + .ADDRB(spr_addr[7:0]), + .DIB(16'h0000), + .ENB(1'b1), + .WEB(1'b0), + .DOB(tbar_dat_o[31:16]) +); + +RAMB4_S16_S16 tbts_ramb4_s16_0( + .CLKA(clk), + .RSTA(rst), + .ADDRA(tb_wadr), + .DIA(tb_timstmp[15:0]), + .ENA(1'b1), + .WEA(tb_enw), + .DOA(), + + .CLKB(clk), + .RSTB(rst), + .ADDRB(spr_addr[7:0]), + .DIB(16'h0000), + .ENB(1'b1), + .WEB(1'b0), + .DOB(tbts_dat_o[15:0]) +); + +RAMB4_S16_S16 tbts_ramb4_s16_1( + .CLKA(clk), + .RSTA(rst), + .ADDRA(tb_wadr), + .DIA(tb_timstmp[31:16]), + .ENA(1'b1), + .WEA(tb_enw), + .DOA(), + + .CLKB(clk), + .RSTB(rst), + .ADDRB(spr_addr[7:0]), + .DIB(16'h0000), + .ENB(1'b1), + .WEB(1'b0), + .DOB(tbts_dat_o[31:16]) +); + +`else +assign tbia_dat_o = 32'h0000_0000; +assign tbim_dat_o = 32'h0000_0000; +assign tbar_dat_o = 32'h0000_0000; +assign tbts_dat_o = 32'h0000_0000; + +`endif // OR1200_DU_TB_IMPLEMENTED + +`else // OR1200_DU_IMPLEMENTED + +// +// When DU is not implemented, drive all outputs as would when DU is disabled +// +assign dbg_bp_o = 1'b0; +assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}}; + +// +// Read DU registers +// +`ifdef OR1200_DU_READREGS +assign spr_dat_o = 32'h0000_0000; +`ifdef OR1200_DU_UNUSED_ZERO +`endif +`endif + +`endif + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_cpu.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_cpu.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_cpu.v (revision 995) @@ -0,0 +1,741 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's CPU //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ, //// +//// ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.9 2002/03/29 16:29:37 lampret +// Fixed some ports in instnatiations that were removed from the modules +// +// Revision 1.8 2002/03/29 15:16:54 lampret +// Some of the warnings fixed. +// +// Revision 1.7 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.6 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.5 2002/01/28 01:15:59 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.4 2002/01/18 14:21:43 lampret +// Fixed 'the NPC single-step fix'. +// +// Revision 1.3 2002/01/18 07:56:00 lampret +// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.19 2001/11/30 18:59:47 simons +// *** empty log message *** +// +// Revision 1.18 2001/11/23 21:42:31 simons +// Program counter divided to PPC and NPC. +// +// Revision 1.17 2001/11/23 08:38:51 lampret +// Changed DSR/DRR behavior and exception detection. +// +// Revision 1.16 2001/11/20 00:57:22 lampret +// Fixed width of du_except. +// +// Revision 1.15 2001/11/18 09:58:28 lampret +// Fixed some l.trap typos. +// +// Revision 1.14 2001/11/18 08:36:28 lampret +// For GDB changed single stepping and disabled trap exception. +// +// Revision 1.13 2001/11/13 10:02:21 lampret +// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) +// +// Revision 1.12 2001/11/12 01:45:40 lampret +// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. +// +// Revision 1.11 2001/11/10 03:43:57 lampret +// Fixed exceptions. +// +// Revision 1.10 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.9 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:35 igorm +// no message +// +// Revision 1.4 2001/08/17 08:01:19 lampret +// IC enable/disable. +// +// Revision 1.3 2001/08/13 03:36:20 lampret +// Added cfg regs. Moved all defines into one defines.v file. More cleanup. +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_cpu( + // Clk & Rst + clk, rst, + + // Insn interface + ic_en, + icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o, + icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i, + immu_en, + + // Debug unit + ex_insn, ex_freeze, branch_op, + spr_dat_npc, rf_dataw, + du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_except, du_dat_cpu, + + // Data interface + dc_en, + dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o, + dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i, + dmmu_en, + + // Interrupt & tick exceptions + sig_int, sig_tick, + + // SPR interface + supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm, + spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_REGFILE_ADDR_WIDTH; + +// +// I/O ports +// + +// +// Clk & Rst +// +input clk; +input rst; + +// +// Insn (IC) interface +// +output ic_en; +output [31:0] icpu_adr_o; +output icpu_cycstb_o; +output [3:0] icpu_sel_o; +output [3:0] icpu_tag_o; +input [31:0] icpu_dat_i; +input icpu_ack_i; +input icpu_rty_i; +input icpu_err_i; +input [31:0] icpu_adr_i; +input [3:0] icpu_tag_i; + +// +// Insn (IMMU) interface +// +output immu_en; + +// +// Debug interface +// +output [31:0] ex_insn; +output ex_freeze; +output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; + +input du_stall; +input [dw-1:0] du_addr; +input [dw-1:0] du_dat_du; +input du_read; +input du_write; +input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; +output [12:0] du_except; +output [dw-1:0] du_dat_cpu; +output [dw-1:0] rf_dataw; + +// +// Data (DC) interface +// +output [31:0] dcpu_adr_o; +output dcpu_cycstb_o; +output dcpu_we_o; +output [3:0] dcpu_sel_o; +output [3:0] dcpu_tag_o; +output [31:0] dcpu_dat_o; +input [31:0] dcpu_dat_i; +input dcpu_ack_i; +input dcpu_rty_i; +input dcpu_err_i; +input [3:0] dcpu_tag_i; +output dc_en; + +// +// Data (DMMU) interface +// +output dmmu_en; + +// +// SPR interface +// +output supv; +input [dw-1:0] spr_dat_pic; +input [dw-1:0] spr_dat_tt; +input [dw-1:0] spr_dat_pm; +input [dw-1:0] spr_dat_dmmu; +input [dw-1:0] spr_dat_immu; +input [dw-1:0] spr_dat_du; +output [dw-1:0] spr_addr; +output [dw-1:0] spr_dat_cpu; +output [dw-1:0] spr_dat_npc; +output [31:0] spr_cs; +output spr_we; + +// +// Interrupt exceptions +// +input sig_int; +input sig_tick; + +// +// Internal wires +// +wire [31:0] if_insn; +wire [31:0] if_pc; +wire [31:2] lr_sav; +wire [aw-1:0] rf_addrw; +wire [aw-1:0] rf_addra; +wire [aw-1:0] rf_addrb; +wire rf_rda; +wire rf_rdb; +wire [dw-1:0] simm; +wire [dw-1:2] branch_addrofs; +wire [`OR1200_ALUOP_WIDTH-1:0] alu_op; +wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; +wire [`OR1200_COMPOP_WIDTH-1:0] comp_op; +wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +wire [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +wire genpc_freeze; +wire if_freeze; +wire id_freeze; +wire ex_freeze; +wire wb_freeze; +wire [`OR1200_SEL_WIDTH-1:0] sel_a; +wire [`OR1200_SEL_WIDTH-1:0] sel_b; +wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; +wire [dw-1:0] rf_dataw; +wire [dw-1:0] rf_dataa; +wire [dw-1:0] rf_datab; +wire [dw-1:0] muxed_b; +wire [dw-1:0] wb_forw; +wire wbforw_valid; +wire [dw-1:0] operand_a; +wire [dw-1:0] operand_b; +wire [dw-1:0] alu_dataout; +wire [dw-1:0] lsu_dataout; +wire [dw-1:0] sprs_dataout; +wire [31:0] lsu_addrofs; +wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; +wire [`OR1200_EXCEPT_WIDTH-1:0] except_type; +wire flushpipe; +wire extend_flush; +wire branch_taken; +wire flag; +wire flagforw; +wire flag_we; +wire lsu_stall; +wire epcr_we; +wire eear_we; +wire esr_we; +wire pc_we; +wire [31:0] epcr; +wire [31:0] eear; +wire [`OR1200_SR_WIDTH-1:0] esr; +wire [`OR1200_SR_WIDTH-1:0] sr; +wire except_start; +wire except_started; +wire [31:0] wb_insn; +wire [15:0] spr_addrimm; +wire sig_syscall; +wire sig_trap; +wire [31:0] spr_dat_cfgr; +wire [31:0] spr_dat_rf; +wire [31:0] spr_dat_npc; +wire [31:0] spr_dat_ppc; +wire [31:0] spr_dat_mac; +wire force_dslot_fetch; +wire no_more_dslot; +wire ex_void; +wire if_stall; +wire id_macrc_op; +wire ex_macrc_op; +wire [`OR1200_MACOP_WIDTH-1:0] mac_op; +wire [31:0] mult_mac_result; +wire mac_stall; +wire [12:0] except_stop; +wire genpc_refetch; +wire rfe; +wire lsu_unstall; +wire except_align; +wire except_dtlbmiss; +wire except_dmmufault; +wire except_illegal; +wire except_itlbmiss; +wire except_immufault; +wire except_ibuserr; +wire except_dbuserr; +wire abort_ex; + +// +// Send exceptions to Debug Unit +// +assign du_except = except_stop; + +// +// Data cache enable +// +assign dc_en = sr[`OR1200_SR_DCE]; + +// +// Instruction cache enable +// +assign ic_en = sr[`OR1200_SR_ICE]; + +// +// DMMU enable +// +assign dmmu_en = sr[`OR1200_SR_DME]; + +// +// IMMU enable +// +assign immu_en = sr[`OR1200_SR_IME]; + +// +// SUPV bit +// +assign supv = sr[`OR1200_SR_SM]; + +// +// Instantiation of instruction fetch block +// +or1200_genpc or1200_genpc( + .clk(clk), + .rst(rst), + .icpu_adr_o(icpu_adr_o), + .icpu_cycstb_o(icpu_cycstb_o), + .icpu_sel_o(icpu_sel_o), + .icpu_tag_o(icpu_tag_o), + .icpu_rty_i(icpu_rty_i), + .icpu_adr_i(icpu_adr_i), + + .branch_op(branch_op), + .except_type(except_type), + .except_start(except_start), + .except_prefix(sr[`OR1200_SR_EPH]), + .branch_addrofs(branch_addrofs), + .lr_restor(operand_b), + .flag(flag), + .taken(branch_taken), + .binsn_addr(lr_sav), + .epcr(epcr), + .spr_dat_i(spr_dat_cpu), + .spr_pc_we(pc_we), + .genpc_refetch(genpc_refetch), + .genpc_freeze(genpc_freeze), + .no_more_dslot(no_more_dslot) +); + +// +// Instantiation of instruction fetch block +// +or1200_if or1200_if( + .clk(clk), + .rst(rst), + .icpu_dat_i(icpu_dat_i), + .icpu_ack_i(icpu_ack_i), + .icpu_err_i(icpu_err_i), + .icpu_adr_i(icpu_adr_i), + .icpu_tag_i(icpu_tag_i), + + .if_freeze(if_freeze), + .if_insn(if_insn), + .if_pc(if_pc), + .flushpipe(flushpipe), + .if_stall(if_stall), + .no_more_dslot(no_more_dslot), + .genpc_refetch(genpc_refetch), + .rfe(rfe), + .except_itlbmiss(except_itlbmiss), + .except_immufault(except_immufault), + .except_ibuserr(except_ibuserr) +); + +// +// Instantiation of instruction decode/control logic +// +or1200_ctrl or1200_ctrl( + .clk(clk), + .rst(rst), + .id_freeze(id_freeze), + .ex_freeze(ex_freeze), + .wb_freeze(wb_freeze), + .flushpipe(flushpipe), + .if_insn(if_insn), + .ex_insn(ex_insn), + .branch_op(branch_op), + .branch_taken(branch_taken), + .rf_addra(rf_addra), + .rf_addrb(rf_addrb), + .rf_rda(rf_rda), + .rf_rdb(rf_rdb), + .alu_op(alu_op), + .mac_op(mac_op), + .shrot_op(shrot_op), + .comp_op(comp_op), + .rf_addrw(rf_addrw), + .rfwb_op(rfwb_op), + .wb_insn(wb_insn), + .simm(simm), + .branch_addrofs(branch_addrofs), + .lsu_addrofs(lsu_addrofs), + .sel_a(sel_a), + .sel_b(sel_b), + .lsu_op(lsu_op), + .multicycle(multicycle), + .spr_addrimm(spr_addrimm), + .wbforw_valid(wbforw_valid), + .sig_syscall(sig_syscall), + .sig_trap(sig_trap), + .force_dslot_fetch(force_dslot_fetch), + .no_more_dslot(no_more_dslot), + .ex_void(ex_void), + .id_macrc_op(id_macrc_op), + .ex_macrc_op(ex_macrc_op), + .rfe(rfe), + .except_illegal(except_illegal) +); + +// +// Instantiation of register file +// +or1200_rf or1200_rf( + .clk(clk), + .rst(rst), + .supv(sr[`OR1200_SR_SM]), + .wb_freeze(wb_freeze), + .addrw(rf_addrw), + .dataw(rf_dataw), + .id_freeze(id_freeze), + .we(rfwb_op[0]), + .flushpipe(flushpipe), + .addra(rf_addra), + .rda(rf_rda), + .dataa(rf_dataa), + .addrb(rf_addrb), + .rdb(rf_rdb), + .datab(rf_datab), + .spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]), + .spr_write(spr_we), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_cpu), + .spr_dat_o(spr_dat_rf) +); + +// +// Instantiation of operand muxes +// +or1200_operandmuxes or1200_operandmuxes( + .clk(clk), + .rst(rst), + .id_freeze(id_freeze), + .ex_freeze(ex_freeze), + .rf_dataa(rf_dataa), + .rf_datab(rf_datab), + .ex_forw(rf_dataw), + .wb_forw(wb_forw), + .simm(simm), + .sel_a(sel_a), + .sel_b(sel_b), + .operand_a(operand_a), + .operand_b(operand_b), + .muxed_b(muxed_b) +); + +// +// Instantiation of CPU's ALU +// +or1200_alu or1200_alu( + .a(operand_a), + .b(operand_b), + .mult_mac_result(mult_mac_result), + .macrc_op(ex_macrc_op), + .alu_op(alu_op), + .shrot_op(shrot_op), + .comp_op(comp_op), + .result(alu_dataout), + .flagforw(flagforw), + .flag_we(flag_we) +); + +// +// Instantiation of CPU's ALU +// +or1200_mult_mac or1200_mult_mac( + .clk(clk), + .rst(rst), + .ex_freeze(ex_freeze), + .id_macrc_op(id_macrc_op), + .macrc_op(ex_macrc_op), + .a(operand_a), + .b(operand_b), + .mac_op(mac_op), + .alu_op(alu_op), + .result(mult_mac_result), + .mac_stall_r(mac_stall), + .spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]), + .spr_write(spr_we), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_cpu), + .spr_dat_o(spr_dat_mac) +); + +// +// Instantiation of CPU's SPRS block +// +or1200_sprs or1200_sprs( + .clk(clk), + .rst(rst), + .addrbase(operand_a), + .addrofs(spr_addrimm), + .dat_i(operand_b), + .alu_op(alu_op), + .flagforw(flagforw), + .flag_we(flag_we), + .flag(flag), + .to_wbmux(sprs_dataout), + + .du_addr(du_addr), + .du_dat_du(du_dat_du), + .du_read(du_read), + .du_write(du_write), + .du_dat_cpu(du_dat_cpu), + + .spr_addr(spr_addr), + .spr_dat_pic(spr_dat_pic), + .spr_dat_tt(spr_dat_tt), + .spr_dat_pm(spr_dat_pm), + .spr_dat_cfgr(spr_dat_cfgr), + .spr_dat_rf(spr_dat_rf), + .spr_dat_npc(spr_dat_npc), + .spr_dat_ppc(spr_dat_ppc), + .spr_dat_mac(spr_dat_mac), + .spr_dat_dmmu(spr_dat_dmmu), + .spr_dat_immu(spr_dat_immu), + .spr_dat_du(spr_dat_du), + .spr_dat_o(spr_dat_cpu), + .spr_cs(spr_cs), + .spr_we(spr_we), + + .epcr_we(epcr_we), + .eear_we(eear_we), + .esr_we(esr_we), + .pc_we(pc_we), + .epcr(epcr), + .eear(eear), + .esr(esr), + .except_started(except_started), + + .sr(sr), + .branch_op(branch_op) +); + +// +// Instantiation of load/store unit +// +or1200_lsu or1200_lsu( + .addrbase(operand_a), + .addrofs(lsu_addrofs), + .lsu_op(lsu_op), + .lsu_datain(operand_b), + .lsu_dataout(lsu_dataout), + .lsu_stall(lsu_stall), + .lsu_unstall(lsu_unstall), + .du_stall(du_stall), + .except_align(except_align), + .except_dtlbmiss(except_dtlbmiss), + .except_dmmufault(except_dmmufault), + .except_dbuserr(except_dbuserr), + + .dcpu_adr_o(dcpu_adr_o), + .dcpu_cycstb_o(dcpu_cycstb_o), + .dcpu_we_o(dcpu_we_o), + .dcpu_sel_o(dcpu_sel_o), + .dcpu_tag_o(dcpu_tag_o), + .dcpu_dat_o(dcpu_dat_o), + .dcpu_dat_i(dcpu_dat_i), + .dcpu_ack_i(dcpu_ack_i), + .dcpu_rty_i(dcpu_rty_i), + .dcpu_err_i(dcpu_err_i), + .dcpu_tag_i(dcpu_tag_i) +); + +// +// Instantiation of write-back muxes +// +or1200_wbmux or1200_wbmux( + .clk(clk), + .rst(rst), + .wb_freeze(wb_freeze), + .rfwb_op(rfwb_op), + .muxin_a(alu_dataout), + .muxin_b(lsu_dataout), + .muxin_c(sprs_dataout), + .muxin_d({lr_sav, 2'b0}), + .muxout(rf_dataw), + .muxreg(wb_forw), + .muxreg_valid(wbforw_valid) +); + +// +// Instantiation of freeze logic +// +or1200_freeze or1200_freeze( + .clk(clk), + .rst(rst), + .multicycle(multicycle), + .flushpipe(flushpipe), + .extend_flush(extend_flush), + .lsu_stall(lsu_stall), + .if_stall(if_stall), + .lsu_unstall(lsu_unstall), + .force_dslot_fetch(force_dslot_fetch), + .abort_ex(abort_ex), + .du_stall(du_stall), + .mac_stall(mac_stall), + .genpc_freeze(genpc_freeze), + .if_freeze(if_freeze), + .id_freeze(id_freeze), + .ex_freeze(ex_freeze), + .wb_freeze(wb_freeze), + .icpu_ack_i(icpu_ack_i), + .icpu_err_i(icpu_err_i) +); + +// +// Instantiation of exception block +// +or1200_except or1200_except( + .clk(clk), + .rst(rst), + .sig_ibuserr(except_ibuserr), + .sig_dbuserr(except_dbuserr), + .sig_illegal(except_illegal), + .sig_align(except_align), + .sig_range(1'b0), + .sig_dtlbmiss(except_dtlbmiss), + .sig_dmmufault(except_dmmufault), + .sig_int(sig_int), + .sig_syscall(sig_syscall), + .sig_trap(sig_trap), + .sig_itlbmiss(except_itlbmiss), + .sig_immufault(except_immufault), + .sig_tick(sig_tick), + .branch_taken(branch_taken), + .icpu_ack_i(icpu_ack_i), + .icpu_err_i(icpu_err_i), + .dcpu_ack_i(dcpu_ack_i), + .dcpu_err_i(dcpu_err_i), + .genpc_freeze(genpc_freeze), + .id_freeze(id_freeze), + .ex_freeze(ex_freeze), + .wb_freeze(wb_freeze), + .if_stall(if_stall), + .if_pc(if_pc), + .lr_sav(lr_sav), + .flushpipe(flushpipe), + .extend_flush(extend_flush), + .except_type(except_type), + .except_start(except_start), + .except_started(except_started), + .except_stop(except_stop), + .ex_void(ex_void), + .spr_dat_ppc(spr_dat_ppc), + .spr_dat_npc(spr_dat_npc), + + .datain(operand_b), + .du_dsr(du_dsr), + .epcr_we(epcr_we), + .eear_we(eear_we), + .esr_we(esr_we), + .pc_we(pc_we), + .epcr(epcr), + .eear(eear), + .esr(esr), + + .lsu_addr(dcpu_adr_o), + .sr(sr), + .abort_ex(abort_ex) +); + +// +// Instantiation of configuration registers +// +or1200_cfgr or1200_cfgr( + .spr_addr(spr_addr), + .spr_dat_o(spr_dat_cfgr) +); + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_xcv_ram32x8d.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_xcv_ram32x8d.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_xcv_ram32x8d.v (revision 995) @@ -0,0 +1,588 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Xilinx Virtex RAM 32x8D //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Virtex dual-port memory //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.7 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.6 2001/10/14 13:12:10 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +`ifdef OR1200_XILINX_RAM32X1D +`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D +module or1200_xcv_ram32x8d +( + DPO, + SPO, + A, + D, + DPRA, + WCLK, + WE +); +output [7:0] DPO; +output [7:0] SPO; +input [4:0] A; +input [4:0] DPRA; +input [7:0] D; +input WCLK; +input WE; + +wire [7:0] DPO_0; +wire [7:0] SPO_0; + +wire [7:0] DPO_1; +wire [7:0] SPO_1; + +wire WE_0 ; +wire WE_1 ; + +assign DPO = DPRA[4] ? DPO_1 : DPO_0 ; +assign SPO = A[4] ? SPO_1 : SPO_0 ; + +assign WE_0 = !A[4] && WE ; +assign WE_1 = A[4] && WE ; + +RAM16X1D ram32x1d_0_0( + .DPO(DPO_0[0]), + .SPO(SPO_0[0]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[0]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_0) +); + +// +// Instantiation of block 1 +// +RAM16X1D ram32x1d_0_1( + .DPO(DPO_0[1]), + .SPO(SPO_0[1]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[1]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_0) +); + +// +// Instantiation of block 2 +// +RAM16X1D ram32x1d_0_2( + .DPO(DPO_0[2]), + .SPO(SPO_0[2]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[2]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_0) +); + +// +// Instantiation of block 3 +// +RAM16X1D ram32x1d_0_3( + .DPO(DPO_0[3]), + .SPO(SPO_0[3]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[3]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_0) +); + +// +// Instantiation of block 4 +// +RAM16X1D ram32x1d_0_4( + .DPO(DPO_0[4]), + .SPO(SPO_0[4]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[4]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_0) +); + +// +// Instantiation of block 5 +// +RAM16X1D ram32x1d_0_5( + .DPO(DPO_0[5]), + .SPO(SPO_0[5]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[5]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_0) +); + +// +// Instantiation of block 6 +// +RAM16X1D ram32x1d_0_6( + .DPO(DPO_0[6]), + .SPO(SPO_0[6]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[6]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_0) +); + +// +// Instantiation of block 7 +// +RAM16X1D ram32x1d_0_7( + .DPO(DPO_0[7]), + .SPO(SPO_0[7]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[7]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_0) +); + +RAM16X1D ram32x1d_1_0( + .DPO(DPO_1[0]), + .SPO(SPO_1[0]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[0]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_1) +); + +// +// Instantiation of block 1 +// +RAM16X1D ram32x1d_1_1( + .DPO(DPO_1[1]), + .SPO(SPO_1[1]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[1]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_1) +); + +// +// Instantiation of block 2 +// +RAM16X1D ram32x1d_1_2( + .DPO(DPO_1[2]), + .SPO(SPO_1[2]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[2]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_1) +); + +// +// Instantiation of block 3 +// +RAM16X1D ram32x1d_1_3( + .DPO(DPO_1[3]), + .SPO(SPO_1[3]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[3]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_1) +); + +// +// Instantiation of block 4 +// +RAM16X1D ram32x1d_1_4( + .DPO(DPO_1[4]), + .SPO(SPO_1[4]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[4]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_1) +); + +// +// Instantiation of block 5 +// +RAM16X1D ram32x1d_1_5( + .DPO(DPO_1[5]), + .SPO(SPO_1[5]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[5]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_1) +); + +// +// Instantiation of block 6 +// +RAM16X1D ram32x1d_1_6( + .DPO(DPO_1[6]), + .SPO(SPO_1[6]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[6]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_1) +); + +// +// Instantiation of block 7 +// +RAM16X1D ram32x1d_1_7( + .DPO(DPO_1[7]), + .SPO(SPO_1[7]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .D(D[7]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .WCLK(WCLK), + .WE(WE_1) +); +endmodule + +`else + +module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE); + +// +// I/O +// +output [7:0] DPO; +output [7:0] SPO; +input [4:0] A; +input [4:0] DPRA; +input [7:0] D; +input WCLK; +input WE; + +// +// Instantiation of block 0 +// +RAM32X1D ram32x1d_0( + .DPO(DPO[0]), + .SPO(SPO[0]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .A4(A[4]), + .D(D[0]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .DPRA4(DPRA[4]), + .WCLK(WCLK), + .WE(WE) +); + +// +// Instantiation of block 1 +// +RAM32X1D ram32x1d_1( + .DPO(DPO[1]), + .SPO(SPO[1]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .A4(A[4]), + .D(D[1]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .DPRA4(DPRA[4]), + .WCLK(WCLK), + .WE(WE) +); + +// +// Instantiation of block 2 +// +RAM32X1D ram32x1d_2( + .DPO(DPO[2]), + .SPO(SPO[2]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .A4(A[4]), + .D(D[2]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .DPRA4(DPRA[4]), + .WCLK(WCLK), + .WE(WE) +); + +// +// Instantiation of block 3 +// +RAM32X1D ram32x1d_3( + .DPO(DPO[3]), + .SPO(SPO[3]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .A4(A[4]), + .D(D[3]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .DPRA4(DPRA[4]), + .WCLK(WCLK), + .WE(WE) +); + +// +// Instantiation of block 4 +// +RAM32X1D ram32x1d_4( + .DPO(DPO[4]), + .SPO(SPO[4]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .A4(A[4]), + .D(D[4]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .DPRA4(DPRA[4]), + .WCLK(WCLK), + .WE(WE) +); + +// +// Instantiation of block 5 +// +RAM32X1D ram32x1d_5( + .DPO(DPO[5]), + .SPO(SPO[5]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .A4(A[4]), + .D(D[5]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .DPRA4(DPRA[4]), + .WCLK(WCLK), + .WE(WE) +); + +// +// Instantiation of block 6 +// +RAM32X1D ram32x1d_6( + .DPO(DPO[6]), + .SPO(SPO[6]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .A4(A[4]), + .D(D[6]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .DPRA4(DPRA[4]), + .WCLK(WCLK), + .WE(WE) +); + +// +// Instantiation of block 7 +// +RAM32X1D ram32x1d_7( + .DPO(DPO[7]), + .SPO(SPO[7]), + .A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(A[3]), + .A4(A[4]), + .D(D[7]), + .DPRA0(DPRA[0]), + .DPRA1(DPRA[1]), + .DPRA2(DPRA[2]), + .DPRA3(DPRA[3]), + .DPRA4(DPRA[4]), + .WCLK(WCLK), + .WE(WE) +); + +endmodule +`endif +`endif Index: tags/rel_3/or1200/rtl/verilog/or1200_rfram_generic.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_rfram_generic.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_rfram_generic.v (revision 995) @@ -0,0 +1,246 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's register file generic memory //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Generic (flip-flop based) register file memory //// +//// //// +//// To Do: //// +//// - nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// $Log: not supported by cvs2svn $ +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_rfram_generic( + // Clock and reset + clk, rst, + + // Port A + ce_a, addr_a, do_a, + + // Port B + ce_b, addr_b, do_b, + + // Port W + ce_w, we_w, addr_w, di_w +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_REGFILE_ADDR_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// Port A +// +input ce_a; +input [aw-1:0] addr_a; +output [dw-1:0] do_a; + +// +// Port B +// +input ce_b; +input [aw-1:0] addr_b; +output [dw-1:0] do_b; + +// +// Port W +// +input ce_w; +input we_w; +input [aw-1:0] addr_w; +input [dw-1:0] di_w; + +// +// Internal wires and regs +// +reg [aw-1:0] intaddr_a; +reg [aw-1:0] intaddr_b; +reg [32*dw-1:0] mem; +reg [dw-1:0] do_a; +reg [dw-1:0] do_b; + +// +// Write port +// +always @(posedge clk or posedge rst) + if (rst) begin + mem <= #1 1024'h0; + end + else if (ce_w & we_w) + case (addr_w) // synopsys parallel_case full_case + 5'd00: mem[32*0+31:32*0] <= #1 di_w; + 5'd01: mem[32*1+31:32*1] <= #1 di_w; + 5'd02: mem[32*2+31:32*2] <= #1 di_w; + 5'd03: mem[32*3+31:32*3] <= #1 di_w; + 5'd04: mem[32*4+31:32*4] <= #1 di_w; + 5'd05: mem[32*5+31:32*5] <= #1 di_w; + 5'd06: mem[32*6+31:32*6] <= #1 di_w; + 5'd07: mem[32*7+31:32*7] <= #1 di_w; + 5'd08: mem[32*8+31:32*8] <= #1 di_w; + 5'd09: mem[32*9+31:32*9] <= #1 di_w; + 5'd10: mem[32*10+31:32*10] <= #1 di_w; + 5'd11: mem[32*11+31:32*11] <= #1 di_w; + 5'd12: mem[32*12+31:32*12] <= #1 di_w; + 5'd13: mem[32*13+31:32*13] <= #1 di_w; + 5'd14: mem[32*14+31:32*14] <= #1 di_w; + 5'd15: mem[32*15+31:32*15] <= #1 di_w; + 5'd16: mem[32*16+31:32*16] <= #1 di_w; + 5'd17: mem[32*17+31:32*17] <= #1 di_w; + 5'd18: mem[32*18+31:32*18] <= #1 di_w; + 5'd19: mem[32*19+31:32*19] <= #1 di_w; + 5'd20: mem[32*20+31:32*20] <= #1 di_w; + 5'd21: mem[32*21+31:32*21] <= #1 di_w; + 5'd22: mem[32*22+31:32*22] <= #1 di_w; + 5'd23: mem[32*23+31:32*23] <= #1 di_w; + 5'd24: mem[32*24+31:32*24] <= #1 di_w; + 5'd25: mem[32*25+31:32*25] <= #1 di_w; + 5'd26: mem[32*26+31:32*26] <= #1 di_w; + 5'd27: mem[32*27+31:32*27] <= #1 di_w; + 5'd28: mem[32*28+31:32*28] <= #1 di_w; + 5'd29: mem[32*29+31:32*29] <= #1 di_w; + 5'd30: mem[32*30+31:32*30] <= #1 di_w; + 5'd31: mem[32*31+31:32*31] <= #1 di_w; + endcase + +// +// Read port A +// +always @(posedge clk or posedge rst) + if (rst) begin + intaddr_a <= #1 5'h00; + end + else if (ce_a) + intaddr_a <= #1 addr_a; + +always @(mem or intaddr_a) + case (intaddr_a) // synopsys parallel_case full_case + 5'd00: do_a = mem[32*0+31:32*0]; + 5'd01: do_a = mem[32*1+31:32*1]; + 5'd02: do_a = mem[32*2+31:32*2]; + 5'd03: do_a = mem[32*3+31:32*3]; + 5'd04: do_a = mem[32*4+31:32*4]; + 5'd05: do_a = mem[32*5+31:32*5]; + 5'd06: do_a = mem[32*6+31:32*6]; + 5'd07: do_a = mem[32*7+31:32*7]; + 5'd08: do_a = mem[32*8+31:32*8]; + 5'd09: do_a = mem[32*9+31:32*9]; + 5'd10: do_a = mem[32*10+31:32*10]; + 5'd11: do_a = mem[32*11+31:32*11]; + 5'd12: do_a = mem[32*12+31:32*12]; + 5'd13: do_a = mem[32*13+31:32*13]; + 5'd14: do_a = mem[32*14+31:32*14]; + 5'd15: do_a = mem[32*15+31:32*15]; + 5'd16: do_a = mem[32*16+31:32*16]; + 5'd17: do_a = mem[32*17+31:32*17]; + 5'd18: do_a = mem[32*18+31:32*18]; + 5'd19: do_a = mem[32*19+31:32*19]; + 5'd20: do_a = mem[32*20+31:32*20]; + 5'd21: do_a = mem[32*21+31:32*21]; + 5'd22: do_a = mem[32*22+31:32*22]; + 5'd23: do_a = mem[32*23+31:32*23]; + 5'd24: do_a = mem[32*24+31:32*24]; + 5'd25: do_a = mem[32*25+31:32*25]; + 5'd26: do_a = mem[32*26+31:32*26]; + 5'd27: do_a = mem[32*27+31:32*27]; + 5'd28: do_a = mem[32*28+31:32*28]; + 5'd29: do_a = mem[32*29+31:32*29]; + 5'd30: do_a = mem[32*30+31:32*30]; + 5'd31: do_a = mem[32*31+31:32*31]; + endcase + +// +// Read port B +// +always @(posedge clk or posedge rst) + if (rst) begin + intaddr_b <= #1 5'h00; + end + else if (ce_b) + intaddr_b <= #1 addr_b; + +always @(mem or intaddr_b) + case (intaddr_b) // synopsys parallel_case full_case + 5'd00: do_b = mem[32*0+31:32*0]; + 5'd01: do_b = mem[32*1+31:32*1]; + 5'd02: do_b = mem[32*2+31:32*2]; + 5'd03: do_b = mem[32*3+31:32*3]; + 5'd04: do_b = mem[32*4+31:32*4]; + 5'd05: do_b = mem[32*5+31:32*5]; + 5'd06: do_b = mem[32*6+31:32*6]; + 5'd07: do_b = mem[32*7+31:32*7]; + 5'd08: do_b = mem[32*8+31:32*8]; + 5'd09: do_b = mem[32*9+31:32*9]; + 5'd10: do_b = mem[32*10+31:32*10]; + 5'd11: do_b = mem[32*11+31:32*11]; + 5'd12: do_b = mem[32*12+31:32*12]; + 5'd13: do_b = mem[32*13+31:32*13]; + 5'd14: do_b = mem[32*14+31:32*14]; + 5'd15: do_b = mem[32*15+31:32*15]; + 5'd16: do_b = mem[32*16+31:32*16]; + 5'd17: do_b = mem[32*17+31:32*17]; + 5'd18: do_b = mem[32*18+31:32*18]; + 5'd19: do_b = mem[32*19+31:32*19]; + 5'd20: do_b = mem[32*20+31:32*20]; + 5'd21: do_b = mem[32*21+31:32*21]; + 5'd22: do_b = mem[32*22+31:32*22]; + 5'd23: do_b = mem[32*23+31:32*23]; + 5'd24: do_b = mem[32*24+31:32*24]; + 5'd25: do_b = mem[32*25+31:32*25]; + 5'd26: do_b = mem[32*26+31:32*26]; + 5'd27: do_b = mem[32*27+31:32*27]; + 5'd28: do_b = mem[32*28+31:32*28]; + 5'd29: do_b = mem[32*29+31:32*29]; + 5'd30: do_b = mem[32*30+31:32*30]; + 5'd31: do_b = mem[32*31+31:32*31]; + endcase + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_rf.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_rf.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_rf.v (revision 995) @@ -0,0 +1,377 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's register file inside CPU //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instantiation of register file memories //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.13 2001/11/20 18:46:15 simons +// Break point bug fixed +// +// Revision 1.12 2001/11/13 10:02:21 lampret +// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) +// +// Revision 1.11 2001/11/12 01:45:40 lampret +// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. +// +// Revision 1.10 2001/11/10 03:43:57 lampret +// Fixed exceptions. +// +// Revision 1.9 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.8 2001/10/14 13:12:10 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.3 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/22 03:31:54 lampret +// Fixed RAM's oen bug. Cache bypass under development. +// +// Revision 1.1 2001/07/20 00:46:21 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_rf( + // Clock and reset + clk, rst, + + // Write i/f + supv, wb_freeze, addrw, dataw, we, flushpipe, + + // Read i/f + id_freeze, addra, addrb, dataa, datab, rda, rdb, + + // Debug + spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_REGFILE_ADDR_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// Write i/f +// +input supv; +input wb_freeze; +input [aw-1:0] addrw; +input [dw-1:0] dataw; +input we; +input flushpipe; + +// +// Read i/f +// +input id_freeze; +input [aw-1:0] addra; +input [aw-1:0] addrb; +output [dw-1:0] dataa; +output [dw-1:0] datab; +input rda; +input rdb; + +// +// SPR access for debugging purposes +// +input spr_cs; +input spr_write; +input [31:0] spr_addr; +input [31:0] spr_dat_i; +output [31:0] spr_dat_o; + +// +// Internal wires and regs +// +wire [dw-1:0] from_rfa; +wire [dw-1:0] from_rfb; +reg [dw:0] dataa_saved; +reg [dw:0] datab_saved; +wire [aw-1:0] rf_addra; +wire [aw-1:0] rf_addrw; +wire [dw-1:0] rf_dataw; +wire rf_we; +wire spr_valid; +wire rf_ena; +wire rf_enb; +reg rf_we_allow; + +// +// SPR access is valid when spr_cs is asserted and +// SPR address matches GPR addresses +// +assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF); + +// +// SPR data output is always from RF A +// +assign spr_dat_o = from_rfa; + +// +// Operand A comes from RF or from saved A register +// +assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa; + +// +// Operand B comes from RF or from saved B register +// +assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb; + +// +// RF A read address is either from SPRS or normal from CPU control +// +assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra; + +// +// RF write address is either from SPRS or normal from CPU control +// +assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw; + +// +// RF write data is either from SPRS or normal from CPU datapath +// +assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw; + +// +// RF write enable is either from SPRS or normal from CPU control +// +always @(posedge rst or posedge clk) + if (rst) + rf_we_allow <= #1 1'b1; + else if (~wb_freeze) + rf_we_allow <= #1 ~flushpipe; + +assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw)); + +// +// CS RF A asserted when instruction reads operand A and ID stage +// is not stalled +// +assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils +// assign rf_ena = 1'b1; // does not work with single-stepping +//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils + +// +// CS RF B asserted when instruction reads operand B and ID stage +// is not stalled +// +assign rf_enb = rdb & ~id_freeze | spr_valid; +// assign rf_enb = 1'b1; +//assign rf_enb = ~id_freeze | spr_valid; // works with broken binutils + +// +// Stores operand from RF_A into temp reg when pipeline is frozen +// +always @(posedge clk or posedge rst) + if (rst) begin + dataa_saved <= #1 33'b0; + end + else if (id_freeze & !dataa_saved[32]) begin + dataa_saved <= #1 {1'b1, from_rfa}; + end + else if (!id_freeze) + dataa_saved <= #1 33'b0; + +// +// Stores operand from RF_B into temp reg when pipeline is frozen +// +always @(posedge clk or posedge rst) + if (rst) begin + datab_saved <= #1 33'b0; + end + else if (id_freeze & !datab_saved[32]) begin + datab_saved <= #1 {1'b1, from_rfb}; + end + else if (!id_freeze) + datab_saved <= #1 33'b0; + +`ifdef OR1200_RFRAM_TWOPORT + +// +// Instantiation of register file two-port RAM A +// +or1200_tpram_32x32 rf_a( + // Port A + .clk_a(clk), + .rst_a(rst), + .ce_a(rf_ena), + .we_a(1'b0), + .oe_a(1'b1), + .addr_a(rf_addra), + .di_a(32'h0000_0000), + .do_a(from_rfa), + + // Port B + .clk_b(clk), + .rst_b(rst), + .ce_b(rf_we), + .we_b(rf_we), + .oe_b(1'b0), + .addr_b(rf_addrw), + .di_b(rf_dataw), + .do_b() +); + +// +// Instantiation of register file two-port RAM B +// +or1200_tpram_32x32 rf_b( + // Port A + .clk_a(clk), + .rst_a(rst), + .ce_a(rf_enb), + .we_a(1'b0), + .oe_a(1'b1), + .addr_a(addrb), + .di_a(32'h0000_0000), + .do_a(from_rfb), + + // Port B + .clk_b(clk), + .rst_b(rst), + .ce_b(rf_we), + .we_b(rf_we), + .oe_b(1'b0), + .addr_b(rf_addrw), + .di_b(rf_dataw), + .do_b() +); + +`else + +`ifdef OR1200_RFRAM_DUALPORT + +// +// Instantiation of register file two-port RAM A +// +or1200_dpram_32x32 rf_a( + // Port A + .clk_a(clk), + .rst_a(rst), + .ce_a(rf_ena), + .oe_a(1'b1), + .addr_a(rf_addra), + .do_a(from_rfa), + + // Port B + .clk_b(clk), + .rst_b(rst), + .ce_b(rf_we), + .we_b(rf_we), + .addr_b(rf_addrw), + .di_b(rf_dataw) +); + +// +// Instantiation of register file two-port RAM B +// +or1200_dpram_32x32 rf_b( + // Port A + .clk_a(clk), + .rst_a(rst), + .ce_a(rf_enb), + .oe_a(1'b1), + .addr_a(addrb), + .do_a(from_rfb), + + // Port B + .clk_b(clk), + .rst_b(rst), + .ce_b(rf_we), + .we_b(rf_we), + .addr_b(rf_addrw), + .di_b(rf_dataw) +); + +`else + +// +// Instantiation of generic (flip-flop based) register file +// +or1200_rfram_generic rf_a( + // Clock and reset + .clk(clk), + .rst(rst), + + // Port A + .ce_a(rf_ena), + .addr_a(rf_addra), + .do_a(from_rfa), + + // Port B + .ce_b(rf_enb), + .addr_b(addrb), + .do_b(from_rfb), + + // Port W + .ce_w(rf_we), + .we_w(rf_we), + .addr_w(rf_addrw), + .di_w(rf_dataw) +); + +`endif +`endif + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_alu.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_alu.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_alu.v (revision 995) @@ -0,0 +1,316 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's ALU //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// ALU //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.5 2002/03/29 16:33:59 lampret +// Added again just recently removed full_case directive +// +// Revision 1.4 2002/03/29 15:16:53 lampret +// Some of the warnings fixed. +// +// Revision 1.3 2002/01/28 01:15:59 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.10 2001/11/12 01:45:40 lampret +// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. +// +// Revision 1.9 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.8 2001/10/19 23:28:45 lampret +// Fixed some synthesis warnings. Configured with caches and MMUs. +// +// Revision 1.7 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:35 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_alu( + a, b, mult_mac_result, macrc_op, + alu_op, shrot_op, comp_op, + result, flagforw, flag_we +); + +parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// +input [width-1:0] a; +input [width-1:0] b; +input [width-1:0] mult_mac_result; +input macrc_op; +input [`OR1200_ALUOP_WIDTH-1:0] alu_op; +input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; +input [`OR1200_COMPOP_WIDTH-1:0] comp_op; +output [width-1:0] result; +output flagforw; +output flag_we; + +// +// Internal wires and regs +// +reg [width-1:0] result; +reg [width-1:0] shifted_rotated; +reg flagforw; +reg flagcomp; +reg flag_we; +// synopsys translate_off +`ifdef OR1200_SIM_ALU_DIV +integer d1; +integer d2; +`endif +// synopsys translate_on +wire [width-1:0] comp_a; +wire [width-1:0] comp_b; +`ifdef OR1200_IMPL_ALU_COMP1 +wire a_eq_b; +wire a_lt_b; +`endif +wire [width-1:0] result_sum; +wire [width-1:0] result_and; + +// +// Combinatorial logic +// +assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]}; +assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]}; +`ifdef OR1200_IMPL_ALU_COMP1 +assign a_eq_b = (comp_a == comp_b); +assign a_lt_b = (comp_a < comp_b); +`endif +assign result_sum = a + b; +assign result_and = a & b; + +// +// Simulation check for bad ALU behavior +// +`ifdef OR1200_WARNINGS +// synopsys translate_off +always @(result) begin + if (result === 32'bx) + $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time); +end +// synopsys translate_on +`endif + +// +// Central part of the ALU +// +always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin + casex (alu_op) // synopsys parallel_case full_case + `OR1200_ALUOP_SHROT : begin + result = shifted_rotated; + end + `OR1200_ALUOP_ADD : begin + result = result_sum; + end + `OR1200_ALUOP_SUB : begin + result = a - b; + end + `OR1200_ALUOP_XOR : begin + result = a ^ b; + end + `OR1200_ALUOP_OR : begin + result = a | b; + end + `OR1200_ALUOP_IMM : begin + result = b; + end + `OR1200_ALUOP_MOVHI : begin + if (macrc_op) begin + result = mult_mac_result; + end + else begin + result = b << 16; + end + end + `OR1200_ALUOP_MUL : begin + result = mult_mac_result; +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result); +// synopsys translate_on +`endif + end +// synopsys translate_off +`ifdef OR1200_SIM_ALU_DIV + `OR1200_ALUOP_DIV : begin + d1 = a; + d2 = b; + $display("DIV operation: %d / %d = %d", d1, d2, d1/d2); + if (d2) + result = d1 / d2; + else + result = 32'h00000000; + end +`endif +`ifdef OR1200_SIM_ALU_DIVU + `OR1200_ALUOP_DIVU : begin + if (b) + result = a / b; + else + result = 32'h00000000; + end +`endif +// synopsys translate_on + `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin + result = result_and; + end + endcase +end + +// +// Generate flag and flag write enable +// +always @(alu_op or result_sum or result_and or flagcomp) begin + casex (alu_op) // synopsys parallel_case + `OR1200_ALUOP_ADD : begin + flagforw = (result_sum == 32'h0000_0000); + flag_we = 1'b0; + end + `OR1200_ALUOP_AND: begin + flagforw = (result_and == 32'h0000_0000); + flag_we = 1'b0; + end + `OR1200_ALUOP_COMP: begin + flagforw = flagcomp; + flag_we = 1'b1; + end + default: begin + flagforw = 1'b0; + flag_we = 1'b0; + end + endcase +end + +// +// Shifts and rotation +// +always @(shrot_op or a or b) begin + case (shrot_op) // synopsys parallel_case + `OR1200_SHROTOP_SLL : + shifted_rotated = (a << b[4:0]); + `OR1200_SHROTOP_SRL : + shifted_rotated = (a >> b[4:0]); + +`ifdef OR1200_IMPL_ALU_ROTATE + `OR1200_SHROTOP_ROR : + shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]); +`endif + default: + shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0]; + endcase +end + +// +// First type of compare implementation +// +`ifdef OR1200_IMPL_ALU_COMP1 +always @(comp_op or a_eq_b or a_lt_b) begin + case(comp_op[2:0]) // synopsys parallel_case + `OR1200_COP_SFEQ: + flagcomp = a_eq_b; + `OR1200_COP_SFNE: + flagcomp = ~a_eq_b; + `OR1200_COP_SFGT: + flagcomp = ~(a_eq_b | a_lt_b); + `OR1200_COP_SFGE: + flagcomp = ~a_lt_b; + `OR1200_COP_SFLT: + flagcomp = a_lt_b; + `OR1200_COP_SFLE: + flagcomp = a_eq_b | a_lt_b; + default: + flagcomp = 1'b0; + endcase +end +`endif + +// +// Second type of compare implementation +// +`ifdef OR1200_IMPL_ALU_COMP2 +always @(comp_op or comp_a or comp_b) begin + case(comp_op[2:0]) // synopsys parallel_case + `OR1200_COP_SFEQ: + flagcomp = (comp_a == comp_b); + `OR1200_COP_SFNE: + flagcomp = (comp_a != comp_b); + `OR1200_COP_SFGT: + flagcomp = (comp_a > comp_b); + `OR1200_COP_SFGE: + flagcomp = (comp_a >= comp_b); + `OR1200_COP_SFLT: + flagcomp = (comp_a < comp_b); + `OR1200_COP_SFLE: + flagcomp = (comp_a <= comp_b); + default: + flagcomp = 1'b0; + endcase +end +`endif + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_ic_top.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_ic_top.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_ic_top.v (revision 995) @@ -0,0 +1,290 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Data Cache top level //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instantiation of all IC blocks. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.5 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.4 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.3 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.10 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF. +// +// Revision 1.9 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:35 igorm +// no message +// +// Revision 1.4 2001/08/13 03:36:20 lampret +// Added cfg regs. Moved all defines into one defines.v file. More cleanup. +// +// Revision 1.3 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/22 03:31:53 lampret +// Fixed RAM's oen bug. Cache bypass under development. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +// +// Data cache +// +module or1200_ic_top( + // Rst, clk and clock control + clk, rst, + + // External i/f + icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o, + icbiu_dat_i, icbiu_ack_i, icbiu_err_i, + + // Internal i/f + ic_en, + icimmu_adr_i, icimmu_cycstb_i, icimmu_ci_i, + icpu_sel_i, icpu_tag_i, + icpu_dat_o, icpu_ack_o, icimmu_rty_o, icimmu_err_o, icimmu_tag_o, + + // SPRs + spr_cs, spr_write, spr_dat_i +); + +parameter dw = `OR1200_OPERAND_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// External I/F +// +output [dw-1:0] icbiu_dat_o; +output [31:0] icbiu_adr_o; +output icbiu_cyc_o; +output icbiu_stb_o; +output icbiu_we_o; +output [3:0] icbiu_sel_o; +output icbiu_cab_o; +input [dw-1:0] icbiu_dat_i; +input icbiu_ack_i; +input icbiu_err_i; + +// +// Internal I/F +// +input ic_en; +input [31:0] icimmu_adr_i; +input icimmu_cycstb_i; +input icimmu_ci_i; +input [3:0] icpu_sel_i; +input [3:0] icpu_tag_i; +output [dw-1:0] icpu_dat_o; +output icpu_ack_o; +output icimmu_rty_o; +output icimmu_err_o; +output [3:0] icimmu_tag_o; + +// +// SPR access +// +input spr_cs; +input spr_write; +input [31:0] spr_dat_i; + +// +// Internal wires and regs +// +wire tag_v; +wire [`OR1200_ICTAG_W-2:0] tag; +wire [dw-1:0] to_icram; +wire [dw-1:0] from_icram; +wire [31:0] saved_addr; +wire [3:0] icram_we; +wire ictag_we; +wire [31:0] ic_addr; +wire icfsm_biu_read; +reg tagcomp_miss; +wire [`OR1200_ICINDXH:`OR1200_ICLS] ictag_addr; +wire ictag_en; +wire ictag_v; +wire ic_inv; +wire icfsm_first_hit_ack; +wire icfsm_first_miss_ack; +wire icfsm_first_miss_err; +wire icfsm_burst; +wire icfsm_tag_we; + +// +// Simple assignments +// +assign icbiu_adr_o = ic_addr; +assign ic_inv = spr_cs & spr_write; +assign ictag_we = icfsm_tag_we | ic_inv; +assign ictag_addr = ic_inv ? spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] : ic_addr[`OR1200_ICINDXH:`OR1200_ICLS]; +assign ictag_en = ic_inv | ic_en; +assign ictag_v = ~ic_inv; + +// +// Data to BIU is from ICRAM when IC is enabled or from LSU when +// IC is disabled +// +assign icbiu_dat_o = 32'h00000000; + +// +// Bypases of the IC when IC is disabled +// +assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icimmu_cycstb_i; +assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icimmu_cycstb_i; +assign icbiu_we_o = 1'b0; +assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icpu_sel_i; +assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0; +assign icimmu_rty_o = ~icpu_ack_o & ~icimmu_err_o; +assign icimmu_tag_o = icimmu_err_o ? `OR1200_ITAG_BE : icpu_tag_i; + +// +// CPU normal and error termination +// +assign icpu_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i; +assign icimmu_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i; + +// +// Select between claddr generated by IC FSM and addr[3:2] generated by LSU +// +assign ic_addr = (icfsm_biu_read) ? saved_addr : icimmu_adr_i; + +// +// Select between input data generated by LSU or by BIU +// +assign to_icram = icbiu_dat_i; + +// +// Select between data generated by ICRAM or passed by BIU +// +assign icpu_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram; + +// +// Tag comparison +// +always @(tag or saved_addr or tag_v) begin + if ((tag != saved_addr[31:`OR1200_ICTAGL]) || !tag_v) + tagcomp_miss = 1'b1; + else + tagcomp_miss = 1'b0; +end + +// +// Instantiation of IC Finite State Machine +// +or1200_ic_fsm or1200_ic_fsm( + .clk(clk), + .rst(rst), + .ic_en(ic_en), + .icimmu_cycstb_i(icimmu_cycstb_i), + .icimmu_ci_i(icimmu_ci_i), + .tagcomp_miss(tagcomp_miss), + .biudata_valid(icbiu_ack_i), + .biudata_error(icbiu_err_i), + .start_addr(icimmu_adr_i), + .saved_addr(saved_addr), + .icram_we(icram_we), + .biu_read(icfsm_biu_read), + .first_hit_ack(icfsm_first_hit_ack), + .first_miss_ack(icfsm_first_miss_ack), + .first_miss_err(icfsm_first_miss_err), + .burst(icfsm_burst), + .tag_we(icfsm_tag_we) +); + +// +// Instantiation of IC main memory +// +or1200_ic_ram or1200_ic_ram( + .clk(clk), + .rst(rst), + .addr(ic_addr[`OR1200_ICINDXH:2]), + .en(ic_en), + .we(icram_we), + .datain(to_icram), + .dataout(from_icram) +); + +// +// Instantiation of IC TAG memory +// +or1200_ic_tag or1200_ic_tag( + .clk(clk), + .rst(rst), + .addr(ictag_addr), + .en(ictag_en), + .we(ictag_we), + .datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}), + .tag_v(tag_v), + .tag(tag) +); + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_cfgr.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_cfgr.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_cfgr.v (revision 995) @@ -0,0 +1,231 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's VR, UPR and Configuration Registers //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// According to OR1K architectural and OR1200 specifications. //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.7 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.6 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:35 igorm +// no message +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:21 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_cfgr( + // RISC Internal Interface + spr_addr, spr_dat_o +); + +// +// RISC Internal Interface +// +input [31:0] spr_addr; // SPR Address +output [31:0] spr_dat_o; // SPR Read Data + +// +// Internal wires & registers +// +reg [31:0] spr_dat_o; // SPR Read Data + +`ifdef OR1200_CFGR_IMPLEMENTED + +// +// Implementation of VR, UPR and configuration registers +// +always @(spr_addr) +`ifdef OR1200_SYS_FULL_DECODE + if (!spr_addr[31:4]) +`endif + case(spr_addr[3:0]) // synopsys parallel_case + `OR1200_SPRGRP_SYS_VR: begin + spr_dat_o[`OR1200_VR_REV_BITS] = `OR1200_VR_REV; + spr_dat_o[`OR1200_VR_RES1_BITS] = `OR1200_VR_RES1; + spr_dat_o[`OR1200_VR_CFG_BITS] = `OR1200_VR_CFG; + spr_dat_o[`OR1200_VR_VER_BITS] = `OR1200_VR_VER; + end + `OR1200_SPRGRP_SYS_UPR: begin + spr_dat_o[`OR1200_UPR_UP_BITS] = `OR1200_UPR_UP; + spr_dat_o[`OR1200_UPR_DCP_BITS] = `OR1200_UPR_DCP; + spr_dat_o[`OR1200_UPR_ICP_BITS] = `OR1200_UPR_ICP; + spr_dat_o[`OR1200_UPR_DMP_BITS] = `OR1200_UPR_DMP; + spr_dat_o[`OR1200_UPR_IMP_BITS] = `OR1200_UPR_IMP; + spr_dat_o[`OR1200_UPR_MP_BITS] = `OR1200_UPR_MP; + spr_dat_o[`OR1200_UPR_DUP_BITS] = `OR1200_UPR_DUP; + spr_dat_o[`OR1200_UPR_PCUP_BITS] = `OR1200_UPR_PCUP; + spr_dat_o[`OR1200_UPR_PMP_BITS] = `OR1200_UPR_PMP; + spr_dat_o[`OR1200_UPR_PICP_BITS] = `OR1200_UPR_PICP; + spr_dat_o[`OR1200_UPR_TTP_BITS] = `OR1200_UPR_TTP; + spr_dat_o[`OR1200_UPR_RES1_BITS] = `OR1200_UPR_RES1; + spr_dat_o[`OR1200_UPR_CUP_BITS] = `OR1200_UPR_CUP; + end + `OR1200_SPRGRP_SYS_CPUCFGR: begin + spr_dat_o[`OR1200_CPUCFGR_NSGF_BITS] = `OR1200_CPUCFGR_NSGF; + spr_dat_o[`OR1200_CPUCFGR_HGF_BITS] = `OR1200_CPUCFGR_HGF; + spr_dat_o[`OR1200_CPUCFGR_OB32S_BITS] = `OR1200_CPUCFGR_OB32S; + spr_dat_o[`OR1200_CPUCFGR_OB64S_BITS] = `OR1200_CPUCFGR_OB64S; + spr_dat_o[`OR1200_CPUCFGR_OF32S_BITS] = `OR1200_CPUCFGR_OF32S; + spr_dat_o[`OR1200_CPUCFGR_OF64S_BITS] = `OR1200_CPUCFGR_OF64S; + spr_dat_o[`OR1200_CPUCFGR_OV64S_BITS] = `OR1200_CPUCFGR_OV64S; + spr_dat_o[`OR1200_CPUCFGR_RES1_BITS] = `OR1200_CPUCFGR_RES1; + end + `OR1200_SPRGRP_SYS_DMMUCFGR: begin + spr_dat_o[`OR1200_DMMUCFGR_NTW_BITS] = `OR1200_DMMUCFGR_NTW; + spr_dat_o[`OR1200_DMMUCFGR_NTS_BITS] = `OR1200_DMMUCFGR_NTS; + spr_dat_o[`OR1200_DMMUCFGR_NAE_BITS] = `OR1200_DMMUCFGR_NAE; + spr_dat_o[`OR1200_DMMUCFGR_CRI_BITS] = `OR1200_DMMUCFGR_CRI; + spr_dat_o[`OR1200_DMMUCFGR_PRI_BITS] = `OR1200_DMMUCFGR_PRI; + spr_dat_o[`OR1200_DMMUCFGR_TEIRI_BITS] = `OR1200_DMMUCFGR_TEIRI; + spr_dat_o[`OR1200_DMMUCFGR_HTR_BITS] = `OR1200_DMMUCFGR_HTR; + spr_dat_o[`OR1200_DMMUCFGR_RES1_BITS] = `OR1200_DMMUCFGR_RES1; + end + `OR1200_SPRGRP_SYS_IMMUCFGR: begin + spr_dat_o[`OR1200_IMMUCFGR_NTW_BITS] = `OR1200_IMMUCFGR_NTW; + spr_dat_o[`OR1200_IMMUCFGR_NTS_BITS] = `OR1200_IMMUCFGR_NTS; + spr_dat_o[`OR1200_IMMUCFGR_NAE_BITS] = `OR1200_IMMUCFGR_NAE; + spr_dat_o[`OR1200_IMMUCFGR_CRI_BITS] = `OR1200_IMMUCFGR_CRI; + spr_dat_o[`OR1200_IMMUCFGR_PRI_BITS] = `OR1200_IMMUCFGR_PRI; + spr_dat_o[`OR1200_IMMUCFGR_TEIRI_BITS] = `OR1200_IMMUCFGR_TEIRI; + spr_dat_o[`OR1200_IMMUCFGR_HTR_BITS] = `OR1200_IMMUCFGR_HTR; + spr_dat_o[`OR1200_IMMUCFGR_RES1_BITS] = `OR1200_IMMUCFGR_RES1; + end + `OR1200_SPRGRP_SYS_DCCFGR: begin + spr_dat_o[`OR1200_DCCFGR_NCW_BITS] = `OR1200_DCCFGR_NCW; + spr_dat_o[`OR1200_DCCFGR_NCS_BITS] = `OR1200_DCCFGR_NCS; + spr_dat_o[`OR1200_DCCFGR_CBS_BITS] = `OR1200_DCCFGR_CBS; + spr_dat_o[`OR1200_DCCFGR_CWS_BITS] = `OR1200_DCCFGR_CWS; + spr_dat_o[`OR1200_DCCFGR_CCRI_BITS] = `OR1200_DCCFGR_CCRI; + spr_dat_o[`OR1200_DCCFGR_CBIRI_BITS] = `OR1200_DCCFGR_CBIRI; + spr_dat_o[`OR1200_DCCFGR_CBPRI_BITS] = `OR1200_DCCFGR_CBPRI; + spr_dat_o[`OR1200_DCCFGR_CBLRI_BITS] = `OR1200_DCCFGR_CBLRI; + spr_dat_o[`OR1200_DCCFGR_CBFRI_BITS] = `OR1200_DCCFGR_CBFRI; + spr_dat_o[`OR1200_DCCFGR_CBWBRI_BITS] = `OR1200_DCCFGR_CBWBRI; + spr_dat_o[`OR1200_DCCFGR_RES1_BITS] = `OR1200_DCCFGR_RES1; + end + `OR1200_SPRGRP_SYS_ICCFGR: begin + spr_dat_o[`OR1200_ICCFGR_NCW_BITS] = `OR1200_ICCFGR_NCW; + spr_dat_o[`OR1200_ICCFGR_NCS_BITS] = `OR1200_ICCFGR_NCS; + spr_dat_o[`OR1200_ICCFGR_CBS_BITS] = `OR1200_ICCFGR_CBS; + spr_dat_o[`OR1200_ICCFGR_CWS_BITS] = `OR1200_ICCFGR_CWS; + spr_dat_o[`OR1200_ICCFGR_CCRI_BITS] = `OR1200_ICCFGR_CCRI; + spr_dat_o[`OR1200_ICCFGR_CBIRI_BITS] = `OR1200_ICCFGR_CBIRI; + spr_dat_o[`OR1200_ICCFGR_CBPRI_BITS] = `OR1200_ICCFGR_CBPRI; + spr_dat_o[`OR1200_ICCFGR_CBLRI_BITS] = `OR1200_ICCFGR_CBLRI; + spr_dat_o[`OR1200_ICCFGR_CBFRI_BITS] = `OR1200_ICCFGR_CBFRI; + spr_dat_o[`OR1200_ICCFGR_CBWBRI_BITS] = `OR1200_ICCFGR_CBWBRI; + spr_dat_o[`OR1200_ICCFGR_RES1_BITS] = `OR1200_ICCFGR_RES1; + end + `OR1200_SPRGRP_SYS_DCFGR: begin + spr_dat_o[`OR1200_DCFGR_NDP_BITS] = `OR1200_DCFGR_NDP; + spr_dat_o[`OR1200_DCFGR_WPCI_BITS] = `OR1200_DCFGR_WPCI; + spr_dat_o[`OR1200_DCFGR_RES1_BITS] = `OR1200_DCFGR_RES1; + end + default: spr_dat_o = 32'h0000_0000; + endcase +`ifdef OR1200_SYS_FULL_DECODE + else + spr_dat_o = 32'h0000_0000; +`endif + +`else + +// +// When configuration registers are not implemented, only +// implement VR and UPR +// +always @(spr_addr) +`ifdef OR1200_SYS_FULL_DECODE + if (!spr_addr[31:4]) +`endif + case(spr_addr[3:0]) + `OR1200_SPRGRP_SYS_VR: begin + spr_dat_o[`OR1200_VR_REV_BITS] = `OR1200_VR_REV; + spr_dat_o[`OR1200_VR_RES1_BITS] = `OR1200_VR_RES1; + spr_dat_o[`OR1200_VR_CFG_BITS] = `OR1200_VR_CFG; + spr_dat_o[`OR1200_VR_VER_BITS] = `OR1200_VR_VER; + end + `OR1200_SPRGRP_SYS_UPR: begin + spr_dat_o[`OR1200_UPR_UP_BITS] = `OR1200_UPR_UP; + spr_dat_o[`OR1200_UPR_DCP_BITS] = `OR1200_UPR_DCP; + spr_dat_o[`OR1200_UPR_ICP_BITS] = `OR1200_UPR_ICP; + spr_dat_o[`OR1200_UPR_DMP_BITS] = `OR1200_UPR_DMP; + spr_dat_o[`OR1200_UPR_IMP_BITS] = `OR1200_UPR_IMP; + spr_dat_o[`OR1200_UPR_MP_BITS] = `OR1200_UPR_MP; + spr_dat_o[`OR1200_UPR_DUP_BITS] = `OR1200_UPR_DUP; + spr_dat_o[`OR1200_UPR_PCUP_BITS] = `OR1200_UPR_PCUP; + spr_dat_o[`OR1200_UPR_PMP_BITS] = `OR1200_UPR_PMP; + spr_dat_o[`OR1200_UPR_PICP_BITS] = `OR1200_UPR_PICP; + spr_dat_o[`OR1200_UPR_TTP_BITS] = `OR1200_UPR_TTP; + spr_dat_o[`OR1200_UPR_RES1_BITS] = `OR1200_UPR_RES1; + spr_dat_o[`OR1200_UPR_CUP_BITS] = `OR1200_UPR_CUP; + end + default: spr_dat_o = 32'h0000_0000; + endcase +`ifdef OR1200_SYS_FULL_DECODE + else + spr_dat_o = 32'h0000_0000; +`endif + +`endif + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_sprs.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_sprs.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_sprs.v (revision 995) @@ -0,0 +1,385 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's interface to SPRs //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Decoding of SPR addresses and access to SPRs //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.6 2002/03/11 01:26:57 lampret +// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. +// +// Revision 1.5 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.4 2002/01/23 07:52:36 lampret +// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. +// +// Revision 1.3 2002/01/19 09:27:49 lampret +// SR[TEE] should be zero after reset. +// +// Revision 1.2 2002/01/18 07:56:00 lampret +// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.12 2001/11/23 21:42:31 simons +// Program counter divided to PPC and NPC. +// +// Revision 1.11 2001/11/23 08:38:51 lampret +// Changed DSR/DRR behavior and exception detection. +// +// Revision 1.10 2001/11/12 01:45:41 lampret +// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. +// +// Revision 1.9 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.8 2001/10/14 13:12:10 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.3 2001/08/13 03:36:20 lampret +// Added cfg regs. Moved all defines into one defines.v file. More cleanup. +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:21 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_sprs( + // Clk & Rst + clk, rst, + + // Internal CPU interface + flagforw, flag_we, flag, addrbase, addrofs, dat_i, alu_op, branch_op, + epcr, eear, esr, except_started, + to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr, + spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac, + + // From/to other RISC units + spr_dat_pic, spr_dat_tt, spr_dat_pm, + spr_dat_dmmu, spr_dat_immu, spr_dat_du, + spr_addr, spr_dat_o, spr_cs, spr_we, + + du_addr, du_dat_du, du_read, + du_write, du_dat_cpu + +); + +parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O Ports +// + +// +// Internal CPU interface +// +input clk; // Clock +input rst; // Reset +output flag; // SR[F] +input flagforw; // From ALU +input flag_we; // From ALU +input [width-1:0] addrbase; // SPR base address +input [15:0] addrofs; // SPR offset +input [width-1:0] dat_i; // SPR write data +input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation +input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation +input [width-1:0] epcr; // EPCR0 +input [width-1:0] eear; // EEAR0 +input [`OR1200_SR_WIDTH-1:0] esr; // ESR0 +input except_started; // Exception was started +output [width-1:0] to_wbmux; // For l.mfspr +output epcr_we; // EPCR0 write enable +output eear_we; // EEAR0 write enable +output esr_we; // ESR0 write enable +output pc_we; // PC write enable +output [`OR1200_SR_WIDTH-1:0] sr; // SR +input [31:0] spr_dat_cfgr; // Data from CFGR +input [31:0] spr_dat_rf; // Data from RF +input [31:0] spr_dat_npc; // Data from NPC +input [31:0] spr_dat_ppc; // Data from PPC +input [31:0] spr_dat_mac; // Data from MAC + +// +// To/from other RISC units +// +input [31:0] spr_dat_pic; // Data from PIC +input [31:0] spr_dat_tt; // Data from TT +input [31:0] spr_dat_pm; // Data from PM +input [31:0] spr_dat_dmmu; // Data from DMMU +input [31:0] spr_dat_immu; // Data from IMMU +input [31:0] spr_dat_du; // Data from DU +output [31:0] spr_addr; // SPR Address +output [31:0] spr_dat_o; // Data to unit +output [31:0] spr_cs; // Unit select +output spr_we; // SPR write enable + +// +// To/from Debug Unit +// +input [width-1:0] du_addr; // Address +input [width-1:0] du_dat_du; // Data from DU to SPRS +input du_read; // Read qualifier +input du_write; // Write qualifier +output [width-1:0] du_dat_cpu; // Data from SPRS to DU + +// +// Internal regs & wires +// +reg [`OR1200_SR_WIDTH-1:0] sr; // SR +reg write_spr; // Write SPR +reg read_spr; // Read SPR +reg [width-1:0] to_wbmux; // For l.mfspr +wire sr_we; // Write enable SR +wire cfgr_sel; // Select for cfg regs +wire rf_sel; // Select for RF +wire npc_sel; // Select for NPC +wire ppc_sel; // Select for PPC +wire sr_sel; // Select for SR +wire epcr_sel; // Select for EPCR0 +wire eear_sel; // Select for EEAR0 +wire esr_sel; // Select for ESR0 +wire [31:0] sys_data; // Read data from system SPRs +wire [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR +wire du_access; // Debug unit access +wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation +reg [31:0] unqualified_cs; // Unqualified chip selects + +// +// Decide if it is debug unit access +// +assign du_access = du_read | du_write; + +// +// Generate sprs opcode +// +assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op; + +// +// Generate SPR address from base address and offset +// OR from debug unit address +// +assign spr_addr = du_access ? du_addr : addrbase | {16'h0000, addrofs}; + +// +// SPR is written by debug unit or by l.mtspr +// +assign spr_dat_o = du_write ? du_dat_du : dat_i; + +// +// debug unit data input: +// - write into debug unit SPRs by debug unit itself +// - read of SPRS by debug unit +// - write into debug unit SPRs by l.mtspr +// +assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i; + +// +// Write into SPRs when l.mtspr +// +assign spr_we = du_write | write_spr; + +// +// Qualify chip selects +// +assign spr_cs = unqualified_cs & {32{read_spr | write_spr}}; + +// +// Decoding of groups +// +always @(spr_addr) + case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case + `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001; + `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010; + `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100; + `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000; + `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000; + `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000; + `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000; + `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000; + `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000; + `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000; + `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000; + `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000; + `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000; + `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000; + `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000; + `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000; + endcase + +// +// SPRs System Group +// + +// +// What to write into SR +// +assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr : {1'b1, spr_dat_o[`OR1200_SR_WIDTH-2:0]}; + +// +// Selects for system SPRs +// +assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR)); +assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF)); +assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC)); +assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC)); +assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR)); +assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR)); +assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR)); +assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR)); + +// +// Write enables for system SPRs +// +assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE); +assign pc_we = (write_spr && (npc_sel | ppc_sel)); +assign epcr_we = (write_spr && epcr_sel); +assign eear_we = (write_spr && eear_sel); +assign esr_we = (write_spr && esr_sel); + +// +// Output from system SPRs +// +assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) | + (spr_dat_rf & {32{read_spr & rf_sel}}) | + (spr_dat_npc & {32{read_spr & npc_sel}}) | + (spr_dat_ppc & {32{read_spr & ppc_sel}}) | + ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) | + (epcr & {32{read_spr & epcr_sel}}) | + (eear & {32{read_spr & eear_sel}}) | + ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}}); + +// +// Flag alias +// +assign flag = sr[`OR1200_SR_F]; + +// +// Supervision register +// +always @(posedge clk or posedge rst) + if (rst) + sr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1}; + else if (except_started) begin + sr[`OR1200_SR_SM] <= #1 1'b1; + sr[`OR1200_SR_TEE] <= #1 1'b0; + sr[`OR1200_SR_IEE] <= #1 1'b0; + sr[`OR1200_SR_DME] <= #1 1'b0; + sr[`OR1200_SR_IME] <= #1 1'b0; + end + else if (sr_we) + sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0]; + else if (flag_we) + sr[`OR1200_SR_F] <= #1 flagforw; + +// +// MTSPR/MFSPR interface +// +always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or + spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin + case (sprs_op) // synopsys parallel_case + `OR1200_ALUOP_MTSR : begin + write_spr = 1'b1; + read_spr = 1'b0; + to_wbmux = 32'b0; + end + `OR1200_ALUOP_MFSR : begin + casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case + `OR1200_SPR_GROUP_TT: + to_wbmux = spr_dat_tt; + `OR1200_SPR_GROUP_PIC: + to_wbmux = spr_dat_pic; + `OR1200_SPR_GROUP_PM: + to_wbmux = spr_dat_pm; + `OR1200_SPR_GROUP_DMMU: + to_wbmux = spr_dat_dmmu; + `OR1200_SPR_GROUP_IMMU: + to_wbmux = spr_dat_immu; + `OR1200_SPR_GROUP_MAC: + to_wbmux = spr_dat_mac; + `OR1200_SPR_GROUP_DU: + to_wbmux = spr_dat_du; + `OR1200_SPR_GROUP_SYS: + to_wbmux = sys_data; + default: + to_wbmux = 32'b0; + endcase + write_spr = 1'b0; + read_spr = 1'b1; + end + default : begin + write_spr = 1'b0; + read_spr = 1'b0; + to_wbmux = 32'b0; + end + endcase +end + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_tt.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_tt.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_tt.v (revision 995) @@ -0,0 +1,220 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Tick Timer //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// TT according to OR1K architectural specification. //// +//// //// +//// To Do: //// +//// None //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2002/02/12 01:33:47 lampret +// No longer using async rst as sync reset for the counter. +// +// Revision 1.2 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.10 2001/11/13 10:00:49 lampret +// Fixed tick timer interrupt reporting by using TTCR[IP] bit. +// +// Revision 1.9 2001/11/10 03:43:57 lampret +// Fixed exceptions. +// +// Revision 1.8 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.7 2001/10/14 13:12:10 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:35 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:23 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_tt( + // RISC Internal Interface + clk, rst, du_stall, + spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, + int +); + +// +// RISC Internal Interface +// +input clk; // Clock +input rst; // Reset +input du_stall; // DU stall +input spr_cs; // SPR CS +input spr_write; // SPR Write +input [31:0] spr_addr; // SPR Address +input [31:0] spr_dat_i; // SPR Write Data +output [31:0] spr_dat_o; // SPR Read Data +output int; // Interrupt output + +`ifdef OR1200_TT_IMPLEMENTED + +// +// TT Mode Register bits (or no register) +// +`ifdef OR1200_TT_TTMR +reg [31:0] ttmr; // TTMR bits +`else +wire [31:0] ttmr; // No TTMR register +`endif + +// +// TT Count Register bits (or no register) +// +`ifdef OR1200_TT_TTCR +reg [31:0] ttcr; // TTCR bits +`else +wire [31:0] ttcr; // No TTCR register +`endif + +// +// Internal wires & regs +// +wire ttmr_sel; // TTMR select +wire ttcr_sel; // TTCR select +wire match; // Asserted when TTMR[TP] + // is equal to TTCR[27:0] +wire restart; // Restart counter when asserted +wire stop; // Stop counter when asserted +reg [31:0] spr_dat_o; // SPR data out + +// +// TT registers address decoder +// +assign ttmr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0; +assign ttcr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0; + +// +// Write to TTMR or update of TTMR[IP] bit +// +`ifdef OR1200_TT_TTMR +always @(posedge clk or posedge rst) + if (rst) + ttmr <= 32'b0; + else if (ttmr_sel && spr_write) + ttmr <= #1 spr_dat_i; + else if (ttmr[`OR1200_TT_TTMR_IE]) + ttmr[`OR1200_TT_TTMR_IP] <= #1 ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]); +`else +assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3 +`endif + +// +// Write to or increment of TTCR +// +`ifdef OR1200_TT_TTCR +always @(posedge clk or posedge rst) + if (rst) + ttcr <= 32'b0; + else if (restart) + ttcr <= #1 32'b0; + else if (ttcr_sel && spr_write) + ttcr <= #1 spr_dat_i; + else if (!stop) + ttcr <= #1 ttcr + 1'd1; +`else +assign ttcr = 32'b0; +`endif + +// +// Read TT registers +// +always @(spr_addr or ttmr or ttcr) + case (spr_addr[`OR1200_TTOFS_BITS]) // synopsys parallel_case +`ifdef OR1200_TT_READREGS + `OR1200_TT_OFS_TTMR: spr_dat_o = ttmr; +`endif + default: spr_dat_o = ttcr; + endcase + +// +// A match when TTMR[TP] is equal to TTCR[27:0] +// +assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0; + +// +// Restart when match and TTMR[M]==0x1 +// +assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01); + +// +// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit +// +assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall; + +// +// Generate an interrupt request +// +assign int = ttmr[`OR1200_TT_TTMR_IP]; + +`else + +// +// When TT is not implemented, drive all outputs as would when TT is disabled +// +assign int = 1'b0; + +// +// Read TT registers +// +`ifdef OR1200_TT_READREGS +assign spr_dat_o = 32'b0; +`endif + +`endif + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_dc_fsm.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_dc_fsm.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_dc_fsm.v (revision 995) @@ -0,0 +1,314 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's DC FSM //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Data cache state machine //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.6 2002/03/28 19:10:40 lampret +// Optimized cache controller FSM. +// +// Revision 1.1.1.1 2002/03/21 16:55:45 lampret +// First import of the "new" XESS XSV environment. +// +// +// Revision 1.5 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.4 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.3 2002/01/28 01:15:59 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.9 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.8 2001/10/19 23:28:46 lampret +// Fixed some synthesis warnings. Configured with caches and MMUs. +// +// Revision 1.7 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:35 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +`define OR1200_DCFSM_IDLE 3'd0 +`define OR1200_DCFSM_CLOAD 3'd1 +`define OR1200_DCFSM_LREFILL3 3'd2 +`define OR1200_DCFSM_CSTORE 3'd3 +`define OR1200_DCFSM_SREFILL4 3'd4 + +// +// Data cache FSM for cache line of 16 bytes (4x singleword) +// + +module or1200_dc_fsm( + // Clock and reset + clk, rst, + + // Internal i/f to top level DC + dc_en, dcdmmu_cycstb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i, + tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr, + dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err, + burst, tag_we, dc_addr +); + +// +// I/O +// +input clk; +input rst; +input dc_en; +input dcdmmu_cycstb_i; +input dcdmmu_ci_i; +input dcpu_we_i; +input [3:0] dcpu_sel_i; +input tagcomp_miss; +input biudata_valid; +input biudata_error; +input [31:0] start_addr; +output [31:0] saved_addr; +output [3:0] dcram_we; +output biu_read; +output biu_write; +output first_hit_ack; +output first_miss_ack; +output first_miss_err; +output burst; +output tag_we; +output [31:0] dc_addr; + +// +// Internal wires and regs +// +reg [31:0] saved_addr_r; +reg [2:0] state; +reg [2:0] cnt; +reg hitmiss_eval; +reg store; +reg load; +reg cache_inhibit; +wire first_store_hit_ack; + +// +// Generate of DCRAM write enables +// +assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcpu_sel_i; +assign tag_we = biu_read & biudata_valid & !cache_inhibit; + +// +// BIU read and write +// +assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load); +assign biu_write = store; + +assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr; +assign saved_addr = saved_addr_r; + +// +// Assert for cache hit first word ready +// Assert for store cache hit first word ready +// Assert for cache miss first word stored/loaded OK +// Assert for cache miss first word stored/loaded with an error +// +assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcdmmu_ci_i | first_store_hit_ack; +assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcdmmu_ci_i; +assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid; +assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error; + +// +// Assert burst when doing reload of complete cache line +// +assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit + | (state == `OR1200_DCFSM_LREFILL3) +`ifdef OR1200_DC_STORE_REFILL + | (state == `OR1200_DCFSM_SREFILL4) +`endif + ; + +// +// Main DC FSM +// +always @(posedge clk or posedge rst) begin + if (rst) begin + state <= #1 `OR1200_DCFSM_IDLE; + saved_addr_r <= #1 32'b0; + hitmiss_eval <= #1 1'b0; + store <= #1 1'b0; + load <= #1 1'b0; + cnt <= #1 3'b000; + cache_inhibit <= #1 1'b0; + end + else + case (state) // synopsys parallel_case + `OR1200_DCFSM_IDLE : + if (dc_en & dcdmmu_cycstb_i & dcpu_we_i) begin // store + state <= #1 `OR1200_DCFSM_CSTORE; + saved_addr_r <= #1 start_addr; + hitmiss_eval <= #1 1'b1; + store <= #1 1'b1; + load <= #1 1'b0; + cache_inhibit <= #1 1'b0; + end + else if (dc_en & dcdmmu_cycstb_i) begin // load + state <= #1 `OR1200_DCFSM_CLOAD; + saved_addr_r <= #1 start_addr; + hitmiss_eval <= #1 1'b1; + store <= #1 1'b0; + load <= #1 1'b1; + cache_inhibit <= #1 1'b0; + end + else begin // idle + hitmiss_eval <= #1 1'b0; + store <= #1 1'b0; + load <= #1 1'b0; + cache_inhibit <= #1 1'b0; + end + `OR1200_DCFSM_CLOAD: begin // load + if (dcdmmu_cycstb_i & dcdmmu_ci_i) + cache_inhibit <= #1 1'b1; + if (hitmiss_eval) + saved_addr_r[31:13] <= #1 start_addr[31:13]; + if ((hitmiss_eval & !dcdmmu_cycstb_i) || // load aborted (usually caused by DMMU) + (biudata_error) || // load terminated with an error + ((cache_inhibit | dcdmmu_ci_i) & biudata_valid)) begin // load from cache-inhibited area + state <= #1 `OR1200_DCFSM_IDLE; + hitmiss_eval <= #1 1'b0; + load <= #1 1'b0; + cache_inhibit <= #1 1'b0; + end + else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill + state <= #1 `OR1200_DCFSM_LREFILL3; + saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1; + hitmiss_eval <= #1 1'b0; + cnt <= #1 `OR1200_DCLS-2; + cache_inhibit <= #1 1'b0; + end + else if (!tagcomp_miss & !dcdmmu_ci_i) begin // load hit, finish immediately + state <= #1 `OR1200_DCFSM_IDLE; + hitmiss_eval <= #1 1'b0; + load <= #1 1'b0; + cache_inhibit <= #1 1'b0; + end + else // load in-progress + hitmiss_eval <= #1 1'b0; + end + `OR1200_DCFSM_LREFILL3 : begin + if (biudata_valid && (|cnt)) begin // refill ack, more loads to come + cnt <= #1 cnt - 'd1; + saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1; + end + else if (biudata_valid) begin // last load of line refill + state <= #1 `OR1200_DCFSM_IDLE; + load <= #1 1'b0; + end + end + `OR1200_DCFSM_CSTORE: begin // store + if (dcdmmu_cycstb_i & dcdmmu_ci_i) + cache_inhibit <= #1 1'b1; + if (hitmiss_eval) + saved_addr_r[31:13] <= #1 start_addr[31:13]; + if ((hitmiss_eval & !dcdmmu_cycstb_i) || // store aborted (usually caused by DMMU) + (biudata_error) || // store terminated with an error + ((cache_inhibit | dcdmmu_ci_i) & biudata_valid)) begin // store to cache-inhibited area + state <= #1 `OR1200_DCFSM_IDLE; + hitmiss_eval <= #1 1'b0; + store <= #1 1'b0; + cache_inhibit <= #1 1'b0; + end +`ifdef OR1200_DC_STORE_REFILL + else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill + state <= #1 `OR1200_DCFSM_SREFILL4; + hitmiss_eval <= #1 1'b0; + store <= #1 1'b0; + load <= #1 1'b1; + cnt <= #1 `OR1200_DCLS-1; + cache_inhibit <= #1 1'b0; + end +`endif + else if (biudata_valid) begin // store hit, finish write-through + state <= #1 `OR1200_DCFSM_IDLE; + hitmiss_eval <= #1 1'b0; + store <= #1 1'b0; + cache_inhibit <= #1 1'b0; + end + else // store write-through in-progress + hitmiss_eval <= #1 1'b0; + end +`ifdef OR1200_DC_STORE_REFILL + `OR1200_DCFSM_SREFILL4 : begin + if (biudata_valid && (|cnt)) begin // refill ack, more loads to come + cnt <= #1 cnt - 'd1; + saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1; + end + else if (biudata_valid) begin // last load of line refill + state <= #1 `OR1200_DCFSM_IDLE; + load <= #1 1'b0; + end + end +`endif + default: + state <= #1 `OR1200_DCFSM_IDLE; + endcase +end + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_if.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_if.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_if.v (revision 995) @@ -0,0 +1,186 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's instruction fetch //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// PC, instruction fetch, interface to IC. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.10 2001/11/20 18:46:15 simons +// Break point bug fixed +// +// Revision 1.9 2001/11/18 09:58:28 lampret +// Fixed some l.trap typos. +// +// Revision 1.8 2001/11/18 08:36:28 lampret +// For GDB changed single stepping and disabled trap exception. +// +// Revision 1.7 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.6 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_if( + // Clock and reset + clk, rst, + + // External i/f to IC + icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i, + + // Internal i/f + if_freeze, if_insn, if_pc, flushpipe, + if_stall, no_more_dslot, genpc_refetch, rfe, + except_itlbmiss, except_immufault, except_ibuserr +); + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// External i/f to IC +// +input [31:0] icpu_dat_i; +input icpu_ack_i; +input icpu_err_i; +input [31:0] icpu_adr_i; +input [3:0] icpu_tag_i; + +// +// Internal i/f +// +input if_freeze; +output [31:0] if_insn; +output [31:0] if_pc; +input flushpipe; +output if_stall; +input no_more_dslot; +output genpc_refetch; +input rfe; +output except_itlbmiss; +output except_immufault; +output except_ibuserr; + +// +// Internal wires and regs +// +reg [31:0] insn_saved; +reg [31:0] addr_saved; +reg saved; + +// +// IF stage insn +// +assign if_insn = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000}; +assign if_pc = saved ? addr_saved : icpu_adr_i; +// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot; +assign if_stall = !icpu_err_i & !icpu_ack_i & !saved; +assign genpc_refetch = saved & icpu_ack_i; +assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot; +assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot; +assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot; + +// +// Flag for saved insn/address +// +always @(posedge clk or posedge rst) + if (rst) + saved <= #1 1'b0; + else if (flushpipe) + saved <= #1 1'b0; + else if (icpu_ack_i & if_freeze & !saved) + saved <= #1 1'b1; + else if (!if_freeze) + saved <= #1 1'b0; + +// +// Store fetched instruction +// +always @(posedge clk or posedge rst) + if (rst) + insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; + else if (flushpipe) + insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; + else if (icpu_ack_i & if_freeze & !saved) + insn_saved <= #1 icpu_dat_i; + else if (!if_freeze) + insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; + +// +// Store fetched instruction's address +// +always @(posedge clk or posedge rst) + if (rst) + addr_saved <= #1 32'h00000000; + else if (flushpipe) + addr_saved <= #1 32'h00000000; + else if (icpu_ack_i & if_freeze & !saved) + addr_saved <= #1 icpu_adr_i; + else if (!if_freeze) + addr_saved <= #1 icpu_adr_i; + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_wbmux.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_wbmux.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_wbmux.v (revision 995) @@ -0,0 +1,165 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Write-back Mux //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// CPU's write-back stage of the pipeline //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.8 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.7 2001/10/14 13:12:10 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:23 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_wbmux( + // Clock and reset + clk, rst, + + // Internal i/f + wb_freeze, rfwb_op, + muxin_a, muxin_b, muxin_c, muxin_d, + muxout, muxreg, muxreg_valid +); + +parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// Internal i/f +// +input wb_freeze; +input [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; +input [width-1:0] muxin_a; +input [width-1:0] muxin_b; +input [width-1:0] muxin_c; +input [width-1:0] muxin_d; +output [width-1:0] muxout; +output [width-1:0] muxreg; +output muxreg_valid; + +// +// Internal wires and regs +// +reg [width-1:0] muxout; +reg [width-1:0] muxreg; +reg muxreg_valid; + +// +// Registered output from the write-back multiplexer +// +always @(posedge clk or posedge rst) begin + if (rst) begin + muxreg <= #1 32'd0; + muxreg_valid <= #1 1'b0; + end + else if (!wb_freeze) begin + muxreg <= #1 muxout; + muxreg_valid <= #1 rfwb_op[0]; + end +end + +// +// Write-back multiplexer +// +always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin +`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux +`else + case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case +`endif + 2'b00: muxout = muxin_a; + 2'b01: begin + muxout = muxin_b; +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display(" WBMUX: muxin_b %h", muxin_b); +// synopsys translate_on +`endif + end + 2'b10: begin + muxout = muxin_c; +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display(" WBMUX: muxin_c %h", muxin_c); +// synopsys translate_on +`endif + end + 2'b11: begin + muxout = muxin_d + 4'h8; +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display(" WBMUX: muxin_d %h", muxin_d + 4'h8); +// synopsys translate_on +`endif + end + endcase +end + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_operandmuxes.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_operandmuxes.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_operandmuxes.v (revision 995) @@ -0,0 +1,184 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's register file read operands mux //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Mux for two register file read operands. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.9 2001/11/12 01:45:40 lampret +// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. +// +// Revision 1.8 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.7 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:05 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_operandmuxes( + // Clock and reset + clk, rst, + + // Internal i/f + id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw, + simm, sel_a, sel_b, operand_a, operand_b, muxed_b +); + +parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// +input clk; +input rst; +input id_freeze; +input ex_freeze; +input [width-1:0] rf_dataa; +input [width-1:0] rf_datab; +input [width-1:0] ex_forw; +input [width-1:0] wb_forw; +input [width-1:0] simm; +input [`OR1200_SEL_WIDTH-1:0] sel_a; +input [`OR1200_SEL_WIDTH-1:0] sel_b; +output [width-1:0] operand_a; +output [width-1:0] operand_b; +output [width-1:0] muxed_b; + +// +// Internal wires and regs +// +reg [width-1:0] operand_a; +reg [width-1:0] operand_b; +reg [width-1:0] muxed_a; +reg [width-1:0] muxed_b; +reg saved_a; +reg saved_b; + +// +// Operand A register +// +always @(posedge clk or posedge rst) begin + if (rst) begin + operand_a <= #1 32'd0; + saved_a <= #1 1'b0; + end else if (!ex_freeze && id_freeze && !saved_a) begin + operand_a <= #1 muxed_a; + saved_a <= #1 1'b1; + end else if (!ex_freeze && !saved_a) begin + operand_a <= #1 muxed_a; + end else if (!ex_freeze && !id_freeze) + saved_a <= #1 1'b0; +end + +// +// Operand B register +// +always @(posedge clk or posedge rst) begin + if (rst) begin + operand_b <= #1 32'd0; + saved_b <= #1 1'b0; + end else if (!ex_freeze && id_freeze && !saved_b) begin + operand_b <= #1 muxed_b; + saved_b <= #1 1'b1; + end else if (!ex_freeze && !saved_b) begin + operand_b <= #1 muxed_b; + end else if (!ex_freeze && !id_freeze) + saved_b <= #1 1'b0; +end + +// +// Forwarding logic for operand A register +// +always @(ex_forw or wb_forw or rf_dataa or sel_a) begin +`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + casex (sel_a) // synopsys parallel_case infer_mux +`else + casex (sel_a) // synopsys parallel_case +`endif + `OR1200_SEL_EX_FORW: + muxed_a = ex_forw; + `OR1200_SEL_WB_FORW: + muxed_a = wb_forw; + default: + muxed_a = rf_dataa; + endcase +end + +// +// Forwarding logic for operand B register +// +always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin +`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + casex (sel_b) // synopsys parallel_case infer_mux +`else + casex (sel_b) // synopsys parallel_case +`endif + `OR1200_SEL_IMM: + muxed_b = simm; + `OR1200_SEL_EX_FORW: + muxed_b = ex_forw; + `OR1200_SEL_WB_FORW: + muxed_b = wb_forw; + default: + muxed_b = rf_datab; + endcase +end + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_pic.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_pic.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_pic.v (revision 995) @@ -0,0 +1,222 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Programmable Interrupt Controller //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// PIC according to OR1K architectural specification. //// +//// //// +//// To Do: //// +//// None //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/01/18 07:56:00 lampret +// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.8 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.7 2001/10/14 13:12:10 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:21 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_pic( + // RISC Internal Interface + clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, + pic_wakeup, int, + + // PIC Interface + pic_int +); + +// +// RISC Internal Interface +// +input clk; // Clock +input rst; // Reset +input spr_cs; // SPR CS +input spr_write; // SPR Write +input [31:0] spr_addr; // SPR Address +input [31:0] spr_dat_i; // SPR Write Data +output [31:0] spr_dat_o; // SPR Read Data +output pic_wakeup; // Wakeup to the PM +output int; // interrupt + // exception request + +// +// PIC Interface +// +input [`OR1200_PIC_INTS-1:0] pic_int;// Interrupt inputs + +`ifdef OR1200_PIC_IMPLEMENTED + +// +// PIC Mask Register bits (or no register) +// +`ifdef OR1200_PIC_PICMR +reg [`OR1200_PIC_INTS-1:2] picmr; // PICMR bits +`else +wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register +`endif + +// +// PIC Status Register bits (or no register) +// +`ifdef OR1200_PIC_PICSR +reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits +`else +wire [`OR1200_PIC_INTS-1:0] picsr; // No PICSR register +`endif + +// +// Internal wires & regs +// +wire picmr_sel; // PICMR select +wire picsr_sel; // PICSR select +wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts +reg [31:0] spr_dat_o; // SPR data out + +// +// PIC registers address decoder +// +assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0; +assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0; + +// +// Write to PICMR +// +`ifdef OR1200_PIC_PICMR +always @(posedge clk or posedge rst) + if (rst) + picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}}; + else if (picmr_sel && spr_write) begin + picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2]; + end +`else +assign picmr = (`OR1200_PIC_INTS)'b1; +`endif + +// +// Write to PICSR, both CPU and external ints +// +`ifdef OR1200_PIC_PICSR +always @(posedge clk or posedge rst) + if (rst) + picsr <= {`OR1200_PIC_INTS-2{1'b0}}; + else if (picsr_sel && spr_write) begin + picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints; + end else + picsr <= #1 picsr | um_ints; +`else +assign picsr = pic_int; +`endif + +// +// Read PIC registers +// +always @(spr_addr or picmr or picsr) + case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys parallel_case +`ifdef OR1200_PIC_READREGS + `OR1200_PIC_OFS_PICMR: begin + spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0}; +`ifdef OR1200_PIC_UNUSED_ZERO + spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}}; +`endif + end +`endif + default: begin + spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr; +`ifdef OR1200_PIC_UNUSED_ZERO + spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}}; +`endif + end + endcase + +// +// Unmasked interrupts +// +assign um_ints = pic_int & {picmr, 2'b11}; + +// +// Generate int +// +assign int = |um_ints; + +// +// Assert pic_wakeup when int is asserted +// +assign pic_wakeup = int; + +`else + +// +// When PIC is not implemented, drive all outputs as would when PIC is disabled +// +assign int = pic_int[1] | pic_int[0]; +assign pic_wakeup= int; + +// +// Read PIC registers +// +`ifdef OR1200_PIC_READREGS +assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0; +`ifdef OR1200_PIC_UNUSED_ZERO +assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0; +`endif +`endif + +`endif + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_dmmu_top.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_dmmu_top.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_dmmu_top.v (revision 995) @@ -0,0 +1,313 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Data MMU top level //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instantiation of all DMMU blocks. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.5 2002/02/14 15:34:02 simons +// Lapsus fixed. +// +// Revision 1.4 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.3 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.6 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.5 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.1 2001/08/17 08:03:35 lampret +// *** empty log message *** +// +// Revision 1.2 2001/07/22 03:31:53 lampret +// Fixed RAM's oen bug. Cache bypass under development. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +// +// Data MMU +// + +module or1200_dmmu_top( + // Rst and clk + clk, rst, + + // CPU i/f + dc_en, dmmu_en, supv, dcpu_adr_i, dcpu_cycstb_i, dcpu_we_i, + dcpu_tag_o, dcpu_err_o, + + // SPR access + spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, + + // DC i/f + dcdmmu_err_i, dcdmmu_tag_i, dcdmmu_adr_o, dcdmmu_cycstb_o, dcdmmu_ci_o +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_OPERAND_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// CPU I/F +// +input dc_en; +input dmmu_en; +input supv; +input [aw-1:0] dcpu_adr_i; +input dcpu_cycstb_i; +input dcpu_we_i; +output [3:0] dcpu_tag_o; +output dcpu_err_o; + +// +// SPR access +// +input spr_cs; +input spr_write; +input [aw-1:0] spr_addr; +input [31:0] spr_dat_i; +output [31:0] spr_dat_o; + +// +// DC I/F +// +input dcdmmu_err_i; +input [3:0] dcdmmu_tag_i; +output [aw-1:0] dcdmmu_adr_o; +output dcdmmu_cycstb_o; +output dcdmmu_ci_o; + +// +// Internal wires and regs +// +wire dtlb_spr_access; +wire [31:`OR1200_DMMU_PS] dtlb_ppn; +wire dtlb_hit; +wire dtlb_uwe; +wire dtlb_ure; +wire dtlb_swe; +wire dtlb_sre; +wire [31:0] dtlb_dat_o; +wire dtlb_en; +wire dtlb_ci; +wire fault; +wire miss; +`ifdef OR1200_NO_DMMU +`else +reg dtlb_done; +reg [31:`OR1200_DMMU_PS] dcpu_vpn_r; +`endif + +// +// Implemented bits inside match and translate registers +// +// dtlbwYmrX: vpn 31-10 v 0 +// dtlbwYtrX: ppn 31-10 swe 9 sre 8 uwe 7 ure 6 +// +// dtlb memory width: +// 19 bits for ppn +// 13 bits for vpn +// 1 bit for valid +// 4 bits for protection +// 1 bit for cache inhibit + +`ifdef OR1200_NO_DMMU + +// +// Put all outputs in inactive state +// +assign spr_dat_o = 32'h00000000; +assign dcdmmu_adr_o = dcpu_adr_i; +assign dcpu_tag_o = dcdmmu_tag_i; +assign dcdmmu_cycstb_o = dcpu_cycstb_i; +assign dcpu_err_o = dcdmmu_err_i; +assign dcdmmu_ci_o = `OR1200_DMMU_CI; + +`else + +// +// DTLB SPR access +// +// 0A00 - 0AFF dtlbmr w0 +// 0A00 - 0A3F dtlbmr w0 [63:0] +// +// 0B00 - 0BFF dtlbtr w0 +// 0B00 - 0B3F dtlbtr w0 [63:0] +// +assign dtlb_spr_access = spr_cs; + +// +// Tags: +// +// OR1200_DTAG_TE - TLB miss Exception +// OR1200_DTAG_PE - Page fault Exception +// +assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : dcdmmu_tag_i; + +// +// dcpu_err_o +// +assign dcpu_err_o = miss | fault | dcdmmu_err_i; + +// +// Assert dtlb_done one clock cycle after new address and dtlb_en must be active. +// +always @(posedge clk or posedge rst) + if (rst) + dtlb_done <= #1 1'b0; + else if (dtlb_en) + dtlb_done <= #1 dcpu_cycstb_i; + else + dtlb_done <= #1 1'b0; + +// +// Cut transfer if something goes wrong with translation. Also delayed signals because of translation delay. +// +assign dcdmmu_cycstb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cycstb_i : ~(miss | fault) & dcpu_cycstb_i; +//assign dcdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i; + +// +// Cache Inhibit +// +assign dcdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI; + +// +// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come +// one clock cycle after offset part. +// +always @(posedge clk or posedge rst) + if (rst) + dcpu_vpn_r <= #1 {31-`OR1200_DMMU_PS{1'b0}}; + else + dcpu_vpn_r <= #1 dcpu_adr_i[31:`OR1200_DMMU_PS]; + +// +// Physical address is either translated virtual address or +// simply equal when DMMU is disabled +// +// assign dcdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : {dcpu_vpn_r, dcpu_adr_i[`OR1200_DMMU_PS-1:0]}; +assign dcdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i; + +// +// Output to SPRS unit +// +assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000; + +// +// Page fault exception logic +// +assign fault = dtlb_done & + ( (!dcpu_we_i & !supv & !dtlb_ure) // Load in user mode not enabled + || (!dcpu_we_i & supv & !dtlb_sre) // Load in supv mode not enabled + || (dcpu_we_i & !supv & !dtlb_uwe) // Store in user mode not enabled + || (dcpu_we_i & supv & !dtlb_swe) ); // Store in supv mode not enabled + +// +// TLB Miss exception logic +// +assign miss = dtlb_done & !dtlb_hit; + +// +// DTLB Enable +// +assign dtlb_en = dmmu_en & dcpu_cycstb_i; + +// +// Instantiation of DTLB +// +or1200_dmmu_tlb or1200_dmmu_tlb( + // Rst and clk + .clk(clk), + .rst(rst), + + // I/F for translation + .tlb_en(dtlb_en), + .vaddr(dcpu_adr_i), + .hit(dtlb_hit), + .ppn(dtlb_ppn), + .uwe(dtlb_uwe), + .ure(dtlb_ure), + .swe(dtlb_swe), + .sre(dtlb_sre), + .ci(dtlb_ci), + + // SPR access + .spr_cs(dtlb_spr_access), + .spr_write(spr_write), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_i), + .spr_dat_o(dtlb_dat_o) +); + +`endif + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_genpc.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_genpc.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_genpc.v (revision 995) @@ -0,0 +1,282 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's generate PC //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// PC, interface to IC. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.5 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.4 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.3 2002/01/18 07:56:00 lampret +// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.10 2001/11/20 18:46:15 simons +// Break point bug fixed +// +// Revision 1.9 2001/11/18 09:58:28 lampret +// Fixed some l.trap typos. +// +// Revision 1.8 2001/11/18 08:36:28 lampret +// For GDB changed single stepping and disabled trap exception. +// +// Revision 1.7 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.6 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_genpc( + // Clock and reset + clk, rst, + + // External i/f to IC + icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o, + icpu_rty_i, icpu_adr_i, + + // Internal i/f + branch_op, except_type, except_prefix, + branch_addrofs, lr_restor, flag, taken, except_start, + binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch, + genpc_freeze, no_more_dslot +); + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// External i/f to IC +// +output [31:0] icpu_adr_o; +output icpu_cycstb_o; +output [3:0] icpu_sel_o; +output [3:0] icpu_tag_o; +input icpu_rty_i; +input [31:0] icpu_adr_i; + +// +// Internal i/f +// +input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +input [`OR1200_EXCEPT_WIDTH-1:0] except_type; +input except_prefix; +input [31:2] branch_addrofs; +input [31:0] lr_restor; +input flag; +output taken; +input except_start; +input [31:2] binsn_addr; +input [31:0] epcr; +input [31:0] spr_dat_i; +input spr_pc_we; +input genpc_refetch; +input genpc_freeze; +input no_more_dslot; + +// +// Internal wires and regs +// +reg [31:2] pcreg; +reg [31:0] pc; +reg taken; /* Set to in case of jump or taken branch */ + +// +// Address of insn to be fecthed +// +assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc; +// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc; + +// +// Control access to IC subsystem +// +// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot; +assign icpu_cycstb_o = !genpc_freeze; +assign icpu_sel_o = 4'b1111; +assign icpu_tag_o = `OR1200_ITAG_NI; + +// +// Async calculation of new PC value. This value is used for addressing the IC. +// +always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type + or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin + casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case + {2'b00, `OR1200_BRANCHOP_NOP}: begin + pc = {pcreg + 'd1, 2'b0}; + taken = 1'b0; + end + {2'b00, `OR1200_BRANCHOP_J}: begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs); +// synopsys translate_on +`endif + pc = {branch_addrofs, 2'b0}; + taken = 1'b1; + end + {2'b00, `OR1200_BRANCHOP_JR}: begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor); +// synopsys translate_on +`endif + pc = lr_restor; + taken = 1'b1; + end + {2'b00, `OR1200_BRANCHOP_BAL}: begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs); +// synopsys translate_on +`endif + pc = {binsn_addr + branch_addrofs, 2'b0}; + taken = 1'b1; + end + {2'b00, `OR1200_BRANCHOP_BF}: + if (flag) begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs); +// synopsys translate_on +`endif + pc = {binsn_addr + branch_addrofs, 2'b0}; + taken = 1'b1; + end + else begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("%t: BRANCHOP_BF: not taken", $time); +// synopsys translate_on +`endif + pc = {pcreg + 'd1, 2'b0}; + taken = 1'b0; + end + {2'b00, `OR1200_BRANCHOP_BNF}: + if (flag) begin + pc = {pcreg + 'd1, 2'b0}; +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("%t: BRANCHOP_BNF: not taken", $time); +// synopsys translate_on +`endif + taken = 1'b0; + end + else begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs); +// synopsys translate_on +`endif + pc = {binsn_addr + branch_addrofs, 2'b0}; + taken = 1'b1; + end + {2'b00, `OR1200_BRANCHOP_RFE}: begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr); +// synopsys translate_on +`endif + pc = epcr; + taken = 1'b1; + end + {2'b01, 3'bxxx}: begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("Starting exception: %h.", except_type); +// synopsys translate_on +`endif + pc = { {4{except_prefix}}, 16'h0000, except_type, 8'h00}; + taken = 1'b1; + end + default: begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("l.mtspr writing into PC: %h.", spr_dat_i); +// synopsys translate_on +`endif + pc = spr_dat_i; + taken = 1'b0; + end + endcase +end + +// +// PC register +// +always @(posedge clk or posedge rst) + if (rst) + pcreg <= #1 30'd63; + else if (spr_pc_we) + pcreg <= #1 spr_dat_i[31:2]; + else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch) +// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch) + pcreg <= #1 pc[31:2]; + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_reg2mem.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_reg2mem.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_reg2mem.v (revision 995) @@ -0,0 +1,134 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's reg2mem aligner //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Aligns register data to memory alignment. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.9 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.8 2001/10/19 23:28:46 lampret +// Fixed some synthesis warnings. Configured with caches and MMUs. +// +// Revision 1.7 2001/10/14 13:12:10 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:21 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_reg2mem(addr, lsu_op, regdata, memdata); + +parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// +input [1:0] addr; +input [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +input [width-1:0] regdata; +output [width-1:0] memdata; + +// +// Internal regs and wires +// +reg [7:0] memdata_hh; +reg [7:0] memdata_hl; +reg [7:0] memdata_lh; +reg [7:0] memdata_ll; + +assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll}; + +// +// Mux to memdata[31:24] +// +always @(lsu_op or addr or regdata) begin + casex({lsu_op, addr[1:0]}) // synopsys parallel_case + {`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0]; + {`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8]; + default : memdata_hh = regdata[31:24]; + endcase +end + +// +// Mux to memdata[23:16] +// +always @(lsu_op or addr or regdata) begin + casex({lsu_op, addr[1:0]}) // synopsys parallel_case + {`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16]; + default : memdata_hl = regdata[7:0]; + endcase +end + +// +// Mux to memdata[15:8] +// +always @(lsu_op or addr or regdata) begin + casex({lsu_op, addr[1:0]}) // synopsys parallel_case + {`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0]; + default : memdata_lh = regdata[15:8]; + endcase +end + +// +// Mux to memdata[7:0] +// +always @(regdata) + memdata_ll = regdata[7:0]; + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_mem2reg.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_mem2reg.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_mem2reg.v (revision 995) @@ -0,0 +1,382 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's mem2reg alignment //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Two versions of Memory to register data alignment. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2002/03/28 19:14:10 lampret +// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.9 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.8 2001/10/19 23:28:46 lampret +// Fixed some synthesis warnings. Configured with caches and MMUs. +// +// Revision 1.7 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_mem2reg(addr, lsu_op, memdata, regdata); + +parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// +input [1:0] addr; +input [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +input [width-1:0] memdata; +output [width-1:0] regdata; + + +// +// In the past faster implementation of mem2reg (today probably slower) +// +`ifdef OR1200_IMPL_MEM2REG2 + +`define OR1200_M2R_BYTE0 4'b0000 +`define OR1200_M2R_BYTE1 4'b0001 +`define OR1200_M2R_BYTE2 4'b0010 +`define OR1200_M2R_BYTE3 4'b0011 +`define OR1200_M2R_EXTB0 4'b0100 +`define OR1200_M2R_EXTB1 4'b0101 +`define OR1200_M2R_EXTB2 4'b0110 +`define OR1200_M2R_EXTB3 4'b0111 +`define OR1200_M2R_ZERO 4'b0000 + +reg [7:0] regdata_hh; +reg [7:0] regdata_hl; +reg [7:0] regdata_lh; +reg [7:0] regdata_ll; +reg [width-1:0] aligned; +reg [3:0] sel_byte0, sel_byte1, + sel_byte2, sel_byte3; + +assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll}; + +// +// Byte select 0 +// +always @(addr or lsu_op) begin + casex({lsu_op[2:0], addr}) // synopsys parallel_case + {3'b01x, 2'b00}: // lbz/lbs 0 + sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3 + {3'b01x, 2'b01}, // lbz/lbs 1 + {3'b10x, 2'b00}: // lhz/lhs 0 + sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2 + {3'b01x, 2'b10}: // lbz/lbs 2 + sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1 + default: // all other cases + sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0 + endcase +end + +// +// Byte select 1 +// +always @(addr or lsu_op) begin + casex({lsu_op[2:0], addr}) // synopsys parallel_case + {3'b010, 2'bxx}: // lbz + sel_byte1 = `OR1200_M2R_ZERO; // zero extend + {3'b011, 2'b00}: // lbs 0 + sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3 + {3'b011, 2'b01}: // lbs 1 + sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2 + {3'b011, 2'b10}: // lbs 2 + sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1 + {3'b011, 2'b11}: // lbs 3 + sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0 + {3'b10x, 2'b00}: // lhz/lhs 0 + sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3 + default: // all other cases + sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1 + endcase +end + +// +// Byte select 2 +// +always @(addr or lsu_op) begin + casex({lsu_op[2:0], addr}) // synopsys parallel_case + {3'b010, 2'bxx}, // lbz + {3'b100, 2'bxx}: // lhz + sel_byte2 = `OR1200_M2R_ZERO; // zero extend + {3'b011, 2'b00}, // lbs 0 + {3'b101, 2'b00}: // lhs 0 + sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3 + {3'b011, 2'b01}: // lbs 1 + sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2 + {3'b011, 2'b10}, // lbs 2 + {3'b101, 2'b10}: // lhs 0 + sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1 + {3'b011, 2'b11}: // lbs 3 + sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0 + default: // all other cases + sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2 + endcase +end + +// +// Byte select 3 +// +always @(addr or lsu_op) begin + casex({lsu_op[2:0], addr}) // synopsys parallel_case + {3'b010, 2'bxx}, // lbz + {3'b100, 2'bxx}: // lhz + sel_byte3 = `OR1200_M2R_ZERO; // zero extend + {3'b011, 2'b00}, // lbs 0 + {3'b101, 2'b00}: // lhs 0 + sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3 + {3'b011, 2'b01}: // lbs 1 + sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2 + {3'b011, 2'b10}, // lbs 2 + {3'b101, 2'b10}: // lhs 0 + sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1 + {3'b011, 2'b11}: // lbs 3 + sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0 + default: // all other cases + sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3 + endcase +end + +// +// Byte 0 +// +always @(sel_byte0 or memdata) begin +`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + case(sel_byte0) // synopsys full_case parallel_case infer_mux +`else + case(sel_byte0) // synopsys full_case parallel_case +`endif + `OR1200_M2R_BYTE0: begin + regdata_ll = memdata[7:0]; + end + `OR1200_M2R_BYTE1: begin + regdata_ll = memdata[15:8]; + end + `OR1200_M2R_BYTE2: begin + regdata_ll = memdata[23:16]; + end + `OR1200_M2R_BYTE3: begin + regdata_ll = memdata[31:24]; + end + endcase +end + +// +// Byte 1 +// +always @(sel_byte1 or memdata) begin +`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + case(sel_byte1) // synopsys full_case parallel_case infer_mux +`else + case(sel_byte1) // synopsys full_case parallel_case +`endif + `OR1200_M2R_ZERO: begin + regdata_lh = 8'h00; + end + `OR1200_M2R_BYTE1: begin + regdata_lh = memdata[15:8]; + end + `OR1200_M2R_BYTE3: begin + regdata_lh = memdata[31:24]; + end + `OR1200_M2R_EXTB0: begin + regdata_lh = {8{memdata[7]}}; + end + `OR1200_M2R_EXTB1: begin + regdata_lh = {8{memdata[15]}}; + end + `OR1200_M2R_EXTB2: begin + regdata_lh = {8{memdata[23]}}; + end + `OR1200_M2R_EXTB3: begin + regdata_lh = {8{memdata[31]}}; + end + endcase +end + +// +// Byte 2 +// +always @(sel_byte2 or memdata) begin +`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + case(sel_byte2) // synopsys full_case parallel_case infer_mux +`else + case(sel_byte2) // synopsys full_case parallel_case +`endif + `OR1200_M2R_ZERO: begin + regdata_hl = 8'h00; + end + `OR1200_M2R_BYTE2: begin + regdata_hl = memdata[23:16]; + end + `OR1200_M2R_EXTB0: begin + regdata_hl = {8{memdata[7]}}; + end + `OR1200_M2R_EXTB1: begin + regdata_hl = {8{memdata[15]}}; + end + `OR1200_M2R_EXTB2: begin + regdata_hl = {8{memdata[23]}}; + end + `OR1200_M2R_EXTB3: begin + regdata_hl = {8{memdata[31]}}; + end + endcase +end + +// +// Byte 3 +// +always @(sel_byte3 or memdata) begin +`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + case(sel_byte3) // synopsys full_case parallel_case infer_mux +`else + case(sel_byte3) // synopsys full_case parallel_case +`endif + `OR1200_M2R_ZERO: begin + regdata_hh = 8'h00; + end + `OR1200_M2R_BYTE3: begin + regdata_hh = memdata[31:24]; + end + `OR1200_M2R_EXTB0: begin + regdata_hh = {8{memdata[7]}}; + end + `OR1200_M2R_EXTB1: begin + regdata_hh = {8{memdata[15]}}; + end + `OR1200_M2R_EXTB2: begin + regdata_hh = {8{memdata[23]}}; + end + `OR1200_M2R_EXTB3: begin + regdata_hh = {8{memdata[31]}}; + end + endcase +end + +`else + +// +// Straightforward implementation of mem2reg +// + +reg [width-1:0] regdata; +reg [width-1:0] aligned; + +// +// Alignment +// +always @(addr or memdata) begin +`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + case(addr) // synopsys infer_mux +`else + case(addr) // synopsys full_case parallel_case +`endif + 2'b00: + aligned = memdata; + 2'b01: + aligned = {memdata[23:0], 8'b0}; + 2'b10: + aligned = {memdata[15:0], 16'b0}; + 2'b11: + aligned = {memdata[7:0], 24'b0}; + endcase +end + +// +// Bytes +// +always @(lsu_op or aligned) begin +`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + case(lsu_op) // synopsys infer_mux +`else + case(lsu_op) // synopsys parallel_case +`endif + `OR1200_LSUOP_LBZ: begin + regdata[7:0] = aligned[31:24]; + regdata[31:8] = 24'b0; + end + `OR1200_LSUOP_LBS: begin + regdata[7:0] = aligned[31:24]; + regdata[31:8] = {24{aligned[31]}}; + end + `OR1200_LSUOP_LHZ: begin + regdata[15:0] = aligned[31:16]; + regdata[31:16] = 16'b0; + end + `OR1200_LSUOP_LHS: begin + regdata[15:0] = aligned[31:16]; + regdata[31:16] = {16{aligned[31]}}; + end + default: + regdata = aligned; + endcase +end + +`endif + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_ic_fsm.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_ic_fsm.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_ic_fsm.v (revision 995) @@ -0,0 +1,252 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's IC FSM //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Data cache state machine //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.6 2002/03/28 19:10:40 lampret +// Optimized cache controller FSM. +// +// Revision 1.1.1.1 2002/03/21 16:55:45 lampret +// First import of the "new" XESS XSV environment. +// +// +// Revision 1.5 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.4 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.3 2002/01/28 01:16:00 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.9 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF. +// +// Revision 1.8 2001/10/19 23:28:46 lampret +// Fixed some synthesis warnings. Configured with caches and MMUs. +// +// Revision 1.7 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:35 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +`define OR1200_ICFSM_IDLE 2'd0 +`define OR1200_ICFSM_CFETCH 2'd1 +`define OR1200_ICFSM_LREFILL3 2'd2 +`define OR1200_ICFSM_IFETCH 2'd3 + +// +// Data cache FSM for cache line of 16 bytes (4x singleword) +// + +module or1200_ic_fsm( + // Clock and reset + clk, rst, + + // Internal i/f to top level IC + ic_en, icimmu_cycstb_i, icimmu_ci_i, + tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr, + icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err, + burst, tag_we +); + +// +// I/O +// +input clk; +input rst; +input ic_en; +input icimmu_cycstb_i; +input icimmu_ci_i; +input tagcomp_miss; +input biudata_valid; +input biudata_error; +input [31:0] start_addr; +output [31:0] saved_addr; +output [3:0] icram_we; +output biu_read; +output first_hit_ack; +output first_miss_ack; +output first_miss_err; +output burst; +output tag_we; + +// +// Internal wires and regs +// +reg [31:0] saved_addr_r; +reg [1:0] state; +reg [2:0] cnt; +reg hitmiss_eval; +reg load; +reg cache_inhibit; + +// +// Generate of ICRAM write enables +// +assign icram_we = {4{load & biudata_valid & !cache_inhibit}}; +assign tag_we = biu_read & biudata_valid & !cache_inhibit; + +// +// BIU read and write +// +assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load); + +//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r; +assign saved_addr = saved_addr_r; + +// +// Assert for cache hit first word ready +// Assert for cache miss first word stored/loaded OK +// Assert for cache miss first word stored/loaded with an error +// +assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icimmu_ci_i; +assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid; +assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error; + +// +// Assert burst when doing reload of complete cache line +// +assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit + | (state == `OR1200_ICFSM_LREFILL3); + +// +// Main IC FSM +// +always @(posedge clk or posedge rst) begin + if (rst) begin + state <= #1 `OR1200_ICFSM_IDLE; + saved_addr_r <= #1 32'b0; + hitmiss_eval <= #1 1'b0; + load <= #1 1'b0; + cnt <= #1 3'b000; + cache_inhibit <= #1 1'b0; + end + else + case (state) // synopsys parallel_case + `OR1200_ICFSM_IDLE : + if (ic_en & icimmu_cycstb_i) begin // fetch + state <= #1 `OR1200_ICFSM_CFETCH; + saved_addr_r <= #1 start_addr; + hitmiss_eval <= #1 1'b1; + load <= #1 1'b1; + cache_inhibit <= #1 1'b0; + end + else begin // idle + hitmiss_eval <= #1 1'b0; + load <= #1 1'b0; + cache_inhibit <= #1 1'b0; + end + `OR1200_ICFSM_CFETCH: begin // fetch + if (icimmu_cycstb_i & icimmu_ci_i) + cache_inhibit <= #1 1'b1; + if (hitmiss_eval) + saved_addr_r[31:13] <= #1 start_addr[31:13]; + if ((!ic_en) || + (hitmiss_eval & !icimmu_cycstb_i) || // fetch aborted (usually caused by IMMU) + (biudata_error) || // fetch terminated with an error + (cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page + state <= #1 `OR1200_ICFSM_IDLE; + hitmiss_eval <= #1 1'b0; + load <= #1 1'b0; + cache_inhibit <= #1 1'b0; + end + else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill + state <= #1 `OR1200_ICFSM_LREFILL3; + saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1; + hitmiss_eval <= #1 1'b0; + cnt <= #1 `OR1200_ICLS-2; + cache_inhibit <= #1 1'b0; + end + else if (!tagcomp_miss & !icimmu_ci_i) begin // fetch hit, finish immediately + saved_addr_r <= #1 start_addr; + cache_inhibit <= #1 1'b0; + end + else if (!icimmu_cycstb_i) begin // fetch aborted (usually caused by exception) + state <= #1 `OR1200_ICFSM_IDLE; + hitmiss_eval <= #1 1'b0; + load <= #1 1'b0; + cache_inhibit <= #1 1'b0; + end + else // fetch in-progress + hitmiss_eval <= #1 1'b0; + end + `OR1200_ICFSM_LREFILL3 : begin + if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come + cnt <= #1 cnt - 'd1; + saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1; + end + else if (biudata_valid) begin // last fetch of line refill + state <= #1 `OR1200_ICFSM_IDLE; + saved_addr_r <= #1 start_addr; + hitmiss_eval <= #1 1'b0; + load <= #1 1'b0; + end + end + default: + state <= #1 `OR1200_ICFSM_IDLE; + endcase +end + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_lsu.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_lsu.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_lsu.v (revision 995) @@ -0,0 +1,192 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Load/Store unit //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Interface between CPU and DC. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.2 2002/01/18 07:56:00 lampret +// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.9 2001/11/30 18:59:47 simons +// *** empty log message *** +// +// Revision 1.8 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.7 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.2 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_lsu( + + // Internal i/f + addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall, + du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr, + + // External i/f to DC + dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o, + dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_REGFILE_ADDR_WIDTH; + +// +// I/O +// + +// +// Internal i/f +// +input [31:0] addrbase; +input [31:0] addrofs; +input [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +input [dw-1:0] lsu_datain; +output [dw-1:0] lsu_dataout; +output lsu_stall; +output lsu_unstall; +input du_stall; +output except_align; +output except_dtlbmiss; +output except_dmmufault; +output except_dbuserr; + +// +// External i/f to DC +// +output [31:0] dcpu_adr_o; +output dcpu_cycstb_o; +output dcpu_we_o; +output [3:0] dcpu_sel_o; +output [3:0] dcpu_tag_o; +output [31:0] dcpu_dat_o; +input [31:0] dcpu_dat_i; +input dcpu_ack_i; +input dcpu_rty_i; +input dcpu_err_i; +input [3:0] dcpu_tag_i; + +// +// Internal wires/regs +// +reg [3:0] dcpu_sel_o; + +// +// Internal I/F assignments +// +assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o; +assign lsu_unstall = dcpu_ack_i; +assign except_align = ((lsu_op == `OR1200_LSUOP_SH) | (lsu_op == `OR1200_LSUOP_LHZ) | (lsu_op == `OR1200_LSUOP_LHS)) & dcpu_adr_o[0] + | ((lsu_op == `OR1200_LSUOP_SW) | (lsu_op == `OR1200_LSUOP_LWZ) | (lsu_op == `OR1200_LSUOP_LWS)) & |dcpu_adr_o[1:0]; +assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE); +assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE); +assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE); + +// +// External I/F assignments +// +assign dcpu_adr_o = addrbase + addrofs; +assign dcpu_cycstb_o = du_stall | lsu_unstall ? 1'b0 : |lsu_op; +assign dcpu_we_o = lsu_op[3]; +assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE; +always @(lsu_op or dcpu_adr_o) + casex({lsu_op, dcpu_adr_o[1:0]}) + {`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000; + {`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100; + {`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010; + {`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001; + {`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100; + {`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011; + {`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111; + {`OR1200_LSUOP_LBZ, 2'b00}, {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000; + {`OR1200_LSUOP_LBZ, 2'b01}, {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100; + {`OR1200_LSUOP_LBZ, 2'b10}, {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010; + {`OR1200_LSUOP_LBZ, 2'b11}, {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001; + {`OR1200_LSUOP_LHZ, 2'b00}, {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100; + {`OR1200_LSUOP_LHZ, 2'b10}, {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011; + {`OR1200_LSUOP_LWZ, 2'b00}, {`OR1200_LSUOP_LWS, 2'b00} : dcpu_sel_o = 4'b1111; + default : dcpu_sel_o = 4'b0000; + endcase + +// +// Instantiation of Memory-to-regfile aligner +// +or1200_mem2reg or1200_mem2reg( + .addr(dcpu_adr_o[1:0]), + .lsu_op(lsu_op), + .memdata(dcpu_dat_i), + .regdata(lsu_dataout) +); + +// +// Instantiation of Regfile-to-memory aligner +// +or1200_reg2mem or1200_reg2mem( + .addr(dcpu_adr_o[1:0]), + .lsu_op(lsu_op), + .regdata(lsu_datain), + .memdata(dcpu_dat_o) +); + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_ctrl.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_ctrl.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_ctrl.v (revision 995) @@ -0,0 +1,963 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Instruction decode //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Majority of instruction decoding is performed here. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.5 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.4 2002/01/28 01:15:59 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.3 2002/01/18 14:21:43 lampret +// Fixed 'the NPC single-step fix'. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.14 2001/11/30 18:59:17 simons +// force_dslot_fetch does not work - allways zero. +// +// Revision 1.13 2001/11/20 18:46:15 simons +// Break point bug fixed +// +// Revision 1.12 2001/11/18 08:36:28 lampret +// For GDB changed single stepping and disabled trap exception. +// +// Revision 1.11 2001/11/13 10:02:21 lampret +// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) +// +// Revision 1.10 2001/11/12 01:45:40 lampret +// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. +// +// Revision 1.9 2001/11/10 03:43:57 lampret +// Fixed exceptions. +// +// Revision 1.8 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.7 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.2 2001/08/13 03:36:20 lampret +// Added cfg regs. Moved all defines into one defines.v file. More cleanup. +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_ctrl( + // Clock and reset + clk, rst, + + // Internal i/f + id_freeze, ex_freeze, wb_freeze, flushpipe, if_insn, ex_insn, branch_op, branch_taken, + rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op, + wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op, + multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap, + force_dslot_fetch, no_more_dslot, ex_void, id_macrc_op, ex_macrc_op, rfe, except_illegal +); + +// +// I/O +// +input clk; +input rst; +input id_freeze; +input ex_freeze; +input wb_freeze; +input flushpipe; +input [31:0] if_insn; +output [31:0] ex_insn; +output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +input branch_taken; +output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw; +output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra; +output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb; +output rf_rda; +output rf_rdb; +output [`OR1200_ALUOP_WIDTH-1:0] alu_op; +output [`OR1200_MACOP_WIDTH-1:0] mac_op; +output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; +output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; +output [31:0] wb_insn; +output [31:0] simm; +output [31:2] branch_addrofs; +output [31:0] lsu_addrofs; +output [`OR1200_SEL_WIDTH-1:0] sel_a; +output [`OR1200_SEL_WIDTH-1:0] sel_b; +output [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +output [`OR1200_COMPOP_WIDTH-1:0] comp_op; +output [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; +output [15:0] spr_addrimm; +input wbforw_valid; +output sig_syscall; +output sig_trap; +output force_dslot_fetch; +output no_more_dslot; +output ex_void; +output id_macrc_op; +output ex_macrc_op; +output rfe; +output except_illegal; + +// +// Internal wires and regs +// +reg [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op; +reg [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +reg [`OR1200_ALUOP_WIDTH-1:0] alu_op; +reg [`OR1200_MACOP_WIDTH-1:0] mac_op; +reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; +reg [31:0] id_insn; +reg [31:0] ex_insn; +reg [31:0] wb_insn; +reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw; +reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw; +reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; +reg [31:0] lsu_addrofs; +reg [`OR1200_SEL_WIDTH-1:0] sel_a; +reg [`OR1200_SEL_WIDTH-1:0] sel_b; +reg sel_imm; +reg [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +reg [`OR1200_COMPOP_WIDTH-1:0] comp_op; +reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; +reg imm_signextend; +reg [15:0] spr_addrimm; +reg sig_syscall; +reg sig_trap; +reg except_illegal; +reg ex_macrc_op; +wire id_void; + +// +// Register file read addresses +// +assign rf_addra = if_insn[20:16]; +assign rf_addrb = if_insn[15:11]; +assign rf_rda = if_insn[31]; +assign rf_rdb = if_insn[30]; + +// +// Force fetch of delay slot instruction when jump/branch is preceeded by load/store +// instructions +// +// SIMON +// assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op)); +assign force_dslot_fetch = 1'b0; +assign no_more_dslot = |branch_op & !id_void & branch_taken | (branch_op == `OR1200_BRANCHOP_RFE); +assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16]; +assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]; + +// +// Sign/Zero extension of immediates +// +assign simm = (imm_signextend == 1'b1) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]}; + +// +// Sign extension of branch offset +// +assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]}; + +// +// l.macrc in ID stage +// +assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16]; + +// +// +// +assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) | (branch_op == `OR1200_BRANCHOP_RFE); + +// +// Generation of sel_a +// +always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw) + if ((id_insn[20:16] == rf_addrw) && rfwb_op[0]) + sel_a = `OR1200_SEL_EX_FORW; + else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid) + sel_a = `OR1200_SEL_WB_FORW; + else + sel_a = `OR1200_SEL_RF; + +// +// Generation of sel_b +// +always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw) + if (sel_imm) + sel_b = `OR1200_SEL_IMM; + else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0]) + sel_b = `OR1200_SEL_EX_FORW; + else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid) + sel_b = `OR1200_SEL_WB_FORW; + else + sel_b = `OR1200_SEL_RF; + +// +// l.macrc in EX stage +// +always @(posedge clk or posedge rst) begin + if (rst) + ex_macrc_op <= #1 1'b0; + else if (!ex_freeze & id_freeze | flushpipe) + ex_macrc_op <= #1 1'b0; + else if (!ex_freeze) + ex_macrc_op <= #1 id_macrc_op; +end + +// +// Decode of spr_addrimm +// +always @(posedge clk or posedge rst) begin + if (rst) + spr_addrimm <= #1 16'h0000; + else if (!ex_freeze & id_freeze | flushpipe) + spr_addrimm <= #1 16'h0000; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + // l.mfspr + `OR1200_OR32_MFSPR: + spr_addrimm <= #1 id_insn[15:0]; + // l.mtspr + default: + spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]}; + endcase + end +end + +// +// Decode of multicycle +// +always @(id_insn) begin + case (id_insn[31:26]) // synopsys parallel_case +`ifdef UNUSED + // l.lwz + `OR1200_OR32_LWZ: + multicycle = `OR1200_TWO_CYCLES; + + // l.lbz + `OR1200_OR32_LBZ: + multicycle = `OR1200_TWO_CYCLES; + + // l.lbs + `OR1200_OR32_LBS: + multicycle = `OR1200_TWO_CYCLES; + + // l.lhz + `OR1200_OR32_LHZ: + multicycle = `OR1200_TWO_CYCLES; + + // l.lhs + `OR1200_OR32_LHS: + multicycle = `OR1200_TWO_CYCLES; + + // l.sw + `OR1200_OR32_SW: + multicycle = `OR1200_TWO_CYCLES; + + // l.sb + `OR1200_OR32_SB: + multicycle = `OR1200_TWO_CYCLES; + + // l.sh + `OR1200_OR32_SH: + multicycle = `OR1200_TWO_CYCLES; +`endif + // ALU instructions except the one with immediate + `OR1200_OR32_ALU: + multicycle = id_insn[`OR1200_ALUMCYC_POS]; + + // Single cycle instructions + default: begin + multicycle = `OR1200_ONE_CYCLE; + end + + endcase + +end + +// +// Decode of imm_signextend +// +always @(id_insn) begin + case (id_insn[31:26]) // synopsys parallel_case + + // l.addi + `OR1200_OR32_ADDI: + imm_signextend = 1'b1; + + // l.addic + `OR1200_OR32_ADDIC: + imm_signextend = 1'b1; + + // l.xori + `OR1200_OR32_XORI: + imm_signextend = 1'b1; + + // l.muli + `OR1200_OR32_MULI: + imm_signextend = 1'b1; + + // l.maci + `OR1200_OR32_MACI: + imm_signextend = 1'b1; + + // SFXX insns with immediate + `OR1200_OR32_SFXXI: + imm_signextend = 1'b1; + + // Instructions with no or zero extended immediate + default: begin + imm_signextend = 1'b0; + end + +endcase + +end + +// +// LSU addr offset +// +always @(lsu_op or ex_insn) begin + lsu_addrofs[10:0] = ex_insn[10:0]; + case(lsu_op) // synopsys parallel_case + `OR1200_LSUOP_SW, `OR1200_LSUOP_SH, `OR1200_LSUOP_SB : + lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]}; + default : + lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]}; + endcase +end + +// +// Register file write address +// +always @(posedge clk or posedge rst) begin + if (rst) + rf_addrw <= #1 5'd0; + else if (!ex_freeze & id_freeze) + rf_addrw <= #1 5'd00; + else if (!ex_freeze) + case (pre_branch_op) // synopsys parallel_case + `OR1200_BRANCHOP_JR, `OR1200_BRANCHOP_BAL: + rf_addrw <= #1 5'd09; // link register r9 + default: + rf_addrw <= #1 id_insn[25:21]; + endcase +end + +// +// rf_addrw in wb stage (used in forwarding logic) +// +always @(posedge clk or posedge rst) begin + if (rst) + wb_rfaddrw <= #1 5'd0; + else if (!wb_freeze) + wb_rfaddrw <= #1 rf_addrw; +end + +// +// Instruction latch in id_insn +// +always @(posedge clk or posedge rst) begin + if (rst) + id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; + else if (flushpipe) + id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // id_insn[16] must be 1 + else if (!id_freeze) begin + id_insn <= #1 if_insn; +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("%t: id_insn <= %h", $time, if_insn); +// synopsys translate_on +`endif + end +end + +// +// Instruction latch in ex_insn +// +always @(posedge clk or posedge rst) begin + if (rst) + ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; + else if (!ex_freeze & id_freeze | flushpipe) + ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // ex_insn[16] must be 1 + else if (!ex_freeze) begin + ex_insn <= #1 id_insn; +`ifdef OR1200_VERBOSE +// synopsys translate_off + $display("%t: ex_insn <= %h", $time, id_insn); +// synopsys translate_on +`endif + end +end + +// +// Instruction latch in wb_insn +// +always @(posedge clk or posedge rst) begin + if (rst) + wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; + else if (flushpipe) + wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // wb_insn[16] must be 1 + else if (!wb_freeze) begin + wb_insn <= #1 ex_insn; + end +end + +// +// Decode of sel_imm +// +always @(posedge clk or posedge rst) begin + if (rst) + sel_imm <= #1 1'b0; + else if (!id_freeze) begin + case (if_insn[31:26]) // synopsys parallel_case + + // j.jalr + `OR1200_OR32_JALR: + sel_imm <= #1 1'b0; + + // l.jr + `OR1200_OR32_JR: + sel_imm <= #1 1'b0; + + // l.rfe + `OR1200_OR32_RFE: + sel_imm <= #1 1'b0; + + // l.mfspr + `OR1200_OR32_MFSPR: + sel_imm <= #1 1'b0; + + // l.mtspr + `OR1200_OR32_MTSPR: + sel_imm <= #1 1'b0; + + // l.sys, l.brk and all three sync insns + `OR1200_OR32_XSYNC: + sel_imm <= #1 1'b0; + + // l.mac/l.msb + `OR1200_OR32_MACMSB: + sel_imm <= #1 1'b0; + + // l.sw + `OR1200_OR32_SW: + sel_imm <= #1 1'b0; + + // l.sb + `OR1200_OR32_SB: + sel_imm <= #1 1'b0; + + // l.sh + `OR1200_OR32_SH: + sel_imm <= #1 1'b0; + + // ALU instructions except the one with immediate + `OR1200_OR32_ALU: + sel_imm <= #1 1'b0; + + // SFXX instructions + `OR1200_OR32_SFXX: + sel_imm <= #1 1'b0; + + // l.nop + `OR1200_OR32_NOP: + sel_imm <= #1 1'b0; + + // All instructions with immediates + default: begin + sel_imm <= #1 1'b1; + end + + endcase + + end +end + +// +// Decode of except_illegal +// +always @(posedge clk or posedge rst) begin + if (rst) + except_illegal <= #1 1'b0; + else if (!ex_freeze & id_freeze | flushpipe) + except_illegal <= #1 1'b0; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + + `OR1200_OR32_J, + `OR1200_OR32_JAL, + `OR1200_OR32_JALR, + `OR1200_OR32_JR, + `OR1200_OR32_BNF, + `OR1200_OR32_BF, + `OR1200_OR32_RFE, + `OR1200_OR32_MOVHI, + `OR1200_OR32_MFSPR, + `OR1200_OR32_XSYNC, + `OR1200_OR32_MACI, + `OR1200_OR32_LWZ, + `OR1200_OR32_LBZ, + `OR1200_OR32_LBS, + `OR1200_OR32_LHZ, + `OR1200_OR32_LHS, + `OR1200_OR32_ADDI, + `OR1200_OR32_ADDIC, + `OR1200_OR32_ANDI, + `OR1200_OR32_ORI, + `OR1200_OR32_XORI, + `OR1200_OR32_MULI, + `OR1200_OR32_SH_ROTI, + `OR1200_OR32_SFXXI, + `OR1200_OR32_MTSPR, + `OR1200_OR32_MACMSB, + `OR1200_OR32_SW, + `OR1200_OR32_SB, + `OR1200_OR32_SH, + `OR1200_OR32_ALU, + `OR1200_OR32_SFXX, + `OR1200_OR32_NOP: + except_illegal <= #1 1'b0; + + // Illegal and OR1200 unsupported instructions + default: + except_illegal <= #1 1'b1; + + endcase + + end +end + +// +// Decode of alu_op +// +always @(posedge clk or posedge rst) begin + if (rst) + alu_op <= #1 `OR1200_ALUOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + alu_op <= #1 `OR1200_ALUOP_NOP; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + + // l.j + `OR1200_OR32_J: + alu_op <= #1 `OR1200_ALUOP_IMM; + + // j.jal + `OR1200_OR32_JAL: + alu_op <= #1 `OR1200_ALUOP_IMM; + + // l.bnf + `OR1200_OR32_BNF: + alu_op <= #1 `OR1200_ALUOP_NOP; + + // l.bf + `OR1200_OR32_BF: + alu_op <= #1 `OR1200_ALUOP_NOP; + + // l.movhi + `OR1200_OR32_MOVHI: + alu_op <= #1 `OR1200_ALUOP_MOVHI; + + // l.mfspr + `OR1200_OR32_MFSPR: + alu_op <= #1 `OR1200_ALUOP_MFSR; + + // l.mtspr + `OR1200_OR32_MTSPR: + alu_op <= #1 `OR1200_ALUOP_MTSR; + + // l.addi + `OR1200_OR32_ADDI: + alu_op <= #1 `OR1200_ALUOP_ADD; + + // l.addic + `OR1200_OR32_ADDIC: + alu_op <= #1 `OR1200_ALUOP_ADD; + + // l.andi + `OR1200_OR32_ANDI: + alu_op <= #1 `OR1200_ALUOP_AND; + + // l.ori + `OR1200_OR32_ORI: + alu_op <= #1 `OR1200_ALUOP_OR; + + // l.xori + `OR1200_OR32_XORI: + alu_op <= #1 `OR1200_ALUOP_XOR; + + // l.muli + `OR1200_OR32_MULI: + alu_op <= #1 `OR1200_ALUOP_MUL; + + // Shift and rotate insns with immediate + `OR1200_OR32_SH_ROTI: + alu_op <= #1 `OR1200_ALUOP_SHROT; + + // SFXX insns with immediate + `OR1200_OR32_SFXXI: + alu_op <= #1 `OR1200_ALUOP_COMP; + + // ALU instructions except the one with immediate + `OR1200_OR32_ALU: + alu_op <= #1 id_insn[3:0]; + + // SFXX instructions + `OR1200_OR32_SFXX: + alu_op <= #1 `OR1200_ALUOP_COMP; + + // Default + default: begin + alu_op <= #1 `OR1200_ALUOP_NOP; + end + + endcase + + end +end + +// +// Decode of mac_op +// +always @(posedge clk or posedge rst) begin + if (rst) + mac_op <= #1 `OR1200_MACOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + mac_op <= #1 `OR1200_MACOP_NOP; + else if (!ex_freeze) + case (id_insn[31:26]) // synopsys parallel_case + + // l.maci + `OR1200_OR32_MACI: + mac_op <= #1 `OR1200_MACOP_MAC; + + // l.nop + `OR1200_OR32_MACMSB: + mac_op <= #1 id_insn[1:0]; + + // Illegal and OR1200 unsupported instructions + default: begin + mac_op <= #1 `OR1200_MACOP_NOP; + end + + endcase + else + mac_op <= #1 `OR1200_MACOP_NOP; +end + +// +// Decode of shrot_op +// +always @(posedge clk or posedge rst) begin + if (rst) + shrot_op <= #1 `OR1200_SHROTOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + shrot_op <= #1 `OR1200_SHROTOP_NOP; + else if (!ex_freeze) begin + shrot_op <= #1 id_insn[`OR1200_SHROTOP_POS]; + end +end + +// +// Decode of rfwb_op +// +always @(posedge clk or posedge rst) begin + if (rst) + rfwb_op <= #1 `OR1200_RFWBOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + rfwb_op <= #1 `OR1200_RFWBOP_NOP; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + + // j.jal + `OR1200_OR32_JAL: + rfwb_op <= #1 `OR1200_RFWBOP_LR; + + // j.jalr + `OR1200_OR32_JALR: + rfwb_op <= #1 `OR1200_RFWBOP_LR; + + // l.movhi + `OR1200_OR32_MOVHI: + rfwb_op <= #1 `OR1200_RFWBOP_ALU; + + // l.mfspr + `OR1200_OR32_MFSPR: + rfwb_op <= #1 `OR1200_RFWBOP_SPRS; + + // l.lwz + `OR1200_OR32_LWZ: + rfwb_op <= #1 `OR1200_RFWBOP_LSU; + + // l.lbz + `OR1200_OR32_LBZ: + rfwb_op <= #1 `OR1200_RFWBOP_LSU; + + // l.lbs + `OR1200_OR32_LBS: + rfwb_op <= #1 `OR1200_RFWBOP_LSU; + + // l.lhz + `OR1200_OR32_LHZ: + rfwb_op <= #1 `OR1200_RFWBOP_LSU; + + // l.lhs + `OR1200_OR32_LHS: + rfwb_op <= #1 `OR1200_RFWBOP_LSU; + + // l.addi + `OR1200_OR32_ADDI: + rfwb_op <= #1 `OR1200_RFWBOP_ALU; + + // l.addic + `OR1200_OR32_ADDIC: + rfwb_op <= #1 `OR1200_RFWBOP_ALU; + + // l.andi + `OR1200_OR32_ANDI: + rfwb_op <= #1 `OR1200_RFWBOP_ALU; + + // l.ori + `OR1200_OR32_ORI: + rfwb_op <= #1 `OR1200_RFWBOP_ALU; + + // l.xori + `OR1200_OR32_XORI: + rfwb_op <= #1 `OR1200_RFWBOP_ALU; + + // l.muli + `OR1200_OR32_MULI: + rfwb_op <= #1 `OR1200_RFWBOP_ALU; + + // Shift and rotate insns with immediate + `OR1200_OR32_SH_ROTI: + rfwb_op <= #1 `OR1200_RFWBOP_ALU; + + // ALU instructions except the one with immediate + `OR1200_OR32_ALU: + rfwb_op <= #1 `OR1200_RFWBOP_ALU; + + // Instructions w/o register-file write-back + default: begin + rfwb_op <= #1 `OR1200_RFWBOP_NOP; + end + + endcase + end +end + +// +// Decode of pre_branch_op +// +always @(posedge clk or posedge rst) begin + if (rst) + pre_branch_op <= #1 `OR1200_BRANCHOP_NOP; + else if (flushpipe) + pre_branch_op <= #1 `OR1200_BRANCHOP_NOP; + else if (!id_freeze) begin + case (if_insn[31:26]) // synopsys parallel_case + + // l.j + `OR1200_OR32_J: + pre_branch_op <= #1 `OR1200_BRANCHOP_BAL; + + // j.jal + `OR1200_OR32_JAL: + pre_branch_op <= #1 `OR1200_BRANCHOP_BAL; + + // j.jalr + `OR1200_OR32_JALR: + pre_branch_op <= #1 `OR1200_BRANCHOP_JR; + + // l.jr + `OR1200_OR32_JR: + pre_branch_op <= #1 `OR1200_BRANCHOP_JR; + + // l.bnf + `OR1200_OR32_BNF: + pre_branch_op <= #1 `OR1200_BRANCHOP_BNF; + + // l.bf + `OR1200_OR32_BF: + pre_branch_op <= #1 `OR1200_BRANCHOP_BF; + + // l.rfe + `OR1200_OR32_RFE: + pre_branch_op <= #1 `OR1200_BRANCHOP_RFE; + + // Non branch instructions + default: begin + pre_branch_op <= #1 `OR1200_BRANCHOP_NOP; + end + endcase + end +end + +// +// Generation of branch_op +// +always @(posedge clk or posedge rst) + if (rst) + branch_op <= #1 `OR1200_BRANCHOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + branch_op <= #1 `OR1200_BRANCHOP_NOP; + else if (!ex_freeze) + branch_op <= #1 pre_branch_op; + +// +// Decode of lsu_op +// +always @(posedge clk or posedge rst) begin + if (rst) + lsu_op <= #1 `OR1200_LSUOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + lsu_op <= #1 `OR1200_LSUOP_NOP; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + + // l.lwz + `OR1200_OR32_LWZ: + lsu_op <= #1 `OR1200_LSUOP_LWZ; + + // l.lbz + `OR1200_OR32_LBZ: + lsu_op <= #1 `OR1200_LSUOP_LBZ; + + // l.lbs + `OR1200_OR32_LBS: + lsu_op <= #1 `OR1200_LSUOP_LBS; + + // l.lhz + `OR1200_OR32_LHZ: + lsu_op <= #1 `OR1200_LSUOP_LHZ; + + // l.lhs + `OR1200_OR32_LHS: + lsu_op <= #1 `OR1200_LSUOP_LHS; + + // l.sw + `OR1200_OR32_SW: + lsu_op <= #1 `OR1200_LSUOP_SW; + + // l.sb + `OR1200_OR32_SB: + lsu_op <= #1 `OR1200_LSUOP_SB; + + // l.sh + `OR1200_OR32_SH: + lsu_op <= #1 `OR1200_LSUOP_SH; + + // Non load/store instructions + default: begin + lsu_op <= #1 `OR1200_LSUOP_NOP; + end + endcase + end +end + +// +// Decode of comp_op +// +always @(posedge clk or posedge rst) begin + if (rst) begin + comp_op <= #1 4'd0; + end else if (!ex_freeze & id_freeze | flushpipe) + comp_op <= #1 4'd0; + else if (!ex_freeze) + comp_op <= #1 id_insn[24:21]; +end + +// +// Decode of l.sys +// +always @(posedge clk or posedge rst) begin + if (rst) + sig_syscall <= #1 1'b0; + else if (!ex_freeze & id_freeze | flushpipe) + sig_syscall <= #1 1'b0; + else if (!ex_freeze) begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000}) + $display("Generating sig_syscall"); +// synopsys translate_on +`endif + sig_syscall <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000}); + end +end + +// +// Decode of l.trap +// +always @(posedge clk or posedge rst) begin + if (rst) + sig_trap <= #1 1'b0; + else if (!ex_freeze & id_freeze | flushpipe) + sig_trap <= #1 1'b0; + else if (!ex_freeze) begin +`ifdef OR1200_VERBOSE +// synopsys translate_off + if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010}) + $display("Generating sig_trap"); +// synopsys translate_on +`endif + sig_trap <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010}); + end +end + +endmodule Index: tags/rel_3/or1200/rtl/verilog/or1200_dpram_32x32.v =================================================================== --- tags/rel_3/or1200/rtl/verilog/or1200_dpram_32x32.v (nonexistent) +++ tags/rel_3/or1200/rtl/verilog/or1200_dpram_32x32.v (revision 995) @@ -0,0 +1,438 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Double-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// +//// //// +//// Description //// +//// This block is a wrapper with common double-port //// +//// synchronous memory interface for different //// +//// types of ASIC and FPGA RAMs. Beside universal memory //// +//// interface it also provides behavioral model of generic //// +//// double-port synchronous RAM. //// +//// It should be used in all OPENCORES designs that want to be //// +//// portable accross different target technologies and //// +//// independent of target memory. //// +//// //// +//// Supported ASIC RAMs are: //// +//// - Artisan Double-Port Sync RAM //// +//// - Avant! Two-Port Sync RAM (*) //// +//// - Virage 2-port Sync RAM //// +//// //// +//// Supported FPGA RAMs are: //// +//// - Xilinx Virtex RAMB4_S16_S16 //// +//// //// +//// To Do: //// +//// - fix Avant! //// +//// - xilinx rams need external tri-state logic //// +//// - add additional RAMs (Altera, VS etc) //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.5 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.4 2002/01/23 07:52:36 lampret +// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. +// +// Revision 1.3 2002/01/19 14:10:22 lampret +// Fixed OR1200_XILINX_RAM32X1D. +// +// Revision 1.2 2002/01/15 06:12:22 lampret +// Fixed module name when compiling with OR1200_XILINX_RAM32X1D +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.10 2001/11/05 14:48:00 lampret +// Added missing endif +// +// Revision 1.9 2001/11/02 18:57:14 lampret +// Modified virtual silicon instantiations. +// +// Revision 1.8 2001/10/22 19:39:56 lampret +// Fixed parameters in generic sprams. +// +// Revision 1.7 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.6 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/30 05:38:02 lampret +// Adding empty directories required by HDL coding guidelines +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "or1200_defines.v" + +module or1200_dpram_32x32( + // Generic synchronous double-port RAM interface + clk_a, rst_a, ce_a, oe_a, addr_a, do_a, + clk_b, rst_b, ce_b, we_b, addr_b, di_b +); + +// +// Default address and data buses width +// +parameter aw = 5; +parameter dw = 32; + +// +// Generic synchronous double-port RAM interface +// +input clk_a; // Clock +input rst_a; // Reset +input ce_a; // Chip enable input +input oe_a; // Output enable input +input [aw-1:0] addr_a; // address bus inputs +output [dw-1:0] do_a; // output data bus +input clk_b; // Clock +input rst_b; // Reset +input ce_b; // Chip enable input +input we_b; // Write enable input +input [aw-1:0] addr_b; // address bus inputs +input [dw-1:0] di_b; // input data bus + +// +// Internal wires and registers +// + +`ifdef OR1200_ARTISAN_SDP + +// +// Instantiation of ASIC memory: +// +// Artisan Synchronous Double-Port RAM (ra2sh) +// +`ifdef UNUSED +art_hsdp_32x32 #(dw, 1<

tags/rel_3/or1200/doc/openrisc1200_spec.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/rel_3/or1200/doc/openrisc1200_spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/rel_3/or1200/doc/openrisc1200_spec.pdf =================================================================== --- tags/rel_3/or1200/doc/openrisc1200_spec.pdf (nonexistent) +++ tags/rel_3/or1200/doc/openrisc1200_spec.pdf (revision 995)

tags/rel_3/or1200/doc/openrisc1200_spec.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/rel_3/or1200/lib/README =================================================================== --- tags/rel_3/or1200/lib/README (nonexistent) +++ tags/rel_3/or1200/lib/README (revision 995) @@ -0,0 +1 @@ +This directory containts memory and standard cell libraries. However proprietary libraries are not in OpenCores CVS. \ No newline at end of file Index: tags/rel_3/or1200/syn/gate/README =================================================================== --- tags/rel_3/or1200/syn/gate/README (nonexistent) +++ tags/rel_3/or1200/syn/gate/README (revision 995) @@ -0,0 +1 @@ +This directory containts gate-level netlists. Index: tags/rel_3/or1200/syn/logs/README =================================================================== --- tags/rel_3/or1200/syn/logs/README (nonexistent) +++ tags/rel_3/or1200/syn/logs/README (revision 995) @@ -0,0 +1 @@ +This directory containts generated reports and synthesis logs. Index: tags/rel_3/or1200/syn/scr/tech_vs_umc18.inc =================================================================== --- tags/rel_3/or1200/syn/scr/tech_vs_umc18.inc (nonexistent) +++ tags/rel_3/or1200/syn/scr/tech_vs_umc18.inc (revision 995) @@ -0,0 +1,16 @@ +/* Set Virtual Silicon UMC 0.18u standard cell library */ + +search_path = {. /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ } +snps = get_unix_variable("SYNOPSYS") +synthetic_library = { \ + snps + "/libraries/syn/dw01.sldb" \ + snps + "/libraries/syn/dw02.sldb" \ + snps + "/libraries/syn/dw03.sldb" \ + snps + "/libraries/syn/dw04.sldb" \ + snps + "/libraries/syn/dw05.sldb" \ + snps + "/libraries/syn/dw06.sldb" \ + snps + "/libraries/syn/dw07.sldb" } +target_library = { umcl18u250t2_typ.db } +link_library = target_library + synthetic_library +symbol_library = { umcl18u250t2.sdb } +

tags/rel_3/or1200/syn/scr/tech_vs_umc18.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_3/or1200/syn/scr/cons_fake_rams.inc =================================================================== --- tags/rel_3/or1200/syn/scr/cons_fake_rams.inc (nonexistent) +++ tags/rel_3/or1200/syn/scr/cons_fake_rams.inc (revision 995) @@ -0,0 +1,39 @@ +/* We "model" fake ram black boxes by setting input/output delays */ + +current_design art_hssp_128x34 +create_clock clk -period CLK_PERIOD +set_output_delay 1.12 -clock clk q +set_input_delay 0.3 -clock clk cen +set_input_delay 0.35 -clock clk wen +set_input_delay 0.1 -clock clk oen +set_input_delay 0.2 -clock clk a +set_input_delay 0.16 -clock clk d + +current_design art_hssp_512x19 +create_clock clk -period CLK_PERIOD +set_output_delay 1.12 -clock clk q +set_input_delay 0.3 -clock clk cen +set_input_delay 0.32 -clock clk wen +set_input_delay 0.1 -clock clk oen +set_input_delay 0.3 -clock clk a +set_input_delay 0.17 -clock clk d + +current_design art_hssp_2048x8 +create_clock clk -period CLK_PERIOD +set_output_delay 1.12 -clock clk q +set_input_delay 0.35 -clock clk cen +set_input_delay 0.37 -clock clk wen +set_input_delay 0.1 -clock clk oen +set_input_delay 0.35 -clock clk a +set_input_delay 0.2 -clock clk d + +current_design art_hdsp_2048x32 +create_clock clk -period CLK_PERIOD +set_output_delay 1.22 -clock clk q +set_input_delay 0.35 -clock clk cen +set_input_delay 0.41 -clock clk wen +set_input_delay 0.1 -clock clk oen +set_input_delay 0.34 -clock clk a +set_input_delay 0.2 -clock clk d + +current_design TOPLEVEL \ No newline at end of file Index: tags/rel_3/or1200/syn/scr/select_tech.inc =================================================================== --- tags/rel_3/or1200/syn/scr/select_tech.inc (nonexistent) +++ tags/rel_3/or1200/syn/scr/select_tech.inc (revision 995) @@ -0,0 +1,3 @@ +TECH = vs_umc18 /* vs_umc18, art_umc18 */ +CLK_PERIOD = 2 /* 333 MHz */ +MAX_AREA = 200000 /* Lets start lightly */ Index: tags/rel_3/or1200/syn/scr/read_fake_rams.inc =================================================================== --- tags/rel_3/or1200/syn/scr/read_fake_rams.inc (nonexistent) +++ tags/rel_3/or1200/syn/scr/read_fake_rams.inc (revision 995) @@ -0,0 +1,17 @@ +/* Set search path for verilog include files */ +search_path = search_path + { RAMS_PATH + fake/ } + +/* Read fake rams' verilog files */ +read -f verilog art_hssp_2048x8.v +read -f verilog art_hdsp_2048x32.v +read -f verilog art_hssp_512x19.v +read -f verilog art_hssp_128x34.v +read -f verilog art_hsdp_32x32.v + +/* Set dont_use attribute on black boxes */ +set_dont_touch art_hssp_512x19 +set_dont_touch art_hssp_128x34 +set_dont_touch art_hssp_2048x8 +set_dont_touch art_hdsp_2048x32 +set_dont_touch art_hsdp_32x32 + Index: tags/rel_3/or1200/syn/scr/top_or1200.scr =================================================================== --- tags/rel_3/or1200/syn/scr/top_or1200.scr (nonexistent) +++ tags/rel_3/or1200/syn/scr/top_or1200.scr (revision 995) @@ -0,0 +1,115 @@ +/* + * User defines + * + */ +TOPLEVEL = or1200 +include select_tech.inc +CLK = clk +RST = rst +CLK_PERIOD = 2.5 /* 400 MHz */ +MAX_AREA = 0 /* Push it */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = no /* yes, no */ +RAMS = art_rams18 /* fake, art_rams18 */ + +/* Starting timestamp */ +sh date + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = initial + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load RAMs */ +if (RAMS == "art_rams18") { + include tech_art_rams18.inc +} else if (RAMS == "fake") { + include read_fake_rams.inc +} else { + echo "Unsupported RAMs" + exit +} + +/* Load HDL source files */ +include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +/* +include tech_art_rams18.inc +list -libraries > ../logs/libs +link +list -libraries > ../logs/libs +*/ +uniquify +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log + +/* Apply constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Transform arithmetics */ +transform_csa -group + +/* Lets do initial synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all +} +compile -incremental -boundary_optimization -map_effort medium + +/* Generate reports for basic synthesis */ +include reports.inc + +/* Dump gate-level from basic synthesis */ +include save_design.inc + +/* Advance to incremental synthesis, push hard */ +if (DO_UNGROUP == "yes") { + ungroup -all +} +STAGE = incremental +compile -incremental -boundary_optimization -ungroup_all -map_effort high + +/* Optimize registers */ +optimize_registers + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Set area constraint */ +STAGE = final +set_max_area MAX_AREA +compile -incremental -boundary_optimization -auto_ungroup -map_effort medium + +/* Dump gate-level from final synthesis */ +include save_design.inc + +/* Generate reports for final synthesis */ +include reports.inc + +/* Verify design */ +if (NO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit + + + + Index: tags/rel_3/or1200/syn/scr/tech_art_rams18.inc =================================================================== --- tags/rel_3/or1200/syn/scr/tech_art_rams18.inc (nonexistent) +++ tags/rel_3/or1200/syn/scr/tech_art_rams18.inc (revision 995) @@ -0,0 +1,19 @@ +/* Set Artisan 0.18u RAMs */ + +search_path = search_path + { RAMS_PATH + art_hssp_2048x8/ } + { RAMS_PATH + art_hdsp_2048x32/ } \ + + { RAMS_PATH + art_hssp_512x19/ } + { RAMS_PATH + art_hssp_128x34/ } + \ + { RAMS_PATH + art_hsdp_32x32/ } +/* +add_module art_hssp_2048x8_typical_syn.lib art_hssp_2048x8_typical_syn +add_module art_hdsp_2048x32_typical_syn.lib art_hdsp_2048x32_typical_syn +add_module art_hssp_512x19_typical_syn.lib art_hssp_512x19_typical_syn +add_module -overwrite art_hssp_128x34_typical_syn.lib typical +*/ + +target_library = target_library + { art_hssp_2048x8_typical_syn.db } + \ + { art_hdsp_2048x32_typical_syn.db } + \ + { art_hssp_512x19_typical_syn.db } + \ + { art_hssp_128x34_typical_syn.db } + \ + { art_hsdp_32x32_typical_syn.db } +link_library = link_library + target_library +

tags/rel_3/or1200/syn/scr/tech_art_rams18.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_3/or1200/syn/scr/dodesign =================================================================== --- tags/rel_3/or1200/syn/scr/dodesign (nonexistent) +++ tags/rel_3/or1200/syn/scr/dodesign (revision 995) @@ -0,0 +1,9 @@ +#!/bin/sh -f + +# nohup dc_shell -f top.scr | tee ../logs/top.log +dc_shell -f top_multp2_32x32.scr > ../logs/top_multp2_32x32.log +dc_shell -f top_cpu.scr > ../logs/top_cpu.log +dc_shell -f top_dc.scr > ../logs/top_dc.log +dc_shell -f top_ic.scr > ../logs/top_ic.log +dc_shell -f top_or1200.scr > ../logs/top_or1200.log +mv command.log ../logs

tags/rel_3/or1200/syn/scr/dodesign Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/rel_3/or1200/syn/scr/top_multp2_32x32.scr =================================================================== --- tags/rel_3/or1200/syn/scr/top_multp2_32x32.scr (nonexistent) +++ tags/rel_3/or1200/syn/scr/top_multp2_32x32.scr (revision 995) @@ -0,0 +1,95 @@ +/* + * User defines for synthesizing multiplier + * + */ +TOPLEVEL = multp2_32x32 +include select_tech.inc +CLK = CLK +RST = rst +CLK_PERIOD = 2 /* 500 MHz */ +MAX_AREA = 0 /* Push hard */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = no /* yes, no */ + +/* Starting timestamp */ +sh date + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = initial + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load HDL source files */ +include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +uniquify +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log + +/* Apply constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Transform arithmetics */ +transform_csa -group + +/* Lets do basic synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all -flatten +} +compile -boundary_optimization -map_effort low + +/* Generate reports for basic synthesis */ +include reports.inc + +/* Dump gate-level from basic synthesis */ +include save_design.inc + +/* Advance to incremental synthesis, push hard */ +STAGE = incremental +compile -incremental -boundary_optimization -auto_ungroup -map_effort medium + +/* Optimize registers */ +optimize_registers + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Set area constraint */ +STAGE = final +set_max_area MAX_AREA +compile -incremental -boundary_optimization -auto_ungroup -map_effort medium + +/* Dump gate-level from final synthesis */ +include save_design.inc + +/* Generate reports for final synthesis */ +include reports.inc + +/* Verify design */ +if (DO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit + + + + Index: tags/rel_3/or1200/syn/scr/cons_art_umc18.inc =================================================================== --- tags/rel_3/or1200/syn/scr/cons_art_umc18.inc (nonexistent) +++ tags/rel_3/or1200/syn/scr/cons_art_umc18.inc (revision 995) @@ -0,0 +1,47 @@ +/* Constraints */ +CLK_UNCERTAINTY = 0.1 /* 100 ps */ +DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */ +DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */ + +/* Clocks constraints */ +create_clock CLK -period CLK_PERIOD +set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY +set_dont_touch_network all_clocks() + +/* Reset constraints */ +set_driving_cell -none RST +set_drive 0 RST +set_dont_touch_network RST + +/* All inputs except reset and clock */ +all_inputs_wo_rst_clk = all_inputs() - CLK - RST + +/* Set output delays and load for output signals + * + * All outputs are assumed to go directly into + * external flip-flops for the purpose of this + * synthesis + */ +set_output_delay DFFHQX2_SETUP -clock CLK all_outputs() +set_load load_of(typical/DFFHQX2/D) * 4 all_outputs() + +/* Input delay and driving cell of all inputs + * + * All these signals are assumed to come directly from + * flip-flops for the purpose of this synthesis + * + */ +set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk +set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk + +/* Set design fanout */ +/* +set_max_fanout 10 TOPLEVEL +*/ + +/* Optimize all near-critical paths to give extra slack for layout */ +c_range = CLK_PERIOD * 0.1 +group_path -critical_range c_range -name CLK -to CLK + +/* Operating conditions */ +set_operating_conditions typical Index: tags/rel_3/or1200/syn/scr/top_dc.scr =================================================================== --- tags/rel_3/or1200/syn/scr/top_dc.scr (nonexistent) +++ tags/rel_3/or1200/syn/scr/top_dc.scr (revision 995) @@ -0,0 +1,107 @@ +/* + * User defines for synthesizing data cache / DMMU unit + * + */ +TOPLEVEL = dc +include select_tech.inc +CLK = clk +RST = rst +CLK_PERIOD = 1.8 /* 555 MHz */ +MAX_AREA = 0 /* Push hard */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = yes /* yes, no */ +RAMS = art_rams18 /* fake, art_rams18 */ + +/* Starting timestamp */ +sh date + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = initial + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load RAMs */ +if (RAMS == "art_rams18") { + include tech_art_rams18.inc +} else if (RAMS == "fake") { + include read_fake_rams.inc +} else { + echo "Unsupported RAMs" + exit +} + +/* Load HDL source files */ +include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +transform_csa -group +uniquify +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log + +/* Apply constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Transform arithmetics */ +transform_csa -group + +/* Lets do basic synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all -flatten +} +compile -boundary_optimization -map_effort low + +/* Generate reports for basic synthesis */ +include reports.inc + +/* Dump gate-level from basic synthesis */ +include save_design.inc + +/* Advance to incremental synthesis, push hard */ +STAGE = incremental +compile -incremental -boundary_optimization -ungroup_all -map_effort high + +/* Optimize registers */ +optimize_registers + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Set area constraint */ +STAGE = final +set_max_area MAX_AREA +compile -incremental -boundary_optimization -auto_ungroup -map_effort medium + +/* Dump gate-level from final synthesis */ +include save_design.inc + +/* Generate reports for final synthesis */ +include reports.inc + +/* Verify design */ +if (DO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit + + + + Index: tags/rel_3/or1200/syn/scr/save_design.inc =================================================================== --- tags/rel_3/or1200/syn/scr/save_design.inc (nonexistent) +++ tags/rel_3/or1200/syn/scr/save_design.inc (revision 995) @@ -0,0 +1,5 @@ +/* Save current design using synopsys format */ +write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db + +/* Save current design using verilog format */ +write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v Index: tags/rel_3/or1200/syn/scr/cons_vs_umc18.inc =================================================================== --- tags/rel_3/or1200/syn/scr/cons_vs_umc18.inc (nonexistent) +++ tags/rel_3/or1200/syn/scr/cons_vs_umc18.inc (revision 995) @@ -0,0 +1,50 @@ +/* Constraints */ +CLK_UNCERTAINTY = 0.1 /* 100 ps */ +DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */ +DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */ + +/* Clocks constraints */ +create_clock CLK -period CLK_PERIOD +set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY +set_dont_touch_network all_clocks() + +/* Reset constraints */ +set_driving_cell -none RST +set_drive 0 RST +set_dont_touch_network RST + +/* All inputs except reset and clock */ +all_inputs_wo_rst_clk = all_inputs() - CLK - RST + +/* Set output delays and load for output signals + * + * All outputs are assumed to go directly into + * external flip-flops for the purpose of this + * synthesis + */ +set_output_delay DFFPQ2_SETUP -clock CLK all_outputs() +set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs() + +/* Input delay and driving cell of all inputs + * + * All these signals are assumed to come directly from + * flip-flops for the purpose of this synthesis + * + */ +set_input_delay DFFPQ2_CKQ -clock CLK all_inputs_wo_rst_clk +set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk + +/* Set design fanout */ +/* +set_max_fanout 10 TOPLEVEL +*/ + +/* Set area constraint */ +set_max_area MAX_AREA + +/* Optimize all near-critical paths to give extra slack for layout */ +c_range = CLK_PERIOD * 0.1 +group_path -critical_range c_range -name CLK -to CLK + +/* Operating conditions */ +set_operating_conditions TYPICAL Index: tags/rel_3/or1200/syn/scr/top_cpu.scr =================================================================== --- tags/rel_3/or1200/syn/scr/top_cpu.scr (nonexistent) +++ tags/rel_3/or1200/syn/scr/top_cpu.scr (revision 995) @@ -0,0 +1,112 @@ +/* + * User defines for synthesizing CPU + * + */ +TOPLEVEL = cpu +include select_tech.inc +CLK = clk +RST = rst +CLK_PERIOD = 2.25 /* 444 MHz */ +MAX_AREA = 0 /* Push hard */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = no /* yes, no */ +RAMS = art_rams18 /* fake, art_rams18 */ + +/* Starting timestamp */ +sh date + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = initial + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load RAMs */ +if (RAMS == "art_rams18") { + include tech_art_rams18.inc +} else if (RAMS == "fake") { + include read_fake_rams.inc +} else { + echo "Unsupported RAMs" + exit +} + +/* Load HDL source files */ +include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +uniquify +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log + +/* Apply constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Transform arithmetics */ +transform_csa -group + +/* Don't touch multp2_32x32 */ +set_dont_touch multp2_32x32 + +/* Lets do basic synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all +} +compile -boundary_optimization -ungroup_all -map_effort medium + +/* Generate reports for basic synthesis */ +include reports.inc + +/* Dump gate-level from basic synthesis */ +include save_design.inc + +/* Remove dont_touch from multp2_32x32 */ +remove_attribute multp2_32x32 dont_touch + +/* Advance to incremental synthesis, push hard */ +STAGE = incremental +compile -incremental -boundary_optimization -ungroup_all -map_effort high + +/* Optimize registers */ +optimize_registers + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Set area constraint */ +STAGE = final +set_max_area MAX_AREA +compile -incremental -boundary_optimization -auto_ungroup -map_effort medium + +/* Dump gate-level from final synthesis */ +include save_design.inc + +/* Generate reports for final synthesis */ +include reports.inc + +/* Verify design */ +if (DO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit + + + + Index: tags/rel_3/or1200/syn/scr/top_ic.scr =================================================================== --- tags/rel_3/or1200/syn/scr/top_ic.scr (nonexistent) +++ tags/rel_3/or1200/syn/scr/top_ic.scr (revision 995) @@ -0,0 +1,106 @@ +/* + * User defines for synthesizing insn cache / IMMU unit + * + */ +TOPLEVEL = ic +include select_tech.inc +CLK = clk +RST = rst +CLK_PERIOD = 1.8 /* 555 MHz */ +MAX_AREA = 0 /* Push hard */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = yes /* yes, no */ +RAMS = art_rams18 /* fake, art_rams18 */ + +/* Starting timestamp */ +sh date + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = initial + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load RAMs */ +if (RAMS == "art_rams18") { + include tech_art_rams18.inc +} else if (RAMS == "fake") { + include read_fake_rams.inc +} else { + echo "Unsupported RAMs" + exit +} + +/* Load HDL source files */ +include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +uniquify +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log + +/* Apply constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Transform arithmetics */ +transform_csa -group + +/* Lets do basic synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all -flatten +} +compile -boundary_optimization -map_effort low + +/* Generate reports for basic synthesis */ +include reports.inc + +/* Dump gate-level from basic synthesis */ +include save_design.inc + +/* Advance to incremental synthesis, push hard */ +STAGE = incremental +compile -incremental -boundary_optimization -ungroup_all -map_effort high + +/* Optimize registers */ +optimize_registers + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Set area constraint */ +STAGE = final +set_max_area MAX_AREA +compile -incremental -boundary_optimization -auto_ungroup -map_effort medium + +/* Dump gate-level from final synthesis */ +include save_design.inc + +/* Generate reports for final synthesis */ +include reports.inc + +/* Verify design */ +if (DO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit + + + + Index: tags/rel_3/or1200/syn/scr/reports.inc =================================================================== --- tags/rel_3/or1200/syn/scr/reports.inc (nonexistent) +++ tags/rel_3/or1200/syn/scr/reports.inc (revision 995) @@ -0,0 +1,10 @@ +/* Basic reports */ +report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log +report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log +report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log +report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log +report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log +/* +report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log +*/ + Index: tags/rel_3/or1200/syn/scr/set_env.inc =================================================================== --- tags/rel_3/or1200/syn/scr/set_env.inc (nonexistent) +++ tags/rel_3/or1200/syn/scr/set_env.inc (revision 995) @@ -0,0 +1,21 @@ +/* Enable Verilog HDL preprocessor */ +hdlin_enable_vpp = true + +/* Enable power analysis */ +power_preserve_rtl_hier_names = true + +/* Set log path */ +LOG_PATH = "../logs/" + +/* Set gate-level netlist path */ +GATE_PATH = "../gate/" + +/* Set RAMS_PATH */ +RAMS_PATH = "../../lib/" + +/* Set RTL source path */ +RTL_PATH = "../../rtl/" + +/* Optimize adders */ +synlib_model_map_effort = high +hlo_share_effort = medium Index: tags/rel_3/or1200/syn/scr/read_design.inc =================================================================== --- tags/rel_3/or1200/syn/scr/read_design.inc (nonexistent) +++ tags/rel_3/or1200/syn/scr/read_design.inc (revision 995) @@ -0,0 +1,56 @@ +/* Set search path for verilog include files */ +search_path = search_path + { RTL_PATH } + { GATE_PATH } + +/* Read verilog files of the Data cache / DMMU */ +if (TOPLEVEL == "dc") { + read -f verilog dc_fsm.v + read -f verilog reg2mem.v + read -f verilog mem2reg.v + read -f verilog dc_ram.v + read -f verilog dc_tag.v + read -f verilog dtlb.v + read -f verilog dc.v +} + +/* Read verilog files for the multiplier */ +if (TOPLEVEL == "multp2_32x32") { + read -f verilog multp2_32x32.v +} + +/* Read verilog files of the CPU */ +if (TOPLEVEL == "cpu") { + read -f verilog alu.v + read -f verilog except.v + read -f verilog frz_logic.v + read -f verilog id.v + read -f verilog ifetch.v + read -f verilog lsu.v + read -f db incremental_multp2_32x32.db + read -f verilog operandmuxes.v + read -f verilog rf.v + read -f verilog sprs.v + read -f verilog traceport.v + read -f verilog wbmux.v + read -f verilog cpu.v +} + +/* Read verilog files of the Instructino cache / IMMU */ +if (TOPLEVEL == "ic") { + read -f verilog ic_fsm.v + read -f verilog ic_ram.v + read -f verilog ic_tag.v + read -f verilog itlb.v + read -f verilog ic.v +} + +/* Top level OR1200 + various smaller OR1200 units */ +if (TOPLEVEL == "or1200") { + read -f verilog pic.v + read -f verilog pm.v + read -f verilog tt.v + read -f verilog wb_biu.v + read -f db incremental_dc.db + read -f db incremental_cpu.db + read -f db incremental_ic.db + read -f verilog or1200.v +} Index: tags/rel_3/or1200/syn/scr/tech_art_umc18.inc =================================================================== --- tags/rel_3/or1200/syn/scr/tech_art_umc18.inc (nonexistent) +++ tags/rel_3/or1200/syn/scr/tech_art_umc18.inc (revision 995) @@ -0,0 +1,17 @@ +/* Set Virtual Silicon UMC 0.18u standard cell library */ + +search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \ + { /libs/Artisan/aci/sc-x/symbols/synopsys/ } +snps = get_unix_variable("SYNOPSYS") +synthetic_library = { \ + snps + "/libraries/syn/dw01.sldb" \ + snps + "/libraries/syn/dw02.sldb" \ + snps + "/libraries/syn/dw03.sldb" \ + snps + "/libraries/syn/dw04.sldb" \ + snps + "/libraries/syn/dw05.sldb" \ + snps + "/libraries/syn/dw06.sldb" \ + snps + "/libraries/syn/dw07.sldb" } +target_library = { typical.db } +link_library = target_library + synthetic_library +symbol_library = { umc18.sdb } +

tags/rel_3/or1200/syn/scr/tech_art_umc18.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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