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/uart.v
0,0 → 1,212
`timescale 1ns / 1ps
// Documented Verilog UART
// Copyright (C) 2010 Timothy Goddard (tim@goddard.net.nz)
// Distributed under the MIT licence.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
module uart(
input clk, // The master clock for this module
input rst, // Synchronous reset.
input rx, // Incoming serial line
output tx, // Outgoing serial line
input transmit, // Signal to transmit
input [7:0] tx_byte, // Byte to transmit
output received, // Indicated that a byte has been received.
output [7:0] rx_byte, // Byte received
output is_receiving, // Low when receive line is idle.
output is_transmitting, // Low when transmit line is idle.
output recv_error // Indicates error in receiving packet.
);
 
parameter CLOCK_DIVIDE = 325; // clock rate (50Mhz) / baud rate (9600) / 16
 
// States for the receiving state machine.
// These are just constants, not parameters to override.
parameter RX_IDLE = 0;
parameter RX_CHECK_START = 1;
parameter RX_READ_BITS = 2;
parameter RX_CHECK_STOP = 3;
parameter RX_DELAY_RESTART = 4;
parameter RX_ERROR = 5;
parameter RX_RECEIVED = 6;
 
// States for the transmitting state machine.
// Constants - do not override.
parameter TX_IDLE = 0;
parameter TX_SENDING = 1;
parameter TX_DELAY_RESTART = 2;
 
reg [10:0] clk_divider = CLOCK_DIVIDE;
 
reg [2:0] recv_state = RX_IDLE;
reg [5:0] rx_countdown;
reg [3:0] rx_bits_remaining;
reg [7:0] rx_data;
 
reg tx_out = 1'b1;
reg [1:0] tx_state = TX_IDLE;
reg [5:0] tx_countdown;
reg [3:0] tx_bits_remaining;
reg [7:0] tx_data;
 
assign received = recv_state == RX_RECEIVED;
assign recv_error = recv_state == RX_ERROR;
assign is_receiving = recv_state != RX_IDLE;
assign rx_byte = rx_data;
 
assign tx = tx_out;
assign is_transmitting = tx_state != TX_IDLE;
 
always @(posedge clk) begin
if (rst) begin
recv_state = RX_IDLE;
tx_state = TX_IDLE;
end
// The clk_divider counter counts down from
// the CLOCK_DIVIDE constant. Whenever it
// reaches 0, 1/16 of the bit period has elapsed.
// Countdown timers for the receiving and transmitting
// state machines are decremented.
clk_divider = clk_divider - 1;
if (!clk_divider) begin
clk_divider = CLOCK_DIVIDE;
rx_countdown = rx_countdown - 1;
tx_countdown = tx_countdown - 1;
end
// Receive state machine
case (recv_state)
RX_IDLE: begin
// A low pulse on the receive line indicates the
// start of data.
if (!rx) begin
// Wait half the period - should resume in the
// middle of this first pulse.
rx_countdown = 8;
recv_state = RX_CHECK_START;
end
end
RX_CHECK_START: begin
if (!rx_countdown) begin
// Check the pulse is still there
if (!rx) begin
// Pulse still there - good
// Wait the bit period to resume half-way
// through the first bit.
rx_countdown = 16;
rx_bits_remaining = 8;
recv_state = RX_READ_BITS;
end else begin
// Pulse lasted less than half the period -
// not a valid transmission.
recv_state = RX_ERROR;
end
end
end
RX_READ_BITS: begin
if (!rx_countdown) begin
// Should be half-way through a bit pulse here.
// Read this bit in, wait for the next if we
// have more to get.
rx_data = {rx, rx_data[7:1]};
rx_countdown = 16;
rx_bits_remaining = rx_bits_remaining - 1;
recv_state = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP;
end
end
RX_CHECK_STOP: begin
if (!rx_countdown) begin
// Should resume half-way through the stop bit
// This should be high - if not, reject the
// transmission and signal an error.
recv_state = rx ? RX_RECEIVED : RX_ERROR;
end
end
RX_DELAY_RESTART: begin
// Waits a set number of cycles before accepting
// another transmission.
recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE;
end
RX_ERROR: begin
// There was an error receiving.
// Raises the recv_error flag for one clock
// cycle while in this state and then waits
// 2 bit periods before accepting another
// transmission.
rx_countdown = 32;
recv_state = RX_DELAY_RESTART;
end
RX_RECEIVED: begin
// Successfully received a byte.
// Raises the received flag for one clock
// cycle while in this state and then waits
// 1/4 bit period before starting back in the
// idle state. This only actually waits for
// 3/4 of the stop bit before resuming, but
// this should not do any harm as the stop bit
// is received the same as the line idle state.
rx_countdown = 4;
recv_state = RX_DELAY_RESTART;
end
endcase
// Transmit state machine
case (tx_state)
TX_IDLE: begin
if (transmit) begin
// If the transmit flag is raised in the idle
// state, start transmitting the current content
// of the tx_byte input.
tx_data = tx_byte;
// Send the initial, low pulse of 1 bit period
// to signal the start, followed by the data
tx_countdown = 16;
tx_out = 0;
tx_bits_remaining = 8;
tx_state = TX_SENDING;
end
end
TX_SENDING: begin
if (!tx_countdown) begin
if (tx_bits_remaining) begin
tx_bits_remaining = tx_bits_remaining - 1;
tx_out = tx_data[0];
tx_data = {1'b0, tx_data[7:1]};
tx_countdown = 16;
tx_state = TX_SENDING;
end else begin
// Set delay to send out 2 stop bits.
tx_out = 1;
tx_countdown = 32;
tx_state = TX_DELAY_RESTART;
end
end
end
TX_DELAY_RESTART: begin
// Wait until tx_countdown reaches the end before
// we send another transmission. This covers the
// "stop bit" delay.
tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE;
end
endcase
end
 
endmodule
/LICENCE
0,0 → 1,21
The MIT License
 
Copyright (c) 2010 Timothy Goddard
 
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
 
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
/README
0,0 → 1,78
Open Source Documented Verilog UART
Published under the terms of the MIT licence. See LICENCE for licensing information.
 
== Purpose ==
 
This module was created as a result of my own need for a UART (serial line I/O) component and frustration at the difficulty of integrating the existing available components in to my own project. All the open source UART modules I found were either difficult to interface with, usually due to being more clever than I wanted them to be and had poor documentation for their interfaces. They were also generally written in VHDL, which since I've never written VHDL made it a little difficult to read to work out the interfacing issues for myself. The frustration of finding such a simple component so hard to use prompted the decision to create my own, and document it for beginners like myself.
 
I hope that this module will be documented to a better standard than most I've come across. Please send me email at tim@goddard.net.nz if you have trouble understanding it. Improvements are also welcome.
 
== What would I use this for? ==
 
A UART is a useful component for controlling asynchronous (without a separate clock line) serial buses. It can be used via a level converter to talk to the RS232 serial port of a computer. This is not, however, the only application. It could also be used as a local chip bus, or with differential signalling to connect to peripherals over quite long distances.
 
== I/O Standards, Compatability ==
 
This follows standard UART signalling methods with the following properties:
 
* Expects to send and receive data as 8 data bits, no parity bits.
* Default baud rate is 9600 with a 50MHz clock. This is configurable.
* Samples values roughly in the middle of each bit (may drift slightly).
* Sends and receives least significant bit first.
* Expects to receive at least 1 stop bit. Will not check for more, but won't fail either.
* Transmits 2 stop bits.
 
== Usage ==
 
The UART component can be included in your application like this:
 
uart MyInstanceName (clk, rst, rx, tx, transmit, tx_byte, received, rx_byte, is_receiving, is_transmitting, recv_error);
 
These are the lines and what they each need to be connected to:
 
* "clk" is the master clock for this component.
By default this will run at 9600 baud with a clock of 50MHz, but this can be altered as described in the "Adjusting Clock Rate / Baud Rate" section below.
 
* "rst" is a synchronous reset line (resets if high when the rising edge of clk arrives).
Raising this high for one cycle of clk will interrupt any transmissions in progress and set it back to an idle state. Doing this unneccessarily is not recommended - the receive component could become confused if reset halfway through a transmission. This can be unconnected if you don't need to reset the component.
 
* "rx" is the serial line which the component will receive data on.
This would usually be connected to an outside pin.
 
* "tx" is the serial line which the component will transmit data on.
This would usually be connected to an outside pin.
 
* The input flag "transmit" is a signal you use to indicate that the UART should start a transmission.
If the transmit line is idle and this is raised for one clock cycle, the component will copy the content of the tx_byte input and start transmitting it. If raised while the line is busy, this signal will be ignored. The is_transmitting output mentioned later can be used to test this and avoid missing a byte.
 
* The input "tx_byte" is an 8-bit bus containing the byte to be transmitted when "transmit" is raised high.
When "transmit" is low, this may change without interrupting the transfer.
 
* "received" is an output flag which is raised high for one cycle of clk when a byte is received.
 
* The output "rx_data" is set to the value of the byte which has just been received when "received" is raised.
It is recommended that this be used immediately in the cycle when "raised" is high or saved in to a register for future use. While this is likely to remain accurate until the start of the next incoming byte arrives, this should not be relied on.
 
* The output "is_receiving" indicates that we are currently receiving data on the rx line.
This could be used for example to provide an early warning that a byte may be about to be received. When this signal is true, it will not become false again until either "received" or "recv_error" has been asserted. If you don't need early warning, this can safely be left disconnected.
 
* The output "is_transmitting" indicates that we are currently sending data on the tx line.
This is often important to track, because we can only send one byte at once. If we need to send another byte and this is high, the code outside will have to wait until this goes low before it can begin. This can be ignored if you know that you will never try to transmit while another transmission is in progress, for example when transmissions happen at fixed intervals longer than the time it takes to transmit a packet (11 bit periods - just under 1.2ms at 9600 baud) .
 
* recv_error is an output indicating that a malformed or incomplete byte was received.
If you simply wish to ignore bad incoming bytes, you can safely leave this signal disconnected.
 
With "rst", "is_receiving" and "recv_error" disconnected, the invocation would look like:
 
uart MyInstanceName (clk, , rx, tx, transmit, tx_byte, received, rx_byte, , is_transmitting, );
 
== Adjusting Clock Rate / Baud Rate ==
 
The clock rate and baud rate can be altered by changing the CLOCK_DIVIDE parameter passed in to the uart module. This value is calculated by taking the clock frequency in Hz (for example, 50MHz is 50,000,000 Hz), dividing it by the baud rate times 16 (for example 9600)
 
CLOCK_DIVIDE = Frequency(clk) / (16 * Baud)
 
In the example given, the resulting constant is 50000000 / (16 * 9600) = 325 . This is the value that the module has by default. To create a UART running at a different rate, insert the CLOCK_DIVIDE value in to the initialisation like:
 
uart #(.CLOCK_DIVIDE( 325 )) MyInstanceName (clk, ...);
 

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