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URL https://opencores.org/ocsvn/parallel_search_for_maximum_weight/parallel_search_for_maximum_weight/trunk

Subversion Repositories parallel_search_for_maximum_weight

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    /parallel_search_for_maximum_weight
    from Rev 7 to Rev 8
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Rev 7 → Rev 8

/trunk/src/carry_cell_NAND.vhd
0,0 → 1,25
library ieee;
use ieee.std_logic_1164.all;
use work.basic_size.all;
entity carry_cell_NAND is
port(
a: IN std_logic;
b: IN std_logic;
choose_prev_bar : in std_logic;
found_prev_bar : in std_logic;
choose_cur : out std_logic;
found_cur : out std_logic
);
end carry_cell_NAND;
architecture behav of carry_cell_NAND is
 
SIGNAL found: std_logic;
SIGNAL choose: std_logic;
SIGNAL gci: std_logic;
SIGNAL gfi: std_logic;
begin
gci <= (NOT a) NOR b;
gfi <= ( a XNOR b);
choose_cur <= choose_prev_bar NAND (found_prev_bar NAND gci);
found_cur <= found_prev_bar NAND gfi;
end behav;
/trunk/src/basic_component.vhd
0,0 → 1,63
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.basic_size.all;
package basic_component is
component parallel_find_top is
GENERIC (N: NATURAL := N ; WIDTH :NATURAL := WIDTH);
port ( a : in WORD_ARRAY;
y : out STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0)
);
end component parallel_find_top;
 
component mux_sel is
GENERIC (level:INTEGER:=0; Cell_count:INTEGER:=8);
port(
left_op: in std_logic_vector(Cell_count-1 downto 0 );
right_op: in std_logic_vector(Cell_count-1 downto 0 );
o: out std_logic_vector(Cell_count-1 downto 0 )
);
end component mux_sel;
 
component Ripple is
GENERIC (cells : Natural:=6);
port(
left_op : IN std_logic_vector (cells -1 DOWNTO 0);
right_op : IN std_logic_vector (cells -1 DOWNTO 0);
choose_cur : out std_logic;
found_cur : out std_logic;
choose_sel : OUT std_logic_vector (cells -1 DOWNTO 0));
end component Ripple;
component Result is
GENERIC (Cell_count : Natural:=6);
port(
i1: in std_logic_vector(Cell_count-1 downto 0);
i2: in std_logic_vector(Cell_count-1 downto 0);
choose_sel : In std_logic_vector(Cell_count-1 downto 0);
o: out std_logic_vector(Cell_count-1 downto 0 ));
end component Result;
COMPONENT carry_cell_NOR is
port(
a: IN std_logic;
b: IN std_logic;
choose_prev : in std_logic;
found_prev : in std_logic;
choose_cur_bar : out std_logic;
found_cur_bar : out std_logic);
end COMPONENT carry_cell_NOR;
COMPONENT carry_cell_NAND is
port(
a: IN std_logic;
b: IN std_logic;
choose_prev_bar : in std_logic;
found_prev_bar : in std_logic;
choose_cur : out std_logic;
found_cur : out std_logic);
end COMPONENT carry_cell_NAND;
 
 
end package basic_component;
 
package body basic_component is
end package body;
/trunk/src/tb.vhd
0,0 → 1,46
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.basic_size.all;
use work.basic_component.all;
entity tb is
port( clk,reset: in std_logic;
in_data : in STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
enable : in STD_LOGIC_VECTOR(N-1 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0)
);
end tb;
architecture behav of tb is
signal inputs_reg0 : WORD_ARRAY;
signal inputs_reg1 : WORD_ARRAY;
signal outputs_reg0 : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
signal outputs_reg1 : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
begin
-- Serial send the data
process(clk)
begin
if clk='1' and clk'event then
for i in 0 to (N-2) loop
inputs_reg0(i+1) <= inputs_reg0(i) ;
end loop ;
inputs_reg0(0) <= in_data ;
end if;
end process;
 
FIND_MAX : parallel_find_top PORT MAP
( a => inputs_reg0,
y => outputs_reg0
);
process(clk,reset)
begin
if reset = '1' then
elsif clk='1' and clk'event then
outputs_reg1 <= outputs_reg0 ;
output <= outputs_reg1 ;
end if;
end process;
end behav;
/trunk/src/Ripple.vhd
0,0 → 1,61
library ieee;
use ieee.std_logic_1164.all;
use work.basic_size.all;
use work.basic_component.all;
entity Ripple is
GENERIC (cells : Natural:=8);
port(
left_op : IN std_logic_vector (cells -1 DOWNTO 0);
right_op : IN std_logic_vector (cells -1 DOWNTO 0);
choose_cur : out std_logic;
found_cur : out std_logic;
choose_sel : OUT std_logic_vector (cells -1 DOWNTO 0));
end entity Ripple;
architecture behav of Ripple is
SIGNAL found_i: std_logic_vector (cells+1 DOWNTO 0);
SIGNAL choose_i: std_logic_vector (cells+1 DOWNTO 0);
SIGNAL a: std_logic_vector (cells DOWNTO 0);
SIGNAL b: std_logic_vector (cells DOWNTO 0);
SIGNAL sel_out: std_logic_vector (cells DOWNTO 0);
begin
 
choose_i(2*((cells+1 )/ 2)) <= '0';
found_i (2*((cells+1 )/ 2)) <= '0';
--rename inputs
re_g:IF (cells mod 2) =0 GENERATE
a(cells-1 DOWNTO 0) <= left_op;
b(cells-1 DOWNTO 0) <= right_op;
END GENERATE re_g;
--PADDING with zero's
--- PADDING ODD to EVEN
pad_gen : IF (cells mod 2) /=0 GENERATE
a <= left_op & '0';
b <= right_op & '0';
END GENERATE pad_gen;
 
-- Start based on the number of Bits if Even or Odd
-- Sure not equal zero
--even_cell :
g_ripple : FOR i In ((cells+1)/2 ) downto 1 generate
BEGIN
carry_cell_NOR_Inst : carry_cell_NOR PORT MAP (
a =>a(2*i-1), b=>b(2*i-1),
choose_prev =>choose_i(2*i ),
found_prev =>found_i(2*i ),
choose_cur_bar =>choose_i(2*i-1 ),
found_cur_bar =>found_i(2*i -1 ));
--Result Muxing
sel_out(2*i-1) <= NOT choose_i(2*i-1);
carry_cell_NAND_Inst : carry_cell_NAND PORT MAP(
a =>a(2*i -2), b=>b(2*i -2),
choose_prev_bar =>choose_i(2*i-1),
found_prev_bar =>found_i(2*i -1 ),
choose_cur =>choose_i(2*i - 2),
found_cur =>found_i(2*i - 2));
sel_out (2*i - 2) <= choose_i(2*i - 2);
end generate g_ripple;
choose_sel <= sel_out(2*((cells+1)/2)-1 DOWNTO (cells mod 2));
choose_cur <=choose_i(cells mod 2) ;
found_cur <= found_i(cells mod 2);
end behav;
/trunk/src/basic_size.vhd
0,0 → 1,64
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package basic_size is
function log2_ceil(N : integer) return integer;
function count_satges(cells : integer) return integer;
function odd_even_stage(i : integer; ripple_width : integer; cs_w : integer) return integer ;
constant width : integer :=8;
constant N : integer := 64;
constant logN : integer := log2_ceil(N);
 
 
--constant P_stages : integer := count_satges(N);
constant K : integer := 2;
 
type n_ports_array is array (0 to N-1) of std_logic_vector(width-1 downto 0);
type max_tornment_array is array (0 to N-2) of std_logic_vector(width-1 downto 0);
 
TYPE WORD IS array (WIDTH-1 DOWNTO 0) of STD_LOGIC;
type WORD_ARRAY is array (0 TO N-1 ) of std_logic_vector(width-1 downto 0);
 
end package basic_size;
 
package body basic_size is
function log2_ceil(N : integer) return integer is
begin
 
if (N <= 2) then
return 1;
else
if (N mod 2 = 0) then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end if;
end function log2_ceil;
 
function count_satges(cells : integer) return integer is
variable K : integer := 2; --original input.
variable P : integer := 0; --original input.
variable a : integer := 1; --original input.
variable series : integer := 0; --original input.
begin
counter : while a**2 +(a*(2*K -1))+2*(K - cells ) - K < 0 loop
a := a + 1;
end loop counter;
return a;
end function count_satges;
 
 
 
function odd_even_stage(i : integer; ripple_width : integer; cs_w : integer) return integer is
variable rp_width : integer := 2 ; --original input.
begin
if i = 0 then
return (ripple_width mod 2);
elsif cs_w mod 2 = 0 then
return i mod 2;
else return 1;
end if;
end function odd_even_stage;
 
end package body;
/trunk/src/mux_sel.vhd
0,0 → 1,40
library ieee;
use ieee.std_logic_1164.all;
use work.basic_size.all;
use work.basic_component.all;
entity mux_sel is
GENERIC (level:INTEGER:=1; Cell_count:INTEGER:=width);
port(
left_op: in std_logic_vector(Cell_count-1 downto 0 );
right_op: in std_logic_vector(Cell_count-1 downto 0 );
o: out std_logic_vector(Cell_count-1 downto 0 )
);
end mux_sel;
architecture behav of mux_sel is
 
 
SIGNAL choose_res : STD_LOGIC_VECTOR(Cell_count-1 downto 0);
SIGNAL choose_cur : STD_LOGIC_VECTOR(Cell_count-1 downto 0);
SIGNAL found_cur : STD_LOGIC_VECTOR(Cell_count-1 downto 0);
SIGNAL choose_prev : STD_LOGIC_VECTOR(Cell_count-1 downto 0);
SIGNAL found_prev : STD_LOGIC_VECTOR(Cell_count-1 downto 0);
begin
 
----------------------------------
ripple_part_inst: Ripple
GENERIC MAP(cells => Cell_count)
PORT MAP(left_op =>left_op (Cell_count-1 downto 0 ),
right_op =>right_op(Cell_count-1 downto 0 ),
choose_cur=>choose_prev(Cell_count-1),
found_cur=>found_prev(Cell_count-1),
choose_sel=>choose_res(Cell_count-1 downto 0 )
);
ripple_part_Res_inst : Result
GENERIC MAP(Cell_count => Cell_count)
PORT MAP(i1 => left_op (Cell_count-1 downto 0 ),
i2 => right_op (Cell_count-1 downto 0 ),
choose_sel => choose_res(Cell_count-1 downto 0 ),
o=>o(Cell_count-1 downto 0)
);
----------------------------------
end behav;
/trunk/src/carry_cell_NOR.vhd
0,0 → 1,25
library ieee;
use ieee.std_logic_1164.all;
use work.basic_size.all;
entity carry_cell_NOR is
port(
a: IN std_logic;
b: IN std_logic;
choose_prev : in std_logic;
found_prev : in std_logic;
choose_cur_bar : out std_logic;
found_cur_bar : out std_logic
);
end carry_cell_NOR;
architecture behav of carry_cell_NOR is
 
SIGNAL found: std_logic;
SIGNAL choose: std_logic;
SIGNAL gci: std_logic;
SIGNAL gfi: std_logic;
begin
gci <= (NOT b) NAND a;
gfi <= ( a XOR b);
choose_cur_bar<= choose_prev NOR (found_prev NOR gci);
found_cur_bar <= ( (found_prev) NOR gfi);
end behav;
/trunk/src/Result.vhd
0,0 → 1,25
library ieee;
use ieee.std_logic_1164.all;
use work.basic_size.all;
entity Result is
GENERIC (Cell_count : Natural:=5);
port(
i1: in std_logic_vector(Cell_count-1 downto 0);
i2: in std_logic_vector(Cell_count-1 downto 0);
choose_sel : In std_logic_vector(Cell_count-1 downto 0);
o: out std_logic_vector(Cell_count-1 downto 0 )
);
end Result;
architecture behav of Result is
 
 
begin
 
--Result
out_g : for i in 0 to Cell_count-1 generate
with choose_sel(i) select
o(i) <= i1(i) when '1' , i2(i) when '0';
end generate out_g;
end behav;
/trunk/src/parallel_find_top.vhd
0,0 → 1,42
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.basic_size.all;
use work.basic_component.all;
entity parallel_find_top is
GENERIC (N: NATURAL := N ; WIDTH :NATURAL := WIDTH);
port ( a : in WORD_ARRAY;
y : out STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0)
);
end parallel_find_top;
 
architecture gen_tree_arch of parallel_find_top is
CONSTANT STAGE : NATURAL :=log2_ceil(N);
type STD_LOGIC_2D is array (STAGE DOWNTO 0, 2**STAGE-1 DOWNTO 0) of STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
SIGNAL p : STD_LOGIC_2D;
BEGIN
--rename inputs
in_gen : FOR i IN 0 TO (N-1) GENERATE
p(STAGE , i) <= a(i);
END GENERATE in_gen;
--PADDING with zero's
pad0_gen : IF (N < 2**STAGE ) GENERATE
zero_gen : FOR i IN N TO 2**STAGE -1 GENERATE
p(STAGE , i) <= (OTHERS=>'0');
END GENERATE zero_gen;
END GENERATE pad0_gen;
 
-- replicate structure
--STAGE_GEN
g : FOR s IN (STAGE-1)DOWNTO 0 GENERATE
--ROW_GEN
q : FOR r IN 0 TO (2**s)-1 GENERATE
BT : mux_sel GENERIC MAP(level=> STAGE-s-1, Cell_count=>WIDTH)
port map(left_op=>p(s+1,2 * r),right_op=>p(s+1, 2*r +1),o=>p(s,r));
END GENERATE q;
END GENERATE g;
--rename output
y <= p(0,0);
end gen_tree_arch;
 
 

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