OpenCores
URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /pcie_ds_dma/trunk
    from Rev 48 to Rev 49
    ↔ Reverse comparison
  •

Rev 48 → Rev 49

/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_user.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_pipe_user.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_user.v
// Description : PIPE User Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4.vhd
-- Version : 1.10
-- Version : 1.11
--
-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express
--
98,7 → 98,7
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0;
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7;
DEV_CAP_EXT_TAG_SUPPORTED : string := "FALSE";
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 1;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
 
DEV_CAP2_ARI_FORWARDING_SUPPORTED : string := "FALSE";
109,7 → 109,7
DEV_CAP2_TPH_COMPLETER_SUPPORTED : bit_vector := X"00";
DEV_CONTROL_EXT_TAG_DEFAULT : string := "FALSE";
 
DISABLE_LANE_REVERSAL : string := "TRUE";
DISABLE_LANE_REVERSAL : string := "FALSE";
DISABLE_RX_POISONED_RESP : string := "FALSE";
DISABLE_SCRAMBLING : string := "FALSE";
DSN_BASE_PTR : bit_vector := X"100";
117,7 → 117,7
DSN_CAP_ON : string := "TRUE";
 
ENABLE_MSG_ROUTE : bit_vector := "00000000000";
ENABLE_RX_TD_ECRC_TRIM : string := "TRUE";
ENABLE_RX_TD_ECRC_TRIM : string := "FALSE";
EXPANSION_ROM : bit_vector := X"00000000";
EXT_CFG_CAP_PTR : bit_vector := X"3F";
EXT_CFG_XP_CAP_PTR : bit_vector := X"3FF";
148,7 → 148,7
LTSSM_MAX_LINK_WIDTH : bit_vector := X"04";
MSI_CAP_MULTIMSGCAP : integer := 0;
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
MSI_CAP_ON : string := "FALSE";
MSI_CAP_ON : string := "TRUE";
MSI_CAP_PER_VECTOR_MASKING_CAPABLE : string := "FALSE";
MSI_CAP_64_BIT_ADDR_CAPABLE : string := "TRUE";
 
165,7 → 165,7
PM_CAP_DSI : string := "FALSE";
PM_CAP_D1SUPPORT : string := "FALSE";
PM_CAP_D2SUPPORT : string := "FALSE";
PM_CAP_NEXTPTR : bit_vector := X"60";
PM_CAP_NEXTPTR : bit_vector := X"48";
PM_CAP_PMESUPPORT : bit_vector := X"0F";
PM_CSR_NOSOFTRST : string := "TRUE";
 
238,14 → 238,14
VC_CAP_REJECT_SNOOP_TRANSACTIONS : string := "FALSE";
 
VC0_CPL_INFINITE : string := "TRUE";
VC0_RX_RAM_LIMIT : bit_vector := X"3FF";
VC0_TOTAL_CREDITS_CD : integer := 370;
VC0_TOTAL_CREDITS_CH : integer := 72;
VC0_TOTAL_CREDITS_NPH : integer := 4;
VC0_TOTAL_CREDITS_NPD : integer := 8;
VC0_TOTAL_CREDITS_PD : integer := 32;
VC0_TOTAL_CREDITS_PH : integer := 4;
VC0_TX_LASTPACKET : integer := 28;
VC0_RX_RAM_LIMIT : bit_vector := X"7FF";
VC0_TOTAL_CREDITS_CD : integer := 461;
VC0_TOTAL_CREDITS_CH : integer := 36;
VC0_TOTAL_CREDITS_NPH : integer := 12;
VC0_TOTAL_CREDITS_NPD : integer := 24;
VC0_TOTAL_CREDITS_PD : integer := 437;
VC0_TOTAL_CREDITS_PH : integer := 32;
VC0_TX_LASTPACKET : integer := 29;
 
VSEC_BASE_PTR : bit_vector := X"000";
VSEC_CAP_NEXTPTR : bit_vector := X"000";
658,7 → 658,7
 
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of pcie_7x : ARCHITECTURE is
"cl_a7pcie_x4,pcie_7x_v1_10,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=FALSE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=4,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=4,VC0_TOTAL_CREDITS_NPD=8,VC0_TOTAL_CREDITS_CH=72,VC0_TOTAL_CREDITS_CD=370,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,REVISION_ID=00,VC_CAP_ON=FALSE}";
"cl_a7pcie_x4,pcie_7x_v1_11,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=2,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=TRUE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=29,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=437,VC0_TOTAL_CREDITS_NPH=12,VC0_TOTAL_CREDITS_NPD=24,VC0_TOTAL_CREDITS_CH=36,VC0_TOTAL_CREDITS_CD=461,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=DISABLE_LANE_REVERSAL=FALSE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,REVISION_ID=00,VC_CAP_ON=FALSE}";
component cl_a7pcie_x4_pcie_top is
generic (
C_DATA_WIDTH : INTEGER range 32 to 128 := 64;
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_bram_top_7x.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_pcie_bram_top_7x.vhd
-- Version : 1.10
-- Version : 1.11
-- Description : bram wrapper for Tx and Rx
-- given the pcie block attributes calculate the number of brams
-- and pipeline stages and instantiate the brams
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_pipe_pipeline.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_pcie_pipe_pipeline.vhd
-- Version : 1.10
-- Version : 1.11
-- Description: PIPE module for 7-Series PCIe Block
--
--
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_brams_7x.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_pcie_brams_7x.vhd
-- Version : 1.10
-- Version : 1.11
-- Description : pcie bram wrapper
-- arrange and connect brams
-- implement address decoding, datapath muxing and pipeline stages
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_gt_rx_valid_filter_7x.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_gt_rx_valid_filter_7x.vhd
-- Version : 1.10
-- Version : 1.11
---- Description: GTX module for 7-series Integrated PCIe Block
----
----
103,14 → 103,14
constant FTSOS_COM : std_logic_vector(7 downto 0) := X"BC";
constant FTSOS_FTS : std_logic_vector(7 downto 0) := X"3C";
 
signal reg_state_eios_det : std_logic_vector(4 downto 0);
signal state_eios_det : std_logic_vector(4 downto 0);
signal reg_state_eios_det : std_logic_vector(4 downto 0):= (others => '0');
signal state_eios_det : std_logic_vector(4 downto 0):= (others => '0');
 
signal reg_eios_detected : std_logic;
signal eios_detected : std_logic;
signal reg_eios_detected : std_logic:= '0';
signal eios_detected : std_logic:= '0';
 
signal reg_symbol_after_eios : std_logic;
signal symbol_after_eios : std_logic;
signal reg_symbol_after_eios : std_logic:= '0';
signal symbol_after_eios : std_logic:= '0';
 
constant USER_RXVLD_IDL : std_logic_vector(3 downto 0) := "0001";
constant USER_RXVLD_EI : std_logic_vector(3 downto 0) := "0010";
118,15 → 118,15
constant USER_RXVLD_EI_DB1 : std_logic_vector(3 downto 0) := "1000";
 
 
signal gt_rxcharisk_q : std_logic_vector( 1 downto 0);
signal gt_rxdata_q : std_logic_vector(15 downto 0);
signal gt_rxvalid_q : std_logic;
signal gt_rxelecidle_q : std_logic;
signal gt_rxcharisk_q : std_logic_vector( 1 downto 0):= (others => '0');
signal gt_rxdata_q : std_logic_vector(15 downto 0):= (others => '0');
signal gt_rxvalid_q : std_logic:= '0';
signal gt_rxelecidle_q : std_logic:= '0';
 
signal gt_rx_status_q : std_logic_vector( 2 downto 0);
signal gt_rx_phy_status_q : std_logic;
signal gt_rx_is_skp0_q : std_logic;
signal gt_rx_is_skp1_q : std_logic;
signal gt_rx_status_q : std_logic_vector( 2 downto 0):= (others => '0');
signal gt_rx_phy_status_q : std_logic:= '0';
signal gt_rx_is_skp0_q : std_logic:= '0';
signal gt_rx_is_skp1_q : std_logic:= '0';
 
begin
 
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_drp.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_pipe_drp.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_drp.v
// Description : PIPE DRP Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_rx.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_axi_basic_rx.vhd
-- Version : 1.10
-- Version : 1.11
-- Description:
-- TRN to AXI RX module. Instantiates pipeline and null generator RX
-- submodules.
124,20 → 124,20
 
ARCHITECTURE TRANS OF cl_a7pcie_x4_axi_basic_rx IS
 
SIGNAL null_rx_tvalid : STD_LOGIC;
SIGNAL null_rx_tlast : STD_LOGIC;
SIGNAL null_rx_tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0);
SIGNAL null_rdst_rdy : STD_LOGIC;
SIGNAL null_is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL null_rx_tvalid : STD_LOGIC:= '0';
SIGNAL null_rx_tlast : STD_LOGIC:= '0';
SIGNAL null_rx_tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):= (others => '0');
SIGNAL null_rdst_rdy : STD_LOGIC:= '0';
SIGNAL null_is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0):= (others => '0');
 
-- Declare intermediate signals for referenced outputs
SIGNAL m_axis_rx_tdata_xhdl0 : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
SIGNAL m_axis_rx_tvalid_xhdl4 : STD_LOGIC;
SIGNAL m_axis_rx_tkeep_xhdl2 : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0);
SIGNAL m_axis_rx_tlast_xhdl1 : STD_LOGIC;
SIGNAL m_axis_rx_tuser_xhdl3 : STD_LOGIC_VECTOR(21 DOWNTO 0);
SIGNAL trn_rdst_rdy_xhdl6 : STD_LOGIC;
SIGNAL np_counter_xhdl5 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL m_axis_rx_tdata_xhdl0 : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0):= (others => '0');
SIGNAL m_axis_rx_tvalid_xhdl4 : STD_LOGIC:= '0';
SIGNAL m_axis_rx_tkeep_xhdl2 : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):= (others => '0');
SIGNAL m_axis_rx_tlast_xhdl1 : STD_LOGIC:= '0';
SIGNAL m_axis_rx_tuser_xhdl3 : STD_LOGIC_VECTOR(21 DOWNTO 0):= (others => '0');
SIGNAL trn_rdst_rdy_xhdl6 : STD_LOGIC:= '0';
SIGNAL np_counter_xhdl5 : STD_LOGIC_VECTOR(2 DOWNTO 0):= (others => '0');
 
COMPONENT cl_a7pcie_x4_axi_basic_rx_null_gen IS
GENERIC (
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_pipe_lane.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_pcie_pipe_lane.vhd
-- Version : 1.10
-- Version : 1.11
--
-- Description: PIPE per lane module for 7-Series PCIe Block
--
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_gt_top.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_gt_top.vhd
-- Version : 1.10
-- Version : 1.11
---- Description: GTX module for 7-series Integrated PCIe Block
----
----
505,45 → 505,45
constant signal_z : std_logic_vector((18*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0) := (others => '0');
 
signal gt_rx_phy_status_wire : std_logic_vector(7 downto 0);
signal gt_rxchanisaligned_wire : std_logic_vector(7 downto 0);
signal gt_rx_data_k_wire : std_logic_vector(31 downto 0);
signal gt_rx_data_wire : std_logic_vector(255 downto 0);
signal gt_rx_elec_idle_wire : std_logic_vector(7 downto 0);
signal gt_rx_status_wire : std_logic_vector(23 downto 0);
signal gt_rx_valid_wire : std_logic_vector(7 downto 0);
signal gt_rx_polarity : std_logic_vector(7 downto 0);
signal gt_power_down : std_logic_vector(15 downto 0);
signal gt_tx_char_disp_mode : std_logic_vector(7 downto 0);
signal gt_tx_data_k : std_logic_vector(31 downto 0);
signal gt_tx_data : std_logic_vector(255 downto 0);
signal gt_tx_detect_rx_loopback : std_logic;
signal gt_tx_elec_idle : std_logic_vector(7 downto 0);
signal gt_rx_elec_idle_reset : std_logic_vector(7 downto 0);
signal plllkdet : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
signal phystatus_rst : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
signal clock_locked : std_logic;
signal pipe_rate_concat : std_logic_vector(1 downto 0);
signal gt_rx_phy_status_wire : std_logic_vector(7 downto 0):= (others => '0');
signal gt_rxchanisaligned_wire : std_logic_vector(7 downto 0):= (others => '0');
signal gt_rx_data_k_wire : std_logic_vector(31 downto 0):= (others => '0');
signal gt_rx_data_wire : std_logic_vector(255 downto 0):= (others => '0');
signal gt_rx_elec_idle_wire : std_logic_vector(7 downto 0):= (others => '0');
signal gt_rx_status_wire : std_logic_vector(23 downto 0):= (others => '0');
signal gt_rx_valid_wire : std_logic_vector(7 downto 0):= (others => '0');
signal gt_rx_polarity : std_logic_vector(7 downto 0):= (others => '0');
signal gt_power_down : std_logic_vector(15 downto 0):= (others => '0');
signal gt_tx_char_disp_mode : std_logic_vector(7 downto 0):= (others => '0');
signal gt_tx_data_k : std_logic_vector(31 downto 0):= (others => '0');
signal gt_tx_data : std_logic_vector(255 downto 0):= (others => '0');
signal gt_tx_detect_rx_loopback : std_logic:= '0';
signal gt_tx_elec_idle : std_logic_vector(7 downto 0):= (others => '0');
signal gt_rx_elec_idle_reset : std_logic_vector(7 downto 0):= (others => '0');
signal plllkdet : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0):= (others => '0');
signal phystatus_rst : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0):= (others => '0');
signal clock_locked : std_logic:= '0';
signal pipe_rate_concat : std_logic_vector(1 downto 0):= (others => '0');
signal pipe_tx_deemph_concat : std_logic_vector((1*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
signal all_phystatus_rst : std_logic;
signal gt_rx_phy_status_wire_filter : std_logic_vector( 7 downto 0);
signal gt_rx_data_k_wire_filter : std_logic_vector( 31 downto 0);
signal gt_rx_data_wire_filter : std_logic_vector(255 downto 0);
signal gt_rx_elec_idle_wire_filter : std_logic_vector( 7 downto 0);
signal gt_rx_status_wire_filter : std_logic_vector( 23 downto 0);
signal gt_rx_valid_wire_filter : std_logic_vector( 7 downto 0);
signal pipe_tx_deemph_concat : std_logic_vector((1*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0):= (others => '0');
signal all_phystatus_rst : std_logic:= '0';
signal gt_rx_phy_status_wire_filter : std_logic_vector( 7 downto 0):= (others => '0');
signal gt_rx_data_k_wire_filter : std_logic_vector( 31 downto 0):= (others => '0');
signal gt_rx_data_wire_filter : std_logic_vector(255 downto 0):= (others => '0');
signal gt_rx_elec_idle_wire_filter : std_logic_vector( 7 downto 0):= (others => '0');
signal gt_rx_status_wire_filter : std_logic_vector( 23 downto 0):= (others => '0');
signal gt_rx_valid_wire_filter : std_logic_vector( 7 downto 0):= (others => '0');
 
signal pl_ltssm_state_q : std_logic_vector( 5 downto 0);
signal pl_ltssm_state_q : std_logic_vector( 5 downto 0):= (others => '0');
 
signal plm_in_l0 : std_logic;
signal plm_in_rl : std_logic;
signal plm_in_dt : std_logic;
signal plm_in_rs : std_logic;
signal plm_in_l0 : std_logic:= '0';
signal plm_in_rl : std_logic:= '0';
signal plm_in_dt : std_logic:= '0';
signal plm_in_rs : std_logic:= '0';
 
signal pipe_clk_int : std_logic;
signal phy_rdy_n_int : std_logic;
signal reg_clock_locked : std_logic;
signal pipe_clk_int : std_logic:= '0';
signal phy_rdy_n_int : std_logic:= '0';
signal reg_clock_locked : std_logic:= '0';
 
 
begin
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_qpll_wrapper.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_qpll_wrapper.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : qpll_wrapper.v
// Description : QPLL Wrapper Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_tx.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_axi_basic_tx.vhd
-- Version : 1.10
-- Version : 1.11
--
-- Description:
-- AXI to TRN TX module. Instantiates pipeline and throttle control TX
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_qpll_reset.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_qpll_reset.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : qpll_reset.v
// Description : QPLL Reset Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_7x.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_pcie_7x.vhd
-- Version : 1.10
-- Version : 1.11
--
-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express
--
540,8 → 540,8
drp_we : in std_logic;
drp_addr : in std_logic_vector(8 downto 0);
drp_di : in std_logic_vector(15 downto 0);
drp_rdy : out std_logic;
drp_do : out std_logic_vector(15 downto 0);
drp_rdy : out std_logic := '0' ;
drp_do : out std_logic_vector(15 downto 0):= (others => '0');
dbg_mode : in std_logic_vector(1 downto 0);
dbg_sub_mode : in std_logic;
pl_dbg_mode : in std_logic_vector( 2 downto 0);
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_bram_7x.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_pcie_bram_7x.vhd
-- Version : 1.10
-- Version : 1.11
-- Description : single bram wrapper for the mb pcie block
-- The bram A port is the write port
-- the B port is the read port
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_gtp_pipe_drp.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_gtp_pipe_drp.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : gtp_pipe_drp.v
// Description : GTP PIPE DRP Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_top.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_pcie_top.vhd
-- Version : 1.10
-- Version : 1.11
-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express
--
--
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_rxeq_scan.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_rxeq_scan.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : rxeq_scan.v
// Description : PIPE RX Equalization Eye Scan Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_pipe_misc.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_pcie_pipe_misc.vhd
-- Version : 1.10
-- Version : 1.11
-- Description: Misc PIPE module for 7-SeriesPCIe Block
--
--
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_sync.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_pipe_sync.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_sync.v
// Description : PIPE Sync Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_rx_null_gen.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_axi_basic_rx_null_gen.vhd
-- Version : 1.10
-- Version : 1.11
--
-- Description:
-- TRN to AXI RX null generator. Generates null packets for use in discontinue situations.
127,34 → 127,34
constant IN_PACKET : std_logic := '1';
-- Signals for tracking a packet on the AXI interface
SIGNAL reg_pkt_len_counter : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL pkt_len_counter : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL pkt_len_counter_dec : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL pkt_done : STD_LOGIC;
SIGNAL reg_pkt_len_counter : STD_LOGIC_VECTOR(11 DOWNTO 0):= (others => '0');
SIGNAL pkt_len_counter : STD_LOGIC_VECTOR(11 DOWNTO 0):= (others => '0');
SIGNAL pkt_len_counter_dec : STD_LOGIC_VECTOR(11 DOWNTO 0):= (others => '0');
SIGNAL pkt_done : STD_LOGIC:= '0';
 
SIGNAL new_pkt_len : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL payload_len : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL new_pkt_len : STD_LOGIC_VECTOR(11 DOWNTO 0):= (others => '0');
SIGNAL payload_len : STD_LOGIC_VECTOR(9 DOWNTO 0):= (others => '0');
SIGNAL payload_len_tmp : STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
SIGNAL packet_fmt : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL packet_td : STD_LOGIC;
SIGNAL packet_overhead : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL packet_fmt : STD_LOGIC_VECTOR(1 DOWNTO 0):= (others => '0');
SIGNAL packet_td : STD_LOGIC:= '0';
SIGNAL packet_overhead : STD_LOGIC_VECTOR(3 DOWNTO 0):= (others => '0');
-- X-HDL generated signals`
 
SIGNAL xhdl2 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL reg_is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL xhdl5 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl7 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl2 : STD_LOGIC_VECTOR(2 DOWNTO 0):= (others => '0');
SIGNAL reg_is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0):= (others => '0');
SIGNAL xhdl5 : STD_LOGIC_VECTOR(1 DOWNTO 0):= (others => '0');
SIGNAL xhdl7 : STD_LOGIC_VECTOR(1 DOWNTO 0):= (others => '0');
--State machine variables and states
SIGNAL next_state : STD_LOGIC;
SIGNAL cur_state : STD_LOGIC;
SIGNAL next_state : STD_LOGIC:= '0';
SIGNAL cur_state : STD_LOGIC:= '0';
 
-- Declare intermediate signals for referenced outputs
SIGNAL null_rx_tlast_xhdl0 : STD_LOGIC;
SIGNAL null_rx_tlast_xhdl0 : STD_LOGIC:= '0';
 
-- Misc.
SIGNAL eof_tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0);
SIGNAL straddle_sof : STD_LOGIC;
SIGNAL eof : STD_LOGIC;
SIGNAL eof_tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):= (others => '0');
SIGNAL straddle_sof : STD_LOGIC:= '0';
SIGNAL eof : STD_LOGIC:= '0';
 
BEGIN
 
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_rx_pipeline.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_axi_basic_rx_pipeline.vhd
-- Version : 1.10
-- Version : 1.11
--
-- Description:
-- TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI.
121,61 → 121,61
 
ARCHITECTURE trans OF cl_a7pcie_x4_axi_basic_rx_pipeline IS
 
SIGNAL is_sof : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL is_sof_prev : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL is_sof : STD_LOGIC_VECTOR(4 DOWNTO 0):= (others => '0');
SIGNAL is_sof_prev : STD_LOGIC_VECTOR(4 DOWNTO 0):= (others => '0');
 
SIGNAL is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL is_eof_prev : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0):= (others => '0');
SIGNAL is_eof_prev : STD_LOGIC_VECTOR(4 DOWNTO 0):= (others => '0');
 
SIGNAL reg_tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0);
SIGNAL tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0);
SIGNAL tkeep_prev : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0);
SIGNAL reg_tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):= (others => '0');
SIGNAL tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):= (others => '0');
SIGNAL tkeep_prev : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):= (others => '0');
 
SIGNAL reg_tlast : STD_LOGIC;
SIGNAL rsrc_rdy_filtered : STD_LOGIC;
SIGNAL reg_tlast : STD_LOGIC:= '0';
SIGNAL rsrc_rdy_filtered : STD_LOGIC:= '0';
 
SIGNAL trn_rd_DW_swapped : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
SIGNAL trn_rd_prev : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
SIGNAL trn_rd_DW_swapped : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0):= (others => '0');
SIGNAL trn_rd_prev : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0):= (others => '0');
 
SIGNAL data_hold : STD_LOGIC;
SIGNAL data_prev : STD_LOGIC;
SIGNAL data_hold : STD_LOGIC:= '0';
SIGNAL data_prev : STD_LOGIC:= '0';
 
SIGNAL trn_reof_prev : STD_LOGIC;
SIGNAL trn_rrem_prev : STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0);
SIGNAL trn_rsrc_rdy_prev : STD_LOGIC;
SIGNAL trn_rsrc_dsc_prev : STD_LOGIC;
SIGNAL trn_rsof_prev : STD_LOGIC;
SIGNAL trn_rbar_hit_prev : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL trn_rerrfwd_prev : STD_LOGIC;
SIGNAL trn_recrc_err_prev : STD_LOGIC;
SIGNAL trn_reof_prev : STD_LOGIC:= '0';
SIGNAL trn_rrem_prev : STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0):= (others => '0');
SIGNAL trn_rsrc_rdy_prev : STD_LOGIC:= '0';
SIGNAL trn_rsrc_dsc_prev : STD_LOGIC:= '0';
SIGNAL trn_rsof_prev : STD_LOGIC:= '0';
SIGNAL trn_rbar_hit_prev : STD_LOGIC_VECTOR(6 DOWNTO 0):= (others => '0');
SIGNAL trn_rerrfwd_prev : STD_LOGIC:= '0';
SIGNAL trn_recrc_err_prev : STD_LOGIC:= '0';
 
-- Null packet handling signals
SIGNAL null_mux_sel : STD_LOGIC;
SIGNAL trn_in_packet : STD_LOGIC;
SIGNAL dsc_flag : STD_LOGIC;
SIGNAL dsc_detect : STD_LOGIC;
SIGNAL reg_dsc_detect : STD_LOGIC;
SIGNAL trn_rsrc_dsc_d : STD_LOGIC;
SIGNAL null_mux_sel : STD_LOGIC:= '0';
SIGNAL trn_in_packet : STD_LOGIC:= '0';
SIGNAL dsc_flag : STD_LOGIC:= '0';
SIGNAL dsc_detect : STD_LOGIC:= '0';
SIGNAL reg_dsc_detect : STD_LOGIC:= '0';
SIGNAL trn_rsrc_dsc_d : STD_LOGIC:= '0';
 
-- Declare intermediate signals for referenced outputs
SIGNAL m_axis_rx_tdata_xhdl0 : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
SIGNAL m_axis_rx_tvalid_xhdl2 : STD_LOGIC;
SIGNAL m_axis_rx_tuser_xhdl1 : STD_LOGIC_VECTOR(21 DOWNTO 0);
SIGNAL trn_rdst_rdy_xhdl4 : STD_LOGIC;
SIGNAL mrd_lower : STD_LOGIC;
SIGNAL mrd_lk_lower : STD_LOGIC;
SIGNAL io_rdwr_lower : STD_LOGIC;
SIGNAL cfg_rdwr_lower : STD_LOGIC;
SIGNAL atomic_lower : STD_LOGIC;
SIGNAL np_pkt_lower : STD_LOGIC;
SIGNAL mrd_upper : STD_LOGIC;
SIGNAL mrd_lk_upper : STD_LOGIC;
SIGNAL io_rdwr_upper : STD_LOGIC;
SIGNAL cfg_rdwr_upper : STD_LOGIC;
SIGNAL atomic_upper : STD_LOGIC;
SIGNAL np_pkt_upper : STD_LOGIC;
SIGNAL pkt_accepted : STD_LOGIC;
SIGNAL reg_np_counter : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL m_axis_rx_tdata_xhdl0 : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0):= (others => '0');
SIGNAL m_axis_rx_tvalid_xhdl2 : STD_LOGIC:= '0';
SIGNAL m_axis_rx_tuser_xhdl1 : STD_LOGIC_VECTOR(21 DOWNTO 0):= (others => '0');
SIGNAL trn_rdst_rdy_xhdl4 : STD_LOGIC:= '0';
SIGNAL mrd_lower : STD_LOGIC:= '0';
SIGNAL mrd_lk_lower : STD_LOGIC:= '0';
SIGNAL io_rdwr_lower : STD_LOGIC:= '0';
SIGNAL cfg_rdwr_lower : STD_LOGIC:= '0';
SIGNAL atomic_lower : STD_LOGIC:= '0';
SIGNAL np_pkt_lower : STD_LOGIC:= '0';
SIGNAL mrd_upper : STD_LOGIC:= '0';
SIGNAL mrd_lk_upper : STD_LOGIC:= '0';
SIGNAL io_rdwr_upper : STD_LOGIC:= '0';
SIGNAL cfg_rdwr_upper : STD_LOGIC:= '0';
SIGNAL atomic_upper : STD_LOGIC:= '0';
SIGNAL np_pkt_upper : STD_LOGIC:= '0';
SIGNAL pkt_accepted : STD_LOGIC:= '0';
SIGNAL reg_np_counter : STD_LOGIC_VECTOR(2 DOWNTO 0):= (others => '0');
 
BEGIN
-- Drive referenced outputs
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_wrapper.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_pipe_wrapper.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_wrapper.v
// Description : PIPE Wrapper for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_tx_pipeline.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_axi_basic_tx_pipeline.vhd
-- Version : 1.10
-- Version : 1.11
--
-- Description:
--AXI to TRN TX pipeline. Converts transmitted data from AXI protocol to
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_reset.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_pipe_reset.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_reset.v
// Description : PIPE Reset Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_clock.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_pipe_clock.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_clock.v
// Description : PIPE Clock Module for 7 Series Transceiver
266,7 → 266,7
 
//---------- Input ------------------------------------
.CLKIN1 (refclk),
//.CLKIN2 (1'd0), // not used, comment out CLKIN2 if it cause implementation issues
.CLKIN2 (1'd0), // not used, comment out CLKIN2 if it cause implementation issues
//.CLKIN2 (refclk), // not used, comment out CLKIN2 if it cause implementation issues
.CLKINSEL (1'd1),
.CLKFBIN (mmcm_fb),
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_rate.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_pipe_rate.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_rate.v
// Description : PIPE Rate Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_gtp_pipe_reset.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_gtp_pipe_reset.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : gtp_pipe_reset.v
// Description : GTP PIPE Reset Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_gt_wrapper.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_gt_wrapper.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : gt_wrapper.v
// Description : GT Wrapper Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_qpll_drp.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_qpll_drp.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : qpll_drp.v
// Description : QPLL DRP Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_top.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_axi_basic_top.vhd
-- Version : 1.10
-- Version : 1.11
--
-- Description:
-- TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules.
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_eq.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_pipe_eq.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_eq.v
// Description : PIPE Equalization Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_gtp_pipe_rate.v
49,7 → 49,7
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : cl_a7pcie_x4_gtp_pipe_rate.v
// Version : 1.10
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : gtp_pipe_rate.v
// Description : PIPE Rate Module for 7 Series Transceiver
/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_tx_thrtl_ctl.vhd
49,7 → 49,7
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : cl_a7pcie_x4_axi_basic_tx_thrtl_ctl.vhd
-- Version : 1.10
-- Version : 1.11
--
-- Description:
-- TX throttle controller. Anticipates back-pressure from PCIe block and
181,75 → 181,75
CONSTANT PM_ENTER_L1 : INTEGER := 32;
CONSTANT POWERSTATE_D0 : INTEGER := 0;
 
SIGNAL lnk_up_thrtl : STD_LOGIC;
SIGNAL lnk_up_trig : STD_LOGIC;
SIGNAL lnk_up_exit : STD_LOGIC;
SIGNAL tbuf_av_min_thrtl : STD_LOGIC;
SIGNAL tbuf_av_min_trig : STD_LOGIC;
SIGNAL tbuf_av_gap_thrtl : STD_LOGIC;
SIGNAL tbuf_gap_cnt : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL tbuf_gap_cnt_t : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL tbuf_av_gap_trig : STD_LOGIC;
SIGNAL tbuf_av_gap_exit : STD_LOGIC;
SIGNAL gap_trig_tlast : STD_LOGIC;
SIGNAL gap_trig_tlast_1 : STD_LOGIC;
SIGNAL gap_trig_decr : STD_LOGIC;
SIGNAL gap_trig_decr_1 : STD_LOGIC;
SIGNAL gap_trig_decr_2 : STD_LOGIC;
SIGNAL tbuf_av_d : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL tcfg_req_thrtl : STD_LOGIC;
SIGNAL tcfg_req_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL trn_tdst_rdy_d : STD_LOGIC;
SIGNAL tcfg_req_trig : STD_LOGIC;
SIGNAL tcfg_req_exit : STD_LOGIC;
SIGNAL tcfg_gnt_log : STD_LOGIC;
SIGNAL tcfg_gnt_pipe : STD_LOGIC_VECTOR(TCFG_GNT_PIPE_STAGES-1 DOWNTO 0);
SIGNAL pre_throttle : STD_LOGIC;
SIGNAL reg_throttle : STD_LOGIC;
SIGNAL exit_crit : STD_LOGIC;
SIGNAL reg_tcfg_gnt : STD_LOGIC;
SIGNAL trn_tcfg_req_d : STD_LOGIC;
SIGNAL tcfg_gnt_pending : STD_LOGIC;
SIGNAL wire_to_turnoff : STD_LOGIC;
SIGNAL reg_turnoff_ok : STD_LOGIC;
SIGNAL tready_thrtl_mux : STD_LOGIC;
SIGNAL ppm_L1_thrtl : STD_LOGIC;
SIGNAL ppm_L1_trig : STD_LOGIC;
SIGNAL ppm_L1_exit : STD_LOGIC;
SIGNAL cfg_pcie_link_state_d : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL trn_rdllp_src_rdy_d : STD_LOGIC;
SIGNAL ppm_L23_thrtl : STD_LOGIC;
SIGNAL ppm_L23_trig : STD_LOGIC;
SIGNAL cfg_turnoff_ok_pending : STD_LOGIC;
SIGNAL reg_tlast : STD_LOGIC;
SIGNAL cur_state : STD_LOGIC;
SIGNAL next_state : STD_LOGIC;
SIGNAL lnk_up_thrtl : STD_LOGIC:= '0';
SIGNAL lnk_up_trig : STD_LOGIC:= '0';
SIGNAL lnk_up_exit : STD_LOGIC:= '0';
SIGNAL tbuf_av_min_thrtl : STD_LOGIC:= '0';
SIGNAL tbuf_av_min_trig : STD_LOGIC:= '0';
SIGNAL tbuf_av_gap_thrtl : STD_LOGIC:= '0';
SIGNAL tbuf_gap_cnt : STD_LOGIC_VECTOR(2 DOWNTO 0):= (others => '0');
SIGNAL tbuf_gap_cnt_t : STD_LOGIC_VECTOR(2 DOWNTO 0):= (others => '0');
SIGNAL tbuf_av_gap_trig : STD_LOGIC:= '0';
SIGNAL tbuf_av_gap_exit : STD_LOGIC:= '0';
SIGNAL gap_trig_tlast : STD_LOGIC:= '0';
SIGNAL gap_trig_tlast_1 : STD_LOGIC:= '0';
SIGNAL gap_trig_decr : STD_LOGIC:= '0';
SIGNAL gap_trig_decr_1 : STD_LOGIC:= '0';
SIGNAL gap_trig_decr_2 : STD_LOGIC:= '0';
SIGNAL tbuf_av_d : STD_LOGIC_VECTOR(5 DOWNTO 0):= (others => '0');
SIGNAL tcfg_req_thrtl : STD_LOGIC:= '0';
SIGNAL tcfg_req_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0):= (others => '0');
SIGNAL trn_tdst_rdy_d : STD_LOGIC:= '0';
SIGNAL tcfg_req_trig : STD_LOGIC:= '0';
SIGNAL tcfg_req_exit : STD_LOGIC:= '0';
SIGNAL tcfg_gnt_log : STD_LOGIC:= '0';
SIGNAL tcfg_gnt_pipe : STD_LOGIC_VECTOR(TCFG_GNT_PIPE_STAGES-1 DOWNTO 0):= (others => '0');
SIGNAL pre_throttle : STD_LOGIC:= '0';
SIGNAL reg_throttle : STD_LOGIC:= '0';
SIGNAL exit_crit : STD_LOGIC:= '0';
SIGNAL reg_tcfg_gnt : STD_LOGIC:= '0';
SIGNAL trn_tcfg_req_d : STD_LOGIC:= '0';
SIGNAL tcfg_gnt_pending : STD_LOGIC:= '0';
SIGNAL wire_to_turnoff : STD_LOGIC:= '0';
SIGNAL reg_turnoff_ok : STD_LOGIC:= '0';
SIGNAL tready_thrtl_mux : STD_LOGIC:= '0';
SIGNAL ppm_L1_thrtl : STD_LOGIC:= '0';
SIGNAL ppm_L1_trig : STD_LOGIC:= '0';
SIGNAL ppm_L1_exit : STD_LOGIC:= '0';
SIGNAL cfg_pcie_link_state_d : STD_LOGIC_VECTOR(2 DOWNTO 0):= (others => '0');
SIGNAL trn_rdllp_src_rdy_d : STD_LOGIC:= '0';
SIGNAL ppm_L23_thrtl : STD_LOGIC:= '0';
SIGNAL ppm_L23_trig : STD_LOGIC:= '0';
SIGNAL cfg_turnoff_ok_pending : STD_LOGIC:= '0';
SIGNAL reg_tlast : STD_LOGIC:= '0';
SIGNAL cur_state : STD_LOGIC:= '0';
SIGNAL next_state : STD_LOGIC:= '0';
 
SIGNAL reg_axi_in_pkt : STD_LOGIC;
SIGNAL axi_in_pkt : STD_LOGIC;
SIGNAL axi_pkt_ending : STD_LOGIC;
SIGNAL axi_throttled : STD_LOGIC;
SIGNAL axi_thrtl_ok : STD_LOGIC;
SIGNAL tx_ecrc_pause : STD_LOGIC;
SIGNAL reg_axi_in_pkt : STD_LOGIC:= '0';
SIGNAL axi_in_pkt : STD_LOGIC:= '0';
SIGNAL axi_pkt_ending : STD_LOGIC:= '0';
SIGNAL axi_throttled : STD_LOGIC:= '0';
SIGNAL axi_thrtl_ok : STD_LOGIC:= '0';
SIGNAL tx_ecrc_pause : STD_LOGIC:= '0';
 
SIGNAL gap_trig_tcfg : STD_LOGIC;
SIGNAL reg_to_turnoff : STD_LOGIC;
SIGNAL reg_tx_ecrc_pkt : STD_LOGIC;
SIGNAL gap_trig_tcfg : STD_LOGIC:= '0';
SIGNAL reg_to_turnoff : STD_LOGIC:= '0';
SIGNAL reg_tx_ecrc_pkt : STD_LOGIC:= '0';
 
SIGNAL tx_ecrc_pkt : STD_LOGIC;
SIGNAL packet_fmt : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL packet_td : STD_LOGIC;
SIGNAL header_len : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL payload_len : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL packet_len : STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL pause_needed : STD_LOGIC;
SIGNAL tx_ecrc_pkt : STD_LOGIC:= '0';
SIGNAL packet_fmt : STD_LOGIC_VECTOR(1 DOWNTO 0):= (others => '0');
SIGNAL packet_td : STD_LOGIC:= '0';
SIGNAL header_len : STD_LOGIC_VECTOR(2 DOWNTO 0):= (others => '0');
SIGNAL payload_len : STD_LOGIC_VECTOR(9 DOWNTO 0):= (others => '0');
SIGNAL packet_len : STD_LOGIC_VECTOR(13 DOWNTO 0):= (others => '0');
SIGNAL pause_needed : STD_LOGIC:= '0';
 
-- Declare intermediate signals for referenced outputs
SIGNAL cfg_turnoff_ok_xhdl0 : STD_LOGIC;
SIGNAL tready_thrtl_xhdl1 : STD_LOGIC;
SIGNAL cfg_turnoff_ok_xhdl0 : STD_LOGIC:= '0';
SIGNAL tready_thrtl_xhdl1 : STD_LOGIC:= '0';
-- TYPE T_STATE is (IDLE_A,THROTTLE);
-- SIGNAL CUR_STATE_A, NEXT_STATE_A : T_STATE;
SIGNAL CUR_STATE_A, NEXT_STATE_A : STD_LOGIC;
SIGNAL CUR_STATE_A, NEXT_STATE_A : STD_LOGIC := '0';
 
constant IDLE : std_logic := '0';
constant THROTTLE : std_logic := '1';
/projects/ac701_a200t_core/src/testbench/stend_ac701_core.vhd
155,7 → 155,7
test_init( "src\testbench\log\test.log" );
-- test_init( "test.log" );
wait for 180 us;
wait for 250 us;
 
--test_dsc_incorrect( cmd, ret );
/projects/ac701_a200t_core/src/testbench/test_pkg.vhd
505,8 → 505,8
write( str, string'("TEST_BLOCK_MAIN" ));
writeline( log, str );
 
-- block_write( cmd, ret, 4, 16#08#, x"0000AA55" );
block_read( cmd, ret, 4, 16#00#, data );
block_write( cmd, ret, 4, 16#08#, x"0000AA55" );
block_read( cmd, ret, 4, 16#08#, data );
 
 
wait for 10 us;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.