URL
https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk
Subversion Repositories pcie_ds_dma
Compare Revisions
- This comparison shows the changes necessary to convert path
/pcie_ds_dma
- from Rev 46 to Rev 47
- ↔ Reverse comparison
Rev 46 → Rev 47
/trunk/core/adm/cl_ac701/rtl/ctrl_adsp_v2_decode_cmd_adr_cs.vhd
0,0 → 1,62
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : ctrl_adsp_v2_decode_cmd_adr_cs |
-- Author : Dmitry Smekhov, Ilya Ivanov |
-- Company : Instrumental System |
-- |
-- Version : 1.1 |
--------------------------------------------------------------------------------------------------- |
-- |
|
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Version 1.1 17.06.2005 |
|
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use ieee.std_logic_arith.all; |
|
-- synopsys translate_off |
library ieee; |
use ieee.vital_timing.all; |
-- synopsys translate_on |
|
library unisim; |
use unisim.VCOMPONENTS.all; |
|
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entity ctrl_adsp_v2_decode_cmd_adr_cs is |
port ( |
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); |
end ctrl_adsp_v2_decode_cmd_adr_cs; |
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architecture ctrl_adsp_v2_decode_cmd_adr_cs of ctrl_adsp_v2_decode_cmd_adr_cs is |
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--attribute rloc : string; |
--attribute rloc of xcs1 : label is "X0Y0"; |
--attribute rloc of xd : label is "X0Y0"; |
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begin |
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cs1 <='0' when adr( 1 downto 0 )="10" |
else '1' after 1 ns; |
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--xcs1: fmap port map( o=>cs1, i1=>'0', i2=>'0', i3=>adr(0), i4=>adr(1) ); |
xd: fd port map( q=>data_cs, c=>clk, d=>cs1 ); |
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end ctrl_adsp_v2_decode_cmd_adr_cs; |
/trunk/core/adm/cl_ac701/rtl/ctrl_adsp_v2_decode_data_cs.vhd
0,0 → 1,101
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : ctrl_adsp_v2_decode_data_cs |
-- Author : Dmitry Smekhov,Ilya Ivanov |
-- Company : Instrumental System |
-- |
-- Version : 1.1 |
--------------------------------------------------------------------------------------------------- |
-- |
|
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Version 1.1 17.06.2005 |
|
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use ieee.std_logic_arith.all; |
|
-- synopsys translate_off |
library ieee; |
use ieee.vital_timing.all; |
-- synopsys translate_on |
|
library unisim; |
use unisim.VCOMPONENTS.all; |
|
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entity ctrl_adsp_v2_decode_data_cs is |
generic( |
|
|
-- 0 - STATUS |
-- 1 - DATA |
-- 2 - CMD_ADR |
); |
port ( |
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); |
end ctrl_adsp_v2_decode_data_cs; |
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architecture ctrl_adsp_v2_decode_data_cs of ctrl_adsp_v2_decode_data_cs is |
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component fmap is |
port( |
i1, i2, i3, i4 : in std_logic; |
o : in std_logic |
); |
end component; |
|
--attribute rloc : string; |
--attribute rloc of fmap : component is "X0Y0"; |
----attribute rloc of xcs1 : label is "R0C0.S0"; |
--attribute rloc of xd : label is "X0Y0"; |
|
begin |
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gen0: if( reg/=3 ) generate |
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cs0 <='1' when adr( 4 downto 2 )=conv_std_logic_vector( trd, 3 ) else '0'; |
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cs1 <='0' when adr( 1 downto 0 )=conv_std_logic_vector( reg, 2 ) |
and rd='0' and cs0='1' |
else '1' after 1 ns; |
--xcs0: fmap port map( o=>cs0, i1=>adr(2), i2=>adr(3), i3=>adr(4), i4=>'0' ); |
|
end generate; |
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gen3: if( reg=3 ) generate |
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cs0 <='1' when adr( 4 downto 2 )=conv_std_logic_vector( trd, 3 ) |
and cmd_data_en='1' else '0'; |
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cs1 <='0' when adr( 1 downto 0 )=conv_std_logic_vector( reg, 2 ) |
and rd='0' and cs0='1' |
else '1' after 1 ns; |
--xcs0: fmap port map( o=>cs0, i1=>adr(2), i2=>adr(3), i3=>adr(4), i4=>cmd_data_en ); |
|
end generate; |
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--xcs1: fmap port map( o=>cs1, i1=>cs0, i2=>rd, i3=>adr(0), i4=>adr(1) ); |
xd: fd port map( q=>data_cs, c=>clk, d=>cs1 ); |
|
|
end ctrl_adsp_v2_decode_data_cs; |
/trunk/core/adm/cl_ac701/rtl/ctrl_blink.vhd
0,0 → 1,151
------------------------------------------------------------------------------- |
-- |
-- Title : ctrl_blink |
-- Design : ambpex5_v11_lx50t_ddr2 |
-- Author : Dmitry Smekhov |
-- Company : NNS |
-- |
------------------------------------------------------------------------------- |
-- |
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-- |
-- |
------------------------------------------------------------------------------- |
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library ieee; |
use ieee.std_logic_1164.all; |
|
package ctrl_blink_pkg is |
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component ctrl_blink is |
generic( |
is_simulation : in integer:=0 |
); |
port( |
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); |
end component; |
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end package; |
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library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
library unisim; |
use unisim.vcomponents.all; |
|
entity ctrl_blink is |
generic( |
is_simulation : in integer:=0 |
); |
port( |
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); |
end ctrl_blink; |
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architecture ctrl_blink of ctrl_blink is |
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signal clk_blink : std_logic; |
signal clk_z1, clk_z2 : std_logic; |
signal mask : std_logic; |
signal cnt : std_logic_vector( 3 downto 0 ); |
signal cnt30k : std_logic_vector( 13 downto 0 ):=(others=>'0'); |
signal ncnt30k : std_logic_vector( 13 downto 0 ); |
|
signal stp : std_logic; |
|
begin |
gen_sim: if( is_simulation=1 ) generate |
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clk_blink <= cnt30k(4) when stp='1' else cnt30k(3); |
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end generate; |
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gen_syn: if( is_simulation=0 ) generate |
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clk_blink <= cnt30k(13) when stp='1' else cnt30k(12); |
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end generate; |
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clk_z1 <= clk_blink after 1 ns when rising_edge( clk ); |
clk_z2 <= clk_z1 after 1 ns when rising_edge( clk ); |
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cnt30k(0) <= ncnt30k(0) when rising_edge( clk30k ); |
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gen_30k: for i in 1 to 13 generate |
fd30k: fd port map( q=>cnt30k(i), c=>cnt30k(i-1), d=>ncnt30k(i) ); |
end generate; |
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ncnt30k <= not cnt30k; |
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pr_state: process( clk ) begin |
|
if( rising_edge( clk ) ) then |
if( clk_z1='1' and clk_z2='0' ) then |
|
case( stp ) is |
when '0' => |
if( pcie_link_up='0' ) then |
stp <= '1' after 1 ns; |
end if; |
mask <= '0' after 1 ns; |
cnt <= "0000" after 1 ns; |
|
when '1' => |
if( pcie_link_up='1' ) then |
stp <= '0' after 1 ns; |
end if; |
if( cnt(3 downto 0 )="0000" ) then |
mask <= '0' after 1 ns; |
elsif( pcie_lstatus(6 downto 4)=cnt( 2 downto 0 ) ) then |
mask <= '1' after 1 ns; |
end if; |
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cnt <= cnt + 1 after 1 ns; |
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when others => null; |
end case; |
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end if; |
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if( reset='0' ) then |
mask <= '0' after 1 ns; |
stp <= '0' after 1 ns; |
end if; |
end if; |
end process; |
|
led_h1 <= reset and ( clk_blink or mask ); |
|
end ctrl_blink; |
/trunk/core/adm/cl_ac701/rtl/pb_adm_ctrl_m2.vhd
0,0 → 1,1240
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : pb_adm_ctrl_m2 |
-- Author : Dmitry Smekhov |
-- Company : Instrumental System |
-- E-mail : dsmv@insys.ru |
-- |
-- Version : 1.0 |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
|
|
-- |
|
|
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Version 1.0 01.04.2010 |
|
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use ieee.std_logic_arith.all; |
|
|
library work; |
use work.adm2_pkg.all; |
|
package pb_adm_ctrl_m2_pkg is |
|
component pb_adm_ctrl_m2 is |
generic ( |
|
trd1_in : in integer:=0; |
trd2_in : in integer:=0; |
trd3_in : in integer:=0; |
trd4_in : in integer:=0; |
trd5_in : in integer:=0; |
trd6_in : in integer:=0; |
trd7_in : in integer:=0; |
|
|
trd1_st : in integer:=0; |
trd2_st : in integer:=0; |
trd3_st : in integer:=0; |
trd4_st : in integer:=0; |
trd5_st : in integer:=0; |
trd6_st : in integer:=0; |
trd7_st : in integer:=0; |
|
|
|
rom0 : in bl_trd_rom; |
rom1 : in bl_trd_rom; |
rom2 : in bl_trd_rom; |
rom3 : in bl_trd_rom; |
rom4 : in bl_trd_rom; |
rom5 : in bl_trd_rom; |
rom6 : in bl_trd_rom; |
rom7 : in bl_trd_rom; |
|
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trd4_mode : in integer:=0 |
); |
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port ( |
---- GLOBAL ---- |
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---- PLD_BUS ---- |
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trd_host_adr : out std_logic_vector( 6 downto 0 ); |
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trd_host_data : out std_logic_vector( 63 downto 0 ); |
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trd4_host_data : out std_logic_vector( 63 downto 0 ); |
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trd_host_cmd : out std_logic_array_16xbl_cmd; |
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trd_data : in std_logic_array_16x64:=(others=>(others=>'0')); |
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trd_cmd_data : in std_logic_array_16x16:=(others=>(others=>'0')); |
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trd_reset_fifo : in std_logic_array_16xbl_reset_fifo:=(others=>'0'); |
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trd_drq : in std_logic_array_16xbl_drq:=(others=>(others=>'0')); |
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int1 : in std_logic:='0'; |
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drq0 : in bl_drq:=('0', '0', '0'); |
drq1 : in bl_drq:=('0', '0', '0'); |
drq2 : in bl_drq:=('0', '0', '0'); |
drq3 : in bl_drq:=('0', '0', '0'); |
|
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irq1 : out std_logic; |
dmar0 : out std_logic; |
dmar1 : out std_logic; |
dmar2 : out std_logic; |
dmar3 : out std_logic |
|
|
); |
end component; |
|
end package pb_adm_ctrl_m2_pkg; |
|
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use ieee.std_logic_arith.all; |
|
|
|
-- synopsys translate_off |
library ieee; |
use ieee.vital_timing.all; |
|
library unisim; |
use unisim.VCOMPONENTS.all; |
-- synopsys translate_on |
|
library work; |
use work.adm2_pkg.all; |
|
entity pb_adm_ctrl_m2 is |
generic ( |
|
trd1_in : in integer:=0; |
trd2_in : in integer:=0; |
trd3_in : in integer:=0; |
trd4_in : in integer:=0; |
trd5_in : in integer:=0; |
trd6_in : in integer:=0; |
trd7_in : in integer:=0; |
|
|
trd1_st : in integer:=0; |
trd2_st : in integer:=0; |
trd3_st : in integer:=0; |
trd4_st : in integer:=0; |
trd5_st : in integer:=0; |
trd6_st : in integer:=0; |
trd7_st : in integer:=0; |
|
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|
rom0 : in bl_trd_rom; |
rom1 : in bl_trd_rom; |
rom2 : in bl_trd_rom; |
rom3 : in bl_trd_rom; |
rom4 : in bl_trd_rom; |
rom5 : in bl_trd_rom; |
rom6 : in bl_trd_rom; |
rom7 : in bl_trd_rom; |
|
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trd4_mode : in integer:=0 |
|
); |
|
port ( |
---- GLOBAL ---- |
|
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---- PLD_BUS ---- |
|
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trd_host_adr : out std_logic_vector( 6 downto 0 ); |
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trd_host_data : out std_logic_vector( 63 downto 0 ); |
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trd4_host_data : out std_logic_vector( 63 downto 0 ); |
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trd_host_cmd : out std_logic_array_16xbl_cmd; |
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trd_data : in std_logic_array_16x64:=(others=>(others=>'0')); |
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trd_cmd_data : in std_logic_array_16x16:=(others=>(others=>'0')); |
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trd_reset_fifo : in std_logic_array_16xbl_reset_fifo:=(others=>'0'); |
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trd_drq : in std_logic_array_16xbl_drq:=(others=>(others=>'0')); |
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int1 : in std_logic:='0'; |
|
drq0 : in bl_drq:=('0', '0', '0'); |
drq1 : in bl_drq:=('0', '0', '0'); |
drq2 : in bl_drq:=('0', '0', '0'); |
drq3 : in bl_drq:=('0', '0', '0'); |
|
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irq1 : out std_logic; |
dmar0 : out std_logic; |
dmar1 : out std_logic; |
dmar2 : out std_logic; |
dmar3 : out std_logic |
|
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); |
end pb_adm_ctrl_m2; |
|
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architecture pb_adm_ctrl_m2 of pb_adm_ctrl_m2 is |
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component ctrl_dram256x16_v2 is |
port ( |
addra: in std_logic_vector(7 downto 0); |
addrb: in std_logic_vector(7 downto 0); |
clka: in std_logic; |
clkb: in std_logic; |
dina: in std_logic_vector(15 downto 0); |
doutb: out std_logic_vector(15 downto 0); |
sinita: in std_logic; |
ena: in std_logic; |
enb: in std_logic; |
wea: in std_logic); |
end component; |
|
component RAMB16_S18 |
-- synopsys translate_off |
generic ( |
|
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|
WRITE_MODE : string := "WRITE_FIRST"; |
INIT : bit_vector := X"00000"; |
SRVAL : bit_vector := X"00000"; |
|
|
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; |
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" |
); |
-- synopsys translate_on |
port ( |
DO : out STD_LOGIC_VECTOR (15 downto 0); |
DOP : out STD_LOGIC_VECTOR (1 downto 0); |
ADDR : in STD_LOGIC_VECTOR (9 downto 0); |
CLK : in STD_ULOGIC; |
DI : in STD_LOGIC_VECTOR (15 downto 0); |
DIP : in STD_LOGIC_VECTOR (1 downto 0); |
EN : in STD_ULOGIC; |
SSR : in STD_ULOGIC; |
WE : in STD_ULOGIC |
); |
end component; |
|
component ctrl_adsp_v2_decode_data_cs is |
generic( |
|
|
-- 0 - STATUS |
-- 1 - DATA |
-- 2 - CMD_ADR |
-- 3 - CMD_DATA |
); |
port ( |
|
|
|
|
|
|
); |
end component; |
|
component ctrl_adsp_v2_decode_data_in_cs is |
port ( |
|
|
|
|
|
|
); |
end component; |
|
|
component ctrl_adsp_v2_decode_ram_cs is |
generic ( |
|
-- 0 - RAM |
-- 1 - ROM |
); |
port ( |
|
|
|
|
|
|
); |
end component; |
|
component ctrl_adsp_v2_decode_data_we is |
generic( |
|
|
-- 0 - STATUS |
-- 1 - DATA |
-- 2 - CMD_ADR |
-- 3 - CMD_DATA |
); |
port ( |
|
|
|
|
|
); |
end component; |
|
|
component ctrl_adsp_v2_decode_cmd_adr_cs is |
port ( |
|
|
|
|
|
); |
end component; |
|
|
|
component ctrl_mux8x48 is |
port ( |
ma: in std_logic_vector(47 downto 0); |
mb: in std_logic_vector(47 downto 0); |
mc: in std_logic_vector(47 downto 0); |
md: in std_logic_vector(47 downto 0); |
me: in std_logic_vector(47 downto 0); |
mf: in std_logic_vector(47 downto 0); |
mg: in std_logic_vector(47 downto 0); |
mh: in std_logic_vector(47 downto 0); |
s: in std_logic_vector(2 downto 0); |
o: out std_logic_vector(47 downto 0)); |
end component; |
|
|
component ctrl_mux16x16 is |
port ( |
ma: in std_logic_vector(15 downto 0); |
mb: in std_logic_vector(15 downto 0); |
mc: in std_logic_vector(15 downto 0); |
md: in std_logic_vector(15 downto 0); |
me: in std_logic_vector(15 downto 0); |
mf: in std_logic_vector(15 downto 0); |
mg: in std_logic_vector(15 downto 0); |
mh: in std_logic_vector(15 downto 0); |
maa: in std_logic_vector(15 downto 0); |
mab: in std_logic_vector(15 downto 0); |
mac: in std_logic_vector(15 downto 0); |
mad: in std_logic_vector(15 downto 0); |
mae: in std_logic_vector(15 downto 0); |
maf: in std_logic_vector(15 downto 0); |
mag: in std_logic_vector(15 downto 0); |
mah: in std_logic_vector(15 downto 0); |
s: in std_logic_vector(3 downto 0); |
o: out std_logic_vector(15 downto 0)); |
end component; |
|
component ctrl_mux8x16r is |
port ( |
ma: in std_logic_vector(15 downto 0); |
mb: in std_logic_vector(15 downto 0); |
mc: in std_logic_vector(15 downto 0); |
md: in std_logic_vector(15 downto 0); |
me: in std_logic_vector(15 downto 0); |
mf: in std_logic_vector(15 downto 0); |
mg: in std_logic_vector(15 downto 0); |
mh: in std_logic_vector(15 downto 0); |
s: in std_logic_vector(2 downto 0); |
q: out std_logic_vector(15 downto 0); |
clk: in std_logic); |
end component; |
|
|
--component s_delay is |
-- port( |
|
|
-- ); |
--end component; |
|
-- XST black box declaration |
--attribute box_type : string; |
--attribute BOX_TYPE of RAMB16_S18 : component is "BLACK_BOX"; |
|
|
|
signal ms1 : std_logic; |
signal wrl1, wrl2, rd1, rd2: std_logic; |
signal adr1, adr2 : std_logic_vector( 6 downto 0 ); |
signal data2 : std_logic_vector( 63 downto 0 ); |
signal rd2z : std_logic; |
|
signal data_out2 : std_logic_vector( 63 downto 0 ); |
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signal cmd_data2 : std_logic_vector( 15 downto 0 ); |
signal rom_data2 : std_logic_vector( 15 downto 0 ); |
signal sinit, dpram_en : std_logic; |
signal dpram_en0 : std_logic; |
signal addra : std_logic_vector( 9 downto 0 ); |
signal addra2 : std_logic_vector( 15 downto 0 ); |
signal dpram_cs2 : std_logic; |
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signal bl_status_cs : std_logic_vector( 7 downto 0 ); |
signal bl_data_cs : std_logic_vector( 7 downto 0 ); |
signal bl_cmd_data_cs : std_logic_vector( 7 downto 0 ); |
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signal bl_data_we : std_logic_vector( 7 downto 0 ); |
signal bl_cmd_adr_we : std_logic_vector( 7 downto 0 ); |
signal bl_cmd_adr_we1 : std_logic_vector( 7 downto 0 ); |
signal bl_cmd_data_we : std_logic_vector( 7 downto 0 ); |
signal bl_cmd_data_we1 : std_logic_vector( 7 downto 0 ); |
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signal ram_cs1, ram_cs2 : std_logic; |
signal rom_cs2 : std_logic; |
signal data_in_cs2 : std_logic; |
signal data_in_cs2_0 : std_logic; |
signal cmd_adr_cs2 : std_logic; |
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signal cmd0_adr, cmd1_adr, cmd2_adr, cmd3_adr: std_logic_vector( 15 downto 0 ); |
signal cmd4_adr, cmd5_adr, cmd6_adr, cmd7_adr: std_logic_vector( 15 downto 0 ); |
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signal rom_di : std_logic_vector( 15 downto 0 ); |
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signal ram_rom_cs : std_logic; |
signal en_ram : std_logic; |
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signal ma, mb, mc, md, me, mf, mg, mh : std_logic_vector( 63 downto 0 ); |
signal maa, mab, mac, mad, mae, maf, mag, mah : std_logic_vector( 15 downto 0 ); |
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signal na, nb, nc, nd, ne, nf, ng, nh : std_logic_vector( 15 downto 0 ); |
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signal mux_sel : std_logic_vector( 3 downto 0 ); |
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signal flyby2 : std_logic; |
signal flag_data_we : std_logic_vector( 7 downto 0 ); |
signal main_mode2_4 : std_logic:='0'; |
signal trd4i_host_data : std_logic_vector( 63 downto 0 ); |
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signal flag_rd_block : std_logic_vector( 15 downto 0 ); |
signal flag_rd_repack : std_logic_vector( 15 downto 0 ); |
signal trd_repack_data : std_logic_array_16x64:=(others=>(others=>'0')); |
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signal lc_data_i : std_logic_vector( 63 downto 0 ); |
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function conv_rom( rom: in bl_trd_rom; mode: integer ) return bit_vector is |
variable ret: bit_vector( 255 downto 0 ); |
begin |
for i in 0 to 15 loop |
ret( i*16+15 downto i*16 ):=to_bitvector( rom( i+mode*16 ), '0' ); |
end loop; |
return ret; |
end conv_rom; |
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function conv_string( rom: in bl_trd_rom; mode: integer ) return string is |
variable str: string( 64 downto 1 ); |
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variable d : std_logic_vector( 15 downto 0 ); |
variable c : std_logic_vector( 3 downto 0 ); |
variable k : integer; |
begin |
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for i in 0 to 15 loop |
d:=rom( i+mode*16 ); |
for j in 0 to 3 loop |
c:=d( j*4+3 downto j*4 ); |
k:=i*4+j+1; |
case c is |
when x"0" => str(k) := '0'; |
when x"1" => str(k) := '1'; |
when x"2" => str(k) := '2'; |
when x"3" => str(k) := '3'; |
when x"4" => str(k) := '4'; |
when x"5" => str(k) := '5'; |
when x"6" => str(k) := '6'; |
when x"7" => str(k) := '7'; |
when x"8" => str(k) := '8'; |
when x"9" => str(k) := '9'; |
when x"A" => str(k) := 'A'; |
when x"B" => str(k) := 'B'; |
when x"C" => str(k) := 'C'; |
when x"D" => str(k) := 'D'; |
when x"E" => str(k) := 'E'; |
when x"F" => str(k) := 'F'; |
when others => null; |
end case; |
end loop; |
end loop; |
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return str; |
end conv_string; |
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constant rom_init_00 : bit_vector( 255 downto 0 ):= conv_rom( rom0, 0 ); |
constant rom_init_01 : bit_vector( 255 downto 0 ):= conv_rom( rom0, 1 ); |
constant rom_init_02 : bit_vector( 255 downto 0 ):= conv_rom( rom1, 0 ); |
constant rom_init_03 : bit_vector( 255 downto 0 ):= conv_rom( rom1, 1 ); |
constant rom_init_04 : bit_vector( 255 downto 0 ):= conv_rom( rom2, 0 ); |
constant rom_init_05 : bit_vector( 255 downto 0 ):= conv_rom( rom2, 1 ); |
constant rom_init_06 : bit_vector( 255 downto 0 ):= conv_rom( rom3, 0 ); |
constant rom_init_07 : bit_vector( 255 downto 0 ):= conv_rom( rom3, 1 ); |
constant rom_init_08 : bit_vector( 255 downto 0 ):= conv_rom( rom4, 0 ); |
constant rom_init_09 : bit_vector( 255 downto 0 ):= conv_rom( rom4, 1 ); |
constant rom_init_0A : bit_vector( 255 downto 0 ):= conv_rom( rom5, 0 ); |
constant rom_init_0B : bit_vector( 255 downto 0 ):= conv_rom( rom5, 1 ); |
constant rom_init_0C : bit_vector( 255 downto 0 ):= conv_rom( rom6, 0 ); |
constant rom_init_0D : bit_vector( 255 downto 0 ):= conv_rom( rom6, 1 ); |
constant rom_init_0E : bit_vector( 255 downto 0 ):= conv_rom( rom7, 0 ); |
constant rom_init_0F : bit_vector( 255 downto 0 ):= conv_rom( rom7, 1 ); |
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constant str_init_00 : string:= conv_string( rom0, 0 ); |
constant str_init_01 : string:= conv_string( rom0, 1 ); |
constant str_init_02 : string:= conv_string( rom1, 0 ); |
constant str_init_03 : string:= conv_string( rom1, 1 ); |
constant str_init_04 : string:= conv_string( rom2, 0 ); |
constant str_init_05 : string:= conv_string( rom2, 1 ); |
constant str_init_06 : string:= conv_string( rom3, 0 ); |
constant str_init_07 : string:= conv_string( rom3, 1 ); |
constant str_init_08 : string:= conv_string( rom4, 0 ); |
constant str_init_09 : string:= conv_string( rom4, 1 ); |
constant str_init_0A : string:= conv_string( rom5, 0 ); |
constant str_init_0B : string:= conv_string( rom5, 1 ); |
constant str_init_0C : string:= conv_string( rom6, 0 ); |
constant str_init_0D : string:= conv_string( rom6, 1 ); |
constant str_init_0E : string:= conv_string( rom7, 0 ); |
constant str_init_0F : string:= conv_string( rom7, 1 ); |
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attribute rom_style : string; |
attribute rom_style of rom : label is "block"; |
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attribute init_10 : string; |
attribute init_11 : string; |
attribute init_12 : string; |
attribute init_13 : string; |
attribute init_14 : string; |
attribute init_15 : string; |
attribute init_16 : string; |
attribute init_17 : string; |
attribute init_18 : string; |
attribute init_19 : string; |
attribute init_1A : string; |
attribute init_1B : string; |
attribute init_1C : string; |
attribute init_1D : string; |
attribute init_1E : string; |
attribute init_1F : string; |
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attribute init_10 of rom : label is str_init_00; |
attribute init_11 of rom : label is str_init_01; |
attribute init_12 of rom : label is str_init_02; |
attribute init_13 of rom : label is str_init_03; |
attribute init_14 of rom : label is str_init_04; |
attribute init_15 of rom : label is str_init_05; |
attribute init_16 of rom : label is str_init_06; |
attribute init_17 of rom : label is str_init_07; |
attribute init_18 of rom : label is str_init_08; |
attribute init_19 of rom : label is str_init_09; |
attribute init_1A of rom : label is str_init_0A; |
attribute init_1B of rom : label is str_init_0B; |
attribute init_1C of rom : label is str_init_0C; |
attribute init_1D of rom : label is str_init_0D; |
attribute init_1E of rom : label is str_init_0E; |
attribute init_1F of rom : label is str_init_0F; |
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begin |
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rd1<= not lc_rd; |
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wrl1<= not lc_wr; |
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pr_ms2: process( reset, clk ) begin |
if( reset='0' ) then |
wrl2<='1'; rd2<='1'; |
elsif( rising_edge( clk ) ) then |
wrl2<=wrl1 after 1 ns; rd2<=rd1 after 1 ns; |
end if; |
end process; |
|
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adr1<=lc_adr( 6 downto 0 ) when test_mode='0' else "0000010"; |
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pr_adr_in: process( clk ) begin |
if( rising_edge( clk ) ) then |
if( test_mode='1' ) then |
adr2<="0000010"; |
else |
adr2<=adr1; |
end if; |
end if; |
end process; |
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data2<=lc_host_data when rising_edge( clk ); |
trd_host_data<=data2; |
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pr_bl_adr_out: process( clk ) begin |
if( rising_edge( clk ) ) then |
trd_host_adr( 6 downto 0 )<=lc_adr( 6 downto 0 ); |
end if; |
end process; |
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rom: RAMB16_S18 |
-- synopsys translate_off |
generic map ( |
INIT_10 => rom_init_00, |
INIT_11 => rom_init_01, |
INIT_12 => rom_init_02, |
INIT_13 => rom_init_03, |
INIT_14 => rom_init_04, |
INIT_15 => rom_init_05, |
INIT_16 => rom_init_06, |
INIT_17 => rom_init_07, |
INIT_18 => rom_init_08, |
INIT_19 => rom_init_09, |
INIT_1A => rom_init_0A, |
INIT_1B => rom_init_0B, |
INIT_1C => rom_init_0C, |
INIT_1D => rom_init_0D, |
INIT_1E => rom_init_0E, |
INIT_1F => rom_init_0F |
) |
-- synopsys translate_on |
port map ( |
DO => rom_data2, |
ADDR(8 downto 0) => addra( 8 downto 0 ), |
ADDR(9) => '0', |
CLK => clk, |
DI => data2( 15 downto 0 ), |
DIP => "00", |
EN => '1', |
SSR => '0', |
WE => dpram_en |
); |
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en_ram <= ((dpram_en or ram_cs1) and not (addra(8)) )or (ram_cs1 and addra(8)); |
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pr_addra: process( clk ) |
variable vsel: bit_vector( 2 downto 0 ); |
begin |
vsel:=to_bitvector( adr1( 5 downto 3 ), '0' ); |
if( rising_edge( clk ) ) then |
addra( 7 downto 5 )<=adr1( 5 downto 3 ); |
ram_cs1<=not rd1; |
case vsel is |
when "000" => |
addra( 4 downto 0 )<=cmd0_adr( 4 downto 0 ); |
addra( 9 downto 8 )<=cmd0_adr( 9 downto 8 ); |
when "001" => |
addra( 4 downto 0 )<=cmd1_adr( 4 downto 0 ); |
addra( 9 downto 8 )<=cmd1_adr( 9 downto 8); |
when "010" => |
addra( 4 downto 0 )<=cmd2_adr( 4 downto 0 ); |
addra( 9 downto 8 )<=cmd2_adr( 9 downto 8); |
when "011" => |
addra( 4 downto 0 )<=cmd3_adr( 4 downto 0 ); |
addra( 9 downto 8 )<=cmd3_adr( 9 downto 8); |
when "100" => |
addra( 4 downto 0 )<=cmd4_adr( 4 downto 0 ); |
addra( 9 downto 8 )<=cmd4_adr( 9 downto 8); |
when "101" => |
addra( 4 downto 0 )<=cmd5_adr( 4 downto 0 ); |
addra( 9 downto 8 )<=cmd5_adr( 9 downto 8); |
when "110" => |
addra( 4 downto 0 )<=cmd6_adr( 4 downto 0 ); |
addra( 9 downto 8 )<=cmd6_adr( 9 downto 8); |
when "111" => |
addra( 4 downto 0 )<=cmd7_adr( 4 downto 0 ); |
addra( 9 downto 8 )<=cmd7_adr( 9 downto 8); |
end case; |
addra2( 9 downto 8 )<=addra( 9 downto 8 ); |
addra2( 4 downto 0 )<=addra( 4 downto 0 ); |
end if; |
end process; |
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pr_dpram_en: process( clk ) |
variable ven: std_logic; |
begin |
ven:='0'; |
if( rising_edge( clk ) ) then |
if( test_mode='0' ) then |
if( wrl1='0' and adr1(2)='1' and adr1(1)='1' ) then ven:='1'; end if; |
end if; |
dpram_en0<=ven; |
end if; |
end process; |
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dpram_en <='1' when dpram_en0='1' and addra(9)='0' and addra(8)='0' else '0'; |
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rd2z <= rd2 after 1 ns when rising_edge( clk ); |
gen_data_cs: for i in 0 to 7 generate |
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xstatus: ctrl_adsp_v2_decode_data_cs |
generic map( trd=>i, reg=>0 ) |
port map ( |
reset => reset, |
clk => clk, |
cmd_data_en =>'0', |
adr => adr1(5 downto 1), |
rd => rd1, |
data_cs => bl_status_cs(i) |
); |
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xdata: ctrl_adsp_v2_decode_data_cs |
generic map( trd=>i, reg=>1 ) |
port map ( |
reset => reset, |
clk => clk, |
cmd_data_en =>'0', |
adr => adr2(5 downto 1), |
rd => rd2z, |
data_cs => bl_data_cs(i) |
); |
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xcmd_data: ctrl_adsp_v2_decode_data_cs |
generic map( trd=>i, reg=>3 ) |
port map( |
reset => reset, |
clk => clk, |
cmd_data_en =>sel_cmd_data, |
adr => adr1( 5 downto 1 ), |
rd => rd1, |
data_cs => bl_cmd_data_cs(i) |
); |
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xdata_we: ctrl_adsp_v2_decode_data_we |
generic map( trd=>i, reg=>1 ) |
port map( |
reset => reset, |
clk => clk, |
adr => adr1( 5 downto 1 ), |
wr => wrl1, |
data_we => bl_data_we(i) |
); |
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xcmd_adr_we: ctrl_adsp_v2_decode_data_we |
generic map( trd=>i, reg=>2 ) |
port map( |
reset => reset, |
clk => clk, |
adr => adr1( 5 downto 1 ), |
wr => wrl1, |
data_we => bl_cmd_adr_we(i) |
); |
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xcmd_data_we: ctrl_adsp_v2_decode_data_we |
generic map( trd=>i, reg=>3 ) |
port map( |
reset => reset, |
clk => clk, |
adr => adr1( 5 downto 1 ), |
wr => wrl1, |
data_we => bl_cmd_data_we(i) |
); |
|
|
end generate; |
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xcmd_ram: ctrl_adsp_v2_decode_ram_cs |
generic map( reg => 0 ) |
port map ( |
reset => reset, |
clk => clk, |
cmd_adr => addra( 9 downto 8 ), |
adr => adr2( 5 downto 1 ), |
rd => rd2, |
data_cs => ram_cs2 |
); |
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xcmd_rom: ctrl_adsp_v2_decode_ram_cs |
generic map( reg => 1 ) |
port map ( |
reset => reset, |
clk => clk, |
cmd_adr => addra( 9 downto 8 ), |
adr => adr2( 5 downto 1 ), |
rd => rd2, |
data_cs => rom_cs2 |
); |
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xcmd_adr: ctrl_adsp_v2_decode_cmd_adr_cs |
port map( |
reset => reset, |
clk => clk, |
adr => adr2( 5 downto 1 ), |
rd => rd2, |
data_cs => cmd_adr_cs2 |
); |
|
--sel_cmd_data <= addra(9); |
sel_cmd_ram <= '1' when addra(9)='0' and addra(8)='0' else '0'; |
sel_cmd_rom <= '1' when addra(9)='0' and addra(8)='1' else '0'; |
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pr_sel_cmd_data: process( adr1, cmd0_adr, cmd1_adr, cmd2_adr, cmd3_adr, |
cmd4_adr, cmd5_adr, cmd6_adr, cmd7_adr ) |
variable vsel: bit_vector( 2 downto 0 ); |
begin |
vsel:=to_bitvector( adr1( 5 downto 3 ), '0' ); |
case vsel is |
when "000" => sel_cmd_data <= cmd0_adr( 9 ); |
when "001" => sel_cmd_data <= cmd1_adr( 9 ); |
when "010" => sel_cmd_data <= cmd2_adr( 9 ); |
when "011" => sel_cmd_data <= cmd3_adr( 9 ); |
when "100" => sel_cmd_data <= cmd4_adr( 9 ); |
when "101" => sel_cmd_data <= cmd5_adr( 9 ); |
when "110" => sel_cmd_data <= cmd6_adr( 9 ); |
when "111" => sel_cmd_data <= cmd7_adr( 9 ); |
end case; |
end process; |
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pr_cmd_adr: process( reset, clk ) begin |
if( reset='0' ) then |
cmd0_adr<=(others=>'0'); |
cmd1_adr<=(others=>'0'); |
cmd2_adr<=(others=>'0'); |
cmd3_adr<=(others=>'0'); |
cmd4_adr<=(others=>'0'); |
cmd5_adr<=(others=>'0'); |
cmd6_adr<=(others=>'0'); |
cmd7_adr<=(others=>'0'); |
elsif( rising_edge( clk ) ) then |
if( bl_cmd_adr_we(0)='1' ) then cmd0_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; |
if( bl_cmd_adr_we(1)='1' ) then cmd1_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; |
if( bl_cmd_adr_we(2)='1' ) then cmd2_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; |
if( bl_cmd_adr_we(3)='1' ) then cmd3_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; |
if( bl_cmd_adr_we(4)='1' ) then cmd4_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; |
if( bl_cmd_adr_we(5)='1' ) then cmd5_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; |
if( bl_cmd_adr_we(6)='1' ) then cmd6_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; |
if( bl_cmd_adr_we(7)='1' ) then cmd7_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; |
end if; |
end process; |
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pr_adr_we1: process( clk ) begin |
if( rising_edge( clk ) ) then |
bl_cmd_adr_we1<=bl_cmd_adr_we; |
end if; |
end process; |
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cmd0_adr( 15 downto 10 ) <= ( others=>'0' ); |
cmd1_adr( 15 downto 10 ) <= ( others=>'0' ); |
cmd2_adr( 15 downto 10 ) <= ( others=>'0' ); |
cmd3_adr( 15 downto 10 ) <= ( others=>'0' ); |
cmd4_adr( 15 downto 10 ) <= ( others=>'0' ); |
cmd5_adr( 15 downto 10 ) <= ( others=>'0' ); |
cmd6_adr( 15 downto 10 ) <= ( others=>'0' ); |
cmd7_adr( 15 downto 10 ) <= ( others=>'0' ); |
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ram_rom_cs <= ram_cs2 and rom_cs2; |
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pr_irq: process( clk ) begin |
if( rising_edge( clk ) ) then |
irq1 <= int1; |
end if; |
end process; |
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dmar0 <= '1' when drq0.en='1' and drq0.req='1' else '0'; |
dmar1 <= '1' when drq1.en='1' and drq1.req='1' else '0'; |
dmar2 <= '1' when drq2.en='1' and drq2.req='1' else '0'; |
dmar3 <= '1' when drq3.en='1' and drq3.req='1' else '0'; |
|
-- |
--gen_cmd_data_we: for i in 0 to 7 generate |
-- |
--xcmd_data_we: s_delay port map( o=>bl_cmd_data_we1(i), i=>bl_cmd_data_we(i) ); |
-- |
--end generate; |
-- |
|
bl_cmd_data_we1 <= bl_cmd_data_we; |
|
gen_trd_cmd: for i in 0 to 7 generate |
|
trd_host_cmd(i).data_we <=bl_data_we(i) and flag_data_we(i); |
trd_host_cmd(i).cmd_data_we <=bl_cmd_data_we1(i); |
trd_host_cmd(i).status_cs <=bl_status_cs(i); |
trd_host_cmd(i).data_cs <=bl_data_cs(i) or flag_rd_block(i); --flag_rd_repack(i); |
trd_host_cmd(i).data_oe <=bl_data_cs(i); |
trd_host_cmd(i).cmd_data_cs <=bl_cmd_data_cs(i); |
trd_host_cmd(i).cmd_adr_we <=bl_cmd_adr_we1(i); |
|
end generate; |
|
trd_host_cmd(0).adr <=cmd0_adr( 9 downto 0 ); |
trd_host_cmd(1).adr <=cmd1_adr( 9 downto 0 ); |
trd_host_cmd(2).adr <=cmd2_adr( 9 downto 0 ); |
trd_host_cmd(3).adr <=cmd3_adr( 9 downto 0 ); |
trd_host_cmd(4).adr <=cmd4_adr( 9 downto 0 ); |
trd_host_cmd(5).adr <=cmd5_adr( 9 downto 0 ); |
trd_host_cmd(6).adr <=cmd6_adr( 9 downto 0 ); |
trd_host_cmd(7).adr <=cmd7_adr( 9 downto 0 ); |
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mux8: ctrl_mux8x48 |
port map ( |
ma => ma( 63 downto 16 ), |
mb => mb( 63 downto 16 ), |
mc => mc( 63 downto 16 ), |
md => md( 63 downto 16 ), |
me => me( 63 downto 16 ), |
mf => mf( 63 downto 16 ), |
mg => mg( 63 downto 16 ), |
mh => mh( 63 downto 16 ), |
s => mux_sel( 2 downto 0 ), |
o => lc_data_i( 63 downto 16 ) ); |
|
|
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mux16: ctrl_mux16x16 |
port map( |
ma => ma( 15 downto 0 ), |
mb => mb( 15 downto 0 ), |
mc => mc( 15 downto 0 ), |
md => md( 15 downto 0 ), |
me => me( 15 downto 0 ), |
mf => mf( 15 downto 0 ), |
mg => mg( 15 downto 0 ), |
mh => mh( 15 downto 0 ), |
maa => maa( 15 downto 0 ), |
mab => mab( 15 downto 0 ), |
mac => mac( 15 downto 0 ), |
mad => mad( 15 downto 0 ), |
mae => mae( 15 downto 0 ), |
maf => maf( 15 downto 0 ), |
mag => mag( 15 downto 0 ), |
mah => mah( 15 downto 0 ), |
s => mux_sel( 3 downto 0 ), |
o => lc_data_i( 15 downto 0 ) ); |
|
lc_data <= lc_data_i after 1 ns when rising_edge( clk ); |
|
ma <= trd_repack_data(0) after 1 ns when rising_edge( clk ); |
|
xd1p: if( trd1_in=1 ) generate mb <= trd_repack_data(1) after 1 ns when rising_edge( clk ); end generate; |
xd1n: if( trd1_in=0 ) generate mb <= (others=>'0'); end generate; |
|
xd2p: if( trd2_in=1 ) generate mc <= trd_repack_data(2) after 1 ns when rising_edge( clk ); end generate; |
xd2n: if( trd2_in=0 ) generate mc <= (others=>'0'); end generate; |
|
xd3p: if( trd3_in=1 ) generate md <= trd_repack_data(3) after 1 ns when rising_edge( clk ); end generate; |
xd3n: if( trd3_in=0 ) generate md <= (others=>'0'); end generate; |
|
xd4p: if( trd4_in=1 ) generate me <= trd_repack_data(4) after 1 ns when rising_edge( clk ); end generate; |
xd4n: if( trd4_in=0 ) generate me <= (others=>'0'); end generate; |
|
xd5p: if( trd5_in=1 ) generate mf <= trd_repack_data(5) after 1 ns when rising_edge( clk ); end generate; |
xd5n: if( trd5_in=0 ) generate mf <= (others=>'0'); end generate; |
|
xd6p: if( trd6_in=1 ) generate mg <= trd_repack_data(6) after 1 ns when rising_edge( clk ); end generate; |
xd6n: if( trd6_in=0 ) generate mg <= (others=>'0'); end generate; |
|
xd7p: if( trd6_in=1 ) generate mh <= trd_repack_data(7) after 1 ns when rising_edge( clk ); end generate; |
xd7n: if( trd6_in=0 ) generate mh <= (others=>'0'); end generate; |
|
|
gen_repack: for ii in 0 to 7 generate |
|
trd_repack_data(ii)( 31 downto 0 ) <= trd_data(ii)( 31 downto 0 ) when flag_rd_repack(ii)='0' else trd_data(ii)( 63 downto 32 ); |
trd_repack_data(ii)( 63 downto 32 ) <= trd_data(ii)( 63 downto 32 ); |
|
pr_flag4: process( clk ) begin |
if( rising_edge( clk ) ) then |
if( trd_drq(ii).en='1' ) then |
flag_rd_repack(ii) <= '0' after 1 ns; |
flag_rd_block(ii) <= '0' after 1 ns; |
elsif( trd_reset_fifo(ii)='0' ) then |
flag_rd_repack(ii) <= '0' after 1 ns; |
flag_rd_block(ii) <= '1' after 1 ns; |
elsif( bl_data_cs(ii)='0' ) then |
flag_rd_repack(ii) <= not flag_rd_repack(ii) after 1 ns; |
flag_rd_block(ii) <= not flag_rd_block(ii) after 1 ns; |
end if; |
end if; |
end process; |
|
end generate; |
|
|
|
|
maa <= rom_data2 after 1 ns when rising_edge( clk ); |
mab <= cmd_data2 after 1 ns when rising_edge( clk ); |
mac <= addra2 after 1 ns when rising_edge( clk ); |
|
mad <= (others=>'-'); |
mae <= (others=>'-'); |
maf <= (others=>'-'); |
mag <= (others=>'-'); |
mah <= (others=>'-'); |
|
|
pr_mux_sel: process( clk ) begin |
if( rising_edge( clk ) ) then |
case( adr2( 2 downto 1 ) ) is |
when "00" => -- STATUS |
mux_sel <= "1001"; |
when "01" => -- DATA |
mux_sel( 2 downto 0 ) <= adr2( 5 downto 3 ); |
mux_sel( 3 ) <= '0'; |
when "10" => -- CMD_ADR |
mux_sel <= "1010"; |
when "11" => -- CMD_DATA |
mux_sel( 3 downto 1 ) <= "100"; |
mux_sel( 0 ) <= addra( 9 ); |
when others => null; |
end case; |
end if; |
end process; |
|
|
|
mux_cmd: ctrl_mux8x16r |
port map ( |
ma => na, |
mb => nb, |
mc => nc, |
md => nd, |
me => ne, |
mf => nf, |
mg => ng, |
mh => nh, |
s => adr2( 5 downto 3 ), |
q => cmd_data2, |
clk => clk |
); |
|
na <= trd_cmd_data(0) after 1 ns when rising_edge( clk ); |
|
xc1p: if( trd1_st=1 ) generate nb <= trd_cmd_data(1) after 1 ns when rising_edge( clk ); end generate; |
xc1n: if( trd1_st=0 ) generate nb <= (others=>'1'); end generate; |
|
xc2p: if( trd2_st=1 ) generate nc <= trd_cmd_data(2) after 1 ns when rising_edge( clk ); end generate; |
xc2n: if( trd2_st=0 ) generate nc <= (others=>'1'); end generate; |
|
xc3p: if( trd3_st=1 ) generate nd <= trd_cmd_data(3) after 1 ns when rising_edge( clk ); end generate; |
xc3n: if( trd3_st=0 ) generate nd <= (others=>'1'); end generate; |
|
xc4p: if( trd4_st=1 ) generate ne <= trd_cmd_data(4) after 1 ns when rising_edge( clk ); end generate; |
xc4n: if( trd4_st=0 ) generate ne <= (others=>'1'); end generate; |
|
xc5p: if( trd5_st=1 ) generate nf <= trd_cmd_data(5) after 1 ns when rising_edge( clk ); end generate; |
xc5n: if( trd5_st=0 ) generate nf <= (others=>'1'); end generate; |
|
xc6p: if( trd6_st=1 ) generate ng <= trd_cmd_data(6) after 1 ns when rising_edge( clk ); end generate; |
xc6n: if( trd6_st=0 ) generate ng <= (others=>'1'); end generate; |
|
xc7p: if( trd7_st=1 ) generate nh <= trd_cmd_data(7) after 1 ns when rising_edge( clk ); end generate; |
xc7n: if( trd7_st=0 ) generate nh <= (others=>'1'); end generate; |
|
|
|
pr_flag_data_we4: process( clk ) begin |
if( rising_edge( clk ) ) then |
if( main_mode2_4='0' ) then |
flag_data_we(4) <= '1' after 1 ns; |
elsif( trd_reset_fifo( 4 )='0' ) then |
flag_data_we(4) <= '0' after 1 ns; |
elsif( bl_data_we( 4 )='1' ) then |
flag_data_we( 4 ) <= not flag_data_we( 4 ) after 1 ns; |
end if; |
end if; |
end process; |
|
trd4i_host_data( 31 downto 0 ) <= data2( 31 downto 0 ) when rising_edge( clk ) and flag_data_we(4)='0' and bl_data_we(4)='1'; |
trd4i_host_data( 63 downto 32 ) <= data2( 31 downto 0 ); |
|
trd4_host_data <= trd4i_host_data when main_mode2_4='1' else data2; |
|
flag_data_we( 3 downto 0 ) <= (others=>'1'); |
flag_data_we( 7 downto 5 ) <= (others=>'1'); |
|
|
gen_mode2: if( trd4_mode=0 ) generate |
|
pr_main_mode2: process( clk ) begin |
if( rising_edge( clk ) ) then |
if( reset='0' ) then |
main_mode2_4 <= '0' after 1 ns; |
elsif( bl_cmd_data_we1(0)='1' and cmd0_adr( 9 downto 8 )="00" and cmd0_adr( 4 downto 0 )="01010" ) then |
main_mode2_4 <= data2(4) after 1 ns; |
end if; |
end if; |
end process; |
|
end generate; |
|
gen_dmar2: if( trd4_mode=2 ) generate |
|
main_mode2_4 <= not trd_drq(4).en; |
|
end generate; |
|
|
end pb_adm_ctrl_m2; |
/trunk/core/adm/cl_ac701/rtl/ctrl_adsp_v2_decode_data_in_cs.vhd
0,0 → 1,67
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : ctrl_adsp_v2_decode_data_in_cs |
-- Author : Dmitry Smekhov, Ilya Ivanov |
-- Company : Instrumental System |
-- |
-- Version : 1.1 |
--------------------------------------------------------------------------------------------------- |
-- |
|
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Version 1.1 17.06.2005 |
|
-- |
--------------------------------------------------------------------------------------------------- |
|
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use ieee.std_logic_arith.all; |
|
-- synopsys translate_off |
library ieee; |
use ieee.vital_timing.all; |
-- synopsys translate_on |
|
library unisim; |
use unisim.VCOMPONENTS.all; |
|
|
entity ctrl_adsp_v2_decode_data_in_cs is |
port ( |
|
|
|
|
|
|
); |
end ctrl_adsp_v2_decode_data_in_cs; |
|
|
architecture ctrl_adsp_v2_decode_data_in_cs of ctrl_adsp_v2_decode_data_in_cs is |
|
|
|
--attribute rloc : string; |
--attribute rloc of xcs1 : label is "X0Y0"; |
--attribute rloc of xd : label is "X0Y0"; |
|
begin |
|
|
|
cs1 <='0' when adr( 1 downto 0 )="00" or |
adr( 1 downto 0 )="01" or |
( adr( 1 downto 0 )="11" and cmd_adr(9)='1' ) |
else '1' after 1 ns; |
|
--xcs1: fmap port map( o=>cs1, i1=>'0', i2=>cmd_adr(9), i3=>adr(0), i4=>adr(1) ); |
xd: fd port map( q=>data_cs, c=>clk, d=>cs1 ); |
|
|
end ctrl_adsp_v2_decode_data_in_cs; |
|
/trunk/core/adm/cl_ac701/rtl/ctrl_adsp_v2_decode_data_we.vhd
0,0 → 1,83
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : ctrl_adsp_v2_decode_data_we |
-- Author : Dmitry Smekhov, Ilya Ivanov |
-- Company : Instrumental System |
-- |
-- Version : 1.1 |
--------------------------------------------------------------------------------------------------- |
-- |
|
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Version 1.1 17.06.2005 |
|
-- |
--------------------------------------------------------------------------------------------------- |
|
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use ieee.std_logic_arith.all; |
|
-- synopsys translate_off |
library ieee; |
use ieee.vital_timing.all; |
-- synopsys translate_on |
|
library unisim; |
use unisim.VCOMPONENTS.all; |
|
|
entity ctrl_adsp_v2_decode_data_we is |
generic( |
|
|
-- 0 - STATUS |
-- 1 - DATA |
-- 2 - CMD_ADR |
-- 3 - CMD_DATA |
); |
port ( |
|
|
|
|
|
); |
end ctrl_adsp_v2_decode_data_we; |
|
|
architecture ctrl_adsp_v2_decode_data_we of ctrl_adsp_v2_decode_data_we is |
|
|
|
|
component fmap is |
port( |
i1, i2, i3, i4 : in std_logic; |
o : in std_logic |
); |
end component; |
|
--attribute rloc : string; |
--attribute rloc of fmap : component is "X0Y0"; |
--attribute rloc of xd : label is "X0Y0"; |
|
begin |
|
|
cs0 <='1' when adr( 4 downto 2 )=conv_std_logic_vector( trd, 3 ) else '0'; |
cs1 <='1' when adr( 1 downto 0 )=conv_std_logic_vector( reg, 2 ) |
and wr='0' and cs0='1' |
else '0' after 1 ns; |
|
|
--xcs0: fmap port map( o=>cs0, i1=>adr(2), i2=>adr(3), i3=>adr(4), i4=>'0' ); |
--xcs1: fmap port map( o=>cs1, i1=>cs0, i2=>wr, i3=>adr(0), i4=>adr(1) ); |
xd: fd port map( q=>data_we, c=>clk, d=>cs1 ); |
|
|
end ctrl_adsp_v2_decode_data_we; |
|
/trunk/core/adm/cl_ac701/rtl/ctrl_adsp_v2_decode_ram_cs.vhd
0,0 → 1,70
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : ctrl_adsp_v2_decode_ram_cs |
-- Author : Dmitry Smekhov, Ilya Ivanov |
-- Company : Instrumental System |
-- |
-- Version : 1.1 |
--------------------------------------------------------------------------------------------------- |
-- |
|
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Version 1.1 17.06.2005 |
|
-- |
--------------------------------------------------------------------------------------------------- |
|
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use ieee.std_logic_arith.all; |
|
-- synopsys translate_off |
library ieee; |
use ieee.vital_timing.all; |
-- synopsys translate_on |
|
library unisim; |
use unisim.VCOMPONENTS.all; |
|
|
entity ctrl_adsp_v2_decode_ram_cs is |
generic ( |
|
-- 0 - RAM |
-- 1 - ROM |
); |
port ( |
|
|
|
|
|
|
); |
end ctrl_adsp_v2_decode_ram_cs; |
|
|
architecture ctrl_adsp_v2_decode_ram_cs of ctrl_adsp_v2_decode_ram_cs is |
|
|
|
--attribute rloc : string; |
--attribute rloc of xcs1 : label is "X0Y0"; |
--attribute rloc of xd : label is "X0Y0"; |
|
begin |
|
|
|
cs1 <='0' when adr( 1 downto 0 )="11" and |
cmd_adr( 9 downto 8 )=conv_std_logic_vector( reg, 2 ) |
else '1' after 1 ns; |
|
--xcs1: fmap port map( o=>cs1, i1=>cmd_adr(8), i2=>cmd_adr(9), i3=>adr(0), i4=>adr(1) ); |
xd: fd port map( q=>data_cs, c=>clk, d=>cs1 ); |
|
|
end ctrl_adsp_v2_decode_ram_cs; |
/trunk/core/adm/cl_ac701/top/cl_ac701.vhd
0,0 → 1,879
------------------------------------------------------------------------------- |
-- |
-- Title : cl_ac701 |
-- Author : Dmitry Smekhov |
-- Company : Instrumental Systems |
-- E-mail : dsmv@insys.ru |
-- |
-- Version : 1.0 |
-- |
------------------------------------------------------------------------------- |
-- |
|
|
-- |
------------------------------------------------------------------------------- |
-- |
-- Version 1.0 17.02.2014 |
|
-- |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
library work; |
use work.adm2_pkg.all; |
|
|
package cl_ac701_pkg is |
|
constant rom_empty: bl_trd_rom:=(others=>x"0000"); |
|
component cl_ac701 is |
generic ( |
|
|
|
|
|
CLKFBOUT_MULT_F : real := 16.000; |
CLKFBOUT_PHASE : real := 0.000; |
CLKIN1_PERIOD : real := 4.000; |
CLKOUT0_DIVIDE_F : real := 1.000; |
CLKOUT0_DUTY_CYCLE : real := 0.500; |
CLKOUT0_PHASE : real := 0.000; |
CLKOUT1_DIVIDE : integer := 4; |
CLKOUT1_DUTY_CYCLE : real := 0.500; |
CLKOUT1_PHASE : real := 0.000; |
CLKOUT2_DIVIDE : integer := 3; |
CLKOUT2_DUTY_CYCLE : real := 0.500; |
CLKOUT2_PHASE : real := 0.000; |
CLKOUT3_DIVIDE : integer := 1; |
CLKOUT3_DUTY_CYCLE : real := 0.500; |
CLKOUT3_PHASE : real := 0.000; |
CLKOUT4_CASCADE : boolean := FALSE; |
CLKOUT4_DIVIDE : integer := 1; |
CLKOUT4_DUTY_CYCLE : real := 0.500; |
CLKOUT4_PHASE : real := 0.000; |
CLKOUT5_DIVIDE : integer := 4; |
CLKOUT5_DUTY_CYCLE : real := 0.500; |
CLKOUT5_PHASE : real := 0.000; |
CLKOUT6_DIVIDE : integer := 3; |
CLKOUT6_DUTY_CYCLE : real := 0.500; |
CLKOUT6_PHASE : real := 0.000; |
CLOCK_HOLD : boolean := FALSE; |
DIVCLK_DIVIDE : integer := 5; |
|
|
|
trd_rom : in std_logic_array_16xbl_trd_rom:=(others=>(others=>(others=>'0'))); |
|
trd_in : in std_logic_vector( 15 downto 0 ):=x"0000"; |
|
trd_st : in std_logic_vector( 15 downto 0 ):=x"0000"; |
|
|
); |
port ( |
---- PCI-Express ---- |
txp : out std_logic_vector( 3 downto 0 ); |
txn : out std_logic_vector( 3 downto 0 ); |
|
rxp : in std_logic_vector( 3 downto 0 ); |
rxn : in std_logic_vector( 3 downto 0 ); |
|
|
mgt100_n : in std_logic; |
|
|
|
|
p : out std_logic_vector( 3 downto 1 ); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
trd_host_adr : out std_logic_vector( 15 downto 0 ); |
|
|
trd_host_data : out std_logic_array_16x64; |
|
|
trd_host_cmd_data : out std_logic_array_16x16; |
|
|
trd_host_cmd : out std_logic_array_16xbl_cmd; |
|
|
trd_data : in std_logic_array_16x64:=(others=>(others=>'0')); |
|
|
trd_cmd_data : in std_logic_array_16x16:=(others=>(others=>'0')); |
|
|
trd_drq : in std_logic_array_16xbl_drq:=(others=>(others=>'0')); |
|
|
trd_main_drq : in std_logic_array_16xbl_drq:=(others=>(others=>'0')); |
|
|
trd_main_sel_drq: in std_logic_array_16x6:=(others=>(others=>'0')); |
|
|
trd_reset_fifo : in std_logic_array_16xbl_reset_fifo:=(others=>'0'); |
|
|
trd_main_irq : in std_logic_array_16xbl_irq:=(others=>'0') |
|
|
); |
end component; |
|
end package; |
|
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
library unisim; |
use unisim.vcomponents.all; |
|
library work; |
use work.adm2_pkg.all; |
|
use work.pb_adm_ctrl_m2_pkg.all; |
use work.ctrl_blink_pkg.all; |
|
|
|
entity cl_ac701 is |
generic ( |
|
|
|
|
|
CLKFBOUT_MULT_F : real := 16.000; |
CLKFBOUT_PHASE : real := 0.000; |
CLKIN1_PERIOD : real := 4.000; |
CLKOUT0_DIVIDE_F : real := 1.000; |
CLKOUT0_DUTY_CYCLE : real := 0.500; |
CLKOUT0_PHASE : real := 0.000; |
CLKOUT1_DIVIDE : integer := 4; |
CLKOUT1_DUTY_CYCLE : real := 0.500; |
CLKOUT1_PHASE : real := 0.000; |
CLKOUT2_DIVIDE : integer := 3; |
CLKOUT2_DUTY_CYCLE : real := 0.500; |
CLKOUT2_PHASE : real := 0.000; |
CLKOUT3_DIVIDE : integer := 1; |
CLKOUT3_DUTY_CYCLE : real := 0.500; |
CLKOUT3_PHASE : real := 0.000; |
CLKOUT4_CASCADE : boolean := FALSE; |
CLKOUT4_DIVIDE : integer := 1; |
CLKOUT4_DUTY_CYCLE : real := 0.500; |
CLKOUT4_PHASE : real := 0.000; |
CLKOUT5_DIVIDE : integer := 4; |
CLKOUT5_DUTY_CYCLE : real := 0.500; |
CLKOUT5_PHASE : real := 0.000; |
CLKOUT6_DIVIDE : integer := 3; |
CLKOUT6_DUTY_CYCLE : real := 0.500; |
CLKOUT6_PHASE : real := 0.000; |
CLOCK_HOLD : boolean := FALSE; |
DIVCLK_DIVIDE : integer := 5; |
|
|
|
trd_rom : in std_logic_array_16xbl_trd_rom:=(others=>(others=>(others=>'0'))); |
|
trd_in : in std_logic_vector( 15 downto 0 ):=x"0000"; |
|
trd_st : in std_logic_vector( 15 downto 0 ):=x"0000"; |
|
|
); |
port ( |
---- PCI-Express ---- |
txp : out std_logic_vector( 3 downto 0 ); |
txn : out std_logic_vector( 3 downto 0 ); |
|
rxp : in std_logic_vector( 3 downto 0 ); |
rxn : in std_logic_vector( 3 downto 0 ); |
|
|
mgt100_n : in std_logic; |
|
|
|
|
p : out std_logic_vector( 3 downto 1 ); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
trd_host_adr : out std_logic_vector( 15 downto 0 ); |
|
|
trd_host_data : out std_logic_array_16x64; |
|
|
trd_host_cmd_data : out std_logic_array_16x16; |
|
|
trd_host_cmd : out std_logic_array_16xbl_cmd; |
|
|
trd_data : in std_logic_array_16x64:=(others=>(others=>'0')); |
|
|
trd_cmd_data : in std_logic_array_16x16:=(others=>(others=>'0')); |
|
|
trd_drq : in std_logic_array_16xbl_drq:=(others=>(others=>'0')); |
|
|
trd_main_drq : in std_logic_array_16xbl_drq:=(others=>(others=>'0')); |
|
|
trd_main_sel_drq: in std_logic_array_16x6:=(others=>(others=>'0')); |
|
|
trd_reset_fifo : in std_logic_array_16xbl_reset_fifo:=(others=>'0'); |
|
|
trd_main_irq : in std_logic_array_16xbl_irq:=(others=>'0') |
|
|
); |
|
|
|
end cl_ac701; |
|
|
architecture cl_ac701 of cl_ac701 is |
|
--------------------------------------------------------------------------- |
|
component cl_adm_simulation is |
|
generic( |
|
trd_rom : in std_logic_array_16xbl_trd_rom:=(others=>(others=>(others=>'0'))); |
|
trd_in : in std_logic_vector( 15 downto 0 ):=x"0000"; |
|
trd_st : in std_logic_vector( 15 downto 0 ):=x"0000"; |
|
|
|
|
); |
|
port( |
|
|
|
clk_out : out std_logic; |
reset_out : out std_logic; |
|
|
|
|
trd_host_adr : out std_logic_vector( 15 downto 0 ); |
|
|
trd_host_data : out std_logic_vector( 63 downto 0 ); |
|
|
trd_host_cmd : out std_logic_array_16xbl_cmd; |
|
|
trd_data : in std_logic_array_16x64:=(others=>(others=>'0')); |
|
|
trd_cmd_data : in std_logic_array_16x16:=(others=>(others=>'0')); |
|
|
trd_main_drq : in std_logic_array_16xbl_drq:=(others=>(others=>'0')); |
|
|
trd_main_sel_drq: in std_logic_array_16x6:=(others=>(others=>'0')); |
|
|
trd_reset_fifo : in std_logic_array_16xbl_reset_fifo:=(others=>'0'); |
|
|
trd_main_irq : in std_logic_array_16xbl_irq:=(others=>'0') |
|
|
); |
|
end component; |
|
|
component pcie_core64_m5 is |
generic ( |
CORE_NAME : in string:="pcie_core64_m4"; |
|
|
|
|
|
|
); |
|
port ( |
|
---- PCI-Express ---- |
txp : out std_logic_vector( 3 downto 0 ); |
txn : out std_logic_vector( 3 downto 0 ); |
|
rxp : in std_logic_vector( 3 downto 0 ); |
rxn : in std_logic_vector( 3 downto 0 ); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
---- BAR1 ---- |
|
|
|
|
|
|
|
|
|
|
); |
end component; |
|
signal mgt100 : std_logic; |
signal perst : std_logic; |
|
signal lc_adr : std_logic_vector( 31 downto 0 ); |
signal lc_host_data : std_logic_vector( 63 downto 0 ); |
signal lc_data : std_logic_vector( 63 downto 0 ); |
signal lc_wr : std_logic; |
signal lc_rd : std_logic; |
signal lc_dma_req : std_logic_vector( 1 downto 0 ); |
signal lc_irq : std_logic; |
|
|
|
|
|
|
|
signal trdi_host_data : std_logic_vector( 63 downto 0 ); |
|
signal dcm_rstp : std_logic; |
signal clk_lock : std_logic; |
signal clk250 : std_logic; |
signal clk200 : std_logic; |
signal clk200x : std_logic; |
signal clk266x : std_logic; |
signal clkfb : std_logic; |
|
signal clk30i : std_logic; |
signal cnt30k0 : std_logic; |
signal cnt30k1 : std_logic; |
signal cnt30k2 : std_logic; |
signal cnt30i0 : std_logic; |
signal cnt30i1 : std_logic; |
signal cnt30i2 : std_logic; |
signal cnt30ce0 : std_logic; |
signal cnt30ce1 : std_logic; |
signal cnt30ce2 : std_logic; |
signal cnt30start : std_logic; |
signal cnt30start1 : std_logic; |
|
|
signal trdi_host_cmd : std_logic_array_16xbl_cmd; |
|
signal clk : std_logic:='0'; |
signal reset : std_logic; |
|
signal pcie_link_up : std_logic; |
signal pcie_lstatus : std_logic_vector( 15 downto 0 ); |
|
signal px : std_logic_vector( 7 downto 0 ); |
|
signal trd4_host_data : std_logic_vector( 63 downto 0 ); |
|
attribute period : string; |
attribute period of clk:signal is "250 MHz"; |
|
attribute buffer_type : string; |
attribute clock_buffer : string; |
--attribute clock_buffer of signal_name: signal is "{bufgdll|ibufg|bufgp|ibuf|none}"; |
attribute buffer_type of clk_out: signal is "none"; |
attribute buffer_type of clk: signal is "none"; |
|
attribute clock_buffer of clk_out : signal is "none"; |
attribute clock_buffer of clk : signal is "none"; |
attribute clock_buffer of clk200_out : signal is "none"; |
|
attribute syn_keep : boolean; |
attribute syn_keep of trd_host_data : signal is true; |
attribute syn_keep of trd_host_cmd_data: signal is true; |
|
begin |
|
xpll: MMCM_BASE |
generic map( |
BANDWIDTH => "OPTIMIZED", |
CLKFBOUT_MULT_F => CLKFBOUT_MULT_F, |
CLKFBOUT_PHASE => CLKFBOUT_PHASE, |
CLKIN1_PERIOD => CLKIN1_PERIOD, |
CLKOUT0_DIVIDE_F => CLKOUT0_DIVIDE_F, |
CLKOUT0_DUTY_CYCLE => CLKOUT0_DUTY_CYCLE, |
CLKOUT0_PHASE => CLKOUT0_PHASE, |
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE, |
CLKOUT1_DUTY_CYCLE => CLKOUT1_DUTY_CYCLE, |
CLKOUT1_PHASE => CLKOUT1_PHASE, |
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE, |
CLKOUT2_DUTY_CYCLE => CLKOUT2_DUTY_CYCLE, |
CLKOUT2_PHASE => CLKOUT2_PHASE, |
CLKOUT3_DIVIDE => CLKOUT3_DIVIDE, |
CLKOUT3_DUTY_CYCLE => CLKOUT3_DUTY_CYCLE, |
CLKOUT3_PHASE => CLKOUT3_PHASE, |
CLKOUT4_CASCADE => CLKOUT4_CASCADE, |
CLKOUT4_DIVIDE => CLKOUT4_DIVIDE, |
CLKOUT4_DUTY_CYCLE => CLKOUT4_DUTY_CYCLE, |
CLKOUT4_PHASE => CLKOUT4_PHASE, |
CLKOUT5_DIVIDE => CLKOUT5_DIVIDE, |
CLKOUT5_DUTY_CYCLE => CLKOUT5_DUTY_CYCLE, |
CLKOUT5_PHASE => CLKOUT5_PHASE, |
CLKOUT6_DIVIDE => CLKOUT6_DIVIDE, |
CLKOUT6_DUTY_CYCLE => CLKOUT6_DUTY_CYCLE, |
CLKOUT6_PHASE => CLKOUT6_PHASE, |
CLOCK_HOLD => CLOCK_HOLD, |
DIVCLK_DIVIDE => DIVCLK_DIVIDE |
-- REF_JITTER1 : real := 0.010; |
-- STARTUP_WAIT : boolean := FALSE |
) |
port map( |
CLKFBOUT => clkfb, |
--CLKFBOUTB : out std_ulogic; |
CLKOUT0 => clk0_pll, |
CLKOUT0B => clk0_pll_b, |
CLKOUT1 => clk1_pll, |
CLKOUT1B => clk1_pll_b, |
CLKOUT2 => clk2_pll, |
CLKOUT2B => clk2_pll_b, |
CLKOUT3 => clk3_pll, |
CLKOUT3B => clk3_pll_b, |
CLKOUT4 => clk4_pll, |
CLKOUT5 => clk200x, |
CLKOUT6 => clk266x, |
LOCKED => clk_lock, |
CLKFBIN => clkfb, |
CLKIN1 => clk250, |
PWRDWN => '0', |
RST => dcm_rstp |
); |
--clk_lock <= '1'; |
clk <= clk250; |
|
xclk200: bufg port map( clk200, clk200x ); |
--xclk266: bufg port map( clk, clk266x ); |
clk200_out <= clk200; |
clk_lock_out <= clk_lock; |
|
|
|
gen_syn: if( is_simulation=0 or is_simulation=2 ) generate |
|
|
clk_out <= clk; |
reset_out <= reset after 1 ns when rising_edge( clk ); |
clk30k <= clk30i; |
|
|
--xmgtclk : IBUFDS port map (O => mgt100, I => mgt100_p, IB => mgt100_n ); |
|
refclk_ibuf : IBUFDS_GTXE1 |
port map( |
O => mgt100, |
ODIV2 => open, |
I => mgt100_p, |
IB => mgt100_n, |
CEB => '0' |
); |
|
xmperst: ibuf port map( perst, bperst ); |
|
|
pcie: pcie_core64_m5 |
generic map( |
|
|
|
|
|
|
) |
|
port map( |
|
---- PCI-Express ---- |
txp => txp, |
txn => txn, |
|
rxp => rxp, |
rxn => rxn, |
|
mgt250 => mgt100, |
|
perst => perst, |
|
px => px, |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
); |
|
|
|
p(1) <= px(0); -- int_req_fl |
p(2) <= px(1); -- int_req_main |
p(3) <= px(2); -- int_ack |
|
|
blink: ctrl_blink |
generic map( |
is_simulation => is_simulation |
) |
port map( |
|
|
|
|
|
|
|
|
); |
|
|
led_h2 <= reset and not dmar1; |
led_h3 <= reset and not dmar0; |
led_h4 <= reset and not px(0); |
|
|
ad: pb_adm_ctrl_m2 |
generic map ( |
|
trd1_in => conv_integer( trd_in(1) ), |
trd2_in => conv_integer( trd_in(2) ), |
trd3_in => conv_integer( trd_in(3) ), |
trd4_in => conv_integer( trd_in(4) ), |
trd5_in => conv_integer( trd_in(5) ), |
trd6_in => conv_integer( trd_in(6) ), |
trd7_in => conv_integer( trd_in(7) ), |
|
|
trd1_st => conv_integer( trd_st(1) ), |
trd2_st => conv_integer( trd_st(2) ), |
trd3_st => conv_integer( trd_st(3) ), |
trd4_st => conv_integer( trd_st(4) ), |
trd5_st => conv_integer( trd_st(5) ), |
trd6_st => conv_integer( trd_st(6) ), |
trd7_st => conv_integer( trd_st(7) ), |
|
|
rom0 => trd_rom(0), |
rom1 => trd_rom(1), |
rom2 => trd_rom(2), |
rom3 => trd_rom(3), |
rom4 => trd_rom(4), |
rom5 => trd_rom(5), |
rom6 => trd_rom(6), |
rom7 => trd_rom(7) |
|
) |
|
port map( |
---- GLOBAL ---- |
|
|
|
---- PLD_BUS ---- |
|
|
|
|
|
|
|
|
|
|
trd_host_adr => trd_host_adr( 6 downto 0 ), |
|
|
trd_host_data => trdi_host_data, |
|
|
trd4_host_data => trd4_host_data, |
|
|
trd_host_cmd => trdi_host_cmd, |
|
|
trd_data => trd_data, |
|
|
trd_cmd_data => trd_cmd_data, |
|
|
trd_reset_fifo => trd_reset_fifo, |
|
|
trd_drq => trd_drq, |
|
|
int1 => trd_main_irq(1), |
|
drq0 => trd_main_drq(0), |
drq1 => trd_main_drq(1), |
drq2 => trd_main_drq(2), |
drq3 => trd_main_drq(3), |
|
|
irq1 => irq1, |
dmar0 => dmar0, |
dmar1 => dmar1, |
dmar2 => dmar2, |
dmar3 => dmar3 |
|
); |
|
|
|
|
lc_dma_req <= dmar1 & dmar0; |
lc_irq <= irq1; |
|
end generate; |
|
gen_simulation: if( is_simulation=1 ) generate |
|
clk_out <= clk; |
|
ctrl: cl_adm_simulation |
|
generic map( |
|
trd_rom => trd_rom, |
|
trd_in => trd_in, |
|
trd_st => trd_st, |
|
|
|
|
) |
|
port map( |
|
|
|
clk_out => clk, |
reset_out => reset_out, |
|
|
|
|
trd_host_adr => trd_host_adr, |
|
|
trd_host_data => trdi_host_data, |
|
|
trd_host_cmd => trdi_host_cmd, |
|
|
trd_data => trd_data, |
|
|
trd_cmd_data => trd_cmd_data, |
|
|
trd_main_drq => trd_main_drq, |
|
|
trd_main_sel_drq=> trd_main_sel_drq, |
|
|
trd_reset_fifo => trd_reset_fifo, |
|
|
trd_main_irq => trd_main_irq |
|
|
); |
|
|
--trd_host_data <= trdi_host_data; |
trd4_host_data <= trdi_host_data; |
|
|
end generate; |
|
|
|
gen_cmd: for ii in 0 to 7 generate |
|
trd_host_cmd(ii).data_cs <= trdi_host_cmd(ii).data_cs; |
trd_host_cmd(ii).data_oe <= '0'; |
trd_host_cmd(ii).cmd_data_cs <= trdi_host_cmd(ii).cmd_data_cs; |
trd_host_cmd(ii).status_cs <= trdi_host_cmd(ii).status_cs; |
|
trd_host_cmd(ii).data_we <= trdi_host_cmd(ii).data_we after 0.4 ns when rising_edge( clk ); |
trd_host_cmd(ii).cmd_data_we <= trdi_host_cmd(ii).cmd_data_we after 0.4 ns when rising_edge( clk ); |
trd_host_cmd(ii).cmd_adr_we <= trdi_host_cmd(ii).cmd_adr_we after 0.4 ns when rising_edge( clk ); |
|
trd_host_cmd(ii).adr <= trdi_host_cmd(ii).adr; |
|
gen_data: if( ii/=4 ) generate |
--trd_host_data(ii) <= trdi_host_data after 0.4 ns when rising_edge( clk ); |
|
gen_bus: for jj in 0 to 63 generate |
attribute syn_keep of xfd : label is true; |
begin |
xfd: fd port map( q=>trd_host_data(ii)(jj), c=>clk, d=>trdi_host_data(jj) ); |
end generate; |
|
end generate; |
|
gen_data_t4: if( ii=4 ) generate |
--trd_host_data(ii) <= trd4_host_data after 0.4 ns when rising_edge( clk ); |
|
gen_bus: for jj in 0 to 63 generate |
attribute syn_keep of xfd : label is true; |
begin |
xfd: fd port map( q=>trd_host_data(ii)(jj), c=>clk, d=>trd4_host_data(jj) ); |
end generate; |
|
end generate; |
|
trd_host_cmd_data(ii) <= trdi_host_data( 15 downto 0 ) after 0.4 ns when rising_edge( clk ); |
|
end generate; |
|
|
|
|
cnt30start <= dcm_rstp after 1 ns when rising_edge( clk250 ); |
cnt30start1 <= cnt30start after 1 ns when rising_edge( clk250 ); |
|
cnt30i0 <= ((cnt30start xor cnt30start1) or cnt30k0) and not cnt30start; |
cnt30i1 <= ((cnt30start xor cnt30start1) or cnt30k1 )and not cnt30start; |
cnt30i2 <= not cnt30k2 and not cnt30start; |
cnt30ce1 <= (cnt30start xor cnt30start1) or cnt30k0 or cnt30start; |
cnt30ce2 <= (cnt30k1 and cnt30ce1) or cnt30start; |
|
xcnt0: srlc32e port map( q31=>cnt30k0, clk=>clk250, d=>cnt30i0, a=>"11111", ce=>'1' ); |
xcnt1: srlc32e port map( q31=>cnt30k1, clk=>clk250, d=>cnt30i1, a=>"11111", ce=>cnt30ce1 ); |
xcnt2: srlc32e port map( q=>cnt30k2, clk=>clk250, d=>cnt30i2, a=>"01001", ce=>cnt30ce2 ); |
|
clk30i <= cnt30k2; |
|
end cl_ac701; |
|
|
|
/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/top/pcie_core64_m10.vhd
678,7 → 678,7
cfg_pmcsr_pme_status => open, |
cfg_pmcsr_powerstate => open, |
|
PIPE_MMCM_RST_N => perst, |
PIPE_MMCM_RST_N => '1', |
sys_clk => mgt250, |
sys_rst_n => perst |
|
/trunk/core/ds_dma64/pcie_src/components/rtl/core64_pb_transaction.vhd
5,7 → 5,7
-- Company : Instrumental Systems |
-- E-mail : dsmv@insys.ru |
-- |
-- Version : 1.1 |
-- Version : 1.2 |
-- |
------------------------------------------------------------------------------- |
-- |
18,6 → 18,11
-- |
------------------------------------------------------------------------------- |
-- |
-- Version 1.2 14.12.2011 |
|
-- |
--------------------------------------------------------------------------------- |
-- |
-- Version 1.1 28.09.2011 Dmitry Smekhov |
|
-- |
46,7 → 51,8
|
|
|
|
|
|
|
|
); |
82,7 → 88,8
|
|
|
|
|
|
|
|
); |
136,7 → 143,8
|
rd_start <= cnt_start and not cnt(9); |
|
xrdz: srl16 port map( q=>rd_start_z, clk=>clk, d=>rd_start, a3=>'0', a2=>'1', a1=>'0', a0=>'1' ); |
--xrdz: srl16 port map( q=>rd_start_z, clk=>clk, d=>rd_start, a3=>'0', a2=>'1', a1=>'0', a0=>'1' ); |
xrdz: srl16 port map( q=>rd_start_z, clk=>clk, d=>rd_start, a3=>lc_rd_cfg(3), a2=>lc_rd_cfg(2), a1=>lc_rd_cfg(1), a0=>lc_rd_cfg(0) ); |
|
pb_slave.stb0 <= pb_master.stb0 after 1 ns when rising_edge( clk ); |
pb_slave.stb1 <= rd_start_z after 1 ns when rising_edge( clk ); |
/trunk/core/ds_dma64/pcie_src/components/pcie_core/pcie_core64_m5.vhd
78,7 → 78,8
|
|
|
|
|
|
|
|
|
93,7 → 94,7
use ieee.std_logic_1164.all; |
|
use work.core64_type_pkg.all; |
use work.pcie_core64_m4_pkg.all; |
--use work.pcie_core64_m4_pkg.all; |
use work.core64_pb_transaction_pkg.all; |
use work.block_pe_main_pkg.all; |
|
142,7 → 143,8
|
|
|
|
|
|
|
|
|
152,6 → 154,62
|
architecture pcie_core64_m5 of pcie_core64_m5 is |
|
|
component pcie_core64_m4 is |
generic ( |
|
|
|
|
|
); |
|
port ( |
|
---- PCI-Express ---- |
txp : out std_logic_vector( 3 downto 0 ); |
txn : out std_logic_vector( 3 downto 0 ); |
|
rxp : in std_logic_vector( 3 downto 0 ); |
rxn : in std_logic_vector( 3 downto 0 ); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
---- BAR1 ---- |
|
|
|
|
|
|
|
); |
end component; |
|
component pcie_core64_m10 is |
generic ( |
|
362,7 → 420,8
lc_wr => lc_wr, |
lc_rd => lc_rd, |
lc_dma_req => lc_dma_req, |
lc_irq => lc_irq |
lc_irq => lc_irq, |
lc_rd_cfg => lc_rd_cfg |
); |
|
|
/trunk/projects/ac701_a200t_core/src/testbench/stend_ac701_core.vhd
0,0 → 1,180
------------------------------------------------------------------------------- |
-- |
-- Title : stend_ambpex5_core |
-- Author : Dmitry Smekhov |
-- Company : Instrumental Systems |
-- E-mail : dsmv@insys.ru |
-- |
-- Version : 1.0 |
-- |
------------------------------------------------------------------------------- |
-- |
-- Description : |
-- |
------------------------------------------------------------------------------- |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_textio.all; |
|
library work; |
|
use work.cmd_sim_pkg.all; |
use work.block_pkg.all; |
use work.ac701_a200t_core_pkg.all; |
use work.xilinx_pcie_rport_m2_pkg.all; |
|
use work.test_pkg.all; |
|
use std.textio.all; |
use std.textio; |
|
entity stend_ac701_core is |
end stend_ac701_core; |
|
|
architecture stend_ac701_core of stend_ac701_core is |
|
|
signal clk250 : std_logic:='0'; |
signal clk250p : std_logic; |
signal clk250n : std_logic; |
|
signal clk100 : std_logic:='0'; |
signal clk100p : std_logic; |
signal clk100n : std_logic; |
|
signal reset : std_logic; |
|
signal txp : std_logic_vector( 3 downto 0 ):=(others=>'0'); |
signal txn : std_logic_vector( 3 downto 0 ):=(others=>'1'); |
signal rxp : std_logic_vector( 3 downto 0 ):=(others=>'0'); |
signal rxn : std_logic_vector( 3 downto 0 ):=(others=>'1'); |
|
signal rp_txp : std_logic_vector( 0 downto 0 ):=(others=>'0'); |
signal rp_txn : std_logic_vector( 0 downto 0 ):=(others=>'1'); |
signal rp_rxp : std_logic_vector( 0 downto 0 ):=(others=>'0'); |
signal rp_rxn : std_logic_vector( 0 downto 0 ):=(others=>'1'); |
|
signal tp : std_logic_vector( 3 downto 1 ); |
signal led1 : std_logic; |
signal led2 : std_logic; |
signal led3 : std_logic; |
signal led4 : std_logic; |
|
|
|
|
|
begin |
|
amb: ac701_a200t_core |
generic map( |
|
) |
port map( |
---- PCI-Express ---- |
pci_exp_txp => txp, |
pci_exp_txn => txn, |
|
pci_exp_rxp => rxp, |
pci_exp_rxn => rxn, |
|
|
sys_clk_n => clk100n, |
|
|
|
|
|
gpio_led1 => led1, |
gpio_led2 => led2, |
gpio_led3 => led3, |
gpio_led4 => led4 |
); |
|
|
rp : xilinx_pcie_rport_m2 |
generic map ( |
REF_CLK_FREQ => 0, |
ALLOW_X8_GEN2 => FALSE, |
PL_FAST_TRAIN => TRUE, |
LINK_CAP_MAX_LINK_SPEED => X"1", |
DEVICE_ID => X"6011", |
LINK_CAP_MAX_LINK_WIDTH => X"01", |
LINK_CAP_MAX_LINK_WIDTH_int => 1, |
LINK_CTRL2_TARGET_LINK_SPEED => X"1", |
LTSSM_MAX_LINK_WIDTH => X"01", |
DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2, |
VC0_TX_LASTPACKET => 29, |
VC0_RX_RAM_LIMIT => X"7FF", |
VC0_TOTAL_CREDITS_PD => (308), |
VC0_TOTAL_CREDITS_CD => (308), |
USER_CLK_FREQ => 1 |
) |
port map ( |
|
sys_clk => clk100, |
sys_reset_n => reset, |
|
pci_exp_txn => rp_txn, |
pci_exp_txp => rp_txp, |
pci_exp_rxn => rp_rxn, |
pci_exp_rxp => rp_rxp, |
|
|
|
|
); |
|
|
clk100 <= not clk100 after 5 ns; |
--clk250 <= not clk250 after 2 ns; |
-- |
--clk250p <= clk250; |
--clk250n <= not clk250; |
|
clk100p <= clk100; |
clk100n <= not clk100; |
|
rxp(0) <= rp_txp(0); |
rxn(0) <= rp_txn(0); |
|
rp_rxp(0) <= txp(0); |
rp_rxn(0) <= txn(0); |
|
reset <= '0', '1' after 5002 ns; |
|
pr_main: process |
|
variable data : std_logic_vector( 31 downto 0 ); |
variable str : LINE; -- pointer to string |
begin |
|
test_init( "src\testbench\log\test.log" ); |
-- test_init( "test.log" ); |
|
wait for 180 us; |
|
|
--test_dsc_incorrect( cmd, ret ); |
|
--test_read_4kb( cmd, ret ); |
--test_adm_read_8kb( cmd, ret ); |
test_adm_read_16kb( cmd, ret ); |
--test_adm_write_16kb( cmd, ret ); |
--test_block_main( cmd, ret ); |
|
test_close; |
-- |
-- Print Final Banner |
report "Init END OF TEST" severity WARNING; |
assert false |
report "End of TEST; Ending simulation (not a Failure)" |
severity FAILURE; |
wait; |
|
end process; |
|
end stend_ac701_core; |
/trunk/projects/ac701_a200t_core/src/testbench/test_pkg.vhd
0,0 → 1,1057
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : test_pkg.vhd |
-- Author : Dmitry Smekhov |
-- Company : Instrumental System |
-- |
-- Version : 1.0 |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
|
-- |
--------------------------------------------------------------------------------------------------- |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use std.textio.all; |
|
|
library work; |
use work.cmd_sim_pkg.all; |
use work.block_pkg.all; |
use work.trd_pkg.all; |
|
|
|
package test_pkg is |
|
|
procedure test_init( |
|
); |
|
|
procedure test_close; |
|
|
|
|
procedure test_dsc_incorrect ( |
|
|
); |
|
|
procedure test_read_4kb ( |
|
|
); |
|
|
|
procedure test_adm_read_8kb ( |
|
|
); |
|
|
procedure test_block_main ( |
|
|
); |
|
|
procedure test_adm_read_16kb ( |
|
|
); |
|
|
procedure test_adm_write_16kb ( |
|
|
); |
|
end package test_pkg; |
|
package body test_pkg is |
|
FILE log: text; |
|
shared variable cnt_ok, cnt_error: integer; |
|
|
procedure test_init( |
|
) is |
begin |
|
file_open( log, fname, WRITE_MODE ); |
cnt_ok:=0; |
cnt_error:=0; |
|
end test_init; |
|
|
procedure test_close is |
variable str : LINE; -- pointer to string |
begin |
|
std.textio.write( str, string'(" " )); |
writeline( log, str ); |
writeline( log, str ); |
|
|
writeline( log, str ); |
|
write( str, cnt_ok ); |
writeline( log, str ); |
|
write( str, cnt_error ); |
writeline( log, str ); |
|
|
file_close( log ); |
|
end test_close; |
|
|
|
|
procedure test_dsc_incorrect ( |
|
|
) |
is |
|
variable adr : std_logic_vector( 31 downto 0 ); |
variable data : std_logic_vector( 31 downto 0 ); |
variable str : line; |
begin |
|
write( str, string'("TEST_DSC_INCORRECT" )); |
writeline( log, str ); |
|
|
for ii in 0 to 127 loop |
adr:= x"00100000"; |
adr:=adr + ii*4; |
int_mem_write( cmd, ret, adr, x"00000000" ); |
end loop; |
|
int_mem_write( cmd, ret, x"00100000", x"03020100" ); |
int_mem_write( cmd, ret, x"001001FC", x"FF00AA00" ); |
|
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE |
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO |
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL |
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH |
block_write( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR |
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START |
|
wait for 10 us; |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
if( data( 15 downto 0 )=x"A021" ) then |
write( str, string'(" - Ok" )); |
cnt_ok := cnt_ok + 1; |
else |
write( str, string'(" - Error" )); |
cnt_error := cnt_error + 1; |
end if; |
|
writeline( log, str ); |
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP |
|
end test_dsc_incorrect; |
|
|
|
procedure test_read_4kb ( |
|
|
) |
is |
|
variable adr : std_logic_vector( 31 downto 0 ); |
variable data : std_logic_vector( 31 downto 0 ); |
variable str : line; |
|
variable error : integer:=0; |
variable dma_complete : integer; |
|
begin |
|
write( str, string'("TEST_READ_4KB" )); |
writeline( log, str ); |
|
|
for ii in 0 to 127 loop |
adr:= x"00100000"; |
adr:=adr + ii*4; |
int_mem_write( cmd, ret, adr, x"00000000" ); |
end loop; |
|
int_mem_write( cmd, ret, x"00100000", x"00008000" ); |
int_mem_write( cmd, ret, x"00100004", x"00000100" ); |
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" ); |
int_mem_write( cmd, ret, x"001001FC", x"762C4953" ); |
|
|
block_write( cmd, ret, 4, 8, x"00000025" ); -- DMA_MODE |
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO |
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL |
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH |
block_write( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR |
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START |
|
wait for 20 us; |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
if( data( 8 )='1' ) then |
|
else |
|
error := error + 1; |
end if; |
|
writeline( log, str ); |
|
if( error=0 ) then |
|
|
dma_complete := 0; |
for ii in 0 to 100 loop |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
if( data(5)='1' ) then |
|
dma_complete := 1; |
end if; |
writeline( log, str ); |
|
if( dma_complete=1 ) then |
exit; |
end if; |
|
wait for 1 us; |
|
end loop; |
|
writeline( log, str ); |
|
if( dma_complete=0 ) then |
|
writeline( log, str ); |
error:=error+1; |
end if; |
|
end if; |
|
for ii in 0 to 3 loop |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
writeline( log, str ); |
wait for 500 ns; |
|
end loop; |
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP |
|
|
writeline( log, str ); |
|
for ii in 0 to 15 loop |
|
adr:= x"00800000"; |
adr:=adr + ii*4; |
int_mem_read( cmd, ret, adr, data ); |
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data ); |
writeline( log, str ); |
|
end loop; |
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO |
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL |
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START |
|
|
writeline( log, str ); |
if( error=0 ) then |
|
cnt_ok := cnt_ok + 1; |
else |
|
cnt_error := cnt_error + 1; |
end if; |
writeline( log, str ); |
writeline( log, str ); |
|
end test_read_4kb; |
|
|
|
procedure test_adm_read_8kb ( |
|
|
) |
is |
|
variable adr : std_logic_vector( 31 downto 0 ); |
variable data : std_logic_vector( 31 downto 0 ); |
variable str : line; |
|
variable error : integer:=0; |
variable dma_complete : integer; |
|
begin |
|
write( str, string'("TEST_ADM_READ_8KB" )); |
writeline( log, str ); |
|
|
for ii in 0 to 127 loop |
adr:= x"00100000"; |
adr:=adr + ii*4; |
int_mem_write( cmd, ret, adr, x"00000000" ); |
end loop; |
|
|
int_mem_write( cmd, ret, x"00100000", x"00008000" ); |
|
|
|
int_mem_write( cmd, ret, x"00100008", x"00008010" ); |
|
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" ); |
int_mem_write( cmd, ret, x"001001FC", x"D6644953" ); |
|
|
|
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE |
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO |
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL |
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH |
block_write( cmd, ret, 4, 23, x"00019000" ); -- LOCAL_ADR |
|
|
|
|
|
|
|
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START |
|
|
|
|
|
|
|
wait for 20 us; |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
if( data( 8 )='1' ) then |
|
else |
|
error := error + 1; |
end if; |
|
writeline( log, str ); |
|
if( error=0 ) then |
|
|
dma_complete := 0; |
for ii in 0 to 100 loop |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
if( data(5)='1' ) then |
|
dma_complete := 1; |
|
|
|
end if; |
writeline( log, str ); |
|
if( dma_complete=1 ) then |
exit; |
end if; |
|
wait for 1 us; |
|
end loop; |
|
writeline( log, str ); |
|
if( dma_complete=0 ) then |
|
writeline( log, str ); |
error:=error+1; |
end if; |
|
end if; |
|
for ii in 0 to 3 loop |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
writeline( log, str ); |
wait for 500 ns; |
|
end loop; |
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP |
|
|
writeline( log, str ); |
|
for ii in 0 to 15 loop |
|
adr:= x"00800000"; |
adr:=adr + ii*4; |
int_mem_read( cmd, ret, adr, data ); |
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data ); |
writeline( log, str ); |
|
end loop; |
|
writeline( log, str ); |
|
|
writeline( log, str ); |
|
for ii in 0 to 15 loop |
|
adr:= x"00801000"; |
adr:=adr + ii*4; |
int_mem_read( cmd, ret, adr, data ); |
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data ); |
writeline( log, str ); |
|
end loop; |
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO |
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL |
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START |
|
|
writeline( log, str ); |
if( error=0 ) then |
|
cnt_ok := cnt_ok + 1; |
else |
|
cnt_error := cnt_error + 1; |
end if; |
writeline( log, str ); |
writeline( log, str ); |
|
end test_adm_read_8kb; |
|
|
|
procedure test_block_main ( |
|
|
) |
is |
|
variable adr : std_logic_vector( 31 downto 0 ); |
variable data : std_logic_vector( 31 downto 0 ); |
variable str : line; |
|
variable error : integer:=0; |
variable dma_complete : integer; |
|
begin |
|
write( str, string'("TEST_BLOCK_MAIN" )); |
writeline( log, str ); |
|
block_read( cmd, ret, 4, 16#00#, data ); |
|
|
wait for 10 us; |
|
|
-- writeline( log, str ); |
-- for ii in 0 to 5 loop |
|
-- write( str, ii ); |
-- for jj in 0 to 7 loop |
-- block_read( cmd, ret, ii, jj, data ); |
-- write( str, " " ); |
-- hwrite( str, data ); |
-- end loop; |
-- writeline( log, str ); |
-- end loop; |
-- |
-- |
-- writeline( log, str ); |
-- |
-- block_read( cmd, ret, 0, 16#10#, data ); |
-- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str ); |
-- |
-- block_write( cmd, ret, 80, 16#08#, x"00000100" ); |
-- |
-- block_read( cmd, ret, 0, 16#10#, data ); |
-- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str ); |
-- |
-- block_write( cmd, ret, 80, 16#08#, x"00000200" ); |
-- |
-- block_read( cmd, ret, 0, 16#10#, data ); |
-- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str ); |
-- |
-- |
-- writeline( log, str ); |
-- if( error=0 ) then |
|
-- cnt_ok := cnt_ok + 1; |
-- else |
|
-- cnt_error := cnt_error + 1; |
-- end if; |
|
for ii in 0 to 127 loop |
|
block_write( cmd, ret, 4, 16#08#, x"0000AA55" ); |
block_read( cmd, ret, 4, 8, data ); |
write( str, string'("READ: " )); hwrite( str, data( 15 downto 0 ) ); writeline( log, str ); |
if( data/=x"0000AA55" ) then |
error:=error+1; |
end if; |
|
end loop; |
|
|
|
|
writeline( log, str ); |
writeline( log, str ); |
|
end test_block_main; |
|
|
|
|
|
procedure test_adm_read_16kb ( |
|
|
) |
is |
|
variable adr : std_logic_vector( 31 downto 0 ); |
variable data : std_logic_vector( 31 downto 0 ); |
variable str : line; |
|
variable error : integer:=0; |
variable dma_complete : integer; |
variable kk : integer; |
variable status : std_logic_vector( 15 downto 0 ); |
|
begin |
|
write( str, string'("TEST_ADM_READ_16KB" )); |
writeline( log, str ); |
|
|
for ii in 0 to 256 loop |
adr:= x"00100000"; |
adr:=adr + ii*4; |
int_mem_write( cmd, ret, adr, x"00000000" ); |
end loop; |
|
|
|
|
int_mem_write( cmd, ret, x"00100000", x"00008000" ); |
|
|
|
int_mem_write( cmd, ret, x"00100008", x"00008010" ); |
|
|
|
|
int_mem_write( cmd, ret, x"00100014", x"00000000" ); |
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" ); |
int_mem_write( cmd, ret, x"001001FC", x"14644953" ); |
|
|
|
|
|
int_mem_write( cmd, ret, x"00100200", x"00008020" ); |
|
|
|
int_mem_write( cmd, ret, x"00100208", x"00008030" ); |
|
|
|
int_mem_write( cmd, ret, x"001003F8", x"00000000" ); |
int_mem_write( cmd, ret, x"001003FC", x"D67C4953" ); |
|
|
|
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE |
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO |
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL |
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH |
block_write( cmd, ret, 4, 23, x"00019000" ); -- LOCAL_ADR |
|
|
|
|
|
|
|
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START |
|
|
|
|
|
|
|
wait for 20 us; |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
if( data( 8 )='1' ) then |
|
else |
|
error := error + 1; |
end if; |
|
writeline( log, str ); |
|
if( error=0 ) then |
|
kk:=0; |
loop |
|
trd_status( cmd, ret, 6, status ); |
write( str, string'("TRD_STATUS: " )); hwrite( str, status ); |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
|
if( data(4)='1' ) then |
|
|
kk:=kk+1; |
if( kk=4 ) then |
exit; |
end if; |
end if; |
writeline( log, str ); |
|
wait for 500 ns; |
|
|
end loop; |
|
|
dma_complete := 0; |
for ii in 0 to 100 loop |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
if( data(5)='1' ) then |
|
dma_complete := 1; |
|
|
|
end if; |
writeline( log, str ); |
|
if( dma_complete=1 ) then |
exit; |
end if; |
|
wait for 1 us; |
|
end loop; |
|
writeline( log, str ); |
|
if( dma_complete=0 ) then |
|
writeline( log, str ); |
error:=error+1; |
end if; |
|
end if; |
|
for ii in 0 to 3 loop |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
writeline( log, str ); |
wait for 500 ns; |
|
end loop; |
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP |
|
|
writeline( log, str ); |
|
for ii in 0 to 15 loop |
|
adr:= x"00800000"; |
adr:=adr + ii*4; |
int_mem_read( cmd, ret, adr, data ); |
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data ); |
writeline( log, str ); |
|
end loop; |
|
writeline( log, str ); |
|
|
writeline( log, str ); |
|
for ii in 0 to 15 loop |
|
adr:= x"00801000"; |
adr:=adr + ii*4; |
int_mem_read( cmd, ret, adr, data ); |
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data ); |
writeline( log, str ); |
|
end loop; |
|
|
writeline( log, str ); |
|
for ii in 0 to 15 loop |
|
adr:= x"00802000"; |
adr:=adr + ii*4; |
int_mem_read( cmd, ret, adr, data ); |
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data ); |
writeline( log, str ); |
|
end loop; |
|
|
|
writeline( log, str ); |
|
for ii in 0 to 15 loop |
|
adr:= x"00803000"; |
adr:=adr + ii*4; |
int_mem_read( cmd, ret, adr, data ); |
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data ); |
writeline( log, str ); |
|
end loop; |
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO |
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL |
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START |
|
|
writeline( log, str ); |
if( error=0 ) then |
|
cnt_ok := cnt_ok + 1; |
else |
|
cnt_error := cnt_error + 1; |
end if; |
writeline( log, str ); |
writeline( log, str ); |
|
end test_adm_read_16kb; |
|
|
|
|
|
procedure test_adm_write_16kb ( |
|
|
) |
is |
|
variable adr : std_logic_vector( 31 downto 0 ); |
variable data : std_logic_vector( 31 downto 0 ); |
variable str : line; |
|
variable error : integer:=0; |
variable dma_complete : integer; |
variable kk : integer; |
variable status : std_logic_vector( 15 downto 0 ); |
|
begin |
|
write( str, string'("TEST_ADM_WRITE_16KB" )); |
writeline( log, str ); |
|
|
for ii in 0 to 256 loop |
adr:= x"00100000"; |
adr:=adr + ii*4; |
int_mem_write( cmd, ret, adr, x"00000000" ); |
end loop; |
|
|
for ii in 0 to 256 loop |
adr:= x"00800000"; |
adr:=adr + ii*4; |
data:=x"00A00000"; |
data:=data + ii; |
int_mem_write( cmd, ret, adr, data ); |
end loop; |
|
for ii in 0 to 1023 loop |
adr:= x"00801000"; |
adr:=adr + ii*4; |
data:=x"00A10000"; |
data:=data + ii; |
int_mem_write( cmd, ret, adr, data ); |
end loop; |
|
for ii in 0 to 256 loop |
adr:= x"00802000"; |
adr:=adr + ii*4; |
data:=x"00A20000"; |
data:=data + ii; |
int_mem_write( cmd, ret, adr, data ); |
end loop; |
|
for ii in 0 to 256 loop |
adr:= x"00803000"; |
adr:=adr + ii*4; |
data:=x"00A30000"; |
data:=data + ii; |
int_mem_write( cmd, ret, adr, data ); |
end loop; |
|
|
|
|
int_mem_write( cmd, ret, x"00100000", x"00008000" ); |
|
|
|
int_mem_write( cmd, ret, x"00100008", x"00008010" ); |
|
|
|
|
int_mem_write( cmd, ret, x"00100014", x"00000000" ); |
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" ); |
int_mem_write( cmd, ret, x"001001FC", x"14A44953" ); |
|
|
|
|
|
int_mem_write( cmd, ret, x"00100200", x"00008020" ); |
|
|
|
int_mem_write( cmd, ret, x"00100208", x"00008030" ); |
|
|
|
int_mem_write( cmd, ret, x"001003F8", x"00000000" ); |
int_mem_write( cmd, ret, x"001003FC", x"D6BC4953" ); |
|
|
|
|
block_write( cmd, ret, 4, 8, x"00000023" ); -- DMA_MODE |
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO |
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL |
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH |
block_write( cmd, ret, 4, 23, x"0001D000" ); -- LOCAL_ADR |
|
|
|
|
|
|
|
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START |
|
|
|
|
|
|
|
wait for 20 us; |
|
|
for ii in 0 to 20 loop |
block_read( cmd, ret, 4, 16, data ); -- STATUS |
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
if( data( 8 )='1' ) then |
|
error := 0; |
exit; |
else |
|
error := error + 1; |
wait for 10 us; |
end if; |
|
writeline( log, str ); |
end loop; |
|
|
if( error=0 ) then |
|
kk:=0; |
loop |
|
trd_status( cmd, ret, 6, status ); |
write( str, string'("TRD_STATUS: " )); hwrite( str, status ); |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
|
if( data(4)='1' ) then |
|
|
kk:=kk+1; |
if( kk=4 ) then |
exit; |
end if; |
end if; |
writeline( log, str ); |
|
wait for 500 ns; |
|
|
end loop; |
|
|
dma_complete := 0; |
for ii in 0 to 100 loop |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
if( data(5)='1' ) then |
|
dma_complete := 1; |
|
|
|
end if; |
writeline( log, str ); |
|
if( dma_complete=1 ) then |
exit; |
end if; |
|
wait for 1 us; |
|
end loop; |
|
writeline( log, str ); |
|
if( dma_complete=0 ) then |
|
writeline( log, str ); |
error:=error+1; |
end if; |
|
end if; |
|
for ii in 0 to 3 loop |
|
block_read( cmd, ret, 4, 16, data ); -- STATUS |
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) ); |
writeline( log, str ); |
wait for 500 ns; |
|
end loop; |
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP |
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO |
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL |
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START |
|
|
writeline( log, str ); |
if( error=0 ) then |
|
cnt_ok := cnt_ok + 1; |
else |
|
cnt_error := cnt_error + 1; |
end if; |
writeline( log, str ); |
writeline( log, str ); |
|
end test_adm_write_16kb; |
|
end package body test_pkg; |
|
|
/trunk/projects/ac701_a200t_core/src/testbench/ahdl/run_ahdl.tcl
0,0 → 1,87
# |
# AHDL regression script. |
# |
|
|
# ROOT/TC folders, etc: |
# |
set ROOT [pwd] |
|
set FAIL_MSG "TEST finished with ERR" |
set PASS_MSG "TEST finished successfully" |
|
set glbl_log "src/testbench/log/global_tc_summary.log" |
|
cd $dsn |
|
set glbl_log_file [open $glbl_log w] |
puts $glbl_log_file "Global AMBPEX5_WISHBONE TC log:" |
close $glbl_log_file |
|
# |
# Procedure: |
# |
proc set_and_run {} { |
set StdArithNoWarnings 1 |
set NumericStdNoWarnings 1 |
set BreakOnAssertion 2 |
|
run -all |
|
quit -sim |
} |
|
proc parse_log { filename tc_name } { |
set err_cnt 0 |
set openfile [open $filename r] |
set ret 0 |
while {[gets $openfile buffer] >= 0} { |
|
set ret [string first $::PASS_MSG $buffer 1] |
#echo $ret |
if { $ret>0 } { |
incr err_cnt |
} |
|
} |
if {$err_cnt>0} {return "$tc_name PASSED"} else {return "$tc_name FAILED"} |
close $openfile |
} |
|
proc run_test { tc_name tc_id tc_time } { |
set log_name "src/testbench/log/console_" |
set log_name $log_name$tc_name.log |
|
#set log_test "src\\testbench\\log\\file_" |
#set log_test $log_test$tc_name.log |
|
|
transcript to $log_name |
asim -noglitch -noglitchmsg +notimingchecks +no_tchk_msg -relax glbl -ieee_nowarn -O5 -L secureip -g test_id=$tc_id +access +r +m+$tc_name stend_ambpex5_wishbone stend_ambpex5_wishbone |
#asim -ieee_nowarn -g test_id=$tc_id -g test_log=$log_test +access +r +m+$tc_name stend_sp605_wishbone stend_sp605_wishbone |
run $tc_time |
endsim; |
|
set glog_file [open $::glbl_log a] |
puts $glog_file [parse_log $log_name $tc_name ] |
close $glog_file |
|
} |
|
# |
# Main BODY: |
# |
|
# |
# |
cd $dsn |
|
# |
# |
onerror {resume} |
|
#run_test "test_dsc_incorrect" 0 "300 us" |
#run_test "test_read_4kB" 1 "300 us" |
run_test "test_adm_read_8kb" 2 "350 us" |
|
exit |
/trunk/projects/ac701_a200t_core/src/top/ac701_a200t_core.vhd
0,0 → 1,565
------------------------------------------------------------------------------- |
-- |
-- Title : ac701_a200t_core |
-- Author : Dmitry Smekhov |
-- Company : Instrumental Systems |
-- E-mail : dsmv@insys.ru |
-- |
-- Version : 1.0 |
-- |
------------------------------------------------------------------------------- |
-- |
|
-- |
------------------------------------------------------------------------------- |
-- |
-- Version 1.0 17.02.2014 |
|
-- |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
package ac701_a200t_core_pkg is |
|
component ac701_a200t_core is |
generic ( |
|
); |
port( |
---- PCI-Express ---- |
pci_exp_txp : out std_logic_vector(3 downto 0); |
pci_exp_txn : out std_logic_vector(3 downto 0); |
pci_exp_rxp : in std_logic_vector(3 downto 0); |
pci_exp_rxn : in std_logic_vector(3 downto 0); |
|
sys_clk_p : in std_logic; |
sys_clk_n : in std_logic; |
sys_reset_n : in std_logic; |
|
|
gpio_led0 : out std_logic; |
gpio_led1 : out std_logic; |
gpio_led2 : out std_logic; |
gpio_led3 : out std_logic; |
gpio_led4 : out std_logic |
|
); |
end component; |
|
end package; |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
|
library unisim; |
use unisim.vcomponents.all; |
|
|
use work.adm2_pkg.all; |
use work.cl_ac701_pkg.all; |
use work.trd_main_v8_pkg.all; |
use work.trd_pio_std_v4_pkg.all; |
use work.trd_admdio64_out_v4_pkg.all; |
use work.trd_admdio64_in_v6_pkg.all; |
use work.trd_test_ctrl_m1_pkg.all; |
|
|
entity ac701_a200t_core is |
generic ( |
|
); |
port( |
---- PCI-Express ---- |
pci_exp_txp : out std_logic_vector(3 downto 0); |
pci_exp_txn : out std_logic_vector(3 downto 0); |
pci_exp_rxp : in std_logic_vector(3 downto 0); |
pci_exp_rxn : in std_logic_vector(3 downto 0); |
|
sys_clk_p : in std_logic; |
sys_clk_n : in std_logic; |
sys_reset_n : in std_logic; |
|
|
gpio_led0 : out std_logic; |
gpio_led1 : out std_logic; |
gpio_led2 : out std_logic; |
gpio_led3 : out std_logic; |
gpio_led4 : out std_logic |
|
); |
end ac701_a200t_core; |
|
|
architecture ac701_a200t_core of ac701_a200t_core is |
|
|
|
|
signal clk : std_logic; |
|
|
signal reset_main : std_logic; |
|
|
signal reset : std_logic; |
|
|
signal trd_host_adr : std_logic_vector( 31 downto 0 ):=(others=>'0'); |
|
|
signal trd_host_data : std_logic_array_16x64; |
|
|
signal trd_host_cmd_data : std_logic_array_16x16; |
|
|
signal trd_host_cmd : std_logic_array_16xbl_cmd; |
|
|
signal trd_data : std_logic_array_16x64:=(others=>(others=>'0')); |
|
|
signal trd_cmd_data : std_logic_array_16x16:=(others=>(others=>'1')); |
|
|
signal trd_drq : std_logic_array_16xbl_drq:=(others=>(others=>'0')); |
|
|
signal trd_irq : std_logic_array_16xbl_irq:=(others=>'0'); |
|
|
signal trd_reset_fifo : std_logic_array_16xbl_reset_fifo:=(others=>'0'); |
|
|
signal trd_main_drq : std_logic_array_16xbl_drq:=(others=>(others=>'0')); |
|
|
signal trd_main_irq : std_logic_array_16xbl_irq:=(others=>'0'); |
|
|
signal trd_main_sel_drq : std_logic_array_16x6:=(others=>(others=>'0')); |
|
signal test_mode : std_logic; |
|
|
signal trd_trd_cmd : std_logic_array_16xbl_cmd; |
|
|
signal trd_flag_rd : std_logic_array_16xbl_fifo_flag; |
|
|
signal di_mode1 : std_logic_vector( 15 downto 0 ); |
signal di_data : std_logic_vector( 63 downto 0 ); |
signal di_data_we : std_logic; |
signal di_flag_wr : bl_fifo_flag; |
signal di_start : std_logic; |
signal di_fifo_rst : std_logic; |
signal di_clk : std_logic; |
|
signal do_mode1 : std_logic_vector( 15 downto 0 ); |
signal do_data : std_logic_vector( 63 downto 0 ); |
signal do_data_cs : std_logic; |
signal do_flag_rd : bl_fifo_flag; |
signal do_start : std_logic; |
signal do_fifo_rst : std_logic; |
signal do_clk : std_logic; |
|
signal clk200 : std_logic; |
signal freq0 : std_logic; |
signal freq1 : std_logic; |
signal freq2 : std_logic; |
|
signal led_h1 : std_logic; |
signal led_h2 : std_logic; |
signal led_h3 : std_logic; |
signal led_h4 : std_logic; |
|
signal led_h1_p : std_logic; |
signal led_h2_p : std_logic; |
signal led_h3_p : std_logic; |
signal led_h4_p : std_logic; |
|
|
signal tp1 : std_logic; |
signal tp2 : std_logic; |
signal tp3 : std_logic; |
|
signal px : std_logic_vector( 3 downto 1 ); |
|
signal clk30k : std_logic; |
|
|
constant rom_main: bl_trd_rom:= |
( |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
31 downto 21 => x"0000" ); |
|
|
constant rom_dio_in: bl_trd_rom:= |
( |
|
|
|
|
|
|
|
|
|
|
constant rom_dio_out: bl_trd_rom:= |
( |
|
|
|
|
|
|
|
|
|
|
|
constant rom_test_ctrl: bl_trd_rom:= |
( |
|
|
|
|
|
|
|
|
|
|
|
constant trd_rom : std_logic_array_16xbl_trd_rom := |
( |
0 => rom_main, |
1 => rom_test_ctrl, |
2 => rom_empty, |
3 => rom_empty, |
4 => rom_empty, |
5 => rom_empty, |
6 => rom_dio_in, |
7 => rom_dio_out, |
others=> rom_empty ); |
|
begin |
|
xled0: obuf_s_16 port map( gpio_led0, '1' ); |
xled1: obuf_s_16 port map( gpio_led1, led_h1_p ); |
xled2: obuf_s_16 port map( gpio_led2, led_h2_p ); |
xled3: obuf_s_16 port map( gpio_led3, led_h3_p ); |
xled4: obuf_s_16 port map( gpio_led4, led_h4_p ); |
|
led_h1_p <= not led_h1; |
led_h2_p <= not led_h2; |
led_h3_p <= not led_h3; |
led_h4_p <= not led_h4; |
|
|
tp1 <= not tp1 when rising_edge( clk ); |
tp2 <= px(2); |
tp3 <= clk30k; |
|
--btp1: obuf_f_16 port map( btp(1), tp1 ); |
--btp2: obuf_f_16 port map( btp(2), tp2 ); |
--btp3: obuf_f_16 port map( btp(3), tp3 ); |
-- |
|
|
|
amb: cl_ac701 |
generic map( |
|
|
|
|
trd_rom => trd_rom, |
|
trd_in => "0000000001000001", |
|
trd_st => "0000000011000011", |
|
|
) |
port map( |
---- PCI-Express ---- |
txp => pci_exp_txp, |
txn => pci_exp_txn, |
|
rxp => pci_exp_rxp, |
rxn => pci_exp_rxn, |
|
|
mgt100_n => sys_clk_n, |
|
|
|
|
p => px, |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
trd_host_adr => trd_host_adr( 15 downto 0 ), |
|
|
trd_host_data => trd_host_data, |
|
|
trd_host_cmd_data=>trd_host_cmd_data, |
|
|
trd_host_cmd => trd_host_cmd, |
|
|
trd_data => trd_data, |
|
|
trd_cmd_data => trd_cmd_data, |
|
|
trd_drq => trd_drq, |
|
|
trd_main_drq => trd_main_drq, |
|
|
trd_main_sel_drq=> trd_main_sel_drq, |
|
|
trd_reset_fifo => trd_reset_fifo, |
|
|
trd_main_irq => trd_main_irq |
|
); |
|
|
|
main: trd_main_v8 |
port map |
( |
|
-- GLOBAL |
reset => reset_main, |
clk => clk, |
|
-- T0 |
adr_in => trd_host_adr( 6 downto 0 ), |
data_in => trd_host_data(0), |
cmd_data_in => trd_host_cmd_data(0), |
|
cmd => trd_host_cmd(0), |
|
data_out => trd_data(0), |
cmd_data_out => trd_cmd_data(0), |
|
|
|
test_mode => test_mode, |
test_mode_init => '1', |
|
b1_irq => trd_irq(1), |
b2_irq => trd_irq(2), |
b3_irq => trd_irq(3), |
b4_irq => trd_irq(4), |
b5_irq => trd_irq(5), |
b6_irq => trd_irq(6), |
b7_irq => trd_irq(7), |
|
|
b1_drq => trd_drq(1), |
b2_drq => trd_drq(2), |
b3_drq => trd_drq(3), |
b4_drq => trd_drq(4), |
b5_drq => trd_drq(5), |
b6_drq => trd_drq(6), |
b7_drq => trd_drq(7), |
|
|
int1 => trd_main_irq(1), |
|
drq0 => trd_main_drq(0), |
drq1 => trd_main_drq(1), |
drq2 => trd_main_drq(2), |
drq3 => trd_main_drq(3), |
|
reset_out => reset, |
|
fifo_rst_out => trd_reset_fifo(0), |
|
|
b_clk => (others=>'0'), |
|
b_start => (others=>'0'), |
|
-- SYNX |
sn_rdy0 => '0', |
sn_rdy1 => '0', |
sn_start_en => '0', |
sn_sync0 => '0' |
|
); |
|
|
|
|
|
dio_in: trd_admdio64_in_v6 |
port map( |
-- GLOBAL |
|
|
|
|
cmd_data_in => trd_host_cmd_data(6), |
cmd => trd_host_cmd(6), |
|
data_out2 => trd_data(6), |
cmd_data_out2 => trd_cmd_data(6), |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
); |
|
trd_reset_fifo(6) <= di_fifo_rst; |
|
|
|
dio_out: trd_admdio64_out_v4 |
port map( |
|
-- GLOBAL |
|
|
|
|
data_in => trd_host_data(7), |
cmd_data_in => trd_host_cmd_data(7), |
|
cmd => trd_host_cmd(7), |
|
cmd_data_out2 => trd_cmd_data(7), |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
); |
|
trd_reset_fifo(7) <= do_fifo_rst; |
|
freq0 <= clk; |
freq1 <= '0'; |
freq2 <= '0'; |
|
|
test_ctrl: trd_test_ctrl_m1 |
generic map( |
|
) |
port map( |
-- GLOBAL |
|
|
|
|
cmd_data_in => trd_host_cmd_data(1), |
|
cmd => trd_host_cmd(1), |
|
cmd_data_out2 => trd_cmd_data(1), |
|
|
|
|
|
---- DIO_IN ---- |
|
|
|
|
|
|
|
|
---- DIO_OUT ---- |
|
|
|
|
|
|
|
|
|
|
|
|
|
); |
|
|
end ac701_a200t_core; |