URL
https://opencores.org/ocsvn/pcie_mini/pcie_mini/trunk
Subversion Repositories pcie_mini
Compare Revisions
- This comparison shows the changes necessary to convert path
/pcie_mini/trunk/example_design
- from Rev 3 to Rev 8
- ↔ Reverse comparison
Rev 3 → Rev 8
/xilinx_pcie2wb.vhd
3,10 → 3,10
-- Engineer: Istvan Nagy, buenos@freemail.hu |
-- |
-- Create Date: 05/30/2010 |
-- Modify date: 04/26/2011 |
-- Modify date: 08/10/2012 |
-- Design Name: pcie_mini |
-- Module Name: xilinx_pcie2wb - Behavioral |
-- Version: 1.1 |
-- Version: 1.2 |
-- Project Name: |
-- Target Devices: Xilinx Series-5/6/7 FPGAs |
-- Tool versions: ISE-DS 12.1 |
43,10 → 43,12
-- Synthesis: Set the "FSM Encoding Algorithm" to "user". |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
|
-- Revision 1.0 - File Created by Istvan Nagy |
-- Revision 1.1 - some fixes by Istvan Nagy |
-- Revision 1.2 - interrupt fix by Stephen Battazzo |
-- |
---------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
208,6 → 210,9
SIGNAL txtlp_data_7 : std_logic_vector(31 downto 0); |
SIGNAL pcie_tlp_tx_complete : std_logic; |
|
--this signal added by StBa, AAC Microtec |
SIGNAL irq_prohibit : std_logic; |
|
SIGNAL pcieirq_state : std_logic_vector(7 downto 0); |
SIGNAL txtrn_counter : std_logic_vector(7 downto 0); |
SIGNAL trn_rx_counter : std_logic_vector(7 downto 0); |
258,91 → 263,92
--Release Date: September 16, 2009. ISE DS 11.4 |
component pcie is |
generic ( |
TL_TX_RAM_RADDR_LATENCY : integer := 0; |
TL_TX_RAM_RDATA_LATENCY : integer := 2; |
TL_RX_RAM_RADDR_LATENCY : integer := 0; |
TL_RX_RAM_RDATA_LATENCY : integer := 2; |
TL_RX_RAM_WRITE_LATENCY : integer := 0; |
VC0_TX_LASTPACKET : integer := 14; |
VC0_RX_RAM_LIMIT : bit_vector := x"7FF"; |
VC0_TOTAL_CREDITS_PH : integer := 32; |
VC0_TOTAL_CREDITS_PD : integer := 211; |
VC0_TOTAL_CREDITS_NPH : integer := 8; |
VC0_TOTAL_CREDITS_CH : integer := 40; |
VC0_TOTAL_CREDITS_CD : integer := 211; |
VC0_CPL_INFINITE : boolean := TRUE; |
BAR0 : bit_vector := x"F0000000"; |
BAR1 : bit_vector := x"00000000"; |
BAR2 : bit_vector := x"00000000"; |
BAR3 : bit_vector := x"00000000"; |
BAR4 : bit_vector := x"00000000"; |
BAR5 : bit_vector := x"00000000"; |
EXPANSION_ROM : bit_vector := "0000000000000000000000"; |
DISABLE_BAR_FILTERING : boolean := FALSE; |
DISABLE_ID_CHECK : boolean := FALSE; |
TL_TFC_DISABLE : boolean := FALSE; |
TL_TX_CHECKS_DISABLE : boolean := FALSE; |
USR_CFG : boolean := FALSE; |
USR_EXT_CFG : boolean := FALSE; |
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2; |
CLASS_CODE : bit_vector := x"068000"; |
CARDBUS_CIS_POINTER : bit_vector := x"00000000"; |
PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1"; |
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"1"; |
PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE; |
PCIE_CAP_INT_MSG_NUM : bit_vector := "00000"; |
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0; |
DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE; |
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7; |
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7; |
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE; |
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE; |
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE; |
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE; |
LINK_CAP_ASPM_SUPPORT : integer := 1; |
LINK_CAP_L0S_EXIT_LATENCY : integer := 7; |
LINK_CAP_L1_EXIT_LATENCY : integer := 7; |
LL_ACK_TIMEOUT : bit_vector := x"0204"; |
LL_ACK_TIMEOUT_EN : boolean := FALSE; |
LL_REPLAY_TIMEOUT : bit_vector := x"0204"; |
LL_REPLAY_TIMEOUT_EN : boolean := FALSE; |
MSI_CAP_MULTIMSGCAP : integer := 0; |
MSI_CAP_MULTIMSG_EXTENSION : integer := 0; |
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE; |
PLM_AUTO_CONFIG : boolean := FALSE; |
FAST_TRAIN : boolean := FALSE; |
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE; |
DISABLE_SCRAMBLING : boolean := FALSE; |
PM_CAP_VERSION : integer := 3; |
PM_CAP_PME_CLOCK : boolean := FALSE; |
PM_CAP_DSI : boolean := FALSE; |
PM_CAP_AUXCURRENT : integer := 0; |
PM_CAP_D1SUPPORT : boolean := TRUE; |
PM_CAP_D2SUPPORT : boolean := TRUE; |
PM_CAP_PMESUPPORT : bit_vector := x"0F"; |
PM_DATA0 : bit_vector := x"04"; |
PM_DATA_SCALE0 : bit_vector := x"0"; |
PM_DATA1 : bit_vector := x"00"; |
PM_DATA_SCALE1 : bit_vector := x"0"; |
PM_DATA2 : bit_vector := x"00"; |
PM_DATA_SCALE2 : bit_vector := x"0"; |
PM_DATA3 : bit_vector := x"00"; |
PM_DATA_SCALE3 : bit_vector := x"0"; |
PM_DATA4 : bit_vector := x"04"; |
PM_DATA_SCALE4 : bit_vector := x"0"; |
PM_DATA5 : bit_vector := x"00"; |
PM_DATA_SCALE5 : bit_vector := x"0"; |
PM_DATA6 : bit_vector := x"00"; |
PM_DATA_SCALE6 : bit_vector := x"0"; |
PM_DATA7 : bit_vector := x"00"; |
PM_DATA_SCALE7 : bit_vector := x"0"; |
PCIE_GENERIC : bit_vector := "000011101111"; |
GTP_SEL : integer := 0; |
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE"; |
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"ABCD"; |
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00"; |
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE"; |
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234"; |
TL_TX_RAM_RADDR_LATENCY : integer := 0; |
TL_TX_RAM_RDATA_LATENCY : integer := 2; |
TL_RX_RAM_RADDR_LATENCY : integer := 0; |
TL_RX_RAM_RDATA_LATENCY : integer := 2; |
TL_RX_RAM_WRITE_LATENCY : integer := 0; |
VC0_TX_LASTPACKET : integer := 14; |
VC0_RX_RAM_LIMIT : bit_vector := x"7FF"; |
VC0_TOTAL_CREDITS_PH : integer := 32; |
VC0_TOTAL_CREDITS_PD : integer := 211; |
VC0_TOTAL_CREDITS_NPH : integer := 8; |
VC0_TOTAL_CREDITS_CH : integer := 40; |
VC0_TOTAL_CREDITS_CD : integer := 211; |
VC0_CPL_INFINITE : boolean := TRUE; |
BAR0 : bit_vector := x"F0000000"; |
BAR1 : bit_vector := x"00000000"; |
BAR2 : bit_vector := x"00000000"; |
BAR3 : bit_vector := x"00000000"; |
BAR4 : bit_vector := x"00000000"; |
BAR5 : bit_vector := x"00000000"; |
EXPANSION_ROM : bit_vector := "0000000000000000000000"; |
DISABLE_BAR_FILTERING : boolean := FALSE; |
DISABLE_ID_CHECK : boolean := FALSE; |
TL_TFC_DISABLE : boolean := FALSE; |
TL_TX_CHECKS_DISABLE : boolean := FALSE; |
USR_CFG : boolean := FALSE; |
USR_EXT_CFG : boolean := FALSE; |
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2; |
CLASS_CODE : bit_vector := x"068000"; |
CARDBUS_CIS_POINTER : bit_vector := x"00000000"; |
PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1"; |
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"1"; |
PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE; |
PCIE_CAP_INT_MSG_NUM : bit_vector := "00000"; |
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0; |
DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE; |
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7; |
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7; |
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE; |
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE; |
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE; |
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE; |
LINK_CAP_ASPM_SUPPORT : integer := 1; |
--LINK_CAP_L0S_EXIT_LATENCY : integer := 7; |
--LINK_CAP_L1_EXIT_LATENCY : integer := 7; |
LL_ACK_TIMEOUT : bit_vector := x"0000"; |
LL_ACK_TIMEOUT_EN : boolean := FALSE; |
--LL_REPLAY_TIMEOUT : bit_vector := x"0204"; |
LL_REPLAY_TIMEOUT : bit_vector := x"0000"; |
LL_REPLAY_TIMEOUT_EN : boolean := FALSE; |
MSI_CAP_MULTIMSGCAP : integer := 0; |
MSI_CAP_MULTIMSG_EXTENSION : integer := 0; |
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE; |
PLM_AUTO_CONFIG : boolean := FALSE; |
FAST_TRAIN : boolean := FALSE; |
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE; |
DISABLE_SCRAMBLING : boolean := FALSE; |
PM_CAP_VERSION : integer := 3; |
PM_CAP_PME_CLOCK : boolean := FALSE; |
PM_CAP_DSI : boolean := FALSE; |
PM_CAP_AUXCURRENT : integer := 0; |
PM_CAP_D1SUPPORT : boolean := TRUE; |
PM_CAP_D2SUPPORT : boolean := TRUE; |
PM_CAP_PMESUPPORT : bit_vector := x"0F"; |
PM_DATA0 : bit_vector := x"04"; |
PM_DATA_SCALE0 : bit_vector := x"0"; |
PM_DATA1 : bit_vector := x"00"; |
PM_DATA_SCALE1 : bit_vector := x"0"; |
PM_DATA2 : bit_vector := x"00"; |
PM_DATA_SCALE2 : bit_vector := x"0"; |
PM_DATA3 : bit_vector := x"00"; |
PM_DATA_SCALE3 : bit_vector := x"0"; |
PM_DATA4 : bit_vector := x"04"; |
PM_DATA_SCALE4 : bit_vector := x"0"; |
PM_DATA5 : bit_vector := x"00"; |
PM_DATA_SCALE5 : bit_vector := x"0"; |
PM_DATA6 : bit_vector := x"00"; |
PM_DATA_SCALE6 : bit_vector := x"0"; |
PM_DATA7 : bit_vector := x"00"; |
PM_DATA_SCALE7 : bit_vector := x"0"; |
PCIE_GENERIC : bit_vector := "000011101111"; |
GTP_SEL : integer := 0; |
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE"; |
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"BADD"; |
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00"; |
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE"; |
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234"; |
REF_CLK_FREQ : integer := 0 |
); |
port ( |
448,11 → 454,13
|
|
---- ------- SYNTHESIS ATTRIBUTES: -------------------------------------------------- |
--attribute keep_hierarchy : string; |
--attribute keep_hierarchy : string; |
--attribute keep_hierarchy of xilinx_pcie2wb: entity is "yes"; |
attribute keep : string; |
attribute keep of cfg_dstatus : signal is "true"; |
attribute keep of tlp_state : signal is "true"; |
|
|
|
-- --------ARCHITECTURE BODY BEGINS ----------------------------------------------- |
begin |
|
541,26 → 549,26
received_hot_reset => received_hot_reset |
); |
|
--block ram for RX TLP: |
Inst_bram_rxtlp: blk_mem_gen_v4_1 PORT MAP( |
clka => trn_clk, |
wea => bram_rxtlp_we, |
addra => bram_rxtlp_writeaddress(8 downto 0), |
dina => bram_rxtlp_writedata, |
clkb => trn_clk, |
addrb => bram_rxtlp_readaddress(8 downto 0), |
doutb => bram_rxtlp_readdata |
); |
|
--block ram for TX TLP: |
Inst_bram_txtlp: blk_mem_gen_v4_1 PORT MAP( |
clka => trn_clk, |
wea => bram_txtlp_we, |
addra => bram_txtlp_writeaddress(8 downto 0), |
dina => bram_txtlp_writedata, |
clkb => trn_clk, |
addrb => bram_txtlp_readaddress(8 downto 0), |
doutb => bram_txtlp_readdata |
--block ram for RX TLP: |
Inst_bram_rxtlp: blk_mem_gen_v4_1 PORT MAP( |
clka => trn_clk, |
wea => bram_rxtlp_we, |
addra => bram_rxtlp_writeaddress(8 downto 0), |
dina => bram_rxtlp_writedata, |
clkb => trn_clk, |
addrb => bram_rxtlp_readaddress(8 downto 0), |
doutb => bram_rxtlp_readdata |
); |
|
--block ram for TX TLP: |
Inst_bram_txtlp: blk_mem_gen_v4_1 PORT MAP( |
clka => trn_clk, |
wea => bram_txtlp_we, |
addra => bram_txtlp_writeaddress(8 downto 0), |
dina => bram_txtlp_writedata, |
clkb => trn_clk, |
addrb => bram_txtlp_readaddress(8 downto 0), |
doutb => bram_txtlp_readdata |
); |
|
|
574,15 → 582,15
--System Signals:-------------------------------- |
|
--Clock Input Buffer for differential system clock |
IBUFDS_inst : IBUFDS |
generic map ( |
DIFF_TERM => TRUE, -- Differential Termination |
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards |
IOSTANDARD => "DEFAULT") |
port map ( |
O => sys_clk, -- Buffer output |
I => sys_clk_p, -- Diff_p buffer input (connect directly to top-level port) |
IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port) |
IBUFDS_inst : IBUFDS |
generic map ( |
DIFF_TERM => TRUE, -- Differential Termination |
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards |
IOSTANDARD => "DEFAULT") |
port map ( |
O => sys_clk, -- Buffer output |
I => sys_clk_p, -- Diff_p buffer input (connect directly to top-level port) |
IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port) |
); |
|
--wishbone clock output: |
1033,9 → 1041,9
rxtlp_requesterid <= (others => '0'); |
tlp_state <= (others => '0'); |
tlp_state_copy <= (others => '0'); |
bram_txtlp_we <= "0"; |
bram_txtlp_writeaddress <= (others => '0'); |
bram_txtlp_writedata <= (others => '0'); |
bram_txtlp_we <= "0"; |
bram_txtlp_writeaddress <= (others => '0'); |
bram_txtlp_writedata <= (others => '0'); |
bram_rxtlp_readaddress <= (others => '0'); |
rxtlp_header_dw1 <= "01111111000000000000000000000000"; |
rxtlp_header_dw2 <= (others => '0'); |
1062,8 → 1070,8
start_write_wb0 <= '0'; |
start_read_wb0 <= '0'; |
tlp_state_copy <= tlp_state; |
bram_txtlp_we <= "0"; |
bram_txtlp_writeaddress <= (others => '0'); |
bram_txtlp_we <= "0"; |
bram_txtlp_writeaddress <= (others => '0'); |
bram_txtlp_writedata <= (others => '0'); |
bram_rxtlp_readaddress <= (others => '0'); |
tlp_datacount <= "00000001"; |
1206,8 → 1214,8
tlp_state <= "00000100"; |
bram_txtlp_writeaddress <= (OTHERS => '0'); |
--pre-write header-DW1: |
bram_txtlp_writedata (31) <= flag1; --reserved |
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion |
bram_txtlp_writedata (31) <= flag1; --reserved |
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion |
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0); |
--Calculate completion header's "rcompl_bytecount_field" from rxtlp_firstdw_be, rxtlp_lastdw_be, tlp_payloadsize_dwords |
if (rxtlp_lastdw_be="0000") then --max 1DW |
1233,17 → 1241,17
tlp_state_copy <= tlp_state; |
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1; |
if (bram_txtlp_writeaddress="000000000") then --if address is 0: launch data for next lock/address(1): header-2.dw |
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID |
bram_txtlp_writedata (15 downto 13) <= "000"; --status= succesful*** |
bram_txtlp_writedata (12) <= '0'; --reserved |
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID |
bram_txtlp_writedata (15 downto 13) <= "000"; --status= succesful*** |
bram_txtlp_writedata (12) <= '0'; --reserved |
bram_txtlp_writedata (11 downto 10) <= "00"; |
bram_txtlp_writedata (9 downto 0) <= rcompl_bytecount_field; --total bytes returned |
bram_txtlp_we <= "1"; |
bram_txtlp_we <= "1"; |
elsif (bram_txtlp_writeaddress="000000001") then --if address is 1: launch data for next lock/address(2): header-3.dw |
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID |
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag |
bram_txtlp_writedata (7) <= '0'; --reserved |
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address |
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID |
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag |
bram_txtlp_writedata (7) <= '0'; --reserved |
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address |
bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0); --lower address |
else --data dwords, disable writes from next clock cycle |
bram_txtlp_we <= "0"; |
1267,23 → 1275,23
tlp_payloadsize_dwords <= "00000000"; |
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1; |
--assembling the TLP packet: ) |
if (bram_txtlp_writeaddress="111111111") then --header 1.dw |
bram_txtlp_we <= "1"; |
bram_txtlp_writedata (31) <= flag1; --reserved |
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion |
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0); |
elsif (bram_txtlp_writeaddress="000000000") then --header 2.dw |
bram_txtlp_we <= "1"; |
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID |
bram_txtlp_writedata (15 downto 13) <= "000"; --status= UNSUPPORTED REQUEST *** |
bram_txtlp_writedata (12) <= '0'; --reserved |
bram_txtlp_writedata (11 downto 0) <= "000000000000"; --remaining byte count |
elsif (bram_txtlp_writeaddress="000000001") then --header 3.dw |
bram_txtlp_we <= "1"; |
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID |
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag |
bram_txtlp_writedata (7) <= '0'; --reserved |
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address |
if (bram_txtlp_writeaddress="111111111") then --header 1.dw |
bram_txtlp_we <= "1"; |
bram_txtlp_writedata (31) <= flag1; --reserved |
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion |
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0); |
elsif (bram_txtlp_writeaddress="000000000") then --header 2.dw |
bram_txtlp_we <= "1"; |
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID |
bram_txtlp_writedata (15 downto 13) <= "000"; --status= UNSUPPORTED REQUEST *** |
bram_txtlp_writedata (12) <= '0'; --reserved |
bram_txtlp_writedata (11 downto 0) <= "000000000000"; --remaining byte count |
elsif (bram_txtlp_writeaddress="000000001") then --header 3.dw |
bram_txtlp_we <= "1"; |
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID |
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag |
bram_txtlp_writedata (7) <= '0'; --reserved |
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address |
bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0); --lower address |
else --data dwords |
bram_txtlp_we <= "0"; |
1312,29 → 1320,29
|
--byte enable encoding to wb_address bit1:0 |
--this does not swap the endian, since only the data is swapped in the pcie packets. |
process ( pciewb_localreset_n, rxtlp_firstdw_be ) |
begin |
if (pciewb_localreset_n = '0') then |
bit10(1 downto 0) <="00"; |
else |
if (rxtlp_firstdw_be ="0001") then |
bit10(1 downto 0) <= "00"; |
elsif (rxtlp_firstdw_be ="0010") then |
bit10(1 downto 0) <= "01"; |
elsif (rxtlp_firstdw_be ="0100") then |
bit10(1 downto 0) <= "10"; |
elsif (rxtlp_firstdw_be ="1000") then |
bit10(1 downto 0) <= "11"; |
elsif (rxtlp_firstdw_be ="0011") then |
bit10(1 downto 0) <= "00"; |
elsif (rxtlp_firstdw_be ="1100") then |
bit10(1 downto 0) <= "10"; |
elsif (rxtlp_firstdw_be ="1111") then |
bit10(1 downto 0) <= "00"; |
else --this should never happen |
bit10(1 downto 0) <= "00"; |
end if; |
end if; |
process ( pciewb_localreset_n, rxtlp_firstdw_be ) |
begin |
if (pciewb_localreset_n = '0') then |
bit10(1 downto 0) <="00"; |
else |
if (rxtlp_firstdw_be ="0001") then |
bit10(1 downto 0) <= "00"; |
elsif (rxtlp_firstdw_be ="0010") then |
bit10(1 downto 0) <= "01"; |
elsif (rxtlp_firstdw_be ="0100") then |
bit10(1 downto 0) <= "10"; |
elsif (rxtlp_firstdw_be ="1000") then |
bit10(1 downto 0) <= "11"; |
elsif (rxtlp_firstdw_be ="0011") then |
bit10(1 downto 0) <= "00"; |
elsif (rxtlp_firstdw_be ="1100") then |
bit10(1 downto 0) <= "10"; |
elsif (rxtlp_firstdw_be ="1111") then |
bit10(1 downto 0) <= "00"; |
else --this should never happen |
bit10(1 downto 0) <= "00"; |
end if; |
end if; |
end process; |
|
|
1366,7 → 1374,12
--03h INTD |
|
cfg_interrupt_di <= "00000000"; --intA used |
|
|
--prohibit IRQ assert when TLP state machine not idle. |
-- if an IRQ is asserted between a read request and completion, it causes an error in the endpoint block. |
-- added by StBa, AAC Microtec, 2012 |
irq_prohibit <= not tlpstm_isin_idle; |
|
process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state, |
cfg_interrupt_rdy_n) |
begin |
1380,7 → 1393,7
|
--********** idle STATE ********** |
when "00000000" => --state 0 |
if (pcie_irq = '1') then |
if (pcie_irq = '1' and irq_prohibit = '0') then |
pcieirq_state <= "00000001"; |
cfg_interrupt_n <= '0'; --active |
else |
1399,7 → 1412,7
|
--********** pcie_irq kept asserted STATE ********** |
when "00000010" => --state 2 |
if (pcie_irq = '0') then --pcie_irq gets deasserted |
if (pcie_irq = '0' and irq_prohibit='0') then --pcie_irq gets deasserted |
pcieirq_state <= "00000011"; |
end if; |
cfg_interrupt_n <= '1'; --inactive |