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/xilinx_pcie2wb.vhd
3,12 → 3,12
-- Engineer: Istvan Nagy, buenos@freemail.hu
--
-- Create Date: 05/30/2010
-- Modify date: 04/26/2011
-- Modify date: 08/10/2012
-- Design Name: pcie_mini
-- Module Name: xilinx_pcie2wb - Behavioral
-- Version: 1.2
-- Project Name:
-- Target Devices: Xilinx Series-5/6/7 FPGAs (This code is tested on Spartan-6 XC6SLX45T)
-- Target Devices: Xilinx Series-5/6/7 FPGAs
-- Tool versions: ISE-DS 12.1
-- Description:
-- PCI-express endpoint block, transaction layer logic and back-end logic. The main
40,39 → 40,15
-- If we generate a new pcie endpoint, then copy the new files from the source
-- directory into the project's directory, and copy the generic section of the "pcie"
-- from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
--
-- Device Type Migration:
-- This core was tested on Xilinx Spartan-6 FPGAs, specifically on the XC6SLX45T.
-- For a new device (not an XC6SLX45T) we have to regenerate the Coregenerator cores,
-- replace all BUFIO2/MGT/BUFG/BRAM (and other) to the chosen device's appropriate resources,
-- in both the VHDL and the UCF sources. Also in the UCF the BUFIO2 and MGT placements
-- will have to be re-specified with the appropriate resources/locations. The coregenerator
-- will have to be set up to generate cores with the same parameters and ports as they are
-- used here (to be useable as a drop-in replacement). Some resources are instantiated as
-- part of the Coregen cores, so they will be chosen by Coregen appropriately, we just need
-- to adjust their LOC placement constraints in the UCF file.
-- Use on 7-series FPGAs:
-- Xilinx Series-7 FPGAs have only 64-bit bus support on the PCIe port for x1/x2,
-- and 28bit for x4/x8. Initial compatibility can be maintained with minimal modifications, by
-- replacing the TX and RX block-ram buffers to assymetrically sized port buffers. 64bit on the PCIE-EP side, and 32-bit on the other side. Also the first entry has to be corrected to be at address zero or address-2, since now it is at address-1 which will get misaligned after a port-width conversion. Also the TRN-interfaces have to be modified to work with the AXI4 interface used by the series-7 PCIE-EP blocks.
 
--
-- Coregenerator parameters:
-- PCIe-EP: Name=pcie, Type=LegacyPCIe-EP, BAR0=mem/256MB, BAR1+=off, ROM=off, Max Payload=512Bytes,
-- ASPM-L1=off, SlotCLK=off, IRQ=INTA, DeviceSpecInit=off, D1/D2=on, PME_from=D0,
-- Set D0 power (4W), DSN=enabled, PCI_ConfSp=off, PCIe_Extended_ConfSp=off,
-- no_scram =off, Xil_Refboard=None, RefClkFreq=125MHz, TranscLoc/Ch="leave default".
-- Blockram: Name=blk_mem_gen_v4_1, Type=SimpleDpRAM, WriteEn=off, Algor=MinArea,
-- WriteWidth=32, WriteDepth=512, Ena=AlwaysEnabled, ReadWidth=32, RegisterPorttB=off
-- LoadInitFile=off, Fill=off, UseRSTB=off.
--
-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
--
-- Revision:
-- Revision 0.01 - File Created
 
-- Revision 1.0 - File Created by Istvan Nagy
-- Revision 1.1 - some fixes by Istvan Nagy
-- Revision 1.2 - interrupt fix by Stephen Battazzo
--
----------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
234,6 → 210,9
SIGNAL txtlp_data_7 : std_logic_vector(31 downto 0);
SIGNAL pcie_tlp_tx_complete : std_logic;
--this signal added by StBa, AAC Microtec
SIGNAL irq_prohibit : std_logic;
SIGNAL pcieirq_state : std_logic_vector(7 downto 0);
SIGNAL txtrn_counter : std_logic_vector(7 downto 0);
SIGNAL trn_rx_counter : std_logic_vector(7 downto 0);
270,12 → 249,11
SIGNAL rcompl_bytecount_field : std_logic_vector(9 downto 0);
SIGNAL rxstm_readytoroll : std_logic;
SIGNAL tlpstm_isin_idle : std_logic;
SIGNAL pcierx_detected : std_logic;
SIGNAL pcierx_detect_ff_clear : std_logic;
-- COMPONENT DECLARATIONS (introducing the IPs) --------------------------------
 
--this is the pcie endpoint core from coregenerator.
285,91 → 263,92
--Release Date: September 16, 2009. ISE DS 11.4
component pcie is
generic (
TL_TX_RAM_RADDR_LATENCY : integer := 0;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_RADDR_LATENCY : integer := 0;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 0;
VC0_TX_LASTPACKET : integer := 14;
VC0_RX_RAM_LIMIT : bit_vector := x"7FF";
VC0_TOTAL_CREDITS_PH : integer := 32;
VC0_TOTAL_CREDITS_PD : integer := 211;
VC0_TOTAL_CREDITS_NPH : integer := 8;
VC0_TOTAL_CREDITS_CH : integer := 40;
VC0_TOTAL_CREDITS_CD : integer := 211;
VC0_CPL_INFINITE : boolean := TRUE;
BAR0 : bit_vector := x"F0000000";
BAR1 : bit_vector := x"00000000";
BAR2 : bit_vector := x"00000000";
BAR3 : bit_vector := x"00000000";
BAR4 : bit_vector := x"00000000";
BAR5 : bit_vector := x"00000000";
EXPANSION_ROM : bit_vector := "0000000000000000000000";
DISABLE_BAR_FILTERING : boolean := FALSE;
DISABLE_ID_CHECK : boolean := FALSE;
TL_TFC_DISABLE : boolean := FALSE;
TL_TX_CHECKS_DISABLE : boolean := FALSE;
USR_CFG : boolean := FALSE;
USR_EXT_CFG : boolean := FALSE;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
CLASS_CODE : bit_vector := x"068000";
CARDBUS_CIS_POINTER : bit_vector := x"00000000";
PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1";
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"1";
PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE;
PCIE_CAP_INT_MSG_NUM : bit_vector := "00000";
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7;
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7;
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
LINK_CAP_ASPM_SUPPORT : integer := 1;
LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
LINK_CAP_L1_EXIT_LATENCY : integer := 7;
LL_ACK_TIMEOUT : bit_vector := x"0204";
LL_ACK_TIMEOUT_EN : boolean := FALSE;
LL_REPLAY_TIMEOUT : bit_vector := x"0204";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
MSI_CAP_MULTIMSGCAP : integer := 0;
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
PLM_AUTO_CONFIG : boolean := FALSE;
FAST_TRAIN : boolean := FALSE;
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
DISABLE_SCRAMBLING : boolean := FALSE;
PM_CAP_VERSION : integer := 3;
PM_CAP_PME_CLOCK : boolean := FALSE;
PM_CAP_DSI : boolean := FALSE;
PM_CAP_AUXCURRENT : integer := 0;
PM_CAP_D1SUPPORT : boolean := TRUE;
PM_CAP_D2SUPPORT : boolean := TRUE;
PM_CAP_PMESUPPORT : bit_vector := x"0F";
PM_DATA0 : bit_vector := x"04";
PM_DATA_SCALE0 : bit_vector := x"0";
PM_DATA1 : bit_vector := x"00";
PM_DATA_SCALE1 : bit_vector := x"0";
PM_DATA2 : bit_vector := x"00";
PM_DATA_SCALE2 : bit_vector := x"0";
PM_DATA3 : bit_vector := x"00";
PM_DATA_SCALE3 : bit_vector := x"0";
PM_DATA4 : bit_vector := x"04";
PM_DATA_SCALE4 : bit_vector := x"0";
PM_DATA5 : bit_vector := x"00";
PM_DATA_SCALE5 : bit_vector := x"0";
PM_DATA6 : bit_vector := x"00";
PM_DATA_SCALE6 : bit_vector := x"0";
PM_DATA7 : bit_vector := x"00";
PM_DATA_SCALE7 : bit_vector := x"0";
PCIE_GENERIC : bit_vector := "000011101111";
GTP_SEL : integer := 0;
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"ABCD";
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234";
TL_TX_RAM_RADDR_LATENCY : integer := 0;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_RADDR_LATENCY : integer := 0;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 0;
VC0_TX_LASTPACKET : integer := 14;
VC0_RX_RAM_LIMIT : bit_vector := x"7FF";
VC0_TOTAL_CREDITS_PH : integer := 32;
VC0_TOTAL_CREDITS_PD : integer := 211;
VC0_TOTAL_CREDITS_NPH : integer := 8;
VC0_TOTAL_CREDITS_CH : integer := 40;
VC0_TOTAL_CREDITS_CD : integer := 211;
VC0_CPL_INFINITE : boolean := TRUE;
BAR0 : bit_vector := x"F0000000";
BAR1 : bit_vector := x"00000000";
BAR2 : bit_vector := x"00000000";
BAR3 : bit_vector := x"00000000";
BAR4 : bit_vector := x"00000000";
BAR5 : bit_vector := x"00000000";
EXPANSION_ROM : bit_vector := "0000000000000000000000";
DISABLE_BAR_FILTERING : boolean := FALSE;
DISABLE_ID_CHECK : boolean := FALSE;
TL_TFC_DISABLE : boolean := FALSE;
TL_TX_CHECKS_DISABLE : boolean := FALSE;
USR_CFG : boolean := FALSE;
USR_EXT_CFG : boolean := FALSE;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
CLASS_CODE : bit_vector := x"068000";
CARDBUS_CIS_POINTER : bit_vector := x"00000000";
PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1";
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"1";
PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE;
PCIE_CAP_INT_MSG_NUM : bit_vector := "00000";
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7;
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7;
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
LINK_CAP_ASPM_SUPPORT : integer := 1;
--LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
--LINK_CAP_L1_EXIT_LATENCY : integer := 7;
LL_ACK_TIMEOUT : bit_vector := x"0000";
LL_ACK_TIMEOUT_EN : boolean := FALSE;
--LL_REPLAY_TIMEOUT : bit_vector := x"0204";
LL_REPLAY_TIMEOUT : bit_vector := x"0000";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
MSI_CAP_MULTIMSGCAP : integer := 0;
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
PLM_AUTO_CONFIG : boolean := FALSE;
FAST_TRAIN : boolean := FALSE;
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
DISABLE_SCRAMBLING : boolean := FALSE;
PM_CAP_VERSION : integer := 3;
PM_CAP_PME_CLOCK : boolean := FALSE;
PM_CAP_DSI : boolean := FALSE;
PM_CAP_AUXCURRENT : integer := 0;
PM_CAP_D1SUPPORT : boolean := TRUE;
PM_CAP_D2SUPPORT : boolean := TRUE;
PM_CAP_PMESUPPORT : bit_vector := x"0F";
PM_DATA0 : bit_vector := x"04";
PM_DATA_SCALE0 : bit_vector := x"0";
PM_DATA1 : bit_vector := x"00";
PM_DATA_SCALE1 : bit_vector := x"0";
PM_DATA2 : bit_vector := x"00";
PM_DATA_SCALE2 : bit_vector := x"0";
PM_DATA3 : bit_vector := x"00";
PM_DATA_SCALE3 : bit_vector := x"0";
PM_DATA4 : bit_vector := x"04";
PM_DATA_SCALE4 : bit_vector := x"0";
PM_DATA5 : bit_vector := x"00";
PM_DATA_SCALE5 : bit_vector := x"0";
PM_DATA6 : bit_vector := x"00";
PM_DATA_SCALE6 : bit_vector := x"0";
PM_DATA7 : bit_vector := x"00";
PM_DATA_SCALE7 : bit_vector := x"0";
PCIE_GENERIC : bit_vector := "000011101111";
GTP_SEL : integer := 0;
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"BADD";
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234";
REF_CLK_FREQ : integer := 0
);
port (
475,11 → 454,13
 
 
---- ------- SYNTHESIS ATTRIBUTES: --------------------------------------------------
--attribute keep_hierarchy : string;
--attribute keep_hierarchy : string;
--attribute keep_hierarchy of xilinx_pcie2wb: entity is "yes";
attribute keep : string;
attribute keep of cfg_dstatus : signal is "true";
attribute keep of tlp_state : signal is "true";
 
 
 
-- --------ARCHITECTURE BODY BEGINS -----------------------------------------------
begin
 
568,26 → 549,26
received_hot_reset => received_hot_reset
);
 
--block ram for RX TLP:
Inst_bram_rxtlp: blk_mem_gen_v4_1 PORT MAP(
clka => trn_clk,
wea => bram_rxtlp_we,
addra => bram_rxtlp_writeaddress(8 downto 0),
dina => bram_rxtlp_writedata,
clkb => trn_clk,
addrb => bram_rxtlp_readaddress(8 downto 0),
doutb => bram_rxtlp_readdata
);
 
--block ram for TX TLP:
Inst_bram_txtlp: blk_mem_gen_v4_1 PORT MAP(
clka => trn_clk,
wea => bram_txtlp_we,
addra => bram_txtlp_writeaddress(8 downto 0),
dina => bram_txtlp_writedata,
clkb => trn_clk,
addrb => bram_txtlp_readaddress(8 downto 0),
doutb => bram_txtlp_readdata
--block ram for RX TLP:
Inst_bram_rxtlp: blk_mem_gen_v4_1 PORT MAP(
clka => trn_clk,
wea => bram_rxtlp_we,
addra => bram_rxtlp_writeaddress(8 downto 0),
dina => bram_rxtlp_writedata,
clkb => trn_clk,
addrb => bram_rxtlp_readaddress(8 downto 0),
doutb => bram_rxtlp_readdata
);
 
--block ram for TX TLP:
Inst_bram_txtlp: blk_mem_gen_v4_1 PORT MAP(
clka => trn_clk,
wea => bram_txtlp_we,
addra => bram_txtlp_writeaddress(8 downto 0),
dina => bram_txtlp_writedata,
clkb => trn_clk,
addrb => bram_txtlp_readaddress(8 downto 0),
doutb => bram_txtlp_readdata
);
 
 
601,15 → 582,15
--System Signals:--------------------------------
--Clock Input Buffer for differential system clock
IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => sys_clk, -- Buffer output
I => sys_clk_p, -- Diff_p buffer input (connect directly to top-level port)
IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port)
IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => sys_clk, -- Buffer output
I => sys_clk_p, -- Diff_p buffer input (connect directly to top-level port)
IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port)
);
 
--wishbone clock output:
969,25 → 950,10
--trn_rnp_ok_ntrn_rnp_ok_n <= '0'; --ready to receive non-posted
--not connected: trn_rerrfwd_n, trn_rsrc_dsc_n, trn_rbar_hit_n
 
--RX detection flip-flop
process (pciewb_localreset_n, trn_clk)
begin
if (pciewb_localreset_n='0') then
pcierx_detected <= '0';
else
if (trn_clk'event and trn_clk = '1') then
if (pcie_just_received_a_new_tlp ='1') then
pcierx_detected <= '1';
elsif (pcierx_detect_ff_clear ='1') then
pcierx_detected <= '0';
end if;
end if;
end if;
end process;
 
 
 
 
-- flow control: INTERFACE TO THE PCIE-EP: - ----
--not used. pcie-ep provides information about credit status.
--unconnected: trn_fc_nph, trn_fc_npd, trn_fc_ph, trn_fc_pd, trn_fc_cplh, trn_fc_cpld
997,7 → 963,6
 
 
 
 
-- --- GLUE LOGIC BETWEEN THE PCIE CORE-IF AND THE WB INTERFACES -----------------------
-- --- ALSO TLP PACKET PROCESSING.
--Theory of operation:
1054,7 → 1019,7
 
--TLP-protocol statemachine:
process (pciewb_localreset_n, trn_clk, tlp_state,
pcierx_detected, tlp_datacount,
pcie_just_received_a_new_tlp, tlp_datacount,
bram_rxtlp_readdata, bram_txtlp_writeaddress, bram_rxtlp_readaddress,
tlp_state_copy, rxtlp_decodedaddress,
rxtlp_header_dw1, rxtlp_header_dw2, rxtlp_header_dw3, rxtlp_header_dw4,
1076,9 → 1041,9
rxtlp_requesterid <= (others => '0');
tlp_state <= (others => '0');
tlp_state_copy <= (others => '0');
bram_txtlp_we <= "0";
bram_txtlp_writeaddress <= (others => '0');
bram_txtlp_writedata <= (others => '0');
bram_txtlp_we <= "0";
bram_txtlp_writeaddress <= (others => '0');
bram_txtlp_writedata <= (others => '0');
bram_rxtlp_readaddress <= (others => '0');
rxtlp_header_dw1 <= "01111111000000000000000000000000";
rxtlp_header_dw2 <= (others => '0');
1089,7 → 1054,6
pcie_rxtlp_tag <= (others => '0');
rcompl_bytecount_field <= (others => '0');
tlpstm_isin_idle <= '1';
pcierx_detect_ff_clear <= '0';
else
if (trn_clk'event and trn_clk = '1') then
case ( tlp_state ) is
1097,7 → 1061,7
--********** IDLE STATE **********
--also re-initialize signals...
when "00000000" => --state 0
if (pcierx_detected='1') then
if (pcie_just_received_a_new_tlp='1') then
tlp_state <= "00000001"; --to tlp decoding state
tlpstm_isin_idle <= '0';
else
1106,8 → 1070,8
start_write_wb0 <= '0';
start_read_wb0 <= '0';
tlp_state_copy <= tlp_state;
bram_txtlp_we <= "0";
bram_txtlp_writeaddress <= (others => '0');
bram_txtlp_we <= "0";
bram_txtlp_writeaddress <= (others => '0');
bram_txtlp_writedata <= (others => '0');
bram_rxtlp_readaddress <= (others => '0');
tlp_datacount <= "00000001";
1127,7 → 1091,6
rxtlp_lastdw_be <= (others => '0');
rxtlp_requesterid <= (others => '0');
rcompl_bytecount_field <= (others => '0');
pcierx_detect_ff_clear <= '0';
 
--********** TLP ARRIVED STATE **********
1140,12 → 1103,10
bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
if (bram_rxtlp_readaddress = "000000010") then
rxtlp_header_dw1 <= bram_rxtlp_readdata;
pcierx_detect_ff_clear <= '1';
elsif (bram_rxtlp_readaddress = "000000011") then
rxtlp_header_dw2 <= bram_rxtlp_readdata;
elsif (bram_rxtlp_readaddress = "000000100") then
rxtlp_header_dw3 <= bram_rxtlp_readdata;
pcierx_detect_ff_clear <= '0';
elsif (bram_rxtlp_readaddress = "000000101") then
rxtlp_header_dw4 <= bram_rxtlp_readdata;
end if;
1216,7 → 1177,6
--* Write restart state *
when "00010100" => --state 20
tlp_state <= "00000010";
tlp_state_copy <= tlp_state;
 
 
--********** READ STATE **********
1249,15 → 1209,13
when "00011110" => --state 30
tlp_state <= "00000011";
bram_txtlp_we <= "0";
tlp_state_copy <= tlp_state;
--intermediate state before completion (to ensure data latch at address-4)
when "01111110" => --state 126
tlp_state <= "00000100";
tlp_state_copy <= tlp_state;
bram_txtlp_writeaddress <= (OTHERS => '0');
--pre-write header-DW1:
bram_txtlp_writedata (31) <= flag1; --reserved
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
bram_txtlp_writedata (31) <= flag1; --reserved
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
--Calculate completion header's "rcompl_bytecount_field" from rxtlp_firstdw_be, rxtlp_lastdw_be, tlp_payloadsize_dwords
if (rxtlp_lastdw_be="0000") then --max 1DW
1283,17 → 1241,17
tlp_state_copy <= tlp_state;
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
if (bram_txtlp_writeaddress="000000000") then --if address is 0: launch data for next lock/address(1): header-2.dw
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
bram_txtlp_writedata (15 downto 13) <= "000"; --status= succesful***
bram_txtlp_writedata (12) <= '0'; --reserved
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
bram_txtlp_writedata (15 downto 13) <= "000"; --status= succesful***
bram_txtlp_writedata (12) <= '0'; --reserved
bram_txtlp_writedata (11 downto 10) <= "00";
bram_txtlp_writedata (9 downto 0) <= rcompl_bytecount_field; --total bytes returned
bram_txtlp_we <= "1";
bram_txtlp_we <= "1";
elsif (bram_txtlp_writeaddress="000000001") then --if address is 1: launch data for next lock/address(2): header-3.dw
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
bram_txtlp_writedata (7) <= '0'; --reserved
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
bram_txtlp_writedata (7) <= '0'; --reserved
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0); --lower address
else --data dwords, disable writes from next clock cycle
bram_txtlp_we <= "0";
1317,23 → 1275,23
tlp_payloadsize_dwords <= "00000000";
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
--assembling the TLP packet: )
if (bram_txtlp_writeaddress="111111111") then --header 1.dw
bram_txtlp_we <= "1";
bram_txtlp_writedata (31) <= flag1; --reserved
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
elsif (bram_txtlp_writeaddress="000000000") then --header 2.dw
bram_txtlp_we <= "1";
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
bram_txtlp_writedata (15 downto 13) <= "000"; --status= UNSUPPORTED REQUEST ***
bram_txtlp_writedata (12) <= '0'; --reserved
bram_txtlp_writedata (11 downto 0) <= "000000000000"; --remaining byte count
elsif (bram_txtlp_writeaddress="000000001") then --header 3.dw
bram_txtlp_we <= "1";
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
bram_txtlp_writedata (7) <= '0'; --reserved
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
if (bram_txtlp_writeaddress="111111111") then --header 1.dw
bram_txtlp_we <= "1";
bram_txtlp_writedata (31) <= flag1; --reserved
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
elsif (bram_txtlp_writeaddress="000000000") then --header 2.dw
bram_txtlp_we <= "1";
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
bram_txtlp_writedata (15 downto 13) <= "000"; --status= UNSUPPORTED REQUEST ***
bram_txtlp_writedata (12) <= '0'; --reserved
bram_txtlp_writedata (11 downto 0) <= "000000000000"; --remaining byte count
elsif (bram_txtlp_writeaddress="000000001") then --header 3.dw
bram_txtlp_we <= "1";
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
bram_txtlp_writedata (7) <= '0'; --reserved
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0); --lower address
else --data dwords
bram_txtlp_we <= "0";
1362,29 → 1320,29
 
--byte enable encoding to wb_address bit1:0
--this does not swap the endian, since only the data is swapped in the pcie packets.
process ( pciewb_localreset_n, rxtlp_firstdw_be )
begin
if (pciewb_localreset_n = '0') then
bit10(1 downto 0) <="00";
else
if (rxtlp_firstdw_be ="0001") then
bit10(1 downto 0) <= "00";
elsif (rxtlp_firstdw_be ="0010") then
bit10(1 downto 0) <= "01";
elsif (rxtlp_firstdw_be ="0100") then
bit10(1 downto 0) <= "10";
elsif (rxtlp_firstdw_be ="1000") then
bit10(1 downto 0) <= "11";
elsif (rxtlp_firstdw_be ="0011") then
bit10(1 downto 0) <= "00";
elsif (rxtlp_firstdw_be ="1100") then
bit10(1 downto 0) <= "10";
elsif (rxtlp_firstdw_be ="1111") then
bit10(1 downto 0) <= "00";
else --this should never happen
bit10(1 downto 0) <= "00";
end if;
end if;
process ( pciewb_localreset_n, rxtlp_firstdw_be )
begin
if (pciewb_localreset_n = '0') then
bit10(1 downto 0) <="00";
else
if (rxtlp_firstdw_be ="0001") then
bit10(1 downto 0) <= "00";
elsif (rxtlp_firstdw_be ="0010") then
bit10(1 downto 0) <= "01";
elsif (rxtlp_firstdw_be ="0100") then
bit10(1 downto 0) <= "10";
elsif (rxtlp_firstdw_be ="1000") then
bit10(1 downto 0) <= "11";
elsif (rxtlp_firstdw_be ="0011") then
bit10(1 downto 0) <= "00";
elsif (rxtlp_firstdw_be ="1100") then
bit10(1 downto 0) <= "10";
elsif (rxtlp_firstdw_be ="1111") then
bit10(1 downto 0) <= "00";
else --this should never happen
bit10(1 downto 0) <= "00";
end if;
end if;
end process;
1416,7 → 1374,12
--03h INTD
 
cfg_interrupt_di <= "00000000"; --intA used
 
--prohibit IRQ assert when TLP state machine not idle.
-- if an IRQ is asserted between a read request and completion, it causes an error in the endpoint block.
-- added by StBa, AAC Microtec, 2012
irq_prohibit <= not tlpstm_isin_idle;
process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
cfg_interrupt_rdy_n)
begin
1430,7 → 1393,7
 
--********** idle STATE **********
when "00000000" => --state 0
if (pcie_irq = '1') then
if (pcie_irq = '1' and irq_prohibit = '0') then
pcieirq_state <= "00000001";
cfg_interrupt_n <= '0'; --active
else
1449,7 → 1412,7
 
--********** pcie_irq kept asserted STATE **********
when "00000010" => --state 2
if (pcie_irq = '0') then --pcie_irq gets deasserted
if (pcie_irq = '0' and irq_prohibit='0') then --pcie_irq gets deasserted
pcieirq_state <= "00000011";
end if;
cfg_interrupt_n <= '1'; --inactive

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