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URL https://opencores.org/ocsvn/pcie_mini/pcie_mini/trunk

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Rev 1 → Rev 2

/trunk/example_design/pcie_mini_constraints.ucf
0,0 → 1,74
################################ PCIE EP IP #####################################
#
# SYS reset (input) signal. The sys_reset_n signal should be
# obtained from the PCI Express interface if possible. For
# slot based form factors, a system reset signal is usually
# present on the connector. For cable based form factors, a
# system reset signal may not be available. In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit. You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
#
#NET sys_reset_n LOC = XXX | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY;
# SYS clock 125 or 250 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Spartan-6 GTP
# Transceiver architecture requires the use of dedicated clock
# resources (FPGA input pins) associated with each GTP Transceiver Tile.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in the example design.
# Please refer to the Spartan-6 GTP Transceiver User Guide
# for guidelines regarding clock resource selection.
#
INST "Inst_s6bfip_pcie/Inst_xilinx_pcie2wb/IBUFDS_inst" LOC = BUFDS_X1Y2;
NET "sys_clk_p" LOC = A10;
NET "sys_clk_n" LOC = B10;
#NET "sys_clk_p" LOC = A10;
#NET "sys_clk_n" LOC = B10;
#
# Transceiver instance placement. This constraint selects the
# transceiver to be used, which also dictates the pinout for the
# transmit and receive differential pairs. Please refer to the
# Spartan-6 GTP Transceiver User Guide for more
# information.
#
# PCIe Lane 0
#INST pcie_i/mgt/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i LOC = GTPA1_DUAL_X0Y0;
INST "Inst_s6bfip_pcie/Inst_xilinx_pcie2wb/inst_pcie/mgt/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i" LOC = GTPA1_DUAL_X0Y0;
NET "pci_exp_txn" LOC = A6;
NET "pci_exp_rxp" LOC = D7;
NET "pci_exp_rxn" LOC = C7;
NET "pci_exp_txp" LOC = B6;
#NET "pci_exp_rxp" LOC = D7;
#NET "pci_exp_rxn" LOC = C7;
#NET "pci_exp_txn" LOC = A6;
#NET "pci_exp_txp" LOC = B6;
#
# Ignore timing on asynchronous signals.
#
NET "sys_reset_n" TIG;
#
# Timing requirements and related constraints.
#
###NET sys_clk_c PERIOD = 10ns;
#NET pcie_i/gt_refclk_out TNM_NET = GT_REFCLK_OUT;
#TIMESPEC TS_GT_REFCLK_OUT = PERIOD GT_REFCLK_OUT 8ns HIGH 50 % ;
#
#Created by Constraints Editor (xc6slx45t-fgg484-2) - 2010/11/14
TIMESPEC TS_Inst_s6bfip_pcie_Inst_xilinx_pcie2wb_inst_pcie_gt_refclk_out = PERIOD "Inst_s6bfip_pcie/Inst_xilinx_pcie2wb/inst_pcie/gt_refclk_out" 10 ns HIGH 50 %;
#
NET "sys_clk_n" TNM_NET = "sys_clk_n";
NET "sys_clk_p" TNM_NET = "sys_clk_p";
TIMESPEC TS_sys_clk_p = PERIOD "sys_clk_p" 10 ns HIGH 50 %;
NET "Inst_s6bfip_pcie/Inst_xilinx_pcie2wb/inst_pcie/gt_refclk_out" TNM_NET = "Inst_s6bfip_pcie/Inst_xilinx_pcie2wb/inst_pcie/gt_refclk_out";
#
#FORCE BUFIO2 PLACEMENT, TO PREVENT RESOURCE CONFLICT
INST "Inst_s6bfip_pcie/Inst_xilinx_pcie2wb/inst_pcie/gt_refclk_bufio2" LOC = BUFIO2_X2Y28;
#
#
NET "sys_reset_n" LOC = F10;
NET "sys_reset_n" IOSTANDARD = LVCMOS33;
#
# The pcie_bar0_wb_clk_o also has to be constrained. On Spartan-6 with x1 interface its 62.5MHz
#
 
 
/trunk/example_design/pcie.vhd
0,0 → 1,988
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information of Xilinx, Inc.
-- and is protected under U.S. and international copyright and other
-- intellectual property laws.
--
-- DISCLAIMER
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Xilinx, and to the maximum extent permitted by
-- applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-- FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-- IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-- and (2) Xilinx shall not be liable (whether in contract or tort, including
-- negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these
-- materials, including for any direct, or any indirect, special, incidental,
-- or consequential loss or damage (including loss of data, profits, goodwill,
-- or any type of loss or damage suffered as a result of any action brought by
-- a third party) even if such damage or loss was reasonably foreseeable or
-- Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in
-- any application requiring fail-safe performance, such as life-support or
-- safety devices or systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any other
-- applications that could lead to death, personal injury, or severe property
-- or environmental damage (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and liability of any use of
-- Xilinx products in Critical Applications, subject only to applicable laws
-- and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-- AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie.vhd
-- Description: Spartan-6 solution wrapper : Endpoint for PCI Express
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_bit.all;
library unisim;
use unisim.vcomponents.all;
--synthesis translate_off
use unisim.vpkg.all;
library secureip;
use secureip.all;
--synthesis translate_on
 
entity pcie is
generic (
TL_TX_RAM_RADDR_LATENCY : integer := 0;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_RADDR_LATENCY : integer := 0;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 0;
VC0_TX_LASTPACKET : integer := 14;
VC0_RX_RAM_LIMIT : bit_vector := x"7FF";
VC0_TOTAL_CREDITS_PH : integer := 32;
VC0_TOTAL_CREDITS_PD : integer := 211;
VC0_TOTAL_CREDITS_NPH : integer := 8;
VC0_TOTAL_CREDITS_CH : integer := 40;
VC0_TOTAL_CREDITS_CD : integer := 211;
VC0_CPL_INFINITE : boolean := TRUE;
BAR0 : bit_vector := x"F0000000";
BAR1 : bit_vector := x"00000000";
BAR2 : bit_vector := x"00000000";
BAR3 : bit_vector := x"00000000";
BAR4 : bit_vector := x"00000000";
BAR5 : bit_vector := x"00000000";
EXPANSION_ROM : bit_vector := "0000000000000000000000";
DISABLE_BAR_FILTERING : boolean := FALSE;
DISABLE_ID_CHECK : boolean := FALSE;
TL_TFC_DISABLE : boolean := FALSE;
TL_TX_CHECKS_DISABLE : boolean := FALSE;
USR_CFG : boolean := FALSE;
USR_EXT_CFG : boolean := FALSE;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
CLASS_CODE : bit_vector := x"068000";
CARDBUS_CIS_POINTER : bit_vector := x"00000000";
PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1";
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"1";
PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE;
PCIE_CAP_INT_MSG_NUM : bit_vector := "00000";
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7;
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7;
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
LINK_CAP_ASPM_SUPPORT : integer := 1;
LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
LINK_CAP_L1_EXIT_LATENCY : integer := 7;
LL_ACK_TIMEOUT : bit_vector := x"0000";
LL_ACK_TIMEOUT_EN : boolean := FALSE;
LL_REPLAY_TIMEOUT : bit_vector := x"0000";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
MSI_CAP_MULTIMSGCAP : integer := 0;
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
PLM_AUTO_CONFIG : boolean := FALSE;
FAST_TRAIN : boolean := FALSE;
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
DISABLE_SCRAMBLING : boolean := FALSE;
PM_CAP_VERSION : integer := 3;
PM_CAP_PME_CLOCK : boolean := FALSE;
PM_CAP_DSI : boolean := FALSE;
PM_CAP_AUXCURRENT : integer := 0;
PM_CAP_D1SUPPORT : boolean := TRUE;
PM_CAP_D2SUPPORT : boolean := TRUE;
PM_CAP_PMESUPPORT : bit_vector := x"0F";
PM_DATA0 : bit_vector := x"04";
PM_DATA_SCALE0 : bit_vector := x"0";
PM_DATA1 : bit_vector := x"00";
PM_DATA_SCALE1 : bit_vector := x"0";
PM_DATA2 : bit_vector := x"00";
PM_DATA_SCALE2 : bit_vector := x"0";
PM_DATA3 : bit_vector := x"00";
PM_DATA_SCALE3 : bit_vector := x"0";
PM_DATA4 : bit_vector := x"04";
PM_DATA_SCALE4 : bit_vector := x"0";
PM_DATA5 : bit_vector := x"00";
PM_DATA_SCALE5 : bit_vector := x"0";
PM_DATA6 : bit_vector := x"00";
PM_DATA_SCALE6 : bit_vector := x"0";
PM_DATA7 : bit_vector := x"00";
PM_DATA_SCALE7 : bit_vector := x"0";
PCIE_GENERIC : bit_vector := "000011101111";
GTP_SEL : integer := 0;
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"ABCD";
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234";
REF_CLK_FREQ : integer := 0
);
port (
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
 
-- Transaction (TRN) Interface
trn_lnk_up_n : out std_logic;
 
-- Tx
trn_td : in std_logic_vector(31 downto 0);
trn_tsof_n : in std_logic;
trn_teof_n : in std_logic;
trn_tsrc_rdy_n : in std_logic;
trn_tdst_rdy_n : out std_logic;
trn_terr_drop_n : out std_logic;
trn_tsrc_dsc_n : in std_logic;
trn_terrfwd_n : in std_logic;
trn_tbuf_av : out std_logic_vector(5 downto 0);
trn_tstr_n : in std_logic;
trn_tcfg_req_n : out std_logic;
trn_tcfg_gnt_n : in std_logic;
 
-- Rx
trn_rd : out std_logic_vector(31 downto 0);
trn_rsof_n : out std_logic;
trn_reof_n : out std_logic;
trn_rsrc_rdy_n : out std_logic;
trn_rsrc_dsc_n : out std_logic;
trn_rdst_rdy_n : in std_logic;
trn_rerrfwd_n : out std_logic;
trn_rnp_ok_n : in std_logic;
trn_rbar_hit_n : out std_logic_vector(6 downto 0);
trn_fc_sel : in std_logic_vector(2 downto 0);
trn_fc_nph : out std_logic_vector(7 downto 0);
trn_fc_npd : out std_logic_vector(11 downto 0);
trn_fc_ph : out std_logic_vector(7 downto 0);
trn_fc_pd : out std_logic_vector(11 downto 0);
trn_fc_cplh : out std_logic_vector(7 downto 0);
trn_fc_cpld : out std_logic_vector(11 downto 0);
 
-- Host (CFG) Interface
cfg_do : out std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : out std_logic;
cfg_dwaddr : in std_logic_vector(9 downto 0);
cfg_rd_en_n : in std_logic;
cfg_err_ur_n : in std_logic;
cfg_err_cor_n : in std_logic;
cfg_err_ecrc_n : in std_logic;
cfg_err_cpl_timeout_n : in std_logic;
cfg_err_cpl_abort_n : in std_logic;
cfg_err_posted_n : in std_logic;
cfg_err_locked_n : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : out std_logic;
cfg_interrupt_n : in std_logic;
cfg_interrupt_rdy_n : out std_logic;
cfg_interrupt_assert_n : in std_logic;
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_turnoff_ok_n : in std_logic;
cfg_to_turnoff_n : out std_logic;
cfg_pm_wake_n : in std_logic;
cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
cfg_trn_pending_n : in std_logic;
cfg_dsn : in std_logic_vector(63 downto 0);
cfg_bus_number : out std_logic_vector(7 downto 0);
cfg_device_number : out std_logic_vector(4 downto 0);
cfg_function_number : out std_logic_vector(2 downto 0);
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
 
-- System Interface
sys_clk : in std_logic;
sys_reset_n : in std_logic;
trn_clk : out std_logic;
trn_reset_n : out std_logic;
received_hot_reset : out std_logic
);
end pcie;
 
architecture rtl of pcie is
 
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of rtl : architecture is
"pcie,s6_pcie_v1_2,{TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=14,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=211,VC0_TOTAL_CREDITS_NPH=8,VC0_TOTAL_CREDITS_CH=40,VC0_TOTAL_CREDITS_CD=211,VC0_CPL_INFINITE=TRUE,BAR0=F0000000,BAR1=00000000,BAR2=00000000,BAR3=00000000,BAR4=00000000,BAR5=00000000,EXPANSION_ROM=000000,USR_CFG=FALSE,USR_EXT_CFG=FALSE,DEV_CAP_MAX_PAYLOAD_SUPPORTED=2,CLASS_CODE=068000,CARDBUS_CIS_POINTER=00000000,PCIE_CAP_CAPABILITY_VERSION=1,PCIE_CAP_DEVICE_PORT_TYPE=1,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,DEV_CAP_ENDPOINT_L0S_LATENCY=7,DEV_CAP_ENDPOINT_L1_LATENCY=7,LINK_CAP_ASPM_SUPPORT=1,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,LINK_STATUS_SLOT_CLOCK_CONFIG=FALSE,ENABLE_RX_TD_ECRC_TRIM=FALSE,DISABLE_SCRAMBLING=FALSE,PM_CAP_DSI=FALSE,PM_CAP_D1SUPPORT=TRUE,PM_CAP_D2SUPPORT=TRUE,PM_CAP_PMESUPPORT=0F,PM_DATA0=04,PM_DATA_SCALE0=0,PM_DATA1=00,PM_DATA_SCALE1=0,PM_DATA2=00,PM_DATA_SCALE2=0,PM_DATA3=00,PM_DATA_SCALE3=0,PM_DATA4=04,PM_DATA_SCALE4=0,PM_DATA5=00,PM_DATA_SCALE5=0,PM_DATA6=00,PM_DATA_SCALE6=0,PM_DATA7=00,PM_DATA_SCALE7=0,PCIE_GENERIC=000010101111,GTP_SEL=0,CFG_VEN_ID=10EE,CFG_DEV_ID=ABCD,CFG_REV_ID=00,CFG_SUBSYS_VEN_ID=10EE,CFG_SUBSYS_ID=1234,REF_CLK_FREQ=0}";
 
------------------------
-- Function Declarations
------------------------
function CALC_CLKFBOUT_MULT(FREQ_SEL : integer) return integer is
begin
case FREQ_SEL is
when 0 => return 5; -- 100 MHz
when 1 => return 4; -- 125 MHz
when others => return 2; -- 250 MHz
end case;
end CALC_CLKFBOUT_MULT;
function CALC_CLKIN_PERIOD(FREQ_SEL : integer) return real is
begin
case FREQ_SEL is
when 0 => return 10.0; -- 100 MHz
when 1 => return 8.0; -- 125 MHz
when others => return 4.0; -- 250 MHz
end case;
end CALC_CLKIN_PERIOD;
 
------------------------
-- Constant Declarations
------------------------
 
constant CLKFBOUT_MULT : integer := CALC_CLKFBOUT_MULT(REF_CLK_FREQ);
constant CLKIN_PERIOD : real := CALC_CLKIN_PERIOD(REF_CLK_FREQ);
 
-------------------------
-- Component Declarations
-------------------------
component pcie_bram_top_s6 is
generic (
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 0;
 
VC0_TX_LASTPACKET : integer := 31;
TLM_TX_OVERHEAD : integer := 24;
TL_TX_RAM_RADDR_LATENCY : integer := 1;
TL_TX_RAM_RDATA_LATENCY : integer := 1;
TL_TX_RAM_WRITE_LATENCY : integer := 1;
 
VC0_RX_LIMIT : integer := 16#1FFF#;
TL_RX_RAM_RADDR_LATENCY : integer := 1;
TL_RX_RAM_RDATA_LATENCY : integer := 1;
TL_RX_RAM_WRITE_LATENCY : integer := 1
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
 
mim_tx_wen : in std_logic;
mim_tx_waddr : in std_logic_vector(11 downto 0);
mim_tx_wdata : in std_logic_vector(35 downto 0);
mim_tx_ren : in std_logic;
mim_tx_rce : in std_logic;
mim_tx_raddr : in std_logic_vector(11 downto 0);
mim_tx_rdata : out std_logic_vector(35 downto 0);
 
mim_rx_wen : in std_logic;
mim_rx_waddr : in std_logic_vector(11 downto 0);
mim_rx_wdata : in std_logic_vector(35 downto 0);
mim_rx_ren : in std_logic;
mim_rx_rce : in std_logic;
mim_rx_raddr : in std_logic_vector(11 downto 0);
mim_rx_rdata : out std_logic_vector(35 downto 0)
);
end component pcie_bram_top_s6;
 
component gtpa1_dual_wrapper_top is
generic (
SIMULATION : boolean
);
port (
rx_polarity : in std_logic;
tx_char_disp_mode : in std_logic_vector(1 downto 0);
tx_char_is_k : in std_logic_vector(1 downto 0);
tx_rcvr_det : in std_logic;
tx_data : in std_logic_vector(15 downto 0);
arp_rxp : in std_logic;
arp_rxn : in std_logic;
sys_rst_n : in std_logic;
sys_clk : in std_logic;
gt_usrclk : in std_logic;
gt_usrclk2x : in std_logic;
gt_tx_elec_idle : in std_logic;
gt_power_down : in std_logic_vector(1 downto 0);
rxreset : in std_logic;
rx_char_is_k : out std_logic_vector(1 downto 0);
rx_data : out std_logic_vector(15 downto 0);
rx_enter_elecidle : out std_logic;
rx_status : out std_logic_vector(2 downto 0);
phystatus : out std_logic;
arp_txp : out std_logic;
arp_txn : out std_logic;
gt_reset_done : out std_logic;
gt_rx_valid : out std_logic;
gt_plllkdet_out : out std_logic;
gt_refclk_out : out std_logic
);
end component gtpa1_dual_wrapper_top;
 
----------------------
-- Signal Declarations
----------------------
 
-- PLL Signals
signal mgt_clk : std_logic;
signal mgt_clk_2x : std_logic;
signal clock_locked : std_logic;
signal gt_refclk_out : std_logic;
signal gt_clk_fb_west_out : std_logic;
signal pll_rst : std_logic;
signal clk_125 : std_logic;
signal clk_250 : std_logic;
signal clk_62_5 : std_logic;
signal gt_refclk_buf : std_logic;
signal gt_refclk_fb : std_logic;
 
signal w_cfg_ven_id : std_logic_vector(15 downto 0);
signal w_cfg_dev_id : std_logic_vector(15 downto 0);
signal w_cfg_rev_id : std_logic_vector(7 downto 0);
signal w_cfg_subsys_ven_id : std_logic_vector(15 downto 0);
signal w_cfg_subsys_id : std_logic_vector(15 downto 0);
 
signal cfg_ltssm_state : std_logic_vector(4 downto 0);
signal cfg_link_control_aspm_control : std_logic_vector(1 downto 0);
signal cfg_link_control_rcb : std_logic;
signal cfg_link_control_common_clock : std_logic;
signal cfg_link_control_extended_sync : std_logic;
signal cfg_command_interrupt_disable : std_logic;
signal cfg_command_serr_en : std_logic;
signal cfg_command_bus_master_enable : std_logic;
signal cfg_command_mem_enable : std_logic;
signal cfg_command_io_enable : std_logic;
signal cfg_dev_status_ur_detected : std_logic;
signal cfg_dev_status_fatal_err_detected : std_logic;
signal cfg_dev_status_nonfatal_err_detected : std_logic;
signal cfg_dev_status_corr_err_detected : std_logic;
signal cfg_dev_control_max_read_req : std_logic_vector(2 downto 0);
signal cfg_dev_control_no_snoop_en : std_logic;
signal cfg_dev_control_aux_power_en : std_logic;
signal cfg_dev_control_phantom_en : std_logic;
signal cfg_dev_cntrol_ext_tag_en : std_logic;
signal cfg_dev_control_max_payload : std_logic_vector(2 downto 0);
signal cfg_dev_control_enable_ro : std_logic;
signal cfg_dev_control_ext_tag_en : std_logic;
signal cfg_dev_control_ur_err_reporting_en : std_logic;
signal cfg_dev_control_fatal_err_reporting_en : std_logic;
signal cfg_dev_control_non_fatal_reporting_en : std_logic;
signal cfg_dev_control_corr_err_reporting_en : std_logic;
 
signal mim_tx_waddr : std_logic_vector(11 downto 0);
signal mim_tx_raddr : std_logic_vector(11 downto 0);
signal mim_rx_waddr : std_logic_vector(11 downto 0);
signal mim_rx_raddr : std_logic_vector(11 downto 0);
signal mim_tx_wdata : std_logic_vector(35 downto 0);
signal mim_tx_rdata : std_logic_vector(35 downto 0);
signal mim_rx_wdata : std_logic_vector(34 downto 0);
signal mim_rx_rdata_unused : std_logic;
signal mim_rx_rdata : std_logic_vector(34 downto 0);
signal mim_tx_wen : std_logic;
signal mim_tx_ren : std_logic;
signal mim_rx_wen : std_logic;
signal mim_rx_ren : std_logic;
 
signal dbg_bad_dllp_status : std_logic;
signal dbg_bad_tlp_lcrc : std_logic;
signal dbg_bad_tlp_seq_num : std_logic;
signal dbg_bad_tlp_status : std_logic;
signal dbg_dl_protocol_status : std_logic;
signal dbg_fc_protocol_err_status : std_logic;
signal dbg_mlfrmd_length : std_logic;
signal dbg_mlfrmd_mps : std_logic;
signal dbg_mlfrmd_tcvc : std_logic;
signal dbg_mlfrmd_tlp_status : std_logic;
signal dbg_mlfrmd_unrec_type : std_logic;
signal dbg_poistlpstatus : std_logic;
signal dbg_rcvr_overflow_status : std_logic;
signal dbg_reg_detected_correctable : std_logic;
signal dbg_reg_detected_fatal : std_logic;
signal dbg_reg_detected_non_fatal : std_logic;
signal dbg_reg_detected_unsupported : std_logic;
signal dbg_rply_rollover_status : std_logic;
signal dbg_rply_timeout_status : std_logic;
signal dbg_ur_no_bar_hit : std_logic;
signal dbg_ur_pois_cfg_wr : std_logic;
signal dbg_ur_status : std_logic;
signal dbg_ur_unsup_msg : std_logic;
 
signal pipe_gt_power_down_a : std_logic_vector(1 downto 0);
signal pipe_gt_power_down_b : std_logic_vector(1 downto 0);
signal pipe_gt_reset_done_a : std_logic;
signal pipe_gt_reset_done_b : std_logic;
signal pipe_gt_tx_elec_idle_a : std_logic;
signal pipe_gt_tx_elec_idle_b : std_logic;
signal pipe_phy_status_a : std_logic;
signal pipe_phy_status_b : std_logic;
signal pipe_rx_charisk_a : std_logic_vector(1 downto 0);
signal pipe_rx_charisk_b : std_logic_vector(1 downto 0);
signal pipe_rx_data_a : std_logic_vector(15 downto 0);
signal pipe_rx_data_b : std_logic_vector(15 downto 0);
signal pipe_rx_enter_elec_idle_a : std_logic;
signal pipe_rx_enter_elec_idle_b : std_logic;
signal pipe_rx_polarity_a : std_logic;
signal pipe_rx_polarity_b : std_logic;
signal pipe_rxreset_a : std_logic;
signal pipe_rxreset_b : std_logic;
signal pipe_rx_status_a : std_logic_vector(2 downto 0);
signal pipe_rx_status_b : std_logic_vector(2 downto 0);
signal pipe_tx_char_disp_mode_a : std_logic_vector(1 downto 0);
signal pipe_tx_char_disp_mode_b : std_logic_vector(1 downto 0);
signal pipe_tx_char_disp_val_a : std_logic_vector(1 downto 0);
signal pipe_tx_char_disp_val_b : std_logic_vector(1 downto 0);
signal pipe_tx_char_is_k_a : std_logic_vector(1 downto 0);
signal pipe_tx_char_is_k_b : std_logic_vector(1 downto 0);
signal pipe_tx_data_a : std_logic_vector(15 downto 0);
signal pipe_tx_data_b : std_logic_vector(15 downto 0);
signal pipe_tx_rcvr_det_a : std_logic;
signal pipe_tx_rcvr_det_b : std_logic;
 
-- GT->PLM PIPE Interface rx
signal rx_char_is_k : std_logic_vector(1 downto 0);
signal rx_data : std_logic_vector(15 downto 0);
signal rx_enter_elecidle : std_logic;
signal rx_status : std_logic_vector(2 downto 0);
signal rx_polarity : std_logic;
 
-- GT<-PLM PIPE Interface tx
signal tx_char_disp_mode : std_logic_vector(1 downto 0);
signal tx_char_is_k : std_logic_vector(1 downto 0);
signal tx_rcvr_det : std_logic;
signal tx_data : std_logic_vector(15 downto 0);
 
-- GT<->PLM PIPE Interface Misc
signal phystatus : std_logic;
 
-- GT<->PLM PIPE Interface MGT Logic I/O
signal gt_reset_done : std_logic;
signal gt_rx_valid : std_logic;
signal gt_tx_elec_idle : std_logic;
signal gt_power_down : std_logic_vector(1 downto 0);
signal rxreset : std_logic;
signal gt_plllkdet_out : std_logic;
 
-- Core outputs which are also used in this module - must make local copies
signal trn_clk_c : std_logic;
signal trn_reset_n_c : std_logic;
signal trn_reset : std_logic;
 
begin
 
-- These values may be brought out and driven dynamically
-- from pins rather than attributes if desired. Note -
-- if they are not statically driven, the values must be
-- stable before sys_reset_n is released
w_cfg_ven_id <= CFG_VEN_ID;
w_cfg_dev_id <= CFG_DEV_ID;
w_cfg_rev_id <= CFG_REV_ID;
w_cfg_subsys_ven_id <= CFG_SUBSYS_VEN_ID;
w_cfg_subsys_id <= CFG_SUBSYS_ID;
 
-- Assign outputs from internal copies
trn_clk <= trn_clk_c;
trn_reset_n <= trn_reset_n_c;
trn_reset <= not trn_reset_n_c;
 
-- Buffer reference clock from MGT
gt_refclk_bufio2 : BUFIO2
port map (
DIVCLK => gt_refclk_buf,
IOCLK => OPEN,
SERDESSTROBE => OPEN,
I => gt_refclk_out
);
 
pll_base_i : PLL_BASE
generic map (
CLKFBOUT_MULT => CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.0,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.0,
COMPENSATION => "INTERNAL"
)
port map (
CLKIN => gt_refclk_buf,
CLKFBIN => gt_refclk_fb,
RST => pll_rst,
CLKOUT0 => clk_250,
CLKOUT1 => clk_125,
CLKOUT2 => clk_62_5,
CLKOUT3 => OPEN,
CLKOUT4 => OPEN,
CLKOUT5 => OPEN,
CLKFBOUT => gt_refclk_fb,
LOCKED => clock_locked
);
 
-------------------------------------
-- Instantiate buffers where required
-------------------------------------
mgt_bufg : BUFG port map (O => mgt_clk, I => clk_125);
mgt2x_bufg : BUFG port map (O => mgt_clk_2x, I => clk_250);
phy_bufg : BUFG port map (O => trn_clk_c, I => clk_62_5);
 
----------------------------
-- PCI Express BRAM Instance
----------------------------
pcie_bram_top: pcie_bram_top_s6
generic map (
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
 
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
TLM_TX_OVERHEAD => 20,
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
-- NOTE: use the RX value here since there is no separate TX value
TL_TX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY,
 
VC0_RX_LIMIT => conv_integer(to_stdlogicvector(VC0_RX_RAM_LIMIT)),
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY
)
port map (
user_clk_i => trn_clk_c,
reset_i => trn_reset,
 
mim_tx_waddr => mim_tx_waddr,
mim_tx_wen => mim_tx_wen,
mim_tx_ren => mim_tx_ren,
mim_tx_rce => '1',
mim_tx_wdata => mim_tx_wdata,
mim_tx_raddr => mim_tx_raddr,
mim_tx_rdata => mim_tx_rdata,
 
mim_rx_waddr => mim_rx_waddr,
mim_rx_wen => mim_rx_wen,
mim_rx_ren => mim_rx_ren,
mim_rx_rce => '1',
mim_rx_wdata(35) => '0',
mim_rx_wdata(34 downto 0) => mim_rx_wdata,
mim_rx_raddr => mim_rx_raddr,
mim_rx_rdata(35) => mim_rx_rdata_unused,
mim_rx_rdata(34 downto 0) => mim_rx_rdata
);
 
---------------------------------
-- PCI Express GTA1_DUAL Instance
---------------------------------
mgt : gtpa1_dual_wrapper_top
generic map (
SIMULATION => FAST_TRAIN
)
port map (
rx_char_is_k => rx_char_is_k,
rx_data => rx_data,
rx_enter_elecidle => rx_enter_elecidle,
rx_status => rx_status,
rx_polarity => rx_polarity,
tx_char_disp_mode => tx_char_disp_mode,
tx_char_is_k => tx_char_is_k,
tx_rcvr_det => tx_rcvr_det,
tx_data => tx_data,
phystatus => phystatus,
gt_usrclk => mgt_clk,
gt_usrclk2x => mgt_clk_2x,
sys_clk => sys_clk,
sys_rst_n => sys_reset_n,
arp_txp => pci_exp_txp,
arp_txn => pci_exp_txn,
arp_rxp => pci_exp_rxp,
arp_rxn => pci_exp_rxn,
gt_reset_done => gt_reset_done,
gt_rx_valid => gt_rx_valid,
gt_plllkdet_out => gt_plllkdet_out,
gt_refclk_out => gt_refclk_out,
gt_tx_elec_idle => gt_tx_elec_idle,
gt_power_down => gt_power_down,
rxreset => rxreset
);
 
-- Generate the reset for the PLL
pll_rst <= (not gt_plllkdet_out) or (not sys_reset_n);
 
---------------------------------------------------------------------------
-- Generate the connection between PCIE_A1 block and the GTPA1_DUAL. When
-- the parameter GTP_SEL is 0, connect to PIPEA, when it is a 1, connect to
-- PIPEB.
---------------------------------------------------------------------------
PIPE_A_SEL : if (GTP_SEL = 0) generate
-- Signals from GTPA1_DUAL to PCIE_A1
pipe_rx_charisk_a <= rx_char_is_k;
pipe_rx_data_a <= rx_data;
pipe_rx_enter_elec_idle_a <= rx_enter_elecidle;
pipe_rx_status_a <= rx_status;
pipe_phy_status_a <= phystatus;
pipe_gt_reset_done_a <= gt_reset_done;
 
-- Unused PCIE_A1 inputs
pipe_rx_charisk_b <= "00";
pipe_rx_data_b <= x"0000";
pipe_rx_enter_elec_idle_b <= '0';
pipe_rx_status_b <= "000";
pipe_phy_status_b <= '0';
pipe_gt_reset_done_b <= '0';
 
-- Signals from PCIE_A1 to GTPA1_DUAL
rx_polarity <= pipe_rx_polarity_a;
tx_char_disp_mode <= pipe_tx_char_disp_mode_a;
tx_char_is_k <= pipe_tx_char_is_k_a;
tx_rcvr_det <= pipe_tx_rcvr_det_a;
tx_data <= pipe_tx_data_a;
gt_tx_elec_idle <= pipe_gt_tx_elec_idle_a;
gt_power_down <= pipe_gt_power_down_a;
rxreset <= pipe_rxreset_a;
end generate PIPE_A_SEL;
 
PIPE_B_SEL : if (GTP_SEL = 1) generate
-- Signals from GTPA1_DUAL to PCIE_A1
pipe_rx_charisk_b <= rx_char_is_k;
pipe_rx_data_b <= rx_data;
pipe_rx_enter_elec_idle_b <= rx_enter_elecidle;
pipe_rx_status_b <= rx_status;
pipe_phy_status_b <= phystatus;
pipe_gt_reset_done_b <= gt_reset_done;
 
-- Unused PCIE_A1 inputs
pipe_rx_charisk_a <= "00";
pipe_rx_data_a <= x"0000";
pipe_rx_enter_elec_idle_a <= '0';
pipe_rx_status_a <= "000";
pipe_phy_status_a <= '0';
pipe_gt_reset_done_a <= '0';
 
-- Signals from PCIE_A1 to GTPA1_DUAL
rx_polarity <= pipe_rx_polarity_b;
tx_char_disp_mode <= pipe_tx_char_disp_mode_b;
tx_char_is_k <= pipe_tx_char_is_k_b;
tx_rcvr_det <= pipe_tx_rcvr_det_b;
tx_data <= pipe_tx_data_b;
gt_tx_elec_idle <= pipe_gt_tx_elec_idle_b;
gt_power_down <= pipe_gt_power_down_b;
rxreset <= pipe_rxreset_b;
end generate PIPE_B_SEL;
 
---------------------------------------------------------------
-- Integrated Endpoint Block for PCI Express Instance (PCIE_A1)
---------------------------------------------------------------
 
PCIE_A1_inst : PCIE_A1
generic map (
BAR0 => BAR0,
BAR1 => BAR1,
BAR2 => BAR2,
BAR3 => BAR3,
BAR4 => BAR4,
BAR5 => BAR5,
CARDBUS_CIS_POINTER => CARDBUS_CIS_POINTER,
CLASS_CODE => CLASS_CODE,
DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY,
DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY,
DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED,
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT,
DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR,
DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING,
DISABLE_ID_CHECK => DISABLE_ID_CHECK,
DISABLE_SCRAMBLING => DISABLE_SCRAMBLING,
ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM,
EXPANSION_ROM => EXPANSION_ROM,
FAST_TRAIN => FAST_TRAIN,
GTP_SEL => GTP_SEL,
LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT,
LINK_CAP_L0S_EXIT_LATENCY => LINK_CAP_L0S_EXIT_LATENCY,
LINK_CAP_L1_EXIT_LATENCY => LINK_CAP_L1_EXIT_LATENCY,
LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG,
LL_ACK_TIMEOUT => LL_ACK_TIMEOUT,
LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN,
LL_REPLAY_TIMEOUT => LL_REPLAY_TIMEOUT,
LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN,
MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION,
MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP,
PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION,
PCIE_CAP_DEVICE_PORT_TYPE => PCIE_CAP_DEVICE_PORT_TYPE,
PCIE_CAP_INT_MSG_NUM => PCIE_CAP_INT_MSG_NUM,
PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED,
PCIE_GENERIC => PCIE_GENERIC,
PLM_AUTO_CONFIG => PLM_AUTO_CONFIG,
PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT,
PM_CAP_DSI => PM_CAP_DSI,
PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT,
PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT,
PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK,
PM_CAP_PMESUPPORT => PM_CAP_PMESUPPORT,
PM_CAP_VERSION => PM_CAP_VERSION,
PM_DATA_SCALE0 => PM_DATA_SCALE0,
PM_DATA_SCALE1 => PM_DATA_SCALE1,
PM_DATA_SCALE2 => PM_DATA_SCALE2,
PM_DATA_SCALE3 => PM_DATA_SCALE3,
PM_DATA_SCALE4 => PM_DATA_SCALE4,
PM_DATA_SCALE5 => PM_DATA_SCALE5,
PM_DATA_SCALE6 => PM_DATA_SCALE6,
PM_DATA_SCALE7 => PM_DATA_SCALE7,
PM_DATA0 => PM_DATA0,
PM_DATA1 => PM_DATA1,
PM_DATA2 => PM_DATA2,
PM_DATA3 => PM_DATA3,
PM_DATA4 => PM_DATA4,
PM_DATA5 => PM_DATA5,
PM_DATA6 => PM_DATA6,
PM_DATA7 => PM_DATA7,
SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT,
SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT,
SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT,
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY,
TL_TFC_DISABLE => TL_TFC_DISABLE,
TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE,
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
USR_CFG => USR_CFG,
USR_EXT_CFG => USR_EXT_CFG,
VC0_CPL_INFINITE => VC0_CPL_INFINITE,
VC0_RX_RAM_LIMIT => VC0_RX_RAM_LIMIT,
VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD,
VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH,
VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH,
VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD,
VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH,
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET
)
port map (
CFGBUSNUMBER => cfg_bus_number,
CFGCOMMANDBUSMASTERENABLE => cfg_command_bus_master_enable,
CFGCOMMANDINTERRUPTDISABLE => cfg_command_interrupt_disable,
CFGCOMMANDIOENABLE => cfg_command_io_enable,
CFGCOMMANDMEMENABLE => cfg_command_mem_enable,
CFGCOMMANDSERREN => cfg_command_serr_en,
CFGDEVCONTROLAUXPOWEREN => cfg_dev_control_aux_power_en,
CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dev_control_corr_err_reporting_en,
CFGDEVCONTROLENABLERO => cfg_dev_control_enable_ro,
CFGDEVCONTROLEXTTAGEN => cfg_dev_control_ext_tag_en,
CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dev_control_fatal_err_reporting_en,
CFGDEVCONTROLMAXPAYLOAD => cfg_dev_control_max_payload,
CFGDEVCONTROLMAXREADREQ => cfg_dev_control_max_read_req,
CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dev_control_non_fatal_reporting_en,
CFGDEVCONTROLNOSNOOPEN => cfg_dev_control_no_snoop_en,
CFGDEVCONTROLPHANTOMEN => cfg_dev_control_phantom_en,
CFGDEVCONTROLURERRREPORTINGEN => cfg_dev_control_ur_err_reporting_en,
CFGDEVICENUMBER => cfg_device_number,
CFGDEVID => w_cfg_dev_id,
CFGDEVSTATUSCORRERRDETECTED => cfg_dev_status_corr_err_detected,
CFGDEVSTATUSFATALERRDETECTED => cfg_dev_status_fatal_err_detected,
CFGDEVSTATUSNONFATALERRDETECTED => cfg_dev_status_nonfatal_err_detected,
CFGDEVSTATUSURDETECTED => cfg_dev_status_ur_detected,
CFGDO => cfg_do,
CFGDSN => cfg_dsn,
CFGDWADDR => cfg_dwaddr,
CFGERRCORN => cfg_err_cor_n,
CFGERRCPLABORTN => cfg_err_cpl_abort_n,
CFGERRCPLRDYN => cfg_err_cpl_rdy_n,
CFGERRCPLTIMEOUTN => cfg_err_cpl_timeout_n,
CFGERRECRCN => cfg_err_ecrc_n,
CFGERRLOCKEDN => cfg_err_locked_n,
CFGERRPOSTEDN => cfg_err_posted_n,
CFGERRTLPCPLHEADER => cfg_err_tlp_cpl_header,
CFGERRURN => cfg_err_ur_n,
CFGFUNCTIONNUMBER => cfg_function_number,
CFGINTERRUPTASSERTN => cfg_interrupt_assert_n,
CFGINTERRUPTDI => cfg_interrupt_di,
CFGINTERRUPTDO => cfg_interrupt_do,
CFGINTERRUPTMMENABLE => cfg_interrupt_mmenable,
CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable,
CFGINTERRUPTN => cfg_interrupt_n,
CFGINTERRUPTRDYN => cfg_interrupt_rdy_n,
CFGLINKCONTOLRCB => cfg_link_control_rcb,
CFGLINKCONTROLASPMCONTROL => cfg_link_control_aspm_control,
CFGLINKCONTROLCOMMONCLOCK => cfg_link_control_common_clock,
CFGLINKCONTROLEXTENDEDSYNC => cfg_link_control_extended_sync,
CFGLTSSMSTATE => cfg_ltssm_state,
CFGPCIELINKSTATEN => cfg_pcie_link_state_n,
CFGPMWAKEN => cfg_pm_wake_n,
CFGRDENN => cfg_rd_en_n,
CFGRDWRDONEN => cfg_rd_wr_done_n,
CFGREVID => w_cfg_rev_id,
CFGSUBSYSID => w_cfg_subsys_id,
CFGSUBSYSVENID => w_cfg_subsys_ven_id,
CFGTOTURNOFFN => cfg_to_turnoff_n,
CFGTRNPENDINGN => cfg_trn_pending_n,
CFGTURNOFFOKN => cfg_turnoff_ok_n,
CFGVENID => w_cfg_ven_id,
CLOCKLOCKED => clock_locked,
DBGBADDLLPSTATUS => dbg_bad_dllp_status,
DBGBADTLPLCRC => dbg_bad_tlp_lcrc,
DBGBADTLPSEQNUM => dbg_bad_tlp_seq_num,
DBGBADTLPSTATUS => dbg_bad_tlp_status,
DBGDLPROTOCOLSTATUS => dbg_dl_protocol_status,
DBGFCPROTOCOLERRSTATUS => dbg_fc_protocol_err_status,
DBGMLFRMDLENGTH => dbg_mlfrmd_length,
DBGMLFRMDMPS => dbg_mlfrmd_mps,
DBGMLFRMDTCVC => dbg_mlfrmd_tcvc,
DBGMLFRMDTLPSTATUS => dbg_mlfrmd_tlp_status,
DBGMLFRMDUNRECTYPE => dbg_mlfrmd_unrec_type,
DBGPOISTLPSTATUS => dbg_poistlpstatus,
DBGRCVROVERFLOWSTATUS => dbg_rcvr_overflow_status,
DBGREGDETECTEDCORRECTABLE => dbg_reg_detected_correctable,
DBGREGDETECTEDFATAL => dbg_reg_detected_fatal,
DBGREGDETECTEDNONFATAL => dbg_reg_detected_non_fatal,
DBGREGDETECTEDUNSUPPORTED => dbg_reg_detected_unsupported,
DBGRPLYROLLOVERSTATUS => dbg_rply_rollover_status,
DBGRPLYTIMEOUTSTATUS => dbg_rply_timeout_status,
DBGURNOBARHIT => dbg_ur_no_bar_hit,
DBGURPOISCFGWR => dbg_ur_pois_cfg_wr,
DBGURSTATUS => dbg_ur_status,
DBGURUNSUPMSG => dbg_ur_unsup_msg,
MGTCLK => mgt_clk,
MIMRXRADDR => mim_rx_raddr,
MIMRXRDATA => mim_rx_rdata,
MIMRXREN => mim_rx_ren,
MIMRXWADDR => mim_rx_waddr,
MIMRXWDATA => mim_rx_wdata,
MIMRXWEN => mim_rx_wen,
MIMTXRADDR => mim_tx_raddr,
MIMTXRDATA => mim_tx_rdata,
MIMTXREN => mim_tx_ren,
MIMTXWADDR => mim_tx_waddr,
MIMTXWDATA => mim_tx_wdata,
MIMTXWEN => mim_tx_wen,
PIPEGTPOWERDOWNA => pipe_gt_power_down_a,
PIPEGTPOWERDOWNB => pipe_gt_power_down_b,
PIPEGTRESETDONEA => pipe_gt_reset_done_a,
PIPEGTRESETDONEB => pipe_gt_reset_done_b,
PIPEGTTXELECIDLEA => pipe_gt_tx_elec_idle_a,
PIPEGTTXELECIDLEB => pipe_gt_tx_elec_idle_b,
PIPEPHYSTATUSA => pipe_phy_status_a,
PIPEPHYSTATUSB => pipe_phy_status_b,
PIPERXCHARISKA => pipe_rx_charisk_a,
PIPERXCHARISKB => pipe_rx_charisk_b,
PIPERXDATAA => pipe_rx_data_a,
PIPERXDATAB => pipe_rx_data_b,
PIPERXENTERELECIDLEA => pipe_rx_enter_elec_idle_a,
PIPERXENTERELECIDLEB => pipe_rx_enter_elec_idle_b,
PIPERXPOLARITYA => pipe_rx_polarity_a,
PIPERXPOLARITYB => pipe_rx_polarity_b,
PIPERXRESETA => pipe_rxreset_a,
PIPERXRESETB => pipe_rxreset_b,
PIPERXSTATUSA => pipe_rx_status_a,
PIPERXSTATUSB => pipe_rx_status_b,
PIPETXCHARDISPMODEA => pipe_tx_char_disp_mode_a,
PIPETXCHARDISPMODEB => pipe_tx_char_disp_mode_b,
PIPETXCHARDISPVALA => pipe_tx_char_disp_val_a,
PIPETXCHARDISPVALB => pipe_tx_char_disp_val_b,
PIPETXCHARISKA => pipe_tx_char_is_k_a,
PIPETXCHARISKB => pipe_tx_char_is_k_b,
PIPETXDATAA => pipe_tx_data_a,
PIPETXDATAB => pipe_tx_data_b,
PIPETXRCVRDETA => pipe_tx_rcvr_det_a,
PIPETXRCVRDETB => pipe_tx_rcvr_det_b,
RECEIVEDHOTRESET => received_hot_reset,
SYSRESETN => sys_reset_n,
TRNFCCPLD => trn_fc_cpld,
TRNFCCPLH => trn_fc_cplh,
TRNFCNPD => trn_fc_npd,
TRNFCNPH => trn_fc_nph,
TRNFCPD => trn_fc_pd,
TRNFCPH => trn_fc_ph,
TRNFCSEL => trn_fc_sel,
TRNLNKUPN => trn_lnk_up_n,
TRNRBARHITN => trn_rbar_hit_n,
TRNRD => trn_rd,
TRNRDSTRDYN => trn_rdst_rdy_n,
TRNREOFN => trn_reof_n,
TRNRERRFWDN => trn_rerrfwd_n,
TRNRNPOKN => trn_rnp_ok_n,
TRNRSOFN => trn_rsof_n,
TRNRSRCDSCN => trn_rsrc_dsc_n,
TRNRSRCRDYN => trn_rsrc_rdy_n,
TRNTBUFAV => trn_tbuf_av,
TRNTCFGGNTN => trn_tcfg_gnt_n,
TRNTCFGREQN => trn_tcfg_req_n,
TRNTD => trn_td,
TRNTDSTRDYN => trn_tdst_rdy_n,
TRNTEOFN => trn_teof_n,
TRNTERRDROPN => trn_terr_drop_n,
TRNTERRFWDN => trn_terrfwd_n,
TRNTSOFN => trn_tsof_n,
TRNTSRCDSCN => trn_tsrc_dsc_n,
TRNTSRCRDYN => trn_tsrc_rdy_n,
TRNTSTRN => trn_tstr_n,
USERCLK => trn_clk_c,
USERRSTN => trn_reset_n_c
);
 
----------------------------------------------------
-- Recreate wrapper outputs from the PCIE_A1 signals
----------------------------------------------------
cfg_status <= x"0000";
 
cfg_command <= "00000" &
cfg_command_interrupt_disable &
"0" &
cfg_command_serr_en &
"00000" &
cfg_command_bus_master_enable &
cfg_command_mem_enable &
cfg_command_io_enable;
 
cfg_dstatus <= "0000000000" &
not cfg_trn_pending_n &
'0' &
cfg_dev_status_ur_detected &
cfg_dev_status_fatal_err_detected &
cfg_dev_status_nonfatal_err_detected &
cfg_dev_status_corr_err_detected;
 
cfg_dcommand <= '0' &
cfg_dev_control_max_read_req &
cfg_dev_control_no_snoop_en &
cfg_dev_control_aux_power_en &
cfg_dev_control_phantom_en &
cfg_dev_control_ext_tag_en &
cfg_dev_control_max_payload &
cfg_dev_control_enable_ro &
cfg_dev_control_ur_err_reporting_en &
cfg_dev_control_fatal_err_reporting_en &
cfg_dev_control_non_fatal_reporting_en &
cfg_dev_control_corr_err_reporting_en;
 
cfg_lstatus <= x"0011";
 
cfg_lcommand <= x"00" &
cfg_link_control_extended_sync &
cfg_link_control_common_clock &
"00" &
cfg_link_control_rcb &
'0' &
cfg_link_control_aspm_control;
 
end rtl;
/trunk/example_design/gtpa1_dual_wrapper.vhd
0,0 → 1,458
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.3
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : gtpa1_dual_wrapper.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module GTPA1_DUAL_WRAPPER (a GTP Wrapper)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of,
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
 
 
--***************************** Entity Declaration ****************************
 
entity GTPA1_DUAL_WRAPPER is
generic
(
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port
(
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X0_Y0)
 
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TILE0_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
TILE0_TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TILE0_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN : in std_logic;
TILE0_CLK01_IN : in std_logic;
TILE0_GTPRESET0_IN : in std_logic;
TILE0_GTPRESET1_IN : in std_logic;
TILE0_PLLLKDET0_OUT : out std_logic;
TILE0_PLLLKDET1_OUT : out std_logic;
TILE0_RESETDONE0_OUT : out std_logic;
TILE0_RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
TILE0_RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
---------------------- Receive Ports - Clock Correction --------------------
TILE0_RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
TILE0_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXENMCOMMAALIGN0_IN : in std_logic;
TILE0_RXENMCOMMAALIGN1_IN : in std_logic;
TILE0_RXENPCOMMAALIGN0_IN : in std_logic;
TILE0_RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0);
TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0);
TILE0_RXRESET0_IN : in std_logic;
TILE0_RXRESET1_IN : in std_logic;
TILE0_RXUSRCLK0_IN : in std_logic;
TILE0_RXUSRCLK1_IN : in std_logic;
TILE0_RXUSRCLK20_IN : in std_logic;
TILE0_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_GATERXELECIDLE0_IN : in std_logic;
TILE0_GATERXELECIDLE1_IN : in std_logic;
TILE0_IGNORESIGDET0_IN : in std_logic;
TILE0_IGNORESIGDET1_IN : in std_logic;
TILE0_RXELECIDLE0_OUT : out std_logic;
TILE0_RXELECIDLE1_OUT : out std_logic;
TILE0_RXN0_IN : in std_logic;
TILE0_RXN1_IN : in std_logic;
TILE0_RXP0_IN : in std_logic;
TILE0_RXP1_IN : in std_logic;
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
TILE0_RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
TILE0_RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
TILE0_PHYSTATUS0_OUT : out std_logic;
TILE0_PHYSTATUS1_OUT : out std_logic;
TILE0_RXVALID0_OUT : out std_logic;
TILE0_RXVALID1_OUT : out std_logic;
-------------------- Receive Ports - RX Polarity Control -------------------
TILE0_RXPOLARITY0_IN : in std_logic;
TILE0_RXPOLARITY1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARISK0_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARISK1_IN : in std_logic_vector(1 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN : in std_logic_vector(15 downto 0);
TILE0_TXDATA1_IN : in std_logic_vector(15 downto 0);
TILE0_TXUSRCLK0_IN : in std_logic;
TILE0_TXUSRCLK1_IN : in std_logic;
TILE0_TXUSRCLK20_IN : in std_logic;
TILE0_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXN0_OUT : out std_logic;
TILE0_TXN1_OUT : out std_logic;
TILE0_TXP0_OUT : out std_logic;
TILE0_TXP1_OUT : out std_logic;
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TILE0_TXDETECTRX0_IN : in std_logic;
TILE0_TXDETECTRX1_IN : in std_logic;
TILE0_TXELECIDLE0_IN : in std_logic;
TILE0_TXELECIDLE1_IN : in std_logic
 
 
);
 
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of GTPA1_DUAL_WRAPPER : entity is "GTPA1_DUAL_WRAPPER,s6_gtpwizard_v1_3,{gtp0_protocol_file=pcie,gtp1_protocol_file=Use_GTP0_settings}";
 
end GTPA1_DUAL_WRAPPER;
 
architecture RTL of GTPA1_DUAL_WRAPPER is
 
--***************************** Signal Declarations *****************************
 
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tile0_plllkdet0_i : std_logic;
signal tile0_plllkdet1_i : std_logic;
 
signal tile0_plllkdet0_i2 : std_logic;
signal tile0_plllkdet1_i2 : std_logic;
 
--*************************** Component Declarations **************************
 
component GTPA1_DUAL_WRAPPER_TILE
generic
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
--
TILE_CLKINDC_B_0 : boolean := FALSE;
TIlE_CLKINDC_B_1 : boolean := FALSE;
--
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN0_IN : in std_logic;
RXENMCOMMAALIGN1_IN : in std_logic;
RXENPCOMMAALIGN0_IN : in std_logic;
RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(15 downto 0);
RXDATA1_OUT : out std_logic_vector(15 downto 0);
RXRESET0_IN : in std_logic;
RXRESET1_IN : in std_logic;
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0_IN : in std_logic;
GATERXELECIDLE1_IN : in std_logic;
IGNORESIGDET0_IN : in std_logic;
IGNORESIGDET1_IN : in std_logic;
RXELECIDLE0_OUT : out std_logic;
RXELECIDLE1_OUT : out std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0_OUT : out std_logic;
PHYSTATUS1_OUT : out std_logic;
RXVALID0_OUT : out std_logic;
RXVALID1_OUT : out std_logic;
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0_IN : in std_logic;
RXPOLARITY1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
TXCHARISK0_IN : in std_logic_vector(1 downto 0);
TXCHARISK1_IN : in std_logic_vector(1 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(15 downto 0);
TXDATA1_IN : in std_logic_vector(15 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic;
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0_IN : in std_logic;
TXDETECTRX1_IN : in std_logic;
TXELECIDLE0_IN : in std_logic;
TXELECIDLE1_IN : in std_logic
 
 
);
end component;
 
 
--********************************* Main Body of Code**************************
 
begin
 
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
 
simulation : if WRAPPER_SIMULATION = 1 generate
 
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i2;
TILE0_PLLLKDET1_OUT <= tile0_plllkdet1_i2;
 
process
begin
wait until tile0_plllkdet0_i'event;
if (tile0_plllkdet0_i = '1') then
tile0_plllkdet0_i2 <= '1' after 100 ns;
else
tile0_plllkdet0_i2 <= tile0_plllkdet0_i;
end if;
end process;
process
begin
wait until tile0_plllkdet1_i'event;
if (tile0_plllkdet1_i = '1') then
tile0_plllkdet1_i2 <= '1' after 100 ns;
else
tile0_plllkdet1_i2 <= tile0_plllkdet1_i;
end if;
end process;
 
end generate simulation;
 
implementation : if WRAPPER_SIMULATION = 0 generate
 
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i;
TILE0_PLLLKDET1_OUT <= tile0_plllkdet1_i;
 
end generate implementation;
 
--------------------------- Tile Instances -------------------------------
 
 
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X0_Y0)
 
tile0_gtpa1_dual_wrapper_i : GTPA1_DUAL_WRAPPER_TILE
generic map
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP => WRAPPER_SIM_GTPRESET_SPEEDUP,
--
TILE_CLKINDC_B_0 => TRUE,
TILE_CLKINDC_B_1 => TRUE,
--
TILE_PLL_SOURCE_0 => "PLL0",
TILE_PLL_SOURCE_1 => "PLL1"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
RXPOWERDOWN0_IN => TILE0_RXPOWERDOWN0_IN,
RXPOWERDOWN1_IN => TILE0_RXPOWERDOWN1_IN,
TXPOWERDOWN0_IN => TILE0_TXPOWERDOWN0_IN,
TXPOWERDOWN1_IN => TILE0_TXPOWERDOWN1_IN,
--------------------------------- PLL Ports --------------------------------
CLK00_IN => TILE0_CLK00_IN,
CLK01_IN => TILE0_CLK01_IN,
GTPRESET0_IN => TILE0_GTPRESET0_IN,
GTPRESET1_IN => TILE0_GTPRESET1_IN,
PLLLKDET0_OUT => tile0_plllkdet0_i,
PLLLKDET1_OUT => tile0_plllkdet1_i,
RESETDONE0_OUT => TILE0_RESETDONE0_OUT,
RESETDONE1_OUT => TILE0_RESETDONE1_OUT,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT => TILE0_RXCHARISK0_OUT,
RXCHARISK1_OUT => TILE0_RXCHARISK1_OUT,
RXDISPERR0_OUT => TILE0_RXDISPERR0_OUT,
RXDISPERR1_OUT => TILE0_RXDISPERR1_OUT,
RXNOTINTABLE0_OUT => TILE0_RXNOTINTABLE0_OUT,
RXNOTINTABLE1_OUT => TILE0_RXNOTINTABLE1_OUT,
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0_OUT => TILE0_RXCLKCORCNT0_OUT,
RXCLKCORCNT1_OUT => TILE0_RXCLKCORCNT1_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN0_IN => TILE0_RXENMCOMMAALIGN0_IN,
RXENMCOMMAALIGN1_IN => TILE0_RXENMCOMMAALIGN1_IN,
RXENPCOMMAALIGN0_IN => TILE0_RXENPCOMMAALIGN0_IN,
RXENPCOMMAALIGN1_IN => TILE0_RXENPCOMMAALIGN1_IN,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT => TILE0_RXDATA0_OUT,
RXDATA1_OUT => TILE0_RXDATA1_OUT,
RXRESET0_IN => TILE0_RXRESET0_IN,
RXRESET1_IN => TILE0_RXRESET1_IN,
RXUSRCLK0_IN => TILE0_RXUSRCLK0_IN,
RXUSRCLK1_IN => TILE0_RXUSRCLK1_IN,
RXUSRCLK20_IN => TILE0_RXUSRCLK20_IN,
RXUSRCLK21_IN => TILE0_RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0_IN => TILE0_GATERXELECIDLE0_IN,
GATERXELECIDLE1_IN => TILE0_GATERXELECIDLE1_IN,
IGNORESIGDET0_IN => TILE0_IGNORESIGDET0_IN,
IGNORESIGDET1_IN => TILE0_IGNORESIGDET1_IN,
RXELECIDLE0_OUT => TILE0_RXELECIDLE0_OUT,
RXELECIDLE1_OUT => TILE0_RXELECIDLE1_OUT,
RXN0_IN => TILE0_RXN0_IN,
RXN1_IN => TILE0_RXN1_IN,
RXP0_IN => TILE0_RXP0_IN,
RXP1_IN => TILE0_RXP1_IN,
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXSTATUS0_OUT => TILE0_RXSTATUS0_OUT,
RXSTATUS1_OUT => TILE0_RXSTATUS1_OUT,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0_OUT => TILE0_PHYSTATUS0_OUT,
PHYSTATUS1_OUT => TILE0_PHYSTATUS1_OUT,
RXVALID0_OUT => TILE0_RXVALID0_OUT,
RXVALID1_OUT => TILE0_RXVALID1_OUT,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0_IN => TILE0_RXPOLARITY0_IN,
RXPOLARITY1_IN => TILE0_RXPOLARITY1_IN,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT => TILE0_GTPCLKOUT0_OUT,
GTPCLKOUT1_OUT => TILE0_GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARDISPMODE0_IN => TILE0_TXCHARDISPMODE0_IN,
TXCHARDISPMODE1_IN => TILE0_TXCHARDISPMODE1_IN,
TXCHARISK0_IN => TILE0_TXCHARISK0_IN,
TXCHARISK1_IN => TILE0_TXCHARISK1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN => TILE0_TXDATA0_IN,
TXDATA1_IN => TILE0_TXDATA1_IN,
TXUSRCLK0_IN => TILE0_TXUSRCLK0_IN,
TXUSRCLK1_IN => TILE0_TXUSRCLK1_IN,
TXUSRCLK20_IN => TILE0_TXUSRCLK20_IN,
TXUSRCLK21_IN => TILE0_TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT => TILE0_TXN0_OUT,
TXN1_OUT => TILE0_TXN1_OUT,
TXP0_OUT => TILE0_TXP0_OUT,
TXP1_OUT => TILE0_TXP1_OUT,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0_IN => TILE0_TXDETECTRX0_IN,
TXDETECTRX1_IN => TILE0_TXDETECTRX1_IN,
TXELECIDLE0_IN => TILE0_TXELECIDLE0_IN,
TXELECIDLE1_IN => TILE0_TXELECIDLE1_IN
 
);
 
end RTL;
/trunk/example_design/gtpa1_dual_wrapper_top.vhd
0,0 → 1,333
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information of Xilinx, Inc.
-- and is protected under U.S. and international copyright and other
-- intellectual property laws.
--
-- DISCLAIMER
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Xilinx, and to the maximum extent permitted by
-- applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-- FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-- IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-- and (2) Xilinx shall not be liable (whether in contract or tort, including
-- negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these
-- materials, including for any direct, or any indirect, special, incidental,
-- or consequential loss or damage (including loss of data, profits, goodwill,
-- or any type of loss or damage suffered as a result of any action brought by
-- a third party) even if such damage or loss was reasonably foreseeable or
-- Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in
-- any application requiring fail-safe performance, such as life-support or
-- safety devices or systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any other
-- applications that could lead to death, personal injury, or severe property
-- or environmental damage (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and liability of any use of
-- Xilinx products in Critical Applications, subject only to applicable laws
-- and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-- AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : gtpa1_dual_wrapper_top.vhd
-- Description: PCI Express Wrapper for GTPA1_DUAL
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_bit.all;
library unisim;
use unisim.vcomponents.all;
--synthesis translate_off
use unisim.vpkg.all;
library secureip;
use secureip.all;
--synthesis translate_on
 
entity gtpa1_dual_wrapper_top is
generic (
SIMULATION : boolean := FALSE
);
port (
-- Clock and reset
sys_rst_n : in std_logic;
sys_clk : in std_logic;
gt_usrclk : in std_logic;
gt_usrclk2x : in std_logic;
gt_refclk_out : out std_logic;
gt_reset_done : out std_logic;
rxreset : in std_logic;
 
-- RX and TX path GTP <-> PCIe
rx_char_is_k : out std_logic_vector(1 downto 0);
rx_data : out std_logic_vector(15 downto 0);
rx_enter_elecidle : out std_logic;
rx_status : out std_logic_vector(2 downto 0);
rx_polarity : in std_logic;
tx_char_disp_mode : in std_logic_vector(1 downto 0);
tx_char_is_k : in std_logic_vector(1 downto 0);
tx_rcvr_det : in std_logic;
tx_data : in std_logic_vector(15 downto 0);
 
-- Status and control path GTP <-> PCIe
phystatus : out std_logic;
gt_rx_valid : out std_logic;
gt_plllkdet_out : out std_logic;
gt_tx_elec_idle : in std_logic;
gt_power_down : in std_logic_vector(1 downto 0);
 
-- PCIe serial datapath
arp_txp : out std_logic;
arp_txn : out std_logic;
arp_rxp : in std_logic;
arp_rxn : in std_logic
);
end gtpa1_dual_wrapper_top;
 
architecture rtl of gtpa1_dual_wrapper_top is
 
------------------------
-- Function Declarations
------------------------
function SIM_INT(SIMULATION : boolean) return integer is
begin
if SIMULATION then
return 1;
else
return 0;
end if;
end SIM_INT;
 
component GTPA1_DUAL_WRAPPER is
generic
(
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port
(
 
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X0_Y0)
 
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TILE0_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
TILE0_TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TILE0_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN : in std_logic;
TILE0_CLK01_IN : in std_logic;
TILE0_GTPRESET0_IN : in std_logic;
TILE0_GTPRESET1_IN : in std_logic;
TILE0_PLLLKDET0_OUT : out std_logic;
TILE0_PLLLKDET1_OUT : out std_logic;
TILE0_RESETDONE0_OUT : out std_logic;
TILE0_RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
TILE0_RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
---------------------- Receive Ports - Clock Correction --------------------
TILE0_RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
TILE0_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXENMCOMMAALIGN0_IN : in std_logic;
TILE0_RXENMCOMMAALIGN1_IN : in std_logic;
TILE0_RXENPCOMMAALIGN0_IN : in std_logic;
TILE0_RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0);
TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0);
TILE0_RXRESET0_IN : in std_logic;
TILE0_RXRESET1_IN : in std_logic;
TILE0_RXUSRCLK0_IN : in std_logic;
TILE0_RXUSRCLK1_IN : in std_logic;
TILE0_RXUSRCLK20_IN : in std_logic;
TILE0_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_GATERXELECIDLE0_IN : in std_logic;
TILE0_GATERXELECIDLE1_IN : in std_logic;
TILE0_IGNORESIGDET0_IN : in std_logic;
TILE0_IGNORESIGDET1_IN : in std_logic;
TILE0_RXELECIDLE0_OUT : out std_logic;
TILE0_RXELECIDLE1_OUT : out std_logic;
TILE0_RXN0_IN : in std_logic;
TILE0_RXN1_IN : in std_logic;
TILE0_RXP0_IN : in std_logic;
TILE0_RXP1_IN : in std_logic;
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
TILE0_RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
TILE0_RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
TILE0_PHYSTATUS0_OUT : out std_logic;
TILE0_PHYSTATUS1_OUT : out std_logic;
TILE0_RXVALID0_OUT : out std_logic;
TILE0_RXVALID1_OUT : out std_logic;
-------------------- Receive Ports - RX Polarity Control -------------------
TILE0_RXPOLARITY0_IN : in std_logic;
TILE0_RXPOLARITY1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARISK0_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARISK1_IN : in std_logic_vector(1 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN : in std_logic_vector(15 downto 0);
TILE0_TXDATA1_IN : in std_logic_vector(15 downto 0);
TILE0_TXUSRCLK0_IN : in std_logic;
TILE0_TXUSRCLK1_IN : in std_logic;
TILE0_TXUSRCLK20_IN : in std_logic;
TILE0_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXN0_OUT : out std_logic;
TILE0_TXN1_OUT : out std_logic;
TILE0_TXP0_OUT : out std_logic;
TILE0_TXP1_OUT : out std_logic;
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TILE0_TXDETECTRX0_IN : in std_logic;
TILE0_TXDETECTRX1_IN : in std_logic;
TILE0_TXELECIDLE0_IN : in std_logic;
TILE0_TXELECIDLE1_IN : in std_logic
);
end component GTPA1_DUAL_WRAPPER;
 
-------------------------------------
-- Local signals
-------------------------------------
 
signal gt_refclk : std_logic_vector(1 downto 0);
signal sys_rst : std_logic;
 
begin
 
GT_i : GTPA1_DUAL_WRAPPER
generic map (
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP => 1,
WRAPPER_SIMULATION => SIM_INT(SIMULATION)
)
port map (
 
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_RXPOWERDOWN0_IN => gt_power_down,
TILE0_RXPOWERDOWN1_IN => "10",
TILE0_TXPOWERDOWN0_IN => gt_power_down,
TILE0_TXPOWERDOWN1_IN => "10",
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN => sys_clk,
TILE0_CLK01_IN => '0',
TILE0_GTPRESET0_IN => sys_rst,
TILE0_GTPRESET1_IN => '1',
TILE0_PLLLKDET0_OUT => gt_plllkdet_out,
TILE0_PLLLKDET1_OUT => OPEN,
TILE0_RESETDONE0_OUT => gt_reset_done,
TILE0_RESETDONE1_OUT => OPEN,
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXCHARISK0_OUT(1) => rx_char_is_k(0),
TILE0_RXCHARISK0_OUT(0) => rx_char_is_k(1),
TILE0_RXCHARISK1_OUT => OPEN,
TILE0_RXDISPERR0_OUT => OPEN,
TILE0_RXDISPERR1_OUT => OPEN,
TILE0_RXNOTINTABLE0_OUT => OPEN,
TILE0_RXNOTINTABLE1_OUT => OPEN,
---------------------- Receive Ports - Clock Correction --------------------
TILE0_RXCLKCORCNT0_OUT => OPEN,
TILE0_RXCLKCORCNT1_OUT => OPEN,
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXENMCOMMAALIGN0_IN => '1',
TILE0_RXENMCOMMAALIGN1_IN => '1',
TILE0_RXENPCOMMAALIGN0_IN => '1',
TILE0_RXENPCOMMAALIGN1_IN => '1',
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT(15 downto 8) => rx_data(7 downto 0),
TILE0_RXDATA0_OUT(7 downto 0) => rx_data(15 downto 8),
TILE0_RXDATA1_OUT => OPEN,
TILE0_RXRESET0_IN => rxreset,
TILE0_RXRESET1_IN => '1',
TILE0_RXUSRCLK0_IN => gt_usrclk2x,
TILE0_RXUSRCLK1_IN => '0',
TILE0_RXUSRCLK20_IN => gt_usrclk,
TILE0_RXUSRCLK21_IN => '0',
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_GATERXELECIDLE0_IN => '0',
TILE0_GATERXELECIDLE1_IN => '0',
TILE0_IGNORESIGDET0_IN => '0',
TILE0_IGNORESIGDET1_IN => '0',
TILE0_RXELECIDLE0_OUT => rx_enter_elecidle,
TILE0_RXELECIDLE1_OUT => OPEN,
TILE0_RXN0_IN => arp_rxn,
TILE0_RXN1_IN => '0',
TILE0_RXP0_IN => arp_rxp,
TILE0_RXP1_IN => '0',
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
TILE0_RXSTATUS0_OUT => rx_status,
TILE0_RXSTATUS1_OUT => OPEN,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
TILE0_PHYSTATUS0_OUT => phystatus,
TILE0_PHYSTATUS1_OUT => OPEN,
TILE0_RXVALID0_OUT => gt_rx_valid,
TILE0_RXVALID1_OUT => OPEN,
-------------------- Receive Ports - RX Polarity Control -------------------
TILE0_RXPOLARITY0_IN => rx_polarity,
TILE0_RXPOLARITY1_IN => '0',
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKOUT0_OUT => gt_refclk,
TILE0_GTPCLKOUT1_OUT => OPEN,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARDISPMODE0_IN(1) => tx_char_disp_mode(0),
TILE0_TXCHARDISPMODE0_IN(0) => tx_char_disp_mode(1),
TILE0_TXCHARDISPMODE1_IN(1) => '0',
TILE0_TXCHARDISPMODE1_IN(0) => '0',
TILE0_TXCHARISK0_IN(1) => tx_char_is_k(0),
TILE0_TXCHARISK0_IN(0) => tx_char_is_k(1),
TILE0_TXCHARISK1_IN(1) => '0',
TILE0_TXCHARISK1_IN(0) => '0',
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN(15 downto 8) => tx_data(7 downto 0),
TILE0_TXDATA0_IN(7 downto 0) => tx_data(15 downto 8),
TILE0_TXDATA1_IN(15 downto 8) => x"00",
TILE0_TXDATA1_IN(7 downto 0) => x"00",
TILE0_TXUSRCLK0_IN => gt_usrclk2x,
TILE0_TXUSRCLK1_IN => '0',
TILE0_TXUSRCLK20_IN => gt_usrclk,
TILE0_TXUSRCLK21_IN => '0',
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXN0_OUT => arp_txn,
TILE0_TXN1_OUT => OPEN,
TILE0_TXP0_OUT => arp_txp,
TILE0_TXP1_OUT => OPEN,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TILE0_TXDETECTRX0_IN => tx_rcvr_det,
TILE0_TXDETECTRX1_IN => '0',
TILE0_TXELECIDLE0_IN => gt_tx_elec_idle,
TILE0_TXELECIDLE1_IN => '0' );
 
sys_rst <= not sys_rst_n;
gt_refclk_out <= gt_refclk(0);
 
end rtl;
 
/trunk/example_design/xilinx_pcie2wb.vhd
0,0 → 1,1455
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Istvan Nagy, buenos@freemail.hu
--
-- Create Date: 15:58:13 05/30/2010
-- Design Name: pcie_mini
-- Module Name: xilinx_pcie2wb - Behavioral
-- Version: 1.0
-- Project Name:
-- Target Devices: Xilinx Series-5/6/7 FPGAs
-- Tool versions: ISE-DS 12.1
-- Description:
-- PCI-express endpoint block, transaction layer logic and back-end logic. The main
-- purpose of this file is to make a useable back-end interface and handle flow control
-- for the xilinx auto-generated PCIe endpoint IP.
-- The PCIe endpoint implements one 256MByte memory BAR (Base Address Register).
-- This 256MBytes size is set up in the core config, and also hardcoded in this
-- file (search for: "256MBytes").
-- This 1 BAR is implemented as a Wishbone master interface with byte addressing,
-- where address [x:2] shows DWORD address, while sel[3:0] decodes the 2 LSBs.
-- ADDRESSES ARE BYTE ADDRESSES.
-- The lower address bits are usually zero, so the slave (MCB) has to select bytes based
-- on the byte select signals: sel[3:0]. The output address of the core contails the 2
-- LSBs as well. The core was only tested with 32-bit accesses, byte-wide might work or not.
-- The TLP logic is capable of handling up to 1k bytes (256 DWORDs) payload data in a
-- single PCIe transaction, and can handle only one request at a time. If a new request
-- is arriving while processing the previous one (e.g. getting the data from a wishbone
-- read), then the state machine will not process it immediately, or it will hang. So
-- the user software has to wait for the previous read completion before issueing a new
-- request. The multiple DWORDs are handled separately by the WB statemachine.
-- Performance: WishBone bus: 62.5MHz, 32bit, 2clk/access -> 125MBytes/sec. The maximum
-- data throughput can be achieved when using the maximum data payload (block).
-- The core uses INTA wirtual wire to signal interrupts.
--
-- x1 PCIe, legacy endpoint, uses a 100MHz ref clock. The generated core had to
-- be edited manually to support 100MHz, as per Xilinx AR#33761.
--
-- Dependencies: The CoreGenerator's configured PCIe core is included.
-- If we generate a new pcie endpoint, then copy the new files from the source
-- directory into the project's directory, and copy the generic section of the "pcie"
-- from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
--
-- Revision:
-- Revision 0.01 - File Created
 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
 
 
entity xilinx_pcie2wb is
Port ( --FPGA PINS(EXTERNAL):
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
sys_clk_n : in std_logic;
sys_clk_p : in std_logic;
sys_reset_n : in std_logic;
--ON CHIP PORTS:
--DATA BUS for BAR0 (wishbone):
pcie_bar0_wb_data_o : out std_logic_vector(31 downto 0);
pcie_bar0_wb_data_i : in std_logic_vector(31 downto 0);
pcie_bar0_wb_addr_o : out std_logic_vector(27 downto 0);
pcie_bar0_wb_cyc_o : out std_logic;
pcie_bar0_wb_stb_o : out std_logic;
pcie_bar0_wb_wr_o : out std_logic;
pcie_bar0_wb_ack_i : in std_logic;
pcie_bar0_wb_clk_o : out std_logic; --62.5MHz
pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0);
--OTHER:
pcie_irq : in std_logic;
pcie_resetout : out std_logic --active high
);
end xilinx_pcie2wb;
 
 
 
 
architecture Behavioral of xilinx_pcie2wb is
 
 
 
-- Internal Signals ------------------------------------------------------------
--SIGNAL dummy : std_logic_vector(15 downto 0); --write data bus
SIGNAL cfg_do : std_logic_vector(31 downto 0);
SIGNAL cfg_rd_wr_done_n : std_logic;
SIGNAL cfg_dwaddr : std_logic_vector(9 downto 0);
SIGNAL cfg_rd_en_n : std_logic;
SIGNAL cfg_err_ur_n : std_logic;
SIGNAL cfg_err_cor_n : std_logic;
SIGNAL cfg_err_ecrc_n : std_logic;
SIGNAL cfg_err_cpl_timeout_n : std_logic;
SIGNAL cfg_err_cpl_abort_n : std_logic;
SIGNAL cfg_err_posted_n : std_logic;
SIGNAL cfg_err_locked_n : std_logic;
SIGNAL cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
SIGNAL cfg_err_cpl_rdy_n : std_logic;
SIGNAL cfg_interrupt_n : std_logic;
SIGNAL cfg_interrupt_rdy_n : std_logic;
SIGNAL cfg_interrupt_assert_n : std_logic;
SIGNAL cfg_interrupt_do : std_logic_vector(7 downto 0);
SIGNAL cfg_interrupt_di : std_logic_vector(7 downto 0);
SIGNAL cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
SIGNAL cfg_interrupt_msienable : std_logic;
SIGNAL cfg_turnoff_ok_n : std_logic;
SIGNAL cfg_to_turnoff_n : std_logic;
SIGNAL cfg_pm_wake_n : std_logic;
SIGNAL cfg_pcie_link_state_n : std_logic_vector(2 downto 0);
SIGNAL cfg_trn_pending_n : std_logic;
SIGNAL cfg_dsn : std_logic_vector(63 downto 0);
SIGNAL cfg_bus_number : std_logic_vector(7 downto 0);
SIGNAL cfg_device_number : std_logic_vector(4 downto 0);
SIGNAL cfg_function_number : std_logic_vector(2 downto 0);
SIGNAL cfg_status : std_logic_vector(15 downto 0);
SIGNAL cfg_command : std_logic_vector(15 downto 0);
SIGNAL cfg_dstatus : std_logic_vector(15 downto 0);
SIGNAL cfg_dcommand : std_logic_vector(15 downto 0);
SIGNAL cfg_lstatus : std_logic_vector(15 downto 0);
SIGNAL cfg_lcommand : std_logic_vector(15 downto 0);
-- System Interface
SIGNAL sys_clk : std_logic;
SIGNAL trn_clk : std_logic;
SIGNAL trn_reset_n : std_logic;
SIGNAL received_hot_reset : std_logic;
-- Transaction (TRN) Interface
SIGNAL trn_lnk_up_n : std_logic;
-- data interface Tx
SIGNAL trn_td : std_logic_vector(31 downto 0);
SIGNAL trn_tsof_n : std_logic;
SIGNAL trn_teof_n : std_logic;
SIGNAL trn_tsrc_rdy_n : std_logic;
SIGNAL trn_tdst_rdy_n : std_logic;
SIGNAL trn_terr_drop_n : std_logic;
SIGNAL trn_tsrc_dsc_n : std_logic;
SIGNAL trn_terrfwd_n : std_logic;
SIGNAL trn_tbuf_av : std_logic_vector(5 downto 0);
SIGNAL trn_tstr_n : std_logic;
SIGNAL trn_tcfg_req_n : std_logic;
SIGNAL trn_tcfg_gnt_n : std_logic;
-- data interface Rx
SIGNAL trn_rd : std_logic_vector(31 downto 0);
SIGNAL trn_rsof_n : std_logic;
SIGNAL trn_reof_n : std_logic;
SIGNAL trn_rsrc_rdy_n : std_logic;
SIGNAL trn_rsrc_dsc_n : std_logic;
SIGNAL trn_rdst_rdy_n : std_logic;
SIGNAL trn_rerrfwd_n : std_logic;
SIGNAL trn_rnp_ok_n : std_logic;
SIGNAL trn_rbar_hit_n : std_logic_vector(6 downto 0);
-- flow control
SIGNAL trn_fc_sel : std_logic_vector(2 downto 0);
SIGNAL trn_fc_nph : std_logic_vector(7 downto 0);
SIGNAL trn_fc_npd : std_logic_vector(11 downto 0);
SIGNAL trn_fc_ph : std_logic_vector(7 downto 0);
SIGNAL trn_fc_pd : std_logic_vector(11 downto 0);
SIGNAL trn_fc_cplh : std_logic_vector(7 downto 0);
SIGNAL trn_fc_cpld : std_logic_vector(11 downto 0);
 
SIGNAL start_read_wb0 : std_logic;
SIGNAL start_write_wb0 : std_logic;
SIGNAL wb_transaction_complete : std_logic;
SIGNAL pcie_bar0_wb_data_i_latched : std_logic_vector(31 downto 0);
SIGNAL pcie_bar0_wb_data_o_feed : std_logic_vector(31 downto 0);
SIGNAL pcie_bar0_wb_addr_o_feed : std_logic_vector(27 downto 0);
SIGNAL pcie_bar0_wb_sel_o_feed : std_logic_vector(3 downto 0);
SIGNAL start_read_wb1 : std_logic;
SIGNAL start_write_wb1 : std_logic;
SIGNAL rd_data_ready_wb1 : std_logic;
 
SIGNAL pcie_just_received_a_new_tlp : std_logic ;
SIGNAL pcie_start_reading_rx_tlp : std_logic ;
SIGNAL pcie_there_is_a_new_tlp_to_transmit : std_logic ;
SIGNAL rxtlp_decodedaddress : std_logic_vector(31 downto 0);
SIGNAL tlp_payloadsize_dwords : std_logic_vector(7 downto 0);
SIGNAL rxtlp_firstdw_be : std_logic_vector(3 downto 0);
SIGNAL rxtlp_lastdw_be : std_logic_vector(3 downto 0);
SIGNAL rxtlp_requesterid : std_logic_vector(15 downto 0);
SIGNAL tlp_state : std_logic_vector(7 downto 0);
SIGNAL tlp_state_copy : std_logic_vector(7 downto 0);
SIGNAL rxtlp_data_0 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_1 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_2 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_3 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_4 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_5 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_6 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_7 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_0 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_1 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_2 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_3 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_4 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_5 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_6 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_7 : std_logic_vector(31 downto 0);
SIGNAL pcie_tlp_tx_complete : std_logic;
SIGNAL pcieirq_state : std_logic_vector(7 downto 0);
SIGNAL txtrn_counter : std_logic_vector(7 downto 0);
SIGNAL trn_rx_counter : std_logic_vector(7 downto 0);
SIGNAL cfg_completer_id : std_logic_vector(15 downto 0);
SIGNAL wb0_state : std_logic_vector(7 downto 0);
SIGNAL epif_tx_state : std_logic_vector(7 downto 0);
SIGNAL epif_rx_state : std_logic_vector(7 downto 0);
SIGNAL bit10 : std_logic_vector(1 downto 0);
 
SIGNAL bram_rxtlp_we : std_logic_vector(0 downto 0);
SIGNAL bram_rxtlp_writeaddress : std_logic_vector(31 downto 0);
SIGNAL bram_rxtlp_writedata : std_logic_vector(31 downto 0);
SIGNAL bram_rxtlp_readaddress : std_logic_vector(31 downto 0);
SIGNAL bram_rxtlp_readdata : std_logic_vector(31 downto 0);
SIGNAL bram_txtlp_we : std_logic_vector(0 downto 0);
SIGNAL bram_txtlp_writeaddress : std_logic_vector(8 downto 0);
SIGNAL bram_txtlp_writedata : std_logic_vector(31 downto 0);
SIGNAL bram_txtlp_readaddress : std_logic_vector(31 downto 0);
SIGNAL bram_txtlp_readdata : std_logic_vector(31 downto 0);
SIGNAL tlp_datacount : std_logic_vector(7 downto 0);
--SIGNAL bram_rxtlp_firstdata_address : std_logic_vector(8 downto 0);
SIGNAL rxtlp_header_dw1 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_header_dw2 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_header_dw3 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_header_dw4 : std_logic_vector(31 downto 0);
SIGNAL flag1 : std_logic;
SIGNAL rxdw1_23_0 : std_logic_vector(23 downto 0);
SIGNAL pcie_rxtlp_tag : std_logic_vector(7 downto 0);
SIGNAL pciewb_localreset_n : std_logic;
SIGNAL cfg_interrupt_assert_n_1 : std_logic;
SIGNAL trn_tsrc_rdy_n_1 : std_logic;
SIGNAL trn_tsof_n1 : std_logic;
SIGNAL rcompl_bytecount_field : std_logic_vector(9 downto 0);
-- COMPONENT DECLARATIONS (introducing the IPs) --------------------------------
 
--this is the pcie endpoint core from coregenerator.
--Core name: Xilinx Spartan-6 Integrated
--Block for PCI Express
--Version: 1.2
--Release Date: September 16, 2009. ISE DS 11.4
component pcie is
generic (
TL_TX_RAM_RADDR_LATENCY : integer := 0;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_RADDR_LATENCY : integer := 0;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 0;
VC0_TX_LASTPACKET : integer := 14;
VC0_RX_RAM_LIMIT : bit_vector := x"7FF";
VC0_TOTAL_CREDITS_PH : integer := 32;
VC0_TOTAL_CREDITS_PD : integer := 211;
VC0_TOTAL_CREDITS_NPH : integer := 8;
VC0_TOTAL_CREDITS_CH : integer := 40;
VC0_TOTAL_CREDITS_CD : integer := 211;
VC0_CPL_INFINITE : boolean := TRUE;
BAR0 : bit_vector := x"F0000000";
BAR1 : bit_vector := x"00000000";
BAR2 : bit_vector := x"00000000";
BAR3 : bit_vector := x"00000000";
BAR4 : bit_vector := x"00000000";
BAR5 : bit_vector := x"00000000";
EXPANSION_ROM : bit_vector := "0000000000000000000000";
DISABLE_BAR_FILTERING : boolean := FALSE;
DISABLE_ID_CHECK : boolean := FALSE;
TL_TFC_DISABLE : boolean := FALSE;
TL_TX_CHECKS_DISABLE : boolean := FALSE;
USR_CFG : boolean := FALSE;
USR_EXT_CFG : boolean := FALSE;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
CLASS_CODE : bit_vector := x"068000";
CARDBUS_CIS_POINTER : bit_vector := x"00000000";
PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1";
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"1";
PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE;
PCIE_CAP_INT_MSG_NUM : bit_vector := "00000";
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7;
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7;
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
LINK_CAP_ASPM_SUPPORT : integer := 1;
LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
LINK_CAP_L1_EXIT_LATENCY : integer := 7;
LL_ACK_TIMEOUT : bit_vector := x"0204";
LL_ACK_TIMEOUT_EN : boolean := FALSE;
LL_REPLAY_TIMEOUT : bit_vector := x"0204";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
MSI_CAP_MULTIMSGCAP : integer := 0;
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
PLM_AUTO_CONFIG : boolean := FALSE;
FAST_TRAIN : boolean := FALSE;
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
DISABLE_SCRAMBLING : boolean := FALSE;
PM_CAP_VERSION : integer := 3;
PM_CAP_PME_CLOCK : boolean := FALSE;
PM_CAP_DSI : boolean := FALSE;
PM_CAP_AUXCURRENT : integer := 0;
PM_CAP_D1SUPPORT : boolean := TRUE;
PM_CAP_D2SUPPORT : boolean := TRUE;
PM_CAP_PMESUPPORT : bit_vector := x"0F";
PM_DATA0 : bit_vector := x"04";
PM_DATA_SCALE0 : bit_vector := x"0";
PM_DATA1 : bit_vector := x"00";
PM_DATA_SCALE1 : bit_vector := x"0";
PM_DATA2 : bit_vector := x"00";
PM_DATA_SCALE2 : bit_vector := x"0";
PM_DATA3 : bit_vector := x"00";
PM_DATA_SCALE3 : bit_vector := x"0";
PM_DATA4 : bit_vector := x"04";
PM_DATA_SCALE4 : bit_vector := x"0";
PM_DATA5 : bit_vector := x"00";
PM_DATA_SCALE5 : bit_vector := x"0";
PM_DATA6 : bit_vector := x"00";
PM_DATA_SCALE6 : bit_vector := x"0";
PM_DATA7 : bit_vector := x"00";
PM_DATA_SCALE7 : bit_vector := x"0";
PCIE_GENERIC : bit_vector := "000011101111";
GTP_SEL : integer := 0;
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"ABCD";
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234";
REF_CLK_FREQ : integer := 0
);
port (
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
 
-- Transaction (TRN) Interface
trn_lnk_up_n : out std_logic;
 
-- Tx
trn_td : in std_logic_vector(31 downto 0);
trn_tsof_n : in std_logic;
trn_teof_n : in std_logic;
trn_tsrc_rdy_n : in std_logic;
trn_tdst_rdy_n : out std_logic;
trn_terr_drop_n : out std_logic;
trn_tsrc_dsc_n : in std_logic;
trn_terrfwd_n : in std_logic;
trn_tbuf_av : out std_logic_vector(5 downto 0);
trn_tstr_n : in std_logic;
trn_tcfg_req_n : out std_logic;
trn_tcfg_gnt_n : in std_logic;
 
-- Rx
trn_rd : out std_logic_vector(31 downto 0);
trn_rsof_n : out std_logic;
trn_reof_n : out std_logic;
trn_rsrc_rdy_n : out std_logic;
trn_rsrc_dsc_n : out std_logic;
trn_rdst_rdy_n : in std_logic;
trn_rerrfwd_n : out std_logic;
trn_rnp_ok_n : in std_logic;
trn_rbar_hit_n : out std_logic_vector(6 downto 0);
trn_fc_sel : in std_logic_vector(2 downto 0);
trn_fc_nph : out std_logic_vector(7 downto 0);
trn_fc_npd : out std_logic_vector(11 downto 0);
trn_fc_ph : out std_logic_vector(7 downto 0);
trn_fc_pd : out std_logic_vector(11 downto 0);
trn_fc_cplh : out std_logic_vector(7 downto 0);
trn_fc_cpld : out std_logic_vector(11 downto 0);
 
-- Host (CFG) Interface
cfg_do : out std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : out std_logic;
cfg_dwaddr : in std_logic_vector(9 downto 0);
cfg_rd_en_n : in std_logic;
cfg_err_ur_n : in std_logic;
cfg_err_cor_n : in std_logic;
cfg_err_ecrc_n : in std_logic;
cfg_err_cpl_timeout_n : in std_logic;
cfg_err_cpl_abort_n : in std_logic;
cfg_err_posted_n : in std_logic;
cfg_err_locked_n : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : out std_logic;
cfg_interrupt_n : in std_logic;
cfg_interrupt_rdy_n : out std_logic;
cfg_interrupt_assert_n : in std_logic;
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_turnoff_ok_n : in std_logic;
cfg_to_turnoff_n : out std_logic;
cfg_pm_wake_n : in std_logic;
cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
cfg_trn_pending_n : in std_logic;
cfg_dsn : in std_logic_vector(63 downto 0);
cfg_bus_number : out std_logic_vector(7 downto 0);
cfg_device_number : out std_logic_vector(4 downto 0);
cfg_function_number : out std_logic_vector(2 downto 0);
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
 
-- System Interface
sys_clk : in std_logic;
sys_reset_n : in std_logic;
trn_clk : out std_logic;
trn_reset_n : out std_logic;
received_hot_reset : out std_logic
);
end component pcie;
 
COMPONENT blk_mem_gen_v4_1
PORT(
clka : IN std_logic;
wea : IN std_logic_vector(0 to 0);
addra : IN std_logic_vector(8 downto 0);
dina : IN std_logic_vector(31 downto 0);
clkb : IN std_logic;
addrb : IN std_logic_vector(8 downto 0);
doutb : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
 
 
---- ------- SYNTHESIS ATTRIBUTES: --------------------------------------------------
--attribute keep_hierarchy : string;
--attribute keep_hierarchy of xilinx_pcie2wb: entity is "yes";
 
 
 
-- --------ARCHITECTURE BODY BEGINS -----------------------------------------------
begin
 
 
cfg_turnoff_ok_n <= '1';
 
-- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------------
 
 
-- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------------
 
inst_pcie : pcie
port map (
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
trn_lnk_up_n => trn_lnk_up_n,
trn_td => trn_td, -- Bus [31 : 0]
trn_tsof_n => trn_tsof_n,
trn_teof_n => trn_teof_n,
trn_tsrc_rdy_n => trn_tsrc_rdy_n,
trn_tdst_rdy_n => trn_tdst_rdy_n,
trn_terr_drop_n => trn_terr_drop_n,
trn_tsrc_dsc_n => trn_tsrc_dsc_n,
trn_terrfwd_n => trn_terrfwd_n,
trn_tbuf_av => trn_tbuf_av, -- Bus [31 : 0]
trn_tstr_n => trn_tstr_n,
trn_tcfg_req_n => trn_tcfg_req_n,
trn_tcfg_gnt_n => trn_tcfg_gnt_n,
trn_rd => trn_rd, -- Bus [31 : 0]
trn_rsof_n => trn_rsof_n,
trn_reof_n => trn_reof_n,
trn_rsrc_rdy_n => trn_rsrc_rdy_n,
trn_rsrc_dsc_n => trn_rsrc_dsc_n,
trn_rdst_rdy_n => trn_rdst_rdy_n,
trn_rerrfwd_n => trn_rerrfwd_n,
trn_rnp_ok_n => trn_rnp_ok_n,
trn_rbar_hit_n => trn_rbar_hit_n, -- Bus [31 : 0]
trn_fc_sel => trn_fc_sel, -- Bus [31 : 0]
trn_fc_nph => trn_fc_nph, -- Bus [31 : 0]
trn_fc_npd => trn_fc_npd, -- Bus [31 : 0]
trn_fc_ph => trn_fc_ph, -- Bus [31 : 0]
trn_fc_pd => trn_fc_pd, -- Bus [31 : 0]
trn_fc_cplh => trn_fc_cplh, -- Bus [31 : 0]
trn_fc_cpld => trn_fc_cpld, -- Bus [31 : 0]
cfg_do => cfg_do, -- Bus [31 : 0]
cfg_rd_wr_done_n => cfg_rd_wr_done_n,
cfg_dwaddr => cfg_dwaddr, -- Bus [31 : 0]
cfg_rd_en_n => cfg_rd_en_n,
cfg_err_ur_n => cfg_err_ur_n,
cfg_err_cor_n => cfg_err_cor_n,
cfg_err_ecrc_n => cfg_err_ecrc_n,
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n => cfg_err_cpl_abort_n,
cfg_err_posted_n => cfg_err_posted_n,
cfg_err_locked_n => cfg_err_locked_n,
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header, -- Bus [31 : 0]
cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n,
cfg_interrupt_n => cfg_interrupt_n,
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
cfg_interrupt_assert_n => cfg_interrupt_assert_n,
cfg_interrupt_do => cfg_interrupt_do, -- Bus [31 : 0]
cfg_interrupt_di => cfg_interrupt_di, -- Bus [31 : 0]
cfg_interrupt_mmenable => cfg_interrupt_mmenable, -- Bus [31 : 0]
cfg_interrupt_msienable => cfg_interrupt_msienable,
cfg_turnoff_ok_n => cfg_turnoff_ok_n,
cfg_to_turnoff_n => cfg_to_turnoff_n,
cfg_pm_wake_n => cfg_pm_wake_n,
cfg_pcie_link_state_n => cfg_pcie_link_state_n, -- Bus [31 : 0]
cfg_trn_pending_n => cfg_trn_pending_n,
cfg_dsn => cfg_dsn, -- Bus [31 : 0]
cfg_bus_number => cfg_bus_number, -- Bus [31 : 0]
cfg_device_number => cfg_device_number, -- Bus [31 : 0]
cfg_function_number => cfg_function_number, -- Bus [31 : 0]
cfg_status => cfg_status, -- Bus [31 : 0]
cfg_command => cfg_command, -- Bus [31 : 0]
cfg_dstatus => cfg_dstatus, -- Bus [31 : 0]
cfg_dcommand => cfg_dcommand, -- Bus [31 : 0]
cfg_lstatus => cfg_lstatus, -- Bus [31 : 0]
cfg_lcommand => cfg_lcommand, -- Bus [31 : 0]
sys_clk => sys_clk,
sys_reset_n => sys_reset_n,
trn_clk => trn_clk,
trn_reset_n => trn_reset_n,
received_hot_reset => received_hot_reset
);
 
--block ram for RX TLP:
Inst_bram_rxtlp: blk_mem_gen_v4_1 PORT MAP(
clka => trn_clk,
wea => bram_rxtlp_we,
addra => bram_rxtlp_writeaddress(8 downto 0),
dina => bram_rxtlp_writedata,
clkb => trn_clk,
addrb => bram_rxtlp_readaddress(8 downto 0),
doutb => bram_rxtlp_readdata
);
 
--block ram for TX TLP:
Inst_bram_txtlp: blk_mem_gen_v4_1 PORT MAP(
clka => trn_clk,
wea => bram_txtlp_we,
addra => bram_txtlp_writeaddress(8 downto 0),
dina => bram_txtlp_writedata,
clkb => trn_clk,
addrb => bram_txtlp_readaddress(8 downto 0),
doutb => bram_txtlp_readdata
);
 
 
 
 
 
-- MAIN LOGIC: ---------------------------------------------------------------------------------------------
--System Signals:--------------------------------
--Clock Input Buffer for differential system clock
IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => sys_clk, -- Buffer output
I => sys_clk_p, -- Diff_p buffer input (connect directly to top-level port)
IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port)
);
 
--wishbone clock output:
pcie_bar0_wb_clk_o <= trn_clk;
--pcie_bar1_wb_clk_o <= trn_clk;
 
--use one of these for resetting logic in this file:
pciewb_localreset_n <= sys_reset_n; --dont wait for the PCIE-EP to finish its init.
--pciewb_localreset_n <= trn_reset_n;
--pciewb_localreset_n <= trn_reset_n and (not trn_lnk_up_n) and (not received_hot_reset);
--reset to the core:
--sys_reset_n comes from toplevel directly to the core. same name
--reset output to other cores:
pcie_resetout <= not pciewb_localreset_n;
--trn_lnk_up_n --not used.
 
--pcie ep ip config port: ----------------------------------------------------------
--trn_fc_sel <= "000";
 
trn_rnp_ok_n <= '0';
--trn_terrfwd_n <= '1';
 
--trn_tcfg_gnt_n <= '0';
 
cfg_err_cor_n <= '1';
cfg_err_ur_n <= '1';
cfg_err_ecrc_n <= '1';
cfg_err_cpl_timeout_n <= '1';
cfg_err_cpl_abort_n <= '1';
cfg_err_posted_n <= '0';
cfg_err_locked_n <= '1';
cfg_pm_wake_n <= '1';
cfg_trn_pending_n <= '1';
 
--trn_tstr_n <= '0';
--cfg_interrupt_assert_n <= '1'; --used in a process at the bottom of this file
--cfg_interrupt_n <= '1';
--cfg_interrupt_di <= x"00"; --intA used
 
cfg_err_tlp_cpl_header <= (OTHERS => '0');
cfg_dwaddr <= (OTHERS => '0');
cfg_rd_en_n <= '1';
--serial number:
cfg_dsn <= (OTHERS => '0');
 
-- AT THE BOTTOM OF THIS FILE:
-- --some fix values:
-- trn_tsrc_dsc_n <= '1'; --no errors on trn bus
-- trn_tstr_n <= '0'; --pipelining (0= link may begin before the entire packet has been written)
-- trn_tcfg_gnt_n <= '0'; --no tlp priorities
-- trn_terrfwd_n <= '1'; --no errors on trn
-- --nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n
 
 
 
--use this in read completion packets:
cfg_completer_id <= cfg_bus_number & cfg_device_number & cfg_function_number;
 
 
 
 
 
-- WISBONE BACK-end INTERFACE ----------------------------------------------------
 
--main state machine: set states, capture inputs, set addr/data outputs
--minimum 2 clock cycles / transaction. writes are posted, reads have wait states.
process (pciewb_localreset_n, trn_clk, wb0_state, start_read_wb0, start_write_wb0,
pcie_bar0_wb_addr_o_feed, pcie_bar0_wb_data_o_feed, pcie_bar0_wb_sel_o_feed)
begin
if (pciewb_localreset_n='0') then
wb0_state <= "00000000";
wb_transaction_complete <= '0';
pcie_bar0_wb_addr_o <= "0000000000000000000000000000";
pcie_bar0_wb_sel_o <= "0000";
pcie_bar0_wb_data_o <= "00000000000000000000000000000000";
wb_transaction_complete <='0';
else
if (trn_clk'event and trn_clk = '1') then
case ( wb0_state ) is
 
--********** IDLE STATE **********
when "00000000" => --state 0
wb_transaction_complete <='0';
pcie_bar0_wb_sel_o(0) <= pcie_bar0_wb_sel_o_feed(3); --swap endianism
pcie_bar0_wb_sel_o(1) <= pcie_bar0_wb_sel_o_feed(2); --swap endianism
pcie_bar0_wb_sel_o(2) <= pcie_bar0_wb_sel_o_feed(1); --swap endianism
pcie_bar0_wb_sel_o(3) <= pcie_bar0_wb_sel_o_feed(0); --swap endianism
--or no endian swap on SEL: pcie_bar0_wb_sel_o <= pcie_bar0_wb_sel_o_feed;
pcie_bar0_wb_addr_o <= pcie_bar0_wb_addr_o_feed;
if (start_read_wb0 ='1') then --go to read
wb0_state <= "00000001";
elsif (start_write_wb0 ='1') then --go to write
wb0_state <= "00000010";
--no endian swap: pcie_bar0_wb_data_o <= pcie_bar0_wb_data_o_feed;
pcie_bar0_wb_data_o (7 downto 0) <= pcie_bar0_wb_data_o_feed(31 downto 24); --swap endianism
pcie_bar0_wb_data_o (15 downto 8) <= pcie_bar0_wb_data_o_feed(23 downto 16); --swap endianism
pcie_bar0_wb_data_o (23 downto 16) <= pcie_bar0_wb_data_o_feed(15 downto 8); --swap endianism
pcie_bar0_wb_data_o (31 downto 24) <= pcie_bar0_wb_data_o_feed(7 downto 0); --swap endianism
end if;
 
--********** READ STATE **********
--set the outputs,
--if ACK asserted, sample the data input
--The hold requirements are oversatisfyed by going back to idle, and by the fact that the slave uses the cyc/stb/wr strobes synchronously.
when "00000001" => --state 1
if (pcie_bar0_wb_ack_i='1') then
--no endian swap: pcie_bar0_wb_data_i_latched <= pcie_bar0_wb_data_i; --sample the incoming data
pcie_bar0_wb_data_i_latched (7 downto 0) <= pcie_bar0_wb_data_i(31 downto 24); --swap endianism
pcie_bar0_wb_data_i_latched (15 downto 8) <= pcie_bar0_wb_data_i(23 downto 16); --swap endianism
pcie_bar0_wb_data_i_latched (23 downto 16) <= pcie_bar0_wb_data_i(15 downto 8); --swap endianism
pcie_bar0_wb_data_i_latched (31 downto 24) <= pcie_bar0_wb_data_i(7 downto 0); --swap endianism
wb_transaction_complete <='1'; --signalling ready, but only for one clock cycle
wb0_state <= "00000000"; --go to state 0
else
wb_transaction_complete <='0';
end if;
 
--********** WRITE STATE **********
--if ACK asserted, go back to idle
--The hold requirements are oversatisfyed by waiting for ACK to remove write data
when "00000010" => --state 2
if (pcie_bar0_wb_ack_i='1') then
wb0_state <= "00000000"; --go to state 0
wb_transaction_complete <='1';
else
wb_transaction_complete <='0';
end if;
when others => --error
wb0_state <= "00000000"; --go to state 0
end case;
end if;
end if;
end process;
--sync control on wb-control signals:
process (pciewb_localreset_n, wb0_state)
begin
if (pciewb_localreset_n='0') then
pcie_bar0_wb_cyc_o <= '0';
pcie_bar0_wb_stb_o <= '0';
pcie_bar0_wb_wr_o <= '0';
else
if (wb0_state = "00000000") then --idle
pcie_bar0_wb_cyc_o <= '0';
pcie_bar0_wb_stb_o <= '0';
pcie_bar0_wb_wr_o <= '0';
elsif (wb0_state = "00000001") then --read
pcie_bar0_wb_cyc_o <= '1';
pcie_bar0_wb_stb_o <= '1';
pcie_bar0_wb_wr_o <= '0';
elsif (wb0_state = "00000010") then --write
pcie_bar0_wb_cyc_o <= '1';
pcie_bar0_wb_stb_o <= '1';
pcie_bar0_wb_wr_o <= '1';
else
pcie_bar0_wb_cyc_o <= '0';
pcie_bar0_wb_stb_o <= '0';
pcie_bar0_wb_wr_o <= '0';
end if;
end if;
end process;
 
 
 
 
 
 
 
 
-- INTERFACE TO THE PCIE-EP IP --------------------------------------------------------
--trn_clk and trn_reset_n are the same as the pcie_resetout and pcie_bar0_wb_clk_o,
--so it is not a clock domain crossing.
 
 
-- TX: INTERFACE TO THE PCIE-EP: TRANSMIT TLP PACKETS:-----
--Read completion is 3DW header. This core only transmits read completion or Unbsupported request packets.
process (pciewb_localreset_n, trn_clk, epif_tx_state, bram_txtlp_readdata , bram_txtlp_readaddress,
pcie_there_is_a_new_tlp_to_transmit, tlp_payloadsize_dwords, txtrn_counter)
begin
if (pciewb_localreset_n='0') then
epif_tx_state <= "00000000";
trn_tsrc_rdy_n_1 <='1';
trn_tsof_n1 <= '1';
trn_teof_n <= '1';
trn_td <= (OTHERS => '0');
pcie_tlp_tx_complete <= '0';
txtrn_counter <= "00000001";
bram_txtlp_readaddress <= (OTHERS => '0');
else
if (trn_clk'event and trn_clk = '1') then
case ( epif_tx_state ) is
 
--********** idle STATE **********
when "00000000" => --state 0
--if there is a new TLP assembled and the EP is ready,
--start the tx-trn bus transaction.
if (pcie_there_is_a_new_tlp_to_transmit='1') then
epif_tx_state <= "00000001"; --next state
end if;
trn_tsrc_rdy_n_1 <='1';
trn_tsof_n1 <= '1';
trn_teof_n <= '1';
trn_td <= (OTHERS => '0');
pcie_tlp_tx_complete <= '0';
txtrn_counter <= "00000001";
bram_txtlp_readaddress <= (OTHERS => '0');
 
--********** ready-wait STATE **********
when "00000001" => --state 1
--if there is a new TLP assembled and the EP is ready,
--start the tx-trn bus transaction.
if (trn_tdst_rdy_n='0') then
epif_tx_state <= "00000010"; --next state
end if;
trn_tsrc_rdy_n_1 <='1';
trn_tsof_n1 <= '1';
trn_teof_n <= '1';
trn_td <= (OTHERS => '0');
pcie_tlp_tx_complete <= '0';
txtrn_counter <= "00000001";
bram_txtlp_readaddress <= (OTHERS => '0');
--********** transfer STATE **********
when "00000010" => --state 2
trn_tsrc_rdy_n_1 <='0';
trn_td <= bram_txtlp_readdata;
if (trn_tdst_rdy_n='0') then
txtrn_counter <= txtrn_counter +1;
bram_txtlp_readaddress <= bram_txtlp_readaddress +1;
end if;
if (txtrn_counter = "00000010") then
trn_tsof_n1 <= '0'; --start
else
trn_tsof_n1 <= '1';
end if;
--test number of dwords:
if (txtrn_counter = tlp_payloadsize_dwords +4) then -- "+3" is the header and "+1" is for the delay
--this is the last dword, next clk is next state
epif_tx_state <= "00000000"; --back to idle, since finished
trn_teof_n <= '0'; --end
pcie_tlp_tx_complete <= '1'; --assert for 1 clk
else
trn_teof_n <= '1'; --not end yet
pcie_tlp_tx_complete <= '0'; --not complete yet
end if;
 
when others => --error
epif_tx_state <= "00000000"; --back to idle
trn_tsrc_rdy_n_1 <='1';
trn_tsof_n1 <= '1';
trn_teof_n <= '1';
trn_td <= (OTHERS => '0');
pcie_tlp_tx_complete <= '0';
txtrn_counter <= "00000001";
end case;
end if;
end if;
end process;
--this (little delay) is to fix a hold time violation created inside the pcie-ep ip:
trn_tsrc_rdy_n <= trn_tsrc_rdy_n_1 or (not pciewb_localreset_n);
trn_tsof_n <= trn_tsof_n1 or (not pciewb_localreset_n);
 
 
--some fix values:
trn_tsrc_dsc_n <= '1'; --no errors on trn bus
trn_tstr_n <= '0'; --pipelining
trn_tcfg_gnt_n <= '0'; --no tlp priorities
trn_terrfwd_n <= '1'; --no errors on trn
--nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n
 
 
 
 
 
-- RX: INTERFACE TO THE PCIE-EP: GET thereceived TLP PACKETS:- ----
process (pciewb_localreset_n, trn_clk, epif_rx_state, tlp_state, trn_rx_counter, bram_rxtlp_writeaddress)
begin
if (pciewb_localreset_n='0') then
pcie_just_received_a_new_tlp <= '0';
epif_rx_state <= "00000000";
trn_rdst_rdy_n <= '1';
trn_rx_counter <= (OTHERS => '0');
bram_rxtlp_we <= "0";
bram_rxtlp_writeaddress <= (OTHERS => '0');
bram_rxtlp_writedata <= (OTHERS => '0');
else
if (trn_clk'event and trn_clk = '1') then
 
if (tlp_state = 0)then
trn_rdst_rdy_n <= '0';
else
trn_rdst_rdy_n <= '1';
end if;
case ( epif_rx_state ) is
 
--********** idle STATE **********
when "00000000" => --state 0
pcie_just_received_a_new_tlp <= '0';
bram_rxtlp_writedata <= trn_rd;
if (trn_rsrc_rdy_n='0' and trn_rsof_n='0') then
trn_rx_counter <= trn_rx_counter +1;
bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1;
epif_rx_state <= "00000001";
--read first DW:
bram_rxtlp_we <= "1";
else
trn_rx_counter <= (OTHERS => '0');
bram_rxtlp_writeaddress <= (OTHERS => '0');
bram_rxtlp_we <= "0";
end if;
 
--********** read STATE **********
when "00000001" => --state 1
if (trn_reof_n ='0') then --last dw
epif_rx_state <= "00000010"; --for the next clk cycle
end if;
if (trn_rsrc_rdy_n='0') then --only act if the EP was ready
trn_rx_counter <= trn_rx_counter +1;
bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1;
bram_rxtlp_writedata <= trn_rd;
end if;
--in an early stage of this transfer, the scheduler can already
--start working on the data, this way its pipelined, so the latency is lower.
if (trn_rx_counter = "00000010") then
pcie_just_received_a_new_tlp <= '1';--assert for one clk only
else
pcie_just_received_a_new_tlp <= '0';
end if;
 
--********** finished filling up RX TLP STATE **********
when "00000010" => --state 2
epif_rx_state <= "00000000";
trn_rx_counter <= (OTHERS => '0');
when others => --error
epif_rx_state <= "00000000"; --go to state 0
end case;
end if;
end if;
end process;
--fixed connections:
--trn_rnp_ok_ntrn_rnp_ok_n <= '0'; --ready to receive non-posted
--not connected: trn_rerrfwd_n, trn_rsrc_dsc_n, trn_rbar_hit_n
 
 
 
 
 
-- flow control: INTERFACE TO THE PCIE-EP: - ----
--not used. pcie-ep provides information about credit status.
--unconnected: trn_fc_nph, trn_fc_npd, trn_fc_ph, trn_fc_pd, trn_fc_cplh, trn_fc_cpld
trn_fc_sel <= "000";
 
 
 
 
 
-- --- GLUE LOGIC BETWEEN THE PCIE CORE-IF AND THE WB INTERFACES -----------------------
-- --- ALSO TLP PACKET PROCESSING.
--Theory of operation:
--RX: If we receive a TLP (pcie_just_received_a_new_tlp goes high for one clock cycle),
--then store it (pcie_received_tlp), decode it (to figure out if its read request,
--posted write or non-supported request), then assert a flag (start_write_wb0 or
--start_read_wb0)to initiate a wishbone cycle.
--TX: At the completion of a wishbone read, the wishbone statemachine asserts the
--wb_transaction_complete flag, so we can assemble the TX TLP packet (pcie_to_transmit_tlp)
--and assert the flag named pcie_there_is_a_new_tlp_to_transmit. This packet will be
--a read completion packet on the PCIe link.
--
--This core can handle 1...8 DWORD accesses in one request (max 256bit payload ),
--and can handle only one request at a time. If a new request is arriving while
--processing the previous one (e.g. getting the data from a wishbone read), then
--the state machine will not process it immediately, or it will hang. So the user
--software has to wait for the previous read completion before issueing a new request.
--The multiple DWORDs are handled separately by the WB statemachine.
--Performance: WishBone bus: 62.5MHz, 32bit, 3clk/access -> 83MBytes/sec
--
--TLP decoding:
--Header+Payload_data+TLP_DIGEST(ECRC).
--received Header:
--First Dword: bit.30/29=format: 00=3DW-header+no_data, 01=4DW-header+no_data,
--10=3DW-header+data, 11=4DW-header+data. bit.28:24=type: 00000 or 00001 are memory
--read requests, 00000 or 00001 are memory write request if type=1x. read request
--completion is 01010 and type=10. bit.9:0 is payload size [DW].
--Second Dword: bit.31:16 is requester ID. bit3:0 is first dword byte enable, bit.7:4 is
--byte enable for last dword data. intermediate dwords have all bytes enabled.
--Third DWORD: address, where bit.1:0=00b. 4DW headers are for 64bit. 64bit adressing
--uses 3rd-dword for addre63:32, 4th dword for addr31:0.
--
--The TLP variables in this core: BRAM memory used store TLP, up to 1-2kBytes
--
--Read completion is 3DW header and routed by completer-ID and requester-ID, not address.
--The core has to store the requester ID and feed it back in the completion packet.
--Completion status: 000=successful, 100=completer_abort, 001=unsupported request. byte
--count is N.of bytes left. lower_address is the first enabled byte of data returned
--with the Completion.
--
-- Completion packet header:
--DW1 >
--7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
--r FMT type----- r TC--- reserv- T E att r r lenght-------------
-- x 0 D P rib
--DW2 >
--7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
--COMPLETER_ID------------------- statu B byte_count-------------
-- CM
--DW3 >
--7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
--REQUESTER_ID------------------- tag------------ r lower_address
 
 
--TLP-protocol statemachine:
process (pciewb_localreset_n, trn_clk, tlp_state,
pcie_just_received_a_new_tlp, tlp_datacount,
bram_rxtlp_readdata, bram_txtlp_writeaddress, bram_rxtlp_readaddress,
tlp_state_copy, rxtlp_decodedaddress,
rxtlp_header_dw1, rxtlp_header_dw2, rxtlp_header_dw3, rxtlp_header_dw4,
bit10, rxtlp_firstdw_be, wb_transaction_complete, flag1, rxdw1_23_0, pcie_rxtlp_tag,
tlp_payloadsize_dwords, pcie_bar0_wb_data_i_latched, cfg_completer_id,
rxtlp_requesterid)
begin
if (pciewb_localreset_n='0') then
start_read_wb0 <= '0';
start_write_wb0 <= '0';
pcie_bar0_wb_data_o_feed <= (others => '0');
pcie_bar0_wb_addr_o_feed <= (others => '0');
pcie_bar0_wb_sel_o_feed <= (others => '0');
pcie_there_is_a_new_tlp_to_transmit <= '0';
rxtlp_decodedaddress<= (others => '0');
tlp_payloadsize_dwords <= (others => '0');
rxtlp_firstdw_be <= (others => '0');
rxtlp_lastdw_be <= (others => '0');
rxtlp_requesterid <= (others => '0');
tlp_state <= (others => '0');
tlp_state_copy <= (others => '0');
bram_txtlp_we <= "0";
bram_txtlp_writeaddress <= (others => '0');
bram_txtlp_writedata <= (others => '0');
bram_rxtlp_readaddress <= (others => '0');
rxtlp_header_dw1 <= "01111111000000000000000000000000";
rxtlp_header_dw2 <= (others => '0');
rxtlp_header_dw3 <= (others => '0');
rxtlp_header_dw4 <= (others => '0');
flag1 <= '0';
rxdw1_23_0 <= (others => '0');
pcie_rxtlp_tag <= (others => '0');
rcompl_bytecount_field <= (others => '0');
else
if (trn_clk'event and trn_clk = '1') then
case ( tlp_state ) is
 
--********** IDLE STATE **********
--also re-initialize signals...
when "00000000" => --state 0
if (pcie_just_received_a_new_tlp='1') then
tlp_state <= "00000001"; --to tlp decoding state
end if;
start_write_wb0 <= '0';
start_read_wb0 <= '0';
tlp_state_copy <= tlp_state;
bram_txtlp_we <= "0";
bram_txtlp_writeaddress <= (others => '0');
bram_txtlp_writedata <= (others => '0');
bram_rxtlp_readaddress <= (others => '0');
tlp_datacount <= "00000001";
rxtlp_header_dw1 <= "01111111000000000000000000000000"; --this is to prevent false decode
pcie_bar0_wb_data_o_feed <= (others => '0');
pcie_bar0_wb_addr_o_feed <= (others => '0');
pcie_bar0_wb_sel_o_feed <= (others => '0');
rxtlp_header_dw1 <= "01111111000000000000000000000000";
rxtlp_header_dw2 <= (others => '0');
rxtlp_header_dw3 <= (others => '0');
rxtlp_header_dw4 <= (others => '0');
rxdw1_23_0 <= (others => '0');
pcie_rxtlp_tag <= (others => '0');
pcie_there_is_a_new_tlp_to_transmit <= '0';
rxtlp_decodedaddress<= (others => '0');
tlp_payloadsize_dwords <= (others => '0');
rxtlp_firstdw_be <= (others => '0');
rxtlp_lastdw_be <= (others => '0');
rxtlp_requesterid <= (others => '0');
rcompl_bytecount_field <= (others => '0');
 
 
--********** TLP ARRIVED STATE **********
--read TLP out of EP, decode and decide,
--latch address/sel/wr_data
--All the "IF"-statements use address+1, because the BRAM read side has data available 1clk late!!!
--Added an ectra clock delay, based on testing, since the data is one more CLK late.
when "00000001" => --state 1
--latch the header:
bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
if (bram_rxtlp_readaddress = "000000010") then
rxtlp_header_dw1 <= bram_rxtlp_readdata;
elsif (bram_rxtlp_readaddress = "000000011") then
rxtlp_header_dw2 <= bram_rxtlp_readdata;
elsif (bram_rxtlp_readaddress = "000000100") then
rxtlp_header_dw3 <= bram_rxtlp_readdata;
elsif (bram_rxtlp_readaddress = "000000101") then
rxtlp_header_dw4 <= bram_rxtlp_readdata;
end if;
--decode some parameters:
tlp_payloadsize_dwords <= rxtlp_header_dw1(7 downto 0);
rxtlp_firstdw_be <= rxtlp_header_dw2(3 downto 0);
rxtlp_lastdw_be <= rxtlp_header_dw2(7 downto 4);
rxtlp_requesterid <= rxtlp_header_dw2(31 downto 16);
flag1 <= rxtlp_header_dw1(31);
rxdw1_23_0 <= rxtlp_header_dw1(23 downto 0); --various fields pcie_received_tlp (22 downto 0);
pcie_rxtlp_tag <= rxtlp_header_dw2(15 downto 8) ; --pcie_received_tlp (47 downto 40);--tag
--decide based on header:
if (rxtlp_header_dw1(30 downto 24)="0000000") then --32bit read
if (bram_rxtlp_readaddress = "000000100") then
rxtlp_decodedaddress <= bram_rxtlp_readdata;
bram_txtlp_writeaddress(8 downto 0) <= "000000011"; --point after the 3dw readcompl header
tlp_state <= "00000011";
end if;
elsif (rxtlp_header_dw1(30 downto 24)="0100000") then --64bit read
if (bram_rxtlp_readaddress = "000000101") then
rxtlp_decodedaddress <= bram_rxtlp_readdata;
bram_txtlp_writeaddress(8 downto 0) <= "000000011"; --point after the 3dw readcompl header
tlp_state <= "00000011";
end if;
elsif (rxtlp_header_dw1(30 downto 24)="1000000") then --32bit write
if (bram_rxtlp_readaddress = "000000100") then
rxtlp_decodedaddress <= bram_rxtlp_readdata;
tlp_state <= "00000010";
end if;
elsif (rxtlp_header_dw1(30 downto 24)="1100000") then --64bit write
if (bram_rxtlp_readaddress = "000000101") then
rxtlp_decodedaddress <= bram_rxtlp_readdata;
tlp_state <= "00000010";
end if;
elsif (rxtlp_header_dw1(30 downto 24)="1111111") then --just wait until this gets a real value
rxtlp_decodedaddress <= bram_rxtlp_readdata;
else --unsupported request
if (bram_rxtlp_readaddress = "000000100") then
tlp_state <= "00000101";
bram_txtlp_writeaddress <= "111111111";
end if;
end if;
 
 
--********** WRITE STATE **********
--initiate WB write(s) (1...N DWORD accesses)
when "00000010" => --state 2
pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1; --256MBytes size is hardcoded here, by cutting 4-MSB off
pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be;
pcie_bar0_wb_data_o_feed <= bram_rxtlp_readdata;
tlp_state_copy <= tlp_state;
if (tlp_state_copy = tlp_state) then
start_write_wb0 <= '0';
else --generate just one pulse, at the first clk cycle in this state
start_write_wb0 <= '1';
end if;
if (wb_transaction_complete='1') then --one DW transfer completed
if (tlp_payloadsize_dwords = tlp_datacount) then --all data completed
tlp_state <= "00000000"; --to idle
else
tlp_state <= "00010100"; --restart wb transaction with new data
bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
tlp_datacount <= tlp_datacount +1;
end if;
end if;
--* Write restart state *
when "00010100" => --state 20
tlp_state <= "00000010";
 
 
--********** READ STATE **********
--initiate WB read, then go to completion state
when "00000011" => --state 3
pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1;
pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be;
tlp_state_copy <= tlp_state;
if (tlp_state_copy = tlp_state) then
start_read_wb0 <= '0';
else --generate just one pulse
start_read_wb0 <= '1';
end if;
if (wb_transaction_complete='1') then
bram_txtlp_writedata <= pcie_bar0_wb_data_i_latched;
bram_txtlp_we <= "1";
if (tlp_payloadsize_dwords = tlp_datacount)then
tlp_state <= "01111110"; --read completion
--bram_txtlp_writeaddress remains the same to capture data in next clock cycle
else
tlp_state <= "00011110"; --one more wb read
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
tlp_datacount <= tlp_datacount +1;
end if;
else
bram_txtlp_we <= "0";
end if;
--* read restart STATE *
when "00011110" => --state 30
tlp_state <= "00000011";
bram_txtlp_we <= "0";
--intermediate state before completion (to ensure data latch at address-4)
when "01111110" => --state 126
tlp_state <= "00000100";
bram_txtlp_writeaddress <= (OTHERS => '0');
--pre-write header-DW1:
bram_txtlp_writedata (31) <= flag1; --reserved
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
--Calculate completion header's "rcompl_bytecount_field" from rxtlp_firstdw_be, rxtlp_lastdw_be, tlp_payloadsize_dwords
if (rxtlp_lastdw_be="0000") then --max 1DW
if (rxtlp_firstdw_be="1111") then --4bytes
rcompl_bytecount_field <= "0000000100";
elsif (rxtlp_firstdw_be="0111" or rxtlp_firstdw_be="1110") then
rcompl_bytecount_field <= "0000000011";
elsif (rxtlp_firstdw_be="0011" or rxtlp_firstdw_be="1100" or rxtlp_firstdw_be="0110") then
rcompl_bytecount_field <= "0000000010";
else
rcompl_bytecount_field <= "0000000001";
end if;
else --more than 1DW: right now we dont support non-aligned multi-Dword accesses
rcompl_bytecount_field(9 downto 2) <= tlp_payloadsize_dwords;
rcompl_bytecount_field(1 downto 0) <= "00";
end if;
 
 
--********** READ COMPLETION STATE **********
--assemble the tx TLP and initiate the transmit
--buffer signals bram_txtlp_we, bram_txtlp_writeaddress, bram_txtlp_writedata
when "00000100" => --state 4
tlp_state_copy <= tlp_state;
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
if (bram_txtlp_writeaddress="000000000") then --if address is 0: launch data for next lock/address(1): header-2.dw
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
bram_txtlp_writedata (15 downto 13) <= "000"; --status= succesful***
bram_txtlp_writedata (12) <= '0'; --reserved
bram_txtlp_writedata (11 downto 10) <= "00";
bram_txtlp_writedata (9 downto 0) <= rcompl_bytecount_field; --total bytes returned
bram_txtlp_we <= "1";
elsif (bram_txtlp_writeaddress="000000001") then --if address is 1: launch data for next lock/address(2): header-3.dw
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
bram_txtlp_writedata (7) <= '0'; --reserved
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0); --lower address
else --data dwords, disable writes from next clock cycle
bram_txtlp_we <= "0";
end if;
--one pulse to start the ep-if statemachine, upon arriving to this state
if (tlp_state_copy = tlp_state) then
pcie_there_is_a_new_tlp_to_transmit <= '0';
else
pcie_there_is_a_new_tlp_to_transmit <= '1';
end if;
--back to idle when the ep-if tx is finished: (wait to avoid overwrite)
if (pcie_tlp_tx_complete='1') then
tlp_state <= "00000000";
end if;
 
 
--********** UNSUPPORTED REQUEST STATE **********
--completion response with status=001
when "00000101" => --state 5
tlp_state_copy <= tlp_state;
tlp_payloadsize_dwords <= "00000000";
--assembling the TLP packet: )
if (bram_txtlp_writeaddress="111111111") then --header 1.dw
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
bram_txtlp_we <= "1";
bram_txtlp_writedata (31) <= flag1; --reserved
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
elsif (bram_txtlp_writeaddress="000000000") then --header 2.dw
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
bram_txtlp_we <= "1";
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
bram_txtlp_writedata (15 downto 13) <= "000"; --status= UNSUPPORTED REQUEST ***
bram_txtlp_writedata (12) <= '0'; --reserved
bram_txtlp_writedata (11 downto 0) <= "000000000000"; --remaining byte count
elsif (bram_txtlp_writeaddress="000000001") then --header 3.dw
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
bram_txtlp_we <= "1";
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
bram_txtlp_writedata (7) <= '0'; --reserved
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0); --lower address
else --data dwords
--2. read data : no data in this type of packet
--this was written directly during the read state.
bram_txtlp_writeaddress <= bram_txtlp_writeaddress;
bram_txtlp_we <= "0";
end if;
--one pulse to start the ep-if statemachine, upon arriving to this state
if (tlp_state_copy = tlp_state) then
pcie_there_is_a_new_tlp_to_transmit <= '0';
else
pcie_there_is_a_new_tlp_to_transmit <= '1';
end if;
--back to idle when finished:
if (pcie_tlp_tx_complete='1') then
tlp_state <= "00000000";
end if;
when others => --error
tlp_state <= "00000000"; --go to state 0
end case;
end if;
end if;
end process; --end tlp statemachine
 
 
 
 
--byte enable encoding to wb_address bit1:0
--this also takes the endian swapping into account.
process ( pciewb_localreset_n, rxtlp_firstdw_be )
begin
if (pciewb_localreset_n = '0') then
bit10(1 downto 0) <="00";
else
if (rxtlp_firstdw_be ="0001") then
bit10(1 downto 0) <= "11";
elsif (rxtlp_firstdw_be ="0010") then
bit10(1 downto 0) <= "10";
elsif (rxtlp_firstdw_be ="0100") then
bit10(1 downto 0) <= "01";
elsif (rxtlp_firstdw_be ="1000") then
bit10(1 downto 0) <= "00";
elsif (rxtlp_firstdw_be ="0011") then
bit10(1 downto 0) <= "10";
elsif (rxtlp_firstdw_be ="1100") then
bit10(1 downto 0) <= "00";
elsif (rxtlp_firstdw_be ="1111") then
bit10(1 downto 0) <= "00";
else --this should never happen
bit10(1 downto 0) <= "00";
end if;
end if;
end process;
--without endian swap:
-- process ( pciewb_localreset_n, rxtlp_firstdw_be )
-- begin
-- if (pciewb_localreset_n = '0') then
-- bit10(1 downto 0) <="00";
-- else
-- if (rxtlp_firstdw_be ="0001") then
-- bit10(1 downto 0) <= "00";
-- elsif (rxtlp_firstdw_be ="0010") then
-- bit10(1 downto 0) <= "01";
-- elsif (rxtlp_firstdw_be ="0100") then
-- bit10(1 downto 0) <= "10";
-- elsif (rxtlp_firstdw_be ="1000") then
-- bit10(1 downto 0) <= "11";
-- elsif (rxtlp_firstdw_be ="0011") then
-- bit10(1 downto 0) <= "00";
-- elsif (rxtlp_firstdw_be ="1100") then
-- bit10(1 downto 0) <= "10";
-- elsif (rxtlp_firstdw_be ="1111") then
-- bit10(1 downto 0) <= "00";
-- else --this should never happen
-- bit10(1 downto 0) <= "00";
-- end if;
-- end if;
-- end process;
 
-- INTERRUPTS: -------------------------------------------------------------------------
--to assert an interrupt, use the cfg_interrupt_assert_n pin.
--datasheet text:
--As shown in Figure 6-30, the user application first asserts cfg_interrupt_n and
--cfg_interrupt_assert_n to assert the interrupt. The user application should select a
--specific interrupt (INTA, INTB, INTC, or INTD) using cfg_interrupt_di[7:0] as shown
--in Table 6-19.
-- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt has been accepted.
--On the following clock cycle, the user application deasserts cfg_interrupt_n and, if the
--Interrupt Disable bit in the PCI Command register is set to 0, the core sends an assert
--interrupt message (Assert_INTA, Assert_INTB, and so forth).
-- After the user application has determined that the interrupt has been serviced, it
--asserts cfg_interrupt_n while deasserting cfg_interrupt_assert_n to deassert the
--interrupt. The appropriate interrupt must be indicated via cfg_interrupt_di[7:0].
-- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt deassertion has
--been accepted. On the following clock cycle, the user application deasserts
--cfg_interrupt_n and the core sends a deassert interrupt message (Deassert_INTA,
--Deassert_INTB, and so forth).
--cfg_interrupt_di[7:0] value Legacy Interrupt
--00h INTA
--01h INTB
--02h INTC
--03h INTD
 
cfg_interrupt_di <= "00000000"; --intA used
 
process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
cfg_interrupt_rdy_n)
begin
if (pciewb_localreset_n='0') then
pcieirq_state <= "00000000";
cfg_interrupt_n <= '1';
cfg_interrupt_assert_n_1 <= '1';
else
if (trn_clk'event and trn_clk = '1') then
case ( pcieirq_state ) is
 
--********** idle STATE **********
when "00000000" => --state 0
if (pcie_irq = '1') then
pcieirq_state <= "00000001";
cfg_interrupt_n <= '0'; --active
else
cfg_interrupt_n <= '1'; --inactive
end if;
cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert
 
--********** assert STATE **********
when "00000001" => --state 1
if (cfg_interrupt_rdy_n ='0') then --ep accepted it
cfg_interrupt_n <= '1'; --deassert the request
pcieirq_state <= "00000010";
else
cfg_interrupt_n <= '0'; --request INTA assertion
end if;
 
--********** pcie_irq kept asserted STATE **********
when "00000010" => --state 2
if (pcie_irq = '0') then --pcie_irq gets deasserted
pcieirq_state <= "00000011";
end if;
cfg_interrupt_n <= '1'; --inactive
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
 
--********** DEassert STATE **********
when "00000011" => --state 3
if (cfg_interrupt_rdy_n ='0') then --ep accepted it
cfg_interrupt_n <= '1'; --deassert the request
pcieirq_state <= "00000000";
else
cfg_interrupt_n <= '0'; --request INTA DEassertion
end if;
 
when others => --error
pcieirq_state <= "00000000"; --go to state 0
end case;
end if;
end if;
end process;
--this (little delay) is to fix a hold time violation created inside the pcie-ep ip:
cfg_interrupt_assert_n <= cfg_interrupt_assert_n_1 or (not pciewb_localreset_n);
 
 
 
 
 
 
-- -------- END OF FILE -------------------------------------------------------------------------------------
end Behavioral;
 
 
/trunk/example_design/blk_mem_gen_v4_1.vhd
0,0 → 1,140
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v4_1.vhd when simulating
-- the core, blk_mem_gen_v4_1. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v4_1 IS
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(8 downto 0);
dina: IN std_logic_VECTOR(31 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(8 downto 0);
doutb: OUT std_logic_VECTOR(31 downto 0));
END blk_mem_gen_v4_1;
 
ARCHITECTURE blk_mem_gen_v4_1_a OF blk_mem_gen_v4_1 IS
-- synthesis translate_off
component wrapped_blk_mem_gen_v4_1
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(8 downto 0);
dina: IN std_logic_VECTOR(31 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(8 downto 0);
doutb: OUT std_logic_VECTOR(31 downto 0));
end component;
 
-- Configuration specification
for all : wrapped_blk_mem_gen_v4_1 use entity XilinxCoreLib.blk_mem_gen_v4_1(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 1,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 32,
c_initb_val => "0",
c_family => "spartan6",
c_read_width_a => 32,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "READ_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "READ_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_softecc_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan6",
c_write_depth_b => 512,
c_write_depth_a => 512,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 9,
c_has_softecc_input_regs_b => 0,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 9,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 32,
c_write_width_a => 32,
c_read_depth_b => 512,
c_read_depth_a => 512,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 1,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v4_1
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb);
-- synthesis translate_on
 
END blk_mem_gen_v4_1_a;
 
/trunk/example_design/pcie_bram_s6.vhd
0,0 → 1,189
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information of Xilinx, Inc.
-- and is protected under U.S. and international copyright and other
-- intellectual property laws.
--
-- DISCLAIMER
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Xilinx, and to the maximum extent permitted by
-- applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-- FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-- IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-- and (2) Xilinx shall not be liable (whether in contract or tort, including
-- negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these
-- materials, including for any direct, or any indirect, special, incidental,
-- or consequential loss or damage (including loss of data, profits, goodwill,
-- or any type of loss or damage suffered as a result of any action brought by
-- a third party) even if such damage or loss was reasonably foreseeable or
-- Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in
-- any application requiring fail-safe performance, such as life-support or
-- safety devices or systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any other
-- applications that could lead to death, personal injury, or severe property
-- or environmental damage (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and liability of any use of
-- Xilinx products in Critical Applications, subject only to applicable laws
-- and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-- AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_bram_s6.vhd
-- Description: BlockRAM module for Spartan-6 PCIe Block
-- The BRAM A port is the write port.
-- The BRAM B port is the read port.
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library unisim;
use unisim.vcomponents.all;
 
entity pcie_bram_s6 is
generic (
DOB_REG : integer := 0; -- 1 use output register, 0 don't use output register
WIDTH : integer := 0 -- supported WIDTH values are: 4, 9, 18, 36
);
port (
user_clk_i : in std_logic; -- user clock
reset_i : in std_logic; -- bram reset
 
wen_i : in std_logic; -- write enable
waddr_i : in std_logic_vector(11 downto 0); -- write address
wdata_i : in std_logic_vector(WIDTH-1 downto 0); -- write data
 
ren_i : in std_logic; -- read enable
rce_i : in std_logic; -- output register clock enable
raddr_i : in std_logic_vector(11 downto 0); -- read address
 
rdata_o : out std_logic_vector(WIDTH-1 downto 0) -- read data
);
end pcie_bram_s6;
 
architecture rtl of pcie_bram_s6 is
 
function CALC_ADDR(constant WIDTH : in integer;
constant addr_in : in std_logic_vector(11 downto 0)
) return std_logic_vector is
variable ADDR : std_logic_vector(13 downto 0);
begin
if WIDTH = 4 then ADDR := addr_in(11 downto 0) & "00";
elsif WIDTH = 9 then ADDR := addr_in(10 downto 0) & "000";
elsif WIDTH = 18 then ADDR := addr_in(9 downto 0) & "0000";
else ADDR := addr_in(8 downto 0) & "00000"; -- WIDTH=36
end if;
return ADDR;
end function CALC_ADDR;
 
signal di_int : std_logic_vector(31 downto 0);
signal dip_int : std_logic_vector(3 downto 0);
signal do_int : std_logic_vector(31 downto 0);
signal dop_int : std_logic_vector(3 downto 0);
signal waddr_int : std_logic_vector(13 downto 0);
signal raddr_int : std_logic_vector(13 downto 0);
signal wen_int : std_logic_vector(3 downto 0);
 
begin
 
--synthesis translate_off
process
begin
case WIDTH is
when 4 | 9 | 18 | 36 =>
null;
when others =>
report "ERROR: WIDTH size " & integer'image(WIDTH) & " is not supported."
severity failure;
end case;
wait;
end process;
--synthesis translate_on
 
-- Wire up BRAM I/Os to module I/Os - map data & parity bits appropriately
width_36 : if (WIDTH = 36) generate
di_int <= wdata_i(31 downto 0);
dip_int <= wdata_i(35 downto 32);
rdata_o(35 downto 32) <= dop_int;
rdata_o(31 downto 0) <= do_int;
end generate width_36;
 
width_18 : if (WIDTH = 18) generate
di_int(31 downto 16) <= (OTHERS => '0');
di_int(15 downto 0) <= wdata_i(15 downto 0);
dip_int(3 downto 2) <= (OTHERS => '0');
dip_int(1 downto 0) <= wdata_i(17 downto 16);
rdata_o(17 downto 16) <= dop_int(1 downto 0);
rdata_o(15 downto 0) <= do_int(15 downto 0);
end generate width_18;
 
width_9 : if (WIDTH = 9) generate
di_int(31 downto 8) <= (OTHERS => '0');
di_int(7 downto 0) <= wdata_i(7 downto 0);
dip_int(3 downto 1) <= (OTHERS => '0');
dip_int(0) <= wdata_i(8);
rdata_o(8) <= dop_int(0);
rdata_o(7 downto 0) <= do_int(7 downto 0);
end generate width_9;
 
width_4 : if (WIDTH = 4) generate
di_int(31 downto 4) <= (OTHERS => '0');
di_int(3 downto 0) <= wdata_i(3 downto 0);
dip_int <= (OTHERS => '0');
rdata_o <= do_int(3 downto 0);
end generate width_4;
 
waddr_int <= CALC_ADDR(WIDTH, waddr_i);
raddr_int <= CALC_ADDR(WIDTH, raddr_i);
wen_int <= wen_i & wen_i & wen_i & wen_i;
 
ramb16 : RAMB16BWER
generic map (
DATA_WIDTH_A => WIDTH,
DATA_WIDTH_B => WIDTH,
DOA_REG => 0,
DOB_REG => DOB_REG,
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE"
)
port map (
CLKA => user_clk_i,
RSTA => reset_i,
DOA => open,
DOPA => open,
ADDRA => waddr_int,
DIA => di_int,
DIPA => dip_int,
ENA => wen_i,
WEA => wen_int,
REGCEA => '0',
 
CLKB => user_clk_i,
RSTB => reset_i,
WEB => "0000",
DIB => x"00000000",
DIPB => "0000",
ADDRB => raddr_int,
DOB => do_int,
DOPB => dop_int,
ENB => ren_i,
REGCEB => rce_i
);
 
end rtl;
 
/trunk/example_design/pcie_bram_top_s6.vhd
0,0 → 1,194
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information of Xilinx, Inc.
-- and is protected under U.S. and international copyright and other
-- intellectual property laws.
--
-- DISCLAIMER
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Xilinx, and to the maximum extent permitted by
-- applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-- FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-- IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-- and (2) Xilinx shall not be liable (whether in contract or tort, including
-- negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these
-- materials, including for any direct, or any indirect, special, incidental,
-- or consequential loss or damage (including loss of data, profits, goodwill,
-- or any type of loss or damage suffered as a result of any action brought by
-- a third party) even if such damage or loss was reasonably foreseeable or
-- Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in
-- any application requiring fail-safe performance, such as life-support or
-- safety devices or systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any other
-- applications that could lead to death, personal injury, or severe property
-- or environmental damage (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and liability of any use of
-- Xilinx products in Critical Applications, subject only to applicable laws
-- and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-- AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_bram_top_s6.vhd
-- Description: BlockRAM top level module for Spartan-6 PCIe Block
--
-- Given the selected core configuration, calculate the number of
-- BRAMs and pipeline stages and instantiate the BRAMS.
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity pcie_bram_top_s6 is
generic (
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 0;
 
VC0_TX_LASTPACKET : integer := 31;
TLM_TX_OVERHEAD : integer := 20;
TL_TX_RAM_RADDR_LATENCY : integer := 1;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_TX_RAM_WRITE_LATENCY : integer := 1;
 
VC0_RX_LIMIT : integer := 16#1FFF#;
TL_RX_RAM_RADDR_LATENCY : integer := 1;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 1
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
 
mim_tx_wen : in std_logic;
mim_tx_waddr : in std_logic_vector(11 downto 0);
mim_tx_wdata : in std_logic_vector(35 downto 0);
mim_tx_ren : in std_logic;
mim_tx_rce : in std_logic;
mim_tx_raddr : in std_logic_vector(11 downto 0);
mim_tx_rdata : out std_logic_vector(35 downto 0);
 
mim_rx_wen : in std_logic;
mim_rx_waddr : in std_logic_vector(11 downto 0);
mim_rx_wdata : in std_logic_vector(35 downto 0);
mim_rx_ren : in std_logic;
mim_rx_rce : in std_logic;
mim_rx_raddr : in std_logic_vector(11 downto 0);
mim_rx_rdata : out std_logic_vector(35 downto 0)
);
end pcie_bram_top_s6;
 
architecture rtl of pcie_bram_top_s6 is
 
component pcie_brams_s6
generic (
NUM_BRAMS : integer;
RAM_RADDR_LATENCY : integer;
RAM_RDATA_LATENCY : integer;
RAM_WRITE_LATENCY : integer
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
wen : in std_logic;
waddr : in std_logic_vector(11 downto 0);
wdata : in std_logic_vector(35 downto 0);
ren : in std_logic;
rce : in std_logic;
raddr : in std_logic_vector(11 downto 0);
rdata : out std_logic_vector(35 downto 0)
);
end component;
 
function CALC_TX_COLS(constant MPS : in integer;
constant LASTPACKET : in integer;
constant OVERHEAD : in integer
) return integer is
variable MPS_BYTES : integer;
variable BYTES_TX : integer;
variable COLS_TX : integer;
begin
-- Decode MPS value
if (MPS = 0) then MPS_BYTES := 128;
elsif (MPS = 1) then MPS_BYTES := 256;
else MPS_BYTES := 512; -- MPS = 2
end if;
 
-- Calculate total bytes from MPS, number of packets, and overhead
BYTES_TX := (LASTPACKET + 1) * (MPS_BYTES + OVERHEAD);
 
-- Determine number of BRAM columns from total bytes
if (BYTES_TX <= 2048) then COLS_TX := 1;
elsif (BYTES_TX <= 4096) then COLS_TX := 2;
else COLS_TX := 4; -- BYTES_TX <= 8192
end if;
return COLS_TX;
end function CALC_TX_COLS;
 
function CALC_RX_COLS(constant LIMIT : in integer) return integer is
variable COLS_RX : integer;
begin
-- Determine number of BRAM columns from total RAM size
if (LIMIT <= 512) then COLS_RX := 1;
elsif (LIMIT <= 1024) then COLS_RX := 2;
else COLS_RX := 4; -- LIMIT <= 2048
end if;
return COLS_RX;
end function CALC_RX_COLS;
 
begin
 
pcie_brams_tx : pcie_brams_s6
generic map(
NUM_BRAMS => CALC_TX_COLS(DEV_CAP_MAX_PAYLOAD_SUPPORTED, VC0_TX_LASTPACKET, TLM_TX_OVERHEAD),
RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY
)
port map (
user_clk_i => user_clk_i,
reset_i => reset_i,
 
waddr => mim_tx_waddr,
wen => mim_tx_wen,
ren => mim_tx_ren,
rce => mim_tx_rce,
wdata => mim_tx_wdata,
raddr => mim_tx_raddr,
rdata => mim_tx_rdata
);
 
pcie_brams_rx : pcie_brams_s6
generic map(
NUM_BRAMS => CALC_RX_COLS(VC0_RX_LIMIT),
RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY
)
port map (
user_clk_i => user_clk_i,
reset_i => reset_i,
 
waddr => mim_rx_waddr,
wen => mim_rx_wen,
ren => mim_rx_ren,
rce => mim_rx_rce,
wdata => mim_rx_wdata,
raddr => mim_rx_raddr,
rdata => mim_rx_rdata
);
 
end rtl;
/trunk/example_design/pcie_brams_s6.vhd
0,0 → 1,276
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information of Xilinx, Inc.
-- and is protected under U.S. and international copyright and other
-- intellectual property laws.
--
-- DISCLAIMER
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Xilinx, and to the maximum extent permitted by
-- applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-- FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-- IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-- and (2) Xilinx shall not be liable (whether in contract or tort, including
-- negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these
-- materials, including for any direct, or any indirect, special, incidental,
-- or consequential loss or damage (including loss of data, profits, goodwill,
-- or any type of loss or damage suffered as a result of any action brought by
-- a third party) even if such damage or loss was reasonably foreseeable or
-- Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in
-- any application requiring fail-safe performance, such as life-support or
-- safety devices or systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any other
-- applications that could lead to death, personal injury, or severe property
-- or environmental damage (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and liability of any use of
-- Xilinx products in Critical Applications, subject only to applicable laws
-- and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-- AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_brams_s6.vhd
-- Description: BlockRAM module for Spartan-6 PCIe Block
--
-- Arranges and connects brams
-- Implements address decoding, datapath muxing and
-- pipeline stages
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity pcie_brams_s6 is
generic (
-- the number of BRAMs to use
-- supported values are:
-- 1,2,4,9
NUM_BRAMS : integer := 0;
 
-- BRAM read address latency
--
-- value meaning
-- ====================================================
-- 0 BRAM read address port sample
-- 1 BRAM read address port sample and a pipeline stage on the address port
RAM_RADDR_LATENCY : integer := 1;
 
-- BRAM read data latency
--
-- value meaning
-- ====================================================
-- 1 no BRAM OREG
-- 2 use BRAM OREG
-- 3 use BRAM OREG and a pipeline stage on the data port
RAM_RDATA_LATENCY : integer := 1;
 
-- BRAM write latency
-- The BRAM write port is synchronous
--
-- value meaning
-- ====================================================
-- 0 BRAM write port sample
-- 1 BRAM write port sample plus pipeline stage
RAM_WRITE_LATENCY : integer := 1
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
wen : in std_logic;
waddr : in std_logic_vector(11 downto 0);
wdata : in std_logic_vector(35 downto 0);
ren : in std_logic;
rce : in std_logic;
raddr : in std_logic_vector(11 downto 0);
rdata : out std_logic_vector(35 downto 0)
);
end pcie_brams_s6;
 
architecture rtl of pcie_brams_s6 is
 
constant TCQ : time := 1 ns; -- Clock-to-out delay to be modeled
 
-- Turn on the bram output register
function CALC_DOB_REG(constant RAM_RDATA_LATENCY : in integer) return integer is
variable DOB_REG : integer;
begin
if (RAM_RDATA_LATENCY > 1) then DOB_REG := 1;
else DOB_REG := 0;
end if;
return DOB_REG;
end function CALC_DOB_REG;
 
-- Calculate the data width of the individual BRAMs
function CALC_WIDTH(constant NUM_BRAMS : in integer) return integer is
variable WIDTH : integer;
begin
if (NUM_BRAMS = 1) then WIDTH := 36;
elsif (NUM_BRAMS = 2) then WIDTH := 18;
elsif (NUM_BRAMS = 4) then WIDTH := 9;
else WIDTH := 4; -- NUM_BRAMS = 9
end if;
return WIDTH;
end function CALC_WIDTH;
 
component pcie_bram_s6 is
generic (
DOB_REG : integer;
WIDTH : integer
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
 
wen_i : in std_logic;
waddr_i : in std_logic_vector(11 downto 0);
wdata_i : in std_logic_vector(CALC_WIDTH(NUM_BRAMS)-1 downto 0);
 
ren_i : in std_logic;
rce_i : in std_logic;
raddr_i : in std_logic_vector(11 downto 0);
 
rdata_o : out std_logic_vector(CALC_WIDTH(NUM_BRAMS)-1 downto 0) -- read data
);
end component;
 
-- Model the delays for RAM write latency
signal wen_int : std_logic;
signal waddr_int : std_logic_vector(11 downto 0);
signal wdata_int : std_logic_vector(35 downto 0);
 
-- Model the delays for RAM read latency
signal ren_int : std_logic;
signal raddr_int : std_logic_vector(11 downto 0);
signal rdata_int : std_logic_vector(35 downto 0);
 
begin
 
--synthesis translate_off
process begin
case NUM_BRAMS is
when 1 | 2 | 4 | 9 =>
null;
when others =>
report "Error NUM_BRAMS size " & integer'image(NUM_BRAMS) & " is not supported." severity failure;
end case; -- case NUM_BRAMS
 
case RAM_RADDR_LATENCY is
when 0 | 1 =>
null;
when others =>
report "Error RAM_RADDR_LATENCY size " & integer'image(RAM_RADDR_LATENCY) & " is not supported." severity failure;
end case; -- case RAM_RADDR_LATENCY
 
case RAM_RDATA_LATENCY is
when 1 | 2 | 3 =>
null;
when others =>
report "Error RAM_RDATA_LATENCY size " & integer'image(RAM_RDATA_LATENCY) & " is not supported." severity failure;
end case; -- case RAM_RDATA_LATENCY
 
case RAM_WRITE_LATENCY is
when 0 | 1 =>
null;
when others =>
report "Error RAM_WRITE_LATENCY size " & integer'image(RAM_WRITE_LATENCY) & " is not supported." severity failure;
end case; -- case RAM_WRITE_LATENCY
 
wait;
end process;
--synthesis translate_on
 
-- 1 stage RAM write pipeline
wr_lat_1 : if(RAM_WRITE_LATENCY = 1) generate
process (user_clk_i) begin
if (reset_i = '1') then
wen_int <= '0' after TCQ;
waddr_int <= (others => '0') after TCQ;
wdata_int <= (others => '0') after TCQ;
elsif (rising_edge(user_clk_i)) then
wen_int <= wen after TCQ;
waddr_int <= waddr after TCQ;
wdata_int <= wdata after TCQ;
end if;
end process;
end generate wr_lat_1;
 
-- No RAM write pipeline
wr_lat_0 : if(RAM_WRITE_LATENCY /= 1) generate
wen_int <= wen;
waddr_int <= waddr;
wdata_int <= wdata;
end generate wr_lat_0;
 
 
-- 1 stage RAM read addr pipeline
raddr_lat_1 : if(RAM_RADDR_LATENCY = 1) generate
process (user_clk_i) begin
if (reset_i = '1') then
ren_int <= '0' after TCQ;
raddr_int <= (others => '0') after TCQ;
elsif (rising_edge(user_clk_i)) then
ren_int <= ren after TCQ;
raddr_int <= raddr after TCQ;
end if;
end process;
end generate raddr_lat_1;
 
-- No RAM read addr pipeline
raddr_lat_0 : if(RAM_RADDR_LATENCY /= 1) generate
ren_int <= ren after TCQ;
raddr_int <= raddr after TCQ;
end generate raddr_lat_0;
 
-- 3 stages RAM read data pipeline (first is internal to BRAM)
rdata_lat_3 : if(RAM_RDATA_LATENCY = 3) generate
process (user_clk_i) begin
if (reset_i = '1') then
rdata <= (others => '0') after TCQ;
elsif (rising_edge(user_clk_i)) then
rdata <= rdata_int after TCQ;
end if;
end process;
end generate rdata_lat_3;
 
-- 1 or 2 stages RAM read data pipeline
rdata_lat_1_2 : if(RAM_RDATA_LATENCY /= 3) generate
rdata <= rdata_int;
end generate rdata_lat_1_2;
 
-- Instantiate BRAM(s)
brams : for i in 0 to (NUM_BRAMS - 1) generate
begin
ram : pcie_bram_s6
generic map (
DOB_REG => CALC_DOB_REG(RAM_RDATA_LATENCY),
WIDTH => CALC_WIDTH(NUM_BRAMS)
)
port map (
user_clk_i => user_clk_i,
reset_i => reset_i,
wen_i => wen_int,
waddr_i => waddr_int,
wdata_i => wdata_int((((i + 1) * CALC_WIDTH(NUM_BRAMS)) - 1) downto (i * CALC_WIDTH(NUM_BRAMS))),
ren_i => ren_int,
rce_i => rce,
raddr_i => raddr_int,
rdata_o => rdata_int((((i + 1) * CALC_WIDTH(NUM_BRAMS)) - 1) downto (i * CALC_WIDTH(NUM_BRAMS)))
);
end generate brams;
 
end rtl;
 
/trunk/example_design/blk_mem_gen_v4_1.ngc
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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/trunk/example_design/gtpa1_dual_wrapper_tile.vhd
0,0 → 1,769
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.3
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : gtpa1_dual_wrapper_tile.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module GTPA1_DUAL_WRAPPER_TILE (a GTPA1_DUAL Tile Wrapper)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of,
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
 
--***************************** Entity Declaration ****************************
 
entity GTPA1_DUAL_WRAPPER_TILE is
generic
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
--
TILE_CLKINDC_B_0 : boolean := FALSE;
TIlE_CLKINDC_B_1 : boolean := FALSE;
--
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN0_IN : in std_logic;
RXENMCOMMAALIGN1_IN : in std_logic;
RXENPCOMMAALIGN0_IN : in std_logic;
RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(15 downto 0);
RXDATA1_OUT : out std_logic_vector(15 downto 0);
RXRESET0_IN : in std_logic;
RXRESET1_IN : in std_logic;
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0_IN : in std_logic;
GATERXELECIDLE1_IN : in std_logic;
IGNORESIGDET0_IN : in std_logic;
IGNORESIGDET1_IN : in std_logic;
RXELECIDLE0_OUT : out std_logic;
RXELECIDLE1_OUT : out std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0_OUT : out std_logic;
PHYSTATUS1_OUT : out std_logic;
RXVALID0_OUT : out std_logic;
RXVALID1_OUT : out std_logic;
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0_IN : in std_logic;
RXPOLARITY1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
TXCHARISK0_IN : in std_logic_vector(1 downto 0);
TXCHARISK1_IN : in std_logic_vector(1 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(15 downto 0);
TXDATA1_IN : in std_logic_vector(15 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic;
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0_IN : in std_logic;
TXDETECTRX1_IN : in std_logic;
TXELECIDLE0_IN : in std_logic;
TXELECIDLE1_IN : in std_logic
 
 
);
 
 
end GTPA1_DUAL_WRAPPER_TILE;
 
architecture RTL of GTPA1_DUAL_WRAPPER_TILE is
 
--**************************** Signal Declarations ****************************
 
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
 
 
-- RX Datapath signals
signal rxdata0_i : std_logic_vector(31 downto 0);
signal rxchariscomma0_float_i : std_logic_vector(1 downto 0);
signal rxcharisk0_float_i : std_logic_vector(1 downto 0);
signal rxdisperr0_float_i : std_logic_vector(1 downto 0);
signal rxnotintable0_float_i : std_logic_vector(1 downto 0);
signal rxrundisp0_float_i : std_logic_vector(1 downto 0);
 
-- TX Datapath signals
signal txdata0_i : std_logic_vector(31 downto 0);
signal txkerr0_float_i : std_logic_vector(1 downto 0);
signal txrundisp0_float_i : std_logic_vector(1 downto 0);
 
-- RX Datapath signals
signal rxdata1_i : std_logic_vector(31 downto 0);
signal rxchariscomma1_float_i : std_logic_vector(1 downto 0);
signal rxcharisk1_float_i : std_logic_vector(1 downto 0);
signal rxdisperr1_float_i : std_logic_vector(1 downto 0);
signal rxnotintable1_float_i : std_logic_vector(1 downto 0);
signal rxrundisp1_float_i : std_logic_vector(1 downto 0);
 
-- TX Datapath signals
signal txdata1_i : std_logic_vector(31 downto 0);
signal txkerr1_float_i : std_logic_vector(1 downto 0);
signal txrundisp1_float_i : std_logic_vector(1 downto 0);
 
--******************************** Main Body of Code***************************
begin
 
--------------------------- Static signal Assignments ---------------------
 
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
------------------- GTP Datapath byte mapping -----------------
 
-- The GTP provides little endian data (first byte received on RXDATA(7 downto 0))
RXDATA0_OUT <= rxdata0_i(15 downto 0);
txdata0_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA0_IN);
 
-- The GTP provides little endian data (first byte received on RXDATA(7 downto 0))
RXDATA1_OUT <= rxdata1_i(15 downto 0);
txdata1_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA1_IN);
 
 
 
----------------------------- GTPA1_DUAL Instance --------------------------
 
gtpa1_dual_i:GTPA1_DUAL
generic map
(
 
--_______________________ Simulation-Only Attributes ___________________
 
SIM_RECEIVER_DETECT_PASS => (TRUE),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("1.0"),
SIM_REFCLK0_SOURCE => ("000"),
SIM_REFCLK1_SOURCE => ("000"),
SIM_GTPRESET_SPEEDUP => (TILE_SIM_GTPRESET_SPEEDUP),
 
--PLL Attributes
CLK25_DIVIDER_0 => (4),
CLKINDC_B_0 => (TILE_CLKINDC_B_0),
CLKRCV_TRST_0 => (TRUE),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_DIVSEL_FB_0 => (5),
PLL_DIVSEL_REF_0 => (2),
PLL_RXDIVSEL_OUT_0 => (1),
PLL_SATA_0 => (FALSE),
PLL_SOURCE_0 => (TILE_PLL_SOURCE_0),
PLL_TXDIVSEL_OUT_0 => (1),
PLLLKDET_CFG_0 => ("111"),
CLK25_DIVIDER_1 => (5),
 
--
CLKINDC_B_1 => (TILE_CLKINDC_B_1),
CLKRCV_TRST_1 => (TRUE),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_DIVSEL_FB_1 => (2),
PLL_DIVSEL_REF_1 => (1),
PLL_RXDIVSEL_OUT_1 => (1),
PLL_SATA_1 => (FALSE),
PLL_SOURCE_1 => (TILE_PLL_SOURCE_1),
PLL_TXDIVSEL_OUT_1 => (1),
PLLLKDET_CFG_1 => ("111"),
PMA_COM_CFG_EAST => (x"000000000"),
PMA_COM_CFG_WEST => (x"000000000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
 
--TX Interface Attributes
CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"),
TX_TDCC_CFG_0 => ("11"),
CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
TX_TDCC_CFG_1 => ("11"),
 
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"00082"),
TX_BUFFER_USE_0 => (TRUE),
TX_XCLK_SEL_0 => ("TXOUT"),
TXRX_INVERT_0 => ("011"),
PMA_TX_CFG_1 => (x"00082"),
TX_BUFFER_USE_1 => (TRUE),
TX_XCLK_SEL_1 => ("TXOUT"),
TXRX_INVERT_1 => ("011"),
 
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => ("00"),
TX_IDLE_DELAY_0 => ("011"),
CM_TRIM_1 => ("00"),
TX_IDLE_DELAY_1 => ("011"),
 
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => ("1111"),
COM_BURST_VAL_1 => ("1111"),
 
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (FALSE),
OOBDETECT_THRESHOLD_0 => ("111"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce048"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (TRUE),
RCV_TERM_VTTRX_0 => (FALSE),
RXEQ_CFG_0 => ("01111011"),
TERMINATION_CTRL_0 => ("10100"),
TERMINATION_OVRD_0 => (FALSE),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (FALSE),
OOBDETECT_THRESHOLD_1 => ("111"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce048"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (TRUE),
RCV_TERM_VTTRX_1 => (FALSE),
RXEQ_CFG_1 => ("01111011"),
TERMINATION_CTRL_1 => ("10100"),
TERMINATION_OVRD_1 => (FALSE),
TX_DETECT_RX_CFG_1 => (x"1832"),
 
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (1),
COMMA_10B_ENABLE_0 => ("1111111111"),
DEC_MCOMMA_DETECT_0 => (TRUE),
DEC_PCOMMA_DETECT_0 => (TRUE),
DEC_VALID_COMMA_ONLY_0 => (TRUE),
MCOMMA_10B_VALUE_0 => ("1010000011"),
MCOMMA_DETECT_0 => (TRUE),
PCOMMA_10B_VALUE_0 => ("0101111100"),
PCOMMA_DETECT_0 => (TRUE),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (1),
COMMA_10B_ENABLE_1 => ("1111111111"),
DEC_MCOMMA_DETECT_1 => (TRUE),
DEC_PCOMMA_DETECT_1 => (TRUE),
DEC_VALID_COMMA_ONLY_1 => (TRUE),
MCOMMA_10B_VALUE_1 => ("1010000011"),
MCOMMA_DETECT_1 => (TRUE),
PCOMMA_10B_VALUE_1 => ("0101111100"),
PCOMMA_DETECT_1 => (TRUE),
RX_SLIDE_MODE_1 => ("PCS"),
 
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (FALSE),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (FALSE),
 
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (TRUE),
RX_EN_IDLE_RESET_BUF_0 => (TRUE),
RX_IDLE_HI_CNT_0 => ("1000"),
RX_IDLE_LO_CNT_0 => ("0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (TRUE),
RX_EN_IDLE_RESET_BUF_1 => (TRUE),
RX_IDLE_HI_CNT_1 => ("1000"),
RX_IDLE_LO_CNT_1 => ("0000"),
RX_XCLK_SEL_1 => ("RXREC"),
 
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (1),
CLK_COR_DET_LEN_0 => (1),
CLK_COR_INSERT_IDLE_FLAG_0 => (FALSE),
CLK_COR_KEEP_IDLE_0 => (FALSE),
CLK_COR_MAX_LAT_0 => (20),
CLK_COR_MIN_LAT_0 => (18),
CLK_COR_PRECEDENCE_0 => (TRUE),
CLK_COR_REPEAT_WAIT_0 => (0),
CLK_COR_SEQ_1_1_0 => ("0100011100"),
CLK_COR_SEQ_1_2_0 => ("0000000000"),
CLK_COR_SEQ_1_3_0 => ("0000000000"),
CLK_COR_SEQ_1_4_0 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_0 => ("0001"),
CLK_COR_SEQ_2_1_0 => ("0000000000"),
CLK_COR_SEQ_2_2_0 => ("0000000000"),
CLK_COR_SEQ_2_3_0 => ("0000000000"),
CLK_COR_SEQ_2_4_0 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_USE_0 => (FALSE),
CLK_CORRECT_USE_0 => (TRUE),
RX_DECODE_SEQ_MATCH_0 => (TRUE),
CLK_COR_ADJ_LEN_1 => (1),
CLK_COR_DET_LEN_1 => (1),
CLK_COR_INSERT_IDLE_FLAG_1 => (FALSE),
CLK_COR_KEEP_IDLE_1 => (FALSE),
CLK_COR_MAX_LAT_1 => (20),
CLK_COR_MIN_LAT_1 => (18),
CLK_COR_PRECEDENCE_1 => (TRUE),
CLK_COR_REPEAT_WAIT_1 => (0),
CLK_COR_SEQ_1_1_1 => ("0100011100"),
CLK_COR_SEQ_1_2_1 => ("0000000000"),
CLK_COR_SEQ_1_3_1 => ("0000000000"),
CLK_COR_SEQ_1_4_1 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_1 => ("0001"),
CLK_COR_SEQ_2_1_1 => ("0000000000"),
CLK_COR_SEQ_2_2_1 => ("0000000000"),
CLK_COR_SEQ_2_3_1 => ("0000000000"),
CLK_COR_SEQ_2_4_1 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_USE_1 => (FALSE),
CLK_CORRECT_USE_1 => (TRUE),
RX_DECODE_SEQ_MATCH_1 => (TRUE),
 
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (FALSE),
CHAN_BOND_SEQ_1_1_0 => ("0001001010"),
CHAN_BOND_SEQ_1_2_0 => ("0001001010"),
CHAN_BOND_SEQ_1_3_0 => ("0001001010"),
CHAN_BOND_SEQ_1_4_0 => ("0110111100"),
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_1_0 => ("0100111100"),
CHAN_BOND_SEQ_2_2_0 => ("0100111100"),
CHAN_BOND_SEQ_2_3_0 => ("0110111100"),
CHAN_BOND_SEQ_2_4_0 => ("0100011100"),
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_USE_0 => (FALSE),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (FALSE),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (FALSE),
CHAN_BOND_SEQ_1_1_1 => ("0001001010"),
CHAN_BOND_SEQ_1_2_1 => ("0001001010"),
CHAN_BOND_SEQ_1_3_1 => ("0001001010"),
CHAN_BOND_SEQ_1_4_1 => ("0110111100"),
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_1_1 => ("0100111100"),
CHAN_BOND_SEQ_2_2_1 => ("0100111100"),
CHAN_BOND_SEQ_2_3_1 => ("0110111100"),
CHAN_BOND_SEQ_2_4_1 => ("0100011100"),
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_USE_1 => (FALSE),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (FALSE),
 
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => ("01010"),
PCI_EXPRESS_MODE_0 => (TRUE),
RX_EN_IDLE_HOLD_CDR_0 => (TRUE),
RX_EN_IDLE_RESET_FR_0 => (TRUE),
RX_EN_IDLE_RESET_PH_0 => (TRUE),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => ("01010"),
PCI_EXPRESS_MODE_1 => (TRUE),
RX_EN_IDLE_HOLD_CDR_1 => (TRUE),
RX_EN_IDLE_RESET_FR_1 => (TRUE),
RX_EN_IDLE_RESET_PH_1 => (TRUE),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
 
--RX SATA Attributes
SATA_BURST_VAL_0 => ("100"),
SATA_IDLE_VAL_0 => ("100"),
SATA_MAX_BURST_0 => (9),
SATA_MAX_INIT_0 => (27),
SATA_MAX_WAKE_0 => (9),
SATA_MIN_BURST_0 => (5),
SATA_MIN_INIT_0 => (15),
SATA_MIN_WAKE_0 => (5),
SATA_BURST_VAL_1 => ("100"),
SATA_IDLE_VAL_1 => ("100"),
SATA_MAX_BURST_1 => (9),
SATA_MAX_INIT_1 => (27),
SATA_MAX_WAKE_1 => (9),
SATA_MIN_BURST_1 => (5),
SATA_MIN_INIT_1 => (15),
SATA_MIN_WAKE_1 => (5)
 
 
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => tied_to_ground_vec_i(2 downto 0),
LOOPBACK1 => tied_to_ground_vec_i(2 downto 0),
RXPOWERDOWN0 => RXPOWERDOWN0_IN,
RXPOWERDOWN1 => RXPOWERDOWN1_IN,
TXPOWERDOWN0 => TXPOWERDOWN0_IN,
TXPOWERDOWN1 => TXPOWERDOWN1_IN,
--------------------------------- PLL Ports --------------------------------
CLK00 => CLK00_IN,
CLK01 => CLK01_IN,
CLK10 => tied_to_ground_i,
CLK11 => tied_to_ground_i,
CLKINEAST0 => tied_to_ground_i,
CLKINEAST1 => tied_to_ground_i,
CLKINWEST0 => tied_to_ground_i,
CLKINWEST1 => tied_to_ground_i,
GCLK00 => tied_to_ground_i,
GCLK01 => tied_to_ground_i,
GCLK10 => tied_to_ground_i,
GCLK11 => tied_to_ground_i,
GTPRESET0 => GTPRESET0_IN,
GTPRESET1 => GTPRESET1_IN,
GTPTEST0 => "00010000",
GTPTEST1 => "00010000",
INTDATAWIDTH0 => tied_to_vcc_i,
INTDATAWIDTH1 => tied_to_vcc_i,
PLLCLK00 => tied_to_ground_i,
PLLCLK01 => tied_to_ground_i,
PLLCLK10 => tied_to_ground_i,
PLLCLK11 => tied_to_ground_i,
PLLLKDET0 => PLLLKDET0_OUT,
PLLLKDET1 => PLLLKDET1_OUT,
PLLLKDETEN0 => tied_to_vcc_i,
PLLLKDETEN1 => tied_to_vcc_i,
PLLPOWERDOWN0 => tied_to_ground_i,
PLLPOWERDOWN1 => tied_to_ground_i,
REFCLKOUT0 => open,
REFCLKOUT1 => open,
REFCLKPLL0 => open,
REFCLKPLL1 => open,
REFCLKPWRDNB0 => tied_to_vcc_i,
REFCLKPWRDNB1 => tied_to_vcc_i,
REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0),
REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0),
RESETDONE0 => RESETDONE0_OUT,
RESETDONE1 => RESETDONE1_OUT,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN0 => tied_to_ground_vec_i(11 downto 0),
TSTIN1 => tied_to_ground_vec_i(11 downto 0),
TSTOUT0 => open,
TSTOUT1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0(3 downto 2) => rxcharisk0_float_i,
RXCHARISK0(1 downto 0) => RXCHARISK0_OUT,
RXCHARISK1(3 downto 2) => rxcharisk1_float_i,
RXCHARISK1(1 downto 0) => RXCHARISK1_OUT,
RXDEC8B10BUSE0 => tied_to_vcc_i,
RXDEC8B10BUSE1 => tied_to_vcc_i,
RXDISPERR0(3 downto 2) => rxdisperr0_float_i,
RXDISPERR0(1 downto 0) => RXDISPERR0_OUT,
RXDISPERR1(3 downto 2) => rxdisperr1_float_i,
RXDISPERR1(1 downto 0) => RXDISPERR1_OUT,
RXNOTINTABLE0(3 downto 2) => rxnotintable0_float_i,
RXNOTINTABLE0(1 downto 0) => RXNOTINTABLE0_OUT,
RXNOTINTABLE1(3 downto 2) => rxnotintable1_float_i,
RXNOTINTABLE1(1 downto 0) => RXNOTINTABLE1_OUT,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
USRCODEERR0 => tied_to_ground_i,
USRCODEERR1 => tied_to_ground_i,
---------------------- Receive Ports - Channel Bonding ---------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXCHBONDI => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER0 => tied_to_ground_i,
RXCHBONDMASTER1 => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE0 => tied_to_ground_i,
RXCHBONDSLAVE1 => tied_to_ground_i,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0 => RXCLKCORCNT0_OUT,
RXCLKCORCNT1 => RXCLKCORCNT1_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => open,
RXBYTEISALIGNED1 => open,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => open,
RXCOMMADET1 => open,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_IN,
RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_IN,
RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_IN,
RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_IN,
RXSLIDE0 => tied_to_ground_i,
RXSLIDE1 => tied_to_ground_i,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i,
RXDATA1 => rxdata1_i,
RXDATAWIDTH0 => "01",
RXDATAWIDTH1 => "01",
RXRECCLK0 => open,
RXRECCLK1 => open,
RXRESET0 => RXRESET0_IN,
RXRESET1 => RXRESET1_IN,
RXUSRCLK0 => RXUSRCLK0_IN,
RXUSRCLK1 => RXUSRCLK1_IN,
RXUSRCLK20 => RXUSRCLK20_IN,
RXUSRCLK21 => RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0 => GATERXELECIDLE0_IN,
GATERXELECIDLE1 => GATERXELECIDLE1_IN,
IGNORESIGDET0 => IGNORESIGDET0_IN,
IGNORESIGDET1 => IGNORESIGDET1_IN,
RCALINEAST => tied_to_ground_vec_i(4 downto 0),
RCALINWEST => tied_to_ground_vec_i(4 downto 0),
RCALOUTEAST => open,
RCALOUTWEST => open,
RXCDRRESET0 => tied_to_ground_i,
RXCDRRESET1 => tied_to_ground_i,
RXELECIDLE0 => RXELECIDLE0_OUT,
RXELECIDLE1 => RXELECIDLE1_OUT,
RXEQMIX0 => "11",
RXEQMIX1 => "11",
RXN0 => RXN0_IN,
RXN1 => RXN1_IN,
RXP0 => RXP0_IN,
RXP1 => RXP1_IN,
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXBUFRESET0 => tied_to_ground_i,
RXBUFRESET1 => tied_to_ground_i,
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXENPMAPHASEALIGN0 => tied_to_ground_i,
RXENPMAPHASEALIGN1 => tied_to_ground_i,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => RXSTATUS0_OUT,
RXSTATUS1 => RXSTATUS1_OUT,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => PHYSTATUS0_OUT,
PHYSTATUS1 => PHYSTATUS1_OUT,
RXVALID0 => RXVALID0_OUT,
RXVALID1 => RXVALID1_OUT,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0 => RXPOLARITY0_IN,
RXPOLARITY1 => RXPOLARITY1_IN,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST => open,
GTPCLKFBSEL0EAST => "10",
GTPCLKFBSEL0WEST => "00",
GTPCLKFBSEL1EAST => "11",
GTPCLKFBSEL1WEST => "01",
GTPCLKFBWEST => open,
GTPCLKOUT0 => GTPCLKOUT0_OUT,
GTPCLKOUT1 => GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE0(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARDISPMODE0(1 downto 0) => TXCHARDISPMODE0_IN,
TXCHARDISPMODE1(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARDISPMODE1(1 downto 0) => TXCHARDISPMODE1_IN,
TXCHARDISPVAL0 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL1 => tied_to_ground_vec_i(3 downto 0),
TXCHARISK0(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARISK0(1 downto 0) => TXCHARISK0_IN,
TXCHARISK1(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARISK1(1 downto 0) => TXCHARISK1_IN,
TXENC8B10BUSE0 => tied_to_vcc_i,
TXENC8B10BUSE1 => tied_to_vcc_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => open,
TXRUNDISP1 => open,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
TXENPMAPHASEALIGN0 => tied_to_ground_i,
TXENPMAPHASEALIGN1 => tied_to_ground_i,
TXPMASETPHASE0 => tied_to_ground_i,
TXPMASETPHASE1 => tied_to_ground_i,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i,
TXDATA1 => txdata1_i,
TXDATAWIDTH0 => "01",
TXDATAWIDTH1 => "01",
TXOUTCLK0 => open,
TXOUTCLK1 => open,
TXRESET0 => tied_to_ground_i,
TXRESET1 => tied_to_ground_i,
TXUSRCLK0 => TXUSRCLK0_IN,
TXUSRCLK1 => TXUSRCLK1_IN,
TXUSRCLK20 => TXUSRCLK20_IN,
TXUSRCLK21 => TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXDIFFCTRL0 => "0111",
TXDIFFCTRL1 => "0111",
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => TXN0_OUT,
TXN1 => TXN1_OUT,
TXP0 => TXP0_OUT,
TXP1 => TXP1_OUT,
TXPREEMPHASIS0 => "100",
TXPREEMPHASIS1 => "100",
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR0 => tied_to_ground_i,
TXPRBSFORCEERR1 => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => TXDETECTRX0_IN,
TXDETECTRX1 => TXDETECTRX1_IN,
TXELECIDLE0 => TXELECIDLE0_IN,
TXELECIDLE1 => TXELECIDLE1_IN,
TXPDOWNASYNCH0 => tied_to_ground_i,
TXPDOWNASYNCH1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
 
);
 
end RTL;
 
 
 
/trunk/main_sources/xilinx_pcie2wb.vhd
0,0 → 1,1455
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Istvan Nagy, buenos@freemail.hu
--
-- Create Date: 15:58:13 05/30/2010
-- Design Name: pcie_mini
-- Module Name: xilinx_pcie2wb - Behavioral
-- Version: 1.0
-- Project Name:
-- Target Devices: Xilinx Series-5/6/7 FPGAs
-- Tool versions: ISE-DS 12.1
-- Description:
-- PCI-express endpoint block, transaction layer logic and back-end logic. The main
-- purpose of this file is to make a useable back-end interface and handle flow control
-- for the xilinx auto-generated PCIe endpoint IP.
-- The PCIe endpoint implements one 256MByte memory BAR (Base Address Register).
-- This 256MBytes size is set up in the core config, and also hardcoded in this
-- file (search for: "256MBytes").
-- This 1 BAR is implemented as a Wishbone master interface with byte addressing,
-- where address [x:2] shows DWORD address, while sel[3:0] decodes the 2 LSBs.
-- ADDRESSES ARE BYTE ADDRESSES.
-- The lower address bits are usually zero, so the slave (MCB) has to select bytes based
-- on the byte select signals: sel[3:0]. The output address of the core contails the 2
-- LSBs as well. The core was only tested with 32-bit accesses, byte-wide might work or not.
-- The TLP logic is capable of handling up to 1k bytes (256 DWORDs) payload data in a
-- single PCIe transaction, and can handle only one request at a time. If a new request
-- is arriving while processing the previous one (e.g. getting the data from a wishbone
-- read), then the state machine will not process it immediately, or it will hang. So
-- the user software has to wait for the previous read completion before issueing a new
-- request. The multiple DWORDs are handled separately by the WB statemachine.
-- Performance: WishBone bus: 62.5MHz, 32bit, 2clk/access -> 125MBytes/sec. The maximum
-- data throughput can be achieved when using the maximum data payload (block).
-- The core uses INTA wirtual wire to signal interrupts.
--
-- x1 PCIe, legacy endpoint, uses a 100MHz ref clock. The generated core had to
-- be edited manually to support 100MHz, as per Xilinx AR#33761.
--
-- Dependencies: The CoreGenerator's configured PCIe core is included.
-- If we generate a new pcie endpoint, then copy the new files from the source
-- directory into the project's directory, and copy the generic section of the "pcie"
-- from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
--
-- Revision:
-- Revision 0.01 - File Created
 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
 
 
entity xilinx_pcie2wb is
Port ( --FPGA PINS(EXTERNAL):
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
sys_clk_n : in std_logic;
sys_clk_p : in std_logic;
sys_reset_n : in std_logic;
--ON CHIP PORTS:
--DATA BUS for BAR0 (wishbone):
pcie_bar0_wb_data_o : out std_logic_vector(31 downto 0);
pcie_bar0_wb_data_i : in std_logic_vector(31 downto 0);
pcie_bar0_wb_addr_o : out std_logic_vector(27 downto 0);
pcie_bar0_wb_cyc_o : out std_logic;
pcie_bar0_wb_stb_o : out std_logic;
pcie_bar0_wb_wr_o : out std_logic;
pcie_bar0_wb_ack_i : in std_logic;
pcie_bar0_wb_clk_o : out std_logic; --62.5MHz
pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0);
--OTHER:
pcie_irq : in std_logic;
pcie_resetout : out std_logic --active high
);
end xilinx_pcie2wb;
 
 
 
 
architecture Behavioral of xilinx_pcie2wb is
 
 
 
-- Internal Signals ------------------------------------------------------------
--SIGNAL dummy : std_logic_vector(15 downto 0); --write data bus
SIGNAL cfg_do : std_logic_vector(31 downto 0);
SIGNAL cfg_rd_wr_done_n : std_logic;
SIGNAL cfg_dwaddr : std_logic_vector(9 downto 0);
SIGNAL cfg_rd_en_n : std_logic;
SIGNAL cfg_err_ur_n : std_logic;
SIGNAL cfg_err_cor_n : std_logic;
SIGNAL cfg_err_ecrc_n : std_logic;
SIGNAL cfg_err_cpl_timeout_n : std_logic;
SIGNAL cfg_err_cpl_abort_n : std_logic;
SIGNAL cfg_err_posted_n : std_logic;
SIGNAL cfg_err_locked_n : std_logic;
SIGNAL cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
SIGNAL cfg_err_cpl_rdy_n : std_logic;
SIGNAL cfg_interrupt_n : std_logic;
SIGNAL cfg_interrupt_rdy_n : std_logic;
SIGNAL cfg_interrupt_assert_n : std_logic;
SIGNAL cfg_interrupt_do : std_logic_vector(7 downto 0);
SIGNAL cfg_interrupt_di : std_logic_vector(7 downto 0);
SIGNAL cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
SIGNAL cfg_interrupt_msienable : std_logic;
SIGNAL cfg_turnoff_ok_n : std_logic;
SIGNAL cfg_to_turnoff_n : std_logic;
SIGNAL cfg_pm_wake_n : std_logic;
SIGNAL cfg_pcie_link_state_n : std_logic_vector(2 downto 0);
SIGNAL cfg_trn_pending_n : std_logic;
SIGNAL cfg_dsn : std_logic_vector(63 downto 0);
SIGNAL cfg_bus_number : std_logic_vector(7 downto 0);
SIGNAL cfg_device_number : std_logic_vector(4 downto 0);
SIGNAL cfg_function_number : std_logic_vector(2 downto 0);
SIGNAL cfg_status : std_logic_vector(15 downto 0);
SIGNAL cfg_command : std_logic_vector(15 downto 0);
SIGNAL cfg_dstatus : std_logic_vector(15 downto 0);
SIGNAL cfg_dcommand : std_logic_vector(15 downto 0);
SIGNAL cfg_lstatus : std_logic_vector(15 downto 0);
SIGNAL cfg_lcommand : std_logic_vector(15 downto 0);
-- System Interface
SIGNAL sys_clk : std_logic;
SIGNAL trn_clk : std_logic;
SIGNAL trn_reset_n : std_logic;
SIGNAL received_hot_reset : std_logic;
-- Transaction (TRN) Interface
SIGNAL trn_lnk_up_n : std_logic;
-- data interface Tx
SIGNAL trn_td : std_logic_vector(31 downto 0);
SIGNAL trn_tsof_n : std_logic;
SIGNAL trn_teof_n : std_logic;
SIGNAL trn_tsrc_rdy_n : std_logic;
SIGNAL trn_tdst_rdy_n : std_logic;
SIGNAL trn_terr_drop_n : std_logic;
SIGNAL trn_tsrc_dsc_n : std_logic;
SIGNAL trn_terrfwd_n : std_logic;
SIGNAL trn_tbuf_av : std_logic_vector(5 downto 0);
SIGNAL trn_tstr_n : std_logic;
SIGNAL trn_tcfg_req_n : std_logic;
SIGNAL trn_tcfg_gnt_n : std_logic;
-- data interface Rx
SIGNAL trn_rd : std_logic_vector(31 downto 0);
SIGNAL trn_rsof_n : std_logic;
SIGNAL trn_reof_n : std_logic;
SIGNAL trn_rsrc_rdy_n : std_logic;
SIGNAL trn_rsrc_dsc_n : std_logic;
SIGNAL trn_rdst_rdy_n : std_logic;
SIGNAL trn_rerrfwd_n : std_logic;
SIGNAL trn_rnp_ok_n : std_logic;
SIGNAL trn_rbar_hit_n : std_logic_vector(6 downto 0);
-- flow control
SIGNAL trn_fc_sel : std_logic_vector(2 downto 0);
SIGNAL trn_fc_nph : std_logic_vector(7 downto 0);
SIGNAL trn_fc_npd : std_logic_vector(11 downto 0);
SIGNAL trn_fc_ph : std_logic_vector(7 downto 0);
SIGNAL trn_fc_pd : std_logic_vector(11 downto 0);
SIGNAL trn_fc_cplh : std_logic_vector(7 downto 0);
SIGNAL trn_fc_cpld : std_logic_vector(11 downto 0);
 
SIGNAL start_read_wb0 : std_logic;
SIGNAL start_write_wb0 : std_logic;
SIGNAL wb_transaction_complete : std_logic;
SIGNAL pcie_bar0_wb_data_i_latched : std_logic_vector(31 downto 0);
SIGNAL pcie_bar0_wb_data_o_feed : std_logic_vector(31 downto 0);
SIGNAL pcie_bar0_wb_addr_o_feed : std_logic_vector(27 downto 0);
SIGNAL pcie_bar0_wb_sel_o_feed : std_logic_vector(3 downto 0);
SIGNAL start_read_wb1 : std_logic;
SIGNAL start_write_wb1 : std_logic;
SIGNAL rd_data_ready_wb1 : std_logic;
 
SIGNAL pcie_just_received_a_new_tlp : std_logic ;
SIGNAL pcie_start_reading_rx_tlp : std_logic ;
SIGNAL pcie_there_is_a_new_tlp_to_transmit : std_logic ;
SIGNAL rxtlp_decodedaddress : std_logic_vector(31 downto 0);
SIGNAL tlp_payloadsize_dwords : std_logic_vector(7 downto 0);
SIGNAL rxtlp_firstdw_be : std_logic_vector(3 downto 0);
SIGNAL rxtlp_lastdw_be : std_logic_vector(3 downto 0);
SIGNAL rxtlp_requesterid : std_logic_vector(15 downto 0);
SIGNAL tlp_state : std_logic_vector(7 downto 0);
SIGNAL tlp_state_copy : std_logic_vector(7 downto 0);
SIGNAL rxtlp_data_0 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_1 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_2 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_3 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_4 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_5 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_6 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_data_7 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_0 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_1 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_2 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_3 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_4 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_5 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_6 : std_logic_vector(31 downto 0);
SIGNAL txtlp_data_7 : std_logic_vector(31 downto 0);
SIGNAL pcie_tlp_tx_complete : std_logic;
SIGNAL pcieirq_state : std_logic_vector(7 downto 0);
SIGNAL txtrn_counter : std_logic_vector(7 downto 0);
SIGNAL trn_rx_counter : std_logic_vector(7 downto 0);
SIGNAL cfg_completer_id : std_logic_vector(15 downto 0);
SIGNAL wb0_state : std_logic_vector(7 downto 0);
SIGNAL epif_tx_state : std_logic_vector(7 downto 0);
SIGNAL epif_rx_state : std_logic_vector(7 downto 0);
SIGNAL bit10 : std_logic_vector(1 downto 0);
 
SIGNAL bram_rxtlp_we : std_logic_vector(0 downto 0);
SIGNAL bram_rxtlp_writeaddress : std_logic_vector(31 downto 0);
SIGNAL bram_rxtlp_writedata : std_logic_vector(31 downto 0);
SIGNAL bram_rxtlp_readaddress : std_logic_vector(31 downto 0);
SIGNAL bram_rxtlp_readdata : std_logic_vector(31 downto 0);
SIGNAL bram_txtlp_we : std_logic_vector(0 downto 0);
SIGNAL bram_txtlp_writeaddress : std_logic_vector(8 downto 0);
SIGNAL bram_txtlp_writedata : std_logic_vector(31 downto 0);
SIGNAL bram_txtlp_readaddress : std_logic_vector(31 downto 0);
SIGNAL bram_txtlp_readdata : std_logic_vector(31 downto 0);
SIGNAL tlp_datacount : std_logic_vector(7 downto 0);
--SIGNAL bram_rxtlp_firstdata_address : std_logic_vector(8 downto 0);
SIGNAL rxtlp_header_dw1 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_header_dw2 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_header_dw3 : std_logic_vector(31 downto 0);
SIGNAL rxtlp_header_dw4 : std_logic_vector(31 downto 0);
SIGNAL flag1 : std_logic;
SIGNAL rxdw1_23_0 : std_logic_vector(23 downto 0);
SIGNAL pcie_rxtlp_tag : std_logic_vector(7 downto 0);
SIGNAL pciewb_localreset_n : std_logic;
SIGNAL cfg_interrupt_assert_n_1 : std_logic;
SIGNAL trn_tsrc_rdy_n_1 : std_logic;
SIGNAL trn_tsof_n1 : std_logic;
SIGNAL rcompl_bytecount_field : std_logic_vector(9 downto 0);
-- COMPONENT DECLARATIONS (introducing the IPs) --------------------------------
 
--this is the pcie endpoint core from coregenerator.
--Core name: Xilinx Spartan-6 Integrated
--Block for PCI Express
--Version: 1.2
--Release Date: September 16, 2009. ISE DS 11.4
component pcie is
generic (
TL_TX_RAM_RADDR_LATENCY : integer := 0;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_RADDR_LATENCY : integer := 0;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 0;
VC0_TX_LASTPACKET : integer := 14;
VC0_RX_RAM_LIMIT : bit_vector := x"7FF";
VC0_TOTAL_CREDITS_PH : integer := 32;
VC0_TOTAL_CREDITS_PD : integer := 211;
VC0_TOTAL_CREDITS_NPH : integer := 8;
VC0_TOTAL_CREDITS_CH : integer := 40;
VC0_TOTAL_CREDITS_CD : integer := 211;
VC0_CPL_INFINITE : boolean := TRUE;
BAR0 : bit_vector := x"F0000000";
BAR1 : bit_vector := x"00000000";
BAR2 : bit_vector := x"00000000";
BAR3 : bit_vector := x"00000000";
BAR4 : bit_vector := x"00000000";
BAR5 : bit_vector := x"00000000";
EXPANSION_ROM : bit_vector := "0000000000000000000000";
DISABLE_BAR_FILTERING : boolean := FALSE;
DISABLE_ID_CHECK : boolean := FALSE;
TL_TFC_DISABLE : boolean := FALSE;
TL_TX_CHECKS_DISABLE : boolean := FALSE;
USR_CFG : boolean := FALSE;
USR_EXT_CFG : boolean := FALSE;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
CLASS_CODE : bit_vector := x"068000";
CARDBUS_CIS_POINTER : bit_vector := x"00000000";
PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1";
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"1";
PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE;
PCIE_CAP_INT_MSG_NUM : bit_vector := "00000";
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7;
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7;
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
LINK_CAP_ASPM_SUPPORT : integer := 1;
LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
LINK_CAP_L1_EXIT_LATENCY : integer := 7;
LL_ACK_TIMEOUT : bit_vector := x"0204";
LL_ACK_TIMEOUT_EN : boolean := FALSE;
LL_REPLAY_TIMEOUT : bit_vector := x"0204";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
MSI_CAP_MULTIMSGCAP : integer := 0;
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
PLM_AUTO_CONFIG : boolean := FALSE;
FAST_TRAIN : boolean := FALSE;
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
DISABLE_SCRAMBLING : boolean := FALSE;
PM_CAP_VERSION : integer := 3;
PM_CAP_PME_CLOCK : boolean := FALSE;
PM_CAP_DSI : boolean := FALSE;
PM_CAP_AUXCURRENT : integer := 0;
PM_CAP_D1SUPPORT : boolean := TRUE;
PM_CAP_D2SUPPORT : boolean := TRUE;
PM_CAP_PMESUPPORT : bit_vector := x"0F";
PM_DATA0 : bit_vector := x"04";
PM_DATA_SCALE0 : bit_vector := x"0";
PM_DATA1 : bit_vector := x"00";
PM_DATA_SCALE1 : bit_vector := x"0";
PM_DATA2 : bit_vector := x"00";
PM_DATA_SCALE2 : bit_vector := x"0";
PM_DATA3 : bit_vector := x"00";
PM_DATA_SCALE3 : bit_vector := x"0";
PM_DATA4 : bit_vector := x"04";
PM_DATA_SCALE4 : bit_vector := x"0";
PM_DATA5 : bit_vector := x"00";
PM_DATA_SCALE5 : bit_vector := x"0";
PM_DATA6 : bit_vector := x"00";
PM_DATA_SCALE6 : bit_vector := x"0";
PM_DATA7 : bit_vector := x"00";
PM_DATA_SCALE7 : bit_vector := x"0";
PCIE_GENERIC : bit_vector := "000011101111";
GTP_SEL : integer := 0;
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"ABCD";
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234";
REF_CLK_FREQ : integer := 0
);
port (
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
 
-- Transaction (TRN) Interface
trn_lnk_up_n : out std_logic;
 
-- Tx
trn_td : in std_logic_vector(31 downto 0);
trn_tsof_n : in std_logic;
trn_teof_n : in std_logic;
trn_tsrc_rdy_n : in std_logic;
trn_tdst_rdy_n : out std_logic;
trn_terr_drop_n : out std_logic;
trn_tsrc_dsc_n : in std_logic;
trn_terrfwd_n : in std_logic;
trn_tbuf_av : out std_logic_vector(5 downto 0);
trn_tstr_n : in std_logic;
trn_tcfg_req_n : out std_logic;
trn_tcfg_gnt_n : in std_logic;
 
-- Rx
trn_rd : out std_logic_vector(31 downto 0);
trn_rsof_n : out std_logic;
trn_reof_n : out std_logic;
trn_rsrc_rdy_n : out std_logic;
trn_rsrc_dsc_n : out std_logic;
trn_rdst_rdy_n : in std_logic;
trn_rerrfwd_n : out std_logic;
trn_rnp_ok_n : in std_logic;
trn_rbar_hit_n : out std_logic_vector(6 downto 0);
trn_fc_sel : in std_logic_vector(2 downto 0);
trn_fc_nph : out std_logic_vector(7 downto 0);
trn_fc_npd : out std_logic_vector(11 downto 0);
trn_fc_ph : out std_logic_vector(7 downto 0);
trn_fc_pd : out std_logic_vector(11 downto 0);
trn_fc_cplh : out std_logic_vector(7 downto 0);
trn_fc_cpld : out std_logic_vector(11 downto 0);
 
-- Host (CFG) Interface
cfg_do : out std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : out std_logic;
cfg_dwaddr : in std_logic_vector(9 downto 0);
cfg_rd_en_n : in std_logic;
cfg_err_ur_n : in std_logic;
cfg_err_cor_n : in std_logic;
cfg_err_ecrc_n : in std_logic;
cfg_err_cpl_timeout_n : in std_logic;
cfg_err_cpl_abort_n : in std_logic;
cfg_err_posted_n : in std_logic;
cfg_err_locked_n : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : out std_logic;
cfg_interrupt_n : in std_logic;
cfg_interrupt_rdy_n : out std_logic;
cfg_interrupt_assert_n : in std_logic;
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_turnoff_ok_n : in std_logic;
cfg_to_turnoff_n : out std_logic;
cfg_pm_wake_n : in std_logic;
cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
cfg_trn_pending_n : in std_logic;
cfg_dsn : in std_logic_vector(63 downto 0);
cfg_bus_number : out std_logic_vector(7 downto 0);
cfg_device_number : out std_logic_vector(4 downto 0);
cfg_function_number : out std_logic_vector(2 downto 0);
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
 
-- System Interface
sys_clk : in std_logic;
sys_reset_n : in std_logic;
trn_clk : out std_logic;
trn_reset_n : out std_logic;
received_hot_reset : out std_logic
);
end component pcie;
 
COMPONENT blk_mem_gen_v4_1
PORT(
clka : IN std_logic;
wea : IN std_logic_vector(0 to 0);
addra : IN std_logic_vector(8 downto 0);
dina : IN std_logic_vector(31 downto 0);
clkb : IN std_logic;
addrb : IN std_logic_vector(8 downto 0);
doutb : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
 
 
---- ------- SYNTHESIS ATTRIBUTES: --------------------------------------------------
--attribute keep_hierarchy : string;
--attribute keep_hierarchy of xilinx_pcie2wb: entity is "yes";
 
 
 
-- --------ARCHITECTURE BODY BEGINS -----------------------------------------------
begin
 
 
cfg_turnoff_ok_n <= '1';
 
-- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------------
 
 
-- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------------
 
inst_pcie : pcie
port map (
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
trn_lnk_up_n => trn_lnk_up_n,
trn_td => trn_td, -- Bus [31 : 0]
trn_tsof_n => trn_tsof_n,
trn_teof_n => trn_teof_n,
trn_tsrc_rdy_n => trn_tsrc_rdy_n,
trn_tdst_rdy_n => trn_tdst_rdy_n,
trn_terr_drop_n => trn_terr_drop_n,
trn_tsrc_dsc_n => trn_tsrc_dsc_n,
trn_terrfwd_n => trn_terrfwd_n,
trn_tbuf_av => trn_tbuf_av, -- Bus [31 : 0]
trn_tstr_n => trn_tstr_n,
trn_tcfg_req_n => trn_tcfg_req_n,
trn_tcfg_gnt_n => trn_tcfg_gnt_n,
trn_rd => trn_rd, -- Bus [31 : 0]
trn_rsof_n => trn_rsof_n,
trn_reof_n => trn_reof_n,
trn_rsrc_rdy_n => trn_rsrc_rdy_n,
trn_rsrc_dsc_n => trn_rsrc_dsc_n,
trn_rdst_rdy_n => trn_rdst_rdy_n,
trn_rerrfwd_n => trn_rerrfwd_n,
trn_rnp_ok_n => trn_rnp_ok_n,
trn_rbar_hit_n => trn_rbar_hit_n, -- Bus [31 : 0]
trn_fc_sel => trn_fc_sel, -- Bus [31 : 0]
trn_fc_nph => trn_fc_nph, -- Bus [31 : 0]
trn_fc_npd => trn_fc_npd, -- Bus [31 : 0]
trn_fc_ph => trn_fc_ph, -- Bus [31 : 0]
trn_fc_pd => trn_fc_pd, -- Bus [31 : 0]
trn_fc_cplh => trn_fc_cplh, -- Bus [31 : 0]
trn_fc_cpld => trn_fc_cpld, -- Bus [31 : 0]
cfg_do => cfg_do, -- Bus [31 : 0]
cfg_rd_wr_done_n => cfg_rd_wr_done_n,
cfg_dwaddr => cfg_dwaddr, -- Bus [31 : 0]
cfg_rd_en_n => cfg_rd_en_n,
cfg_err_ur_n => cfg_err_ur_n,
cfg_err_cor_n => cfg_err_cor_n,
cfg_err_ecrc_n => cfg_err_ecrc_n,
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n => cfg_err_cpl_abort_n,
cfg_err_posted_n => cfg_err_posted_n,
cfg_err_locked_n => cfg_err_locked_n,
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header, -- Bus [31 : 0]
cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n,
cfg_interrupt_n => cfg_interrupt_n,
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
cfg_interrupt_assert_n => cfg_interrupt_assert_n,
cfg_interrupt_do => cfg_interrupt_do, -- Bus [31 : 0]
cfg_interrupt_di => cfg_interrupt_di, -- Bus [31 : 0]
cfg_interrupt_mmenable => cfg_interrupt_mmenable, -- Bus [31 : 0]
cfg_interrupt_msienable => cfg_interrupt_msienable,
cfg_turnoff_ok_n => cfg_turnoff_ok_n,
cfg_to_turnoff_n => cfg_to_turnoff_n,
cfg_pm_wake_n => cfg_pm_wake_n,
cfg_pcie_link_state_n => cfg_pcie_link_state_n, -- Bus [31 : 0]
cfg_trn_pending_n => cfg_trn_pending_n,
cfg_dsn => cfg_dsn, -- Bus [31 : 0]
cfg_bus_number => cfg_bus_number, -- Bus [31 : 0]
cfg_device_number => cfg_device_number, -- Bus [31 : 0]
cfg_function_number => cfg_function_number, -- Bus [31 : 0]
cfg_status => cfg_status, -- Bus [31 : 0]
cfg_command => cfg_command, -- Bus [31 : 0]
cfg_dstatus => cfg_dstatus, -- Bus [31 : 0]
cfg_dcommand => cfg_dcommand, -- Bus [31 : 0]
cfg_lstatus => cfg_lstatus, -- Bus [31 : 0]
cfg_lcommand => cfg_lcommand, -- Bus [31 : 0]
sys_clk => sys_clk,
sys_reset_n => sys_reset_n,
trn_clk => trn_clk,
trn_reset_n => trn_reset_n,
received_hot_reset => received_hot_reset
);
 
--block ram for RX TLP:
Inst_bram_rxtlp: blk_mem_gen_v4_1 PORT MAP(
clka => trn_clk,
wea => bram_rxtlp_we,
addra => bram_rxtlp_writeaddress(8 downto 0),
dina => bram_rxtlp_writedata,
clkb => trn_clk,
addrb => bram_rxtlp_readaddress(8 downto 0),
doutb => bram_rxtlp_readdata
);
 
--block ram for TX TLP:
Inst_bram_txtlp: blk_mem_gen_v4_1 PORT MAP(
clka => trn_clk,
wea => bram_txtlp_we,
addra => bram_txtlp_writeaddress(8 downto 0),
dina => bram_txtlp_writedata,
clkb => trn_clk,
addrb => bram_txtlp_readaddress(8 downto 0),
doutb => bram_txtlp_readdata
);
 
 
 
 
 
-- MAIN LOGIC: ---------------------------------------------------------------------------------------------
--System Signals:--------------------------------
--Clock Input Buffer for differential system clock
IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => sys_clk, -- Buffer output
I => sys_clk_p, -- Diff_p buffer input (connect directly to top-level port)
IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port)
);
 
--wishbone clock output:
pcie_bar0_wb_clk_o <= trn_clk;
--pcie_bar1_wb_clk_o <= trn_clk;
 
--use one of these for resetting logic in this file:
pciewb_localreset_n <= sys_reset_n; --dont wait for the PCIE-EP to finish its init.
--pciewb_localreset_n <= trn_reset_n;
--pciewb_localreset_n <= trn_reset_n and (not trn_lnk_up_n) and (not received_hot_reset);
--reset to the core:
--sys_reset_n comes from toplevel directly to the core. same name
--reset output to other cores:
pcie_resetout <= not pciewb_localreset_n;
--trn_lnk_up_n --not used.
 
--pcie ep ip config port: ----------------------------------------------------------
--trn_fc_sel <= "000";
 
trn_rnp_ok_n <= '0';
--trn_terrfwd_n <= '1';
 
--trn_tcfg_gnt_n <= '0';
 
cfg_err_cor_n <= '1';
cfg_err_ur_n <= '1';
cfg_err_ecrc_n <= '1';
cfg_err_cpl_timeout_n <= '1';
cfg_err_cpl_abort_n <= '1';
cfg_err_posted_n <= '0';
cfg_err_locked_n <= '1';
cfg_pm_wake_n <= '1';
cfg_trn_pending_n <= '1';
 
--trn_tstr_n <= '0';
--cfg_interrupt_assert_n <= '1'; --used in a process at the bottom of this file
--cfg_interrupt_n <= '1';
--cfg_interrupt_di <= x"00"; --intA used
 
cfg_err_tlp_cpl_header <= (OTHERS => '0');
cfg_dwaddr <= (OTHERS => '0');
cfg_rd_en_n <= '1';
--serial number:
cfg_dsn <= (OTHERS => '0');
 
-- AT THE BOTTOM OF THIS FILE:
-- --some fix values:
-- trn_tsrc_dsc_n <= '1'; --no errors on trn bus
-- trn_tstr_n <= '0'; --pipelining (0= link may begin before the entire packet has been written)
-- trn_tcfg_gnt_n <= '0'; --no tlp priorities
-- trn_terrfwd_n <= '1'; --no errors on trn
-- --nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n
 
 
 
--use this in read completion packets:
cfg_completer_id <= cfg_bus_number & cfg_device_number & cfg_function_number;
 
 
 
 
 
-- WISBONE BACK-end INTERFACE ----------------------------------------------------
 
--main state machine: set states, capture inputs, set addr/data outputs
--minimum 2 clock cycles / transaction. writes are posted, reads have wait states.
process (pciewb_localreset_n, trn_clk, wb0_state, start_read_wb0, start_write_wb0,
pcie_bar0_wb_addr_o_feed, pcie_bar0_wb_data_o_feed, pcie_bar0_wb_sel_o_feed)
begin
if (pciewb_localreset_n='0') then
wb0_state <= "00000000";
wb_transaction_complete <= '0';
pcie_bar0_wb_addr_o <= "0000000000000000000000000000";
pcie_bar0_wb_sel_o <= "0000";
pcie_bar0_wb_data_o <= "00000000000000000000000000000000";
wb_transaction_complete <='0';
else
if (trn_clk'event and trn_clk = '1') then
case ( wb0_state ) is
 
--********** IDLE STATE **********
when "00000000" => --state 0
wb_transaction_complete <='0';
pcie_bar0_wb_sel_o(0) <= pcie_bar0_wb_sel_o_feed(3); --swap endianism
pcie_bar0_wb_sel_o(1) <= pcie_bar0_wb_sel_o_feed(2); --swap endianism
pcie_bar0_wb_sel_o(2) <= pcie_bar0_wb_sel_o_feed(1); --swap endianism
pcie_bar0_wb_sel_o(3) <= pcie_bar0_wb_sel_o_feed(0); --swap endianism
--or no endian swap on SEL: pcie_bar0_wb_sel_o <= pcie_bar0_wb_sel_o_feed;
pcie_bar0_wb_addr_o <= pcie_bar0_wb_addr_o_feed;
if (start_read_wb0 ='1') then --go to read
wb0_state <= "00000001";
elsif (start_write_wb0 ='1') then --go to write
wb0_state <= "00000010";
--no endian swap: pcie_bar0_wb_data_o <= pcie_bar0_wb_data_o_feed;
pcie_bar0_wb_data_o (7 downto 0) <= pcie_bar0_wb_data_o_feed(31 downto 24); --swap endianism
pcie_bar0_wb_data_o (15 downto 8) <= pcie_bar0_wb_data_o_feed(23 downto 16); --swap endianism
pcie_bar0_wb_data_o (23 downto 16) <= pcie_bar0_wb_data_o_feed(15 downto 8); --swap endianism
pcie_bar0_wb_data_o (31 downto 24) <= pcie_bar0_wb_data_o_feed(7 downto 0); --swap endianism
end if;
 
--********** READ STATE **********
--set the outputs,
--if ACK asserted, sample the data input
--The hold requirements are oversatisfyed by going back to idle, and by the fact that the slave uses the cyc/stb/wr strobes synchronously.
when "00000001" => --state 1
if (pcie_bar0_wb_ack_i='1') then
--no endian swap: pcie_bar0_wb_data_i_latched <= pcie_bar0_wb_data_i; --sample the incoming data
pcie_bar0_wb_data_i_latched (7 downto 0) <= pcie_bar0_wb_data_i(31 downto 24); --swap endianism
pcie_bar0_wb_data_i_latched (15 downto 8) <= pcie_bar0_wb_data_i(23 downto 16); --swap endianism
pcie_bar0_wb_data_i_latched (23 downto 16) <= pcie_bar0_wb_data_i(15 downto 8); --swap endianism
pcie_bar0_wb_data_i_latched (31 downto 24) <= pcie_bar0_wb_data_i(7 downto 0); --swap endianism
wb_transaction_complete <='1'; --signalling ready, but only for one clock cycle
wb0_state <= "00000000"; --go to state 0
else
wb_transaction_complete <='0';
end if;
 
--********** WRITE STATE **********
--if ACK asserted, go back to idle
--The hold requirements are oversatisfyed by waiting for ACK to remove write data
when "00000010" => --state 2
if (pcie_bar0_wb_ack_i='1') then
wb0_state <= "00000000"; --go to state 0
wb_transaction_complete <='1';
else
wb_transaction_complete <='0';
end if;
when others => --error
wb0_state <= "00000000"; --go to state 0
end case;
end if;
end if;
end process;
--sync control on wb-control signals:
process (pciewb_localreset_n, wb0_state)
begin
if (pciewb_localreset_n='0') then
pcie_bar0_wb_cyc_o <= '0';
pcie_bar0_wb_stb_o <= '0';
pcie_bar0_wb_wr_o <= '0';
else
if (wb0_state = "00000000") then --idle
pcie_bar0_wb_cyc_o <= '0';
pcie_bar0_wb_stb_o <= '0';
pcie_bar0_wb_wr_o <= '0';
elsif (wb0_state = "00000001") then --read
pcie_bar0_wb_cyc_o <= '1';
pcie_bar0_wb_stb_o <= '1';
pcie_bar0_wb_wr_o <= '0';
elsif (wb0_state = "00000010") then --write
pcie_bar0_wb_cyc_o <= '1';
pcie_bar0_wb_stb_o <= '1';
pcie_bar0_wb_wr_o <= '1';
else
pcie_bar0_wb_cyc_o <= '0';
pcie_bar0_wb_stb_o <= '0';
pcie_bar0_wb_wr_o <= '0';
end if;
end if;
end process;
 
 
 
 
 
 
 
 
-- INTERFACE TO THE PCIE-EP IP --------------------------------------------------------
--trn_clk and trn_reset_n are the same as the pcie_resetout and pcie_bar0_wb_clk_o,
--so it is not a clock domain crossing.
 
 
-- TX: INTERFACE TO THE PCIE-EP: TRANSMIT TLP PACKETS:-----
--Read completion is 3DW header. This core only transmits read completion or Unbsupported request packets.
process (pciewb_localreset_n, trn_clk, epif_tx_state, bram_txtlp_readdata , bram_txtlp_readaddress,
pcie_there_is_a_new_tlp_to_transmit, tlp_payloadsize_dwords, txtrn_counter)
begin
if (pciewb_localreset_n='0') then
epif_tx_state <= "00000000";
trn_tsrc_rdy_n_1 <='1';
trn_tsof_n1 <= '1';
trn_teof_n <= '1';
trn_td <= (OTHERS => '0');
pcie_tlp_tx_complete <= '0';
txtrn_counter <= "00000001";
bram_txtlp_readaddress <= (OTHERS => '0');
else
if (trn_clk'event and trn_clk = '1') then
case ( epif_tx_state ) is
 
--********** idle STATE **********
when "00000000" => --state 0
--if there is a new TLP assembled and the EP is ready,
--start the tx-trn bus transaction.
if (pcie_there_is_a_new_tlp_to_transmit='1') then
epif_tx_state <= "00000001"; --next state
end if;
trn_tsrc_rdy_n_1 <='1';
trn_tsof_n1 <= '1';
trn_teof_n <= '1';
trn_td <= (OTHERS => '0');
pcie_tlp_tx_complete <= '0';
txtrn_counter <= "00000001";
bram_txtlp_readaddress <= (OTHERS => '0');
 
--********** ready-wait STATE **********
when "00000001" => --state 1
--if there is a new TLP assembled and the EP is ready,
--start the tx-trn bus transaction.
if (trn_tdst_rdy_n='0') then
epif_tx_state <= "00000010"; --next state
end if;
trn_tsrc_rdy_n_1 <='1';
trn_tsof_n1 <= '1';
trn_teof_n <= '1';
trn_td <= (OTHERS => '0');
pcie_tlp_tx_complete <= '0';
txtrn_counter <= "00000001";
bram_txtlp_readaddress <= (OTHERS => '0');
--********** transfer STATE **********
when "00000010" => --state 2
trn_tsrc_rdy_n_1 <='0';
trn_td <= bram_txtlp_readdata;
if (trn_tdst_rdy_n='0') then
txtrn_counter <= txtrn_counter +1;
bram_txtlp_readaddress <= bram_txtlp_readaddress +1;
end if;
if (txtrn_counter = "00000010") then
trn_tsof_n1 <= '0'; --start
else
trn_tsof_n1 <= '1';
end if;
--test number of dwords:
if (txtrn_counter = tlp_payloadsize_dwords +4) then -- "+3" is the header and "+1" is for the delay
--this is the last dword, next clk is next state
epif_tx_state <= "00000000"; --back to idle, since finished
trn_teof_n <= '0'; --end
pcie_tlp_tx_complete <= '1'; --assert for 1 clk
else
trn_teof_n <= '1'; --not end yet
pcie_tlp_tx_complete <= '0'; --not complete yet
end if;
 
when others => --error
epif_tx_state <= "00000000"; --back to idle
trn_tsrc_rdy_n_1 <='1';
trn_tsof_n1 <= '1';
trn_teof_n <= '1';
trn_td <= (OTHERS => '0');
pcie_tlp_tx_complete <= '0';
txtrn_counter <= "00000001";
end case;
end if;
end if;
end process;
--this (little delay) is to fix a hold time violation created inside the pcie-ep ip:
trn_tsrc_rdy_n <= trn_tsrc_rdy_n_1 or (not pciewb_localreset_n);
trn_tsof_n <= trn_tsof_n1 or (not pciewb_localreset_n);
 
 
--some fix values:
trn_tsrc_dsc_n <= '1'; --no errors on trn bus
trn_tstr_n <= '0'; --pipelining
trn_tcfg_gnt_n <= '0'; --no tlp priorities
trn_terrfwd_n <= '1'; --no errors on trn
--nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n
 
 
 
 
 
-- RX: INTERFACE TO THE PCIE-EP: GET thereceived TLP PACKETS:- ----
process (pciewb_localreset_n, trn_clk, epif_rx_state, tlp_state, trn_rx_counter, bram_rxtlp_writeaddress)
begin
if (pciewb_localreset_n='0') then
pcie_just_received_a_new_tlp <= '0';
epif_rx_state <= "00000000";
trn_rdst_rdy_n <= '1';
trn_rx_counter <= (OTHERS => '0');
bram_rxtlp_we <= "0";
bram_rxtlp_writeaddress <= (OTHERS => '0');
bram_rxtlp_writedata <= (OTHERS => '0');
else
if (trn_clk'event and trn_clk = '1') then
 
if (tlp_state = 0)then
trn_rdst_rdy_n <= '0';
else
trn_rdst_rdy_n <= '1';
end if;
case ( epif_rx_state ) is
 
--********** idle STATE **********
when "00000000" => --state 0
pcie_just_received_a_new_tlp <= '0';
bram_rxtlp_writedata <= trn_rd;
if (trn_rsrc_rdy_n='0' and trn_rsof_n='0') then
trn_rx_counter <= trn_rx_counter +1;
bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1;
epif_rx_state <= "00000001";
--read first DW:
bram_rxtlp_we <= "1";
else
trn_rx_counter <= (OTHERS => '0');
bram_rxtlp_writeaddress <= (OTHERS => '0');
bram_rxtlp_we <= "0";
end if;
 
--********** read STATE **********
when "00000001" => --state 1
if (trn_reof_n ='0') then --last dw
epif_rx_state <= "00000010"; --for the next clk cycle
end if;
if (trn_rsrc_rdy_n='0') then --only act if the EP was ready
trn_rx_counter <= trn_rx_counter +1;
bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1;
bram_rxtlp_writedata <= trn_rd;
end if;
--in an early stage of this transfer, the scheduler can already
--start working on the data, this way its pipelined, so the latency is lower.
if (trn_rx_counter = "00000010") then
pcie_just_received_a_new_tlp <= '1';--assert for one clk only
else
pcie_just_received_a_new_tlp <= '0';
end if;
 
--********** finished filling up RX TLP STATE **********
when "00000010" => --state 2
epif_rx_state <= "00000000";
trn_rx_counter <= (OTHERS => '0');
when others => --error
epif_rx_state <= "00000000"; --go to state 0
end case;
end if;
end if;
end process;
--fixed connections:
--trn_rnp_ok_ntrn_rnp_ok_n <= '0'; --ready to receive non-posted
--not connected: trn_rerrfwd_n, trn_rsrc_dsc_n, trn_rbar_hit_n
 
 
 
 
 
-- flow control: INTERFACE TO THE PCIE-EP: - ----
--not used. pcie-ep provides information about credit status.
--unconnected: trn_fc_nph, trn_fc_npd, trn_fc_ph, trn_fc_pd, trn_fc_cplh, trn_fc_cpld
trn_fc_sel <= "000";
 
 
 
 
 
-- --- GLUE LOGIC BETWEEN THE PCIE CORE-IF AND THE WB INTERFACES -----------------------
-- --- ALSO TLP PACKET PROCESSING.
--Theory of operation:
--RX: If we receive a TLP (pcie_just_received_a_new_tlp goes high for one clock cycle),
--then store it (pcie_received_tlp), decode it (to figure out if its read request,
--posted write or non-supported request), then assert a flag (start_write_wb0 or
--start_read_wb0)to initiate a wishbone cycle.
--TX: At the completion of a wishbone read, the wishbone statemachine asserts the
--wb_transaction_complete flag, so we can assemble the TX TLP packet (pcie_to_transmit_tlp)
--and assert the flag named pcie_there_is_a_new_tlp_to_transmit. This packet will be
--a read completion packet on the PCIe link.
--
--This core can handle 1...8 DWORD accesses in one request (max 256bit payload ),
--and can handle only one request at a time. If a new request is arriving while
--processing the previous one (e.g. getting the data from a wishbone read), then
--the state machine will not process it immediately, or it will hang. So the user
--software has to wait for the previous read completion before issueing a new request.
--The multiple DWORDs are handled separately by the WB statemachine.
--Performance: WishBone bus: 62.5MHz, 32bit, 3clk/access -> 83MBytes/sec
--
--TLP decoding:
--Header+Payload_data+TLP_DIGEST(ECRC).
--received Header:
--First Dword: bit.30/29=format: 00=3DW-header+no_data, 01=4DW-header+no_data,
--10=3DW-header+data, 11=4DW-header+data. bit.28:24=type: 00000 or 00001 are memory
--read requests, 00000 or 00001 are memory write request if type=1x. read request
--completion is 01010 and type=10. bit.9:0 is payload size [DW].
--Second Dword: bit.31:16 is requester ID. bit3:0 is first dword byte enable, bit.7:4 is
--byte enable for last dword data. intermediate dwords have all bytes enabled.
--Third DWORD: address, where bit.1:0=00b. 4DW headers are for 64bit. 64bit adressing
--uses 3rd-dword for addre63:32, 4th dword for addr31:0.
--
--The TLP variables in this core: BRAM memory used store TLP, up to 1-2kBytes
--
--Read completion is 3DW header and routed by completer-ID and requester-ID, not address.
--The core has to store the requester ID and feed it back in the completion packet.
--Completion status: 000=successful, 100=completer_abort, 001=unsupported request. byte
--count is N.of bytes left. lower_address is the first enabled byte of data returned
--with the Completion.
--
-- Completion packet header:
--DW1 >
--7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
--r FMT type----- r TC--- reserv- T E att r r lenght-------------
-- x 0 D P rib
--DW2 >
--7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
--COMPLETER_ID------------------- statu B byte_count-------------
-- CM
--DW3 >
--7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
--REQUESTER_ID------------------- tag------------ r lower_address
 
 
--TLP-protocol statemachine:
process (pciewb_localreset_n, trn_clk, tlp_state,
pcie_just_received_a_new_tlp, tlp_datacount,
bram_rxtlp_readdata, bram_txtlp_writeaddress, bram_rxtlp_readaddress,
tlp_state_copy, rxtlp_decodedaddress,
rxtlp_header_dw1, rxtlp_header_dw2, rxtlp_header_dw3, rxtlp_header_dw4,
bit10, rxtlp_firstdw_be, wb_transaction_complete, flag1, rxdw1_23_0, pcie_rxtlp_tag,
tlp_payloadsize_dwords, pcie_bar0_wb_data_i_latched, cfg_completer_id,
rxtlp_requesterid)
begin
if (pciewb_localreset_n='0') then
start_read_wb0 <= '0';
start_write_wb0 <= '0';
pcie_bar0_wb_data_o_feed <= (others => '0');
pcie_bar0_wb_addr_o_feed <= (others => '0');
pcie_bar0_wb_sel_o_feed <= (others => '0');
pcie_there_is_a_new_tlp_to_transmit <= '0';
rxtlp_decodedaddress<= (others => '0');
tlp_payloadsize_dwords <= (others => '0');
rxtlp_firstdw_be <= (others => '0');
rxtlp_lastdw_be <= (others => '0');
rxtlp_requesterid <= (others => '0');
tlp_state <= (others => '0');
tlp_state_copy <= (others => '0');
bram_txtlp_we <= "0";
bram_txtlp_writeaddress <= (others => '0');
bram_txtlp_writedata <= (others => '0');
bram_rxtlp_readaddress <= (others => '0');
rxtlp_header_dw1 <= "01111111000000000000000000000000";
rxtlp_header_dw2 <= (others => '0');
rxtlp_header_dw3 <= (others => '0');
rxtlp_header_dw4 <= (others => '0');
flag1 <= '0';
rxdw1_23_0 <= (others => '0');
pcie_rxtlp_tag <= (others => '0');
rcompl_bytecount_field <= (others => '0');
else
if (trn_clk'event and trn_clk = '1') then
case ( tlp_state ) is
 
--********** IDLE STATE **********
--also re-initialize signals...
when "00000000" => --state 0
if (pcie_just_received_a_new_tlp='1') then
tlp_state <= "00000001"; --to tlp decoding state
end if;
start_write_wb0 <= '0';
start_read_wb0 <= '0';
tlp_state_copy <= tlp_state;
bram_txtlp_we <= "0";
bram_txtlp_writeaddress <= (others => '0');
bram_txtlp_writedata <= (others => '0');
bram_rxtlp_readaddress <= (others => '0');
tlp_datacount <= "00000001";
rxtlp_header_dw1 <= "01111111000000000000000000000000"; --this is to prevent false decode
pcie_bar0_wb_data_o_feed <= (others => '0');
pcie_bar0_wb_addr_o_feed <= (others => '0');
pcie_bar0_wb_sel_o_feed <= (others => '0');
rxtlp_header_dw1 <= "01111111000000000000000000000000";
rxtlp_header_dw2 <= (others => '0');
rxtlp_header_dw3 <= (others => '0');
rxtlp_header_dw4 <= (others => '0');
rxdw1_23_0 <= (others => '0');
pcie_rxtlp_tag <= (others => '0');
pcie_there_is_a_new_tlp_to_transmit <= '0';
rxtlp_decodedaddress<= (others => '0');
tlp_payloadsize_dwords <= (others => '0');
rxtlp_firstdw_be <= (others => '0');
rxtlp_lastdw_be <= (others => '0');
rxtlp_requesterid <= (others => '0');
rcompl_bytecount_field <= (others => '0');
 
 
--********** TLP ARRIVED STATE **********
--read TLP out of EP, decode and decide,
--latch address/sel/wr_data
--All the "IF"-statements use address+1, because the BRAM read side has data available 1clk late!!!
--Added an ectra clock delay, based on testing, since the data is one more CLK late.
when "00000001" => --state 1
--latch the header:
bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
if (bram_rxtlp_readaddress = "000000010") then
rxtlp_header_dw1 <= bram_rxtlp_readdata;
elsif (bram_rxtlp_readaddress = "000000011") then
rxtlp_header_dw2 <= bram_rxtlp_readdata;
elsif (bram_rxtlp_readaddress = "000000100") then
rxtlp_header_dw3 <= bram_rxtlp_readdata;
elsif (bram_rxtlp_readaddress = "000000101") then
rxtlp_header_dw4 <= bram_rxtlp_readdata;
end if;
--decode some parameters:
tlp_payloadsize_dwords <= rxtlp_header_dw1(7 downto 0);
rxtlp_firstdw_be <= rxtlp_header_dw2(3 downto 0);
rxtlp_lastdw_be <= rxtlp_header_dw2(7 downto 4);
rxtlp_requesterid <= rxtlp_header_dw2(31 downto 16);
flag1 <= rxtlp_header_dw1(31);
rxdw1_23_0 <= rxtlp_header_dw1(23 downto 0); --various fields pcie_received_tlp (22 downto 0);
pcie_rxtlp_tag <= rxtlp_header_dw2(15 downto 8) ; --pcie_received_tlp (47 downto 40);--tag
--decide based on header:
if (rxtlp_header_dw1(30 downto 24)="0000000") then --32bit read
if (bram_rxtlp_readaddress = "000000100") then
rxtlp_decodedaddress <= bram_rxtlp_readdata;
bram_txtlp_writeaddress(8 downto 0) <= "000000011"; --point after the 3dw readcompl header
tlp_state <= "00000011";
end if;
elsif (rxtlp_header_dw1(30 downto 24)="0100000") then --64bit read
if (bram_rxtlp_readaddress = "000000101") then
rxtlp_decodedaddress <= bram_rxtlp_readdata;
bram_txtlp_writeaddress(8 downto 0) <= "000000011"; --point after the 3dw readcompl header
tlp_state <= "00000011";
end if;
elsif (rxtlp_header_dw1(30 downto 24)="1000000") then --32bit write
if (bram_rxtlp_readaddress = "000000100") then
rxtlp_decodedaddress <= bram_rxtlp_readdata;
tlp_state <= "00000010";
end if;
elsif (rxtlp_header_dw1(30 downto 24)="1100000") then --64bit write
if (bram_rxtlp_readaddress = "000000101") then
rxtlp_decodedaddress <= bram_rxtlp_readdata;
tlp_state <= "00000010";
end if;
elsif (rxtlp_header_dw1(30 downto 24)="1111111") then --just wait until this gets a real value
rxtlp_decodedaddress <= bram_rxtlp_readdata;
else --unsupported request
if (bram_rxtlp_readaddress = "000000100") then
tlp_state <= "00000101";
bram_txtlp_writeaddress <= "111111111";
end if;
end if;
 
 
--********** WRITE STATE **********
--initiate WB write(s) (1...N DWORD accesses)
when "00000010" => --state 2
pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1; --256MBytes size is hardcoded here, by cutting 4-MSB off
pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be;
pcie_bar0_wb_data_o_feed <= bram_rxtlp_readdata;
tlp_state_copy <= tlp_state;
if (tlp_state_copy = tlp_state) then
start_write_wb0 <= '0';
else --generate just one pulse, at the first clk cycle in this state
start_write_wb0 <= '1';
end if;
if (wb_transaction_complete='1') then --one DW transfer completed
if (tlp_payloadsize_dwords = tlp_datacount) then --all data completed
tlp_state <= "00000000"; --to idle
else
tlp_state <= "00010100"; --restart wb transaction with new data
bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
tlp_datacount <= tlp_datacount +1;
end if;
end if;
--* Write restart state *
when "00010100" => --state 20
tlp_state <= "00000010";
 
 
--********** READ STATE **********
--initiate WB read, then go to completion state
when "00000011" => --state 3
pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1;
pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be;
tlp_state_copy <= tlp_state;
if (tlp_state_copy = tlp_state) then
start_read_wb0 <= '0';
else --generate just one pulse
start_read_wb0 <= '1';
end if;
if (wb_transaction_complete='1') then
bram_txtlp_writedata <= pcie_bar0_wb_data_i_latched;
bram_txtlp_we <= "1";
if (tlp_payloadsize_dwords = tlp_datacount)then
tlp_state <= "01111110"; --read completion
--bram_txtlp_writeaddress remains the same to capture data in next clock cycle
else
tlp_state <= "00011110"; --one more wb read
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
tlp_datacount <= tlp_datacount +1;
end if;
else
bram_txtlp_we <= "0";
end if;
--* read restart STATE *
when "00011110" => --state 30
tlp_state <= "00000011";
bram_txtlp_we <= "0";
--intermediate state before completion (to ensure data latch at address-4)
when "01111110" => --state 126
tlp_state <= "00000100";
bram_txtlp_writeaddress <= (OTHERS => '0');
--pre-write header-DW1:
bram_txtlp_writedata (31) <= flag1; --reserved
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
--Calculate completion header's "rcompl_bytecount_field" from rxtlp_firstdw_be, rxtlp_lastdw_be, tlp_payloadsize_dwords
if (rxtlp_lastdw_be="0000") then --max 1DW
if (rxtlp_firstdw_be="1111") then --4bytes
rcompl_bytecount_field <= "0000000100";
elsif (rxtlp_firstdw_be="0111" or rxtlp_firstdw_be="1110") then
rcompl_bytecount_field <= "0000000011";
elsif (rxtlp_firstdw_be="0011" or rxtlp_firstdw_be="1100" or rxtlp_firstdw_be="0110") then
rcompl_bytecount_field <= "0000000010";
else
rcompl_bytecount_field <= "0000000001";
end if;
else --more than 1DW: right now we dont support non-aligned multi-Dword accesses
rcompl_bytecount_field(9 downto 2) <= tlp_payloadsize_dwords;
rcompl_bytecount_field(1 downto 0) <= "00";
end if;
 
 
--********** READ COMPLETION STATE **********
--assemble the tx TLP and initiate the transmit
--buffer signals bram_txtlp_we, bram_txtlp_writeaddress, bram_txtlp_writedata
when "00000100" => --state 4
tlp_state_copy <= tlp_state;
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
if (bram_txtlp_writeaddress="000000000") then --if address is 0: launch data for next lock/address(1): header-2.dw
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
bram_txtlp_writedata (15 downto 13) <= "000"; --status= succesful***
bram_txtlp_writedata (12) <= '0'; --reserved
bram_txtlp_writedata (11 downto 10) <= "00";
bram_txtlp_writedata (9 downto 0) <= rcompl_bytecount_field; --total bytes returned
bram_txtlp_we <= "1";
elsif (bram_txtlp_writeaddress="000000001") then --if address is 1: launch data for next lock/address(2): header-3.dw
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
bram_txtlp_writedata (7) <= '0'; --reserved
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0); --lower address
else --data dwords, disable writes from next clock cycle
bram_txtlp_we <= "0";
end if;
--one pulse to start the ep-if statemachine, upon arriving to this state
if (tlp_state_copy = tlp_state) then
pcie_there_is_a_new_tlp_to_transmit <= '0';
else
pcie_there_is_a_new_tlp_to_transmit <= '1';
end if;
--back to idle when the ep-if tx is finished: (wait to avoid overwrite)
if (pcie_tlp_tx_complete='1') then
tlp_state <= "00000000";
end if;
 
 
--********** UNSUPPORTED REQUEST STATE **********
--completion response with status=001
when "00000101" => --state 5
tlp_state_copy <= tlp_state;
tlp_payloadsize_dwords <= "00000000";
--assembling the TLP packet: )
if (bram_txtlp_writeaddress="111111111") then --header 1.dw
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
bram_txtlp_we <= "1";
bram_txtlp_writedata (31) <= flag1; --reserved
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
elsif (bram_txtlp_writeaddress="000000000") then --header 2.dw
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
bram_txtlp_we <= "1";
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
bram_txtlp_writedata (15 downto 13) <= "000"; --status= UNSUPPORTED REQUEST ***
bram_txtlp_writedata (12) <= '0'; --reserved
bram_txtlp_writedata (11 downto 0) <= "000000000000"; --remaining byte count
elsif (bram_txtlp_writeaddress="000000001") then --header 3.dw
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
bram_txtlp_we <= "1";
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
bram_txtlp_writedata (7) <= '0'; --reserved
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0); --lower address
else --data dwords
--2. read data : no data in this type of packet
--this was written directly during the read state.
bram_txtlp_writeaddress <= bram_txtlp_writeaddress;
bram_txtlp_we <= "0";
end if;
--one pulse to start the ep-if statemachine, upon arriving to this state
if (tlp_state_copy = tlp_state) then
pcie_there_is_a_new_tlp_to_transmit <= '0';
else
pcie_there_is_a_new_tlp_to_transmit <= '1';
end if;
--back to idle when finished:
if (pcie_tlp_tx_complete='1') then
tlp_state <= "00000000";
end if;
when others => --error
tlp_state <= "00000000"; --go to state 0
end case;
end if;
end if;
end process; --end tlp statemachine
 
 
 
 
--byte enable encoding to wb_address bit1:0
--this also takes the endian swapping into account.
process ( pciewb_localreset_n, rxtlp_firstdw_be )
begin
if (pciewb_localreset_n = '0') then
bit10(1 downto 0) <="00";
else
if (rxtlp_firstdw_be ="0001") then
bit10(1 downto 0) <= "11";
elsif (rxtlp_firstdw_be ="0010") then
bit10(1 downto 0) <= "10";
elsif (rxtlp_firstdw_be ="0100") then
bit10(1 downto 0) <= "01";
elsif (rxtlp_firstdw_be ="1000") then
bit10(1 downto 0) <= "00";
elsif (rxtlp_firstdw_be ="0011") then
bit10(1 downto 0) <= "10";
elsif (rxtlp_firstdw_be ="1100") then
bit10(1 downto 0) <= "00";
elsif (rxtlp_firstdw_be ="1111") then
bit10(1 downto 0) <= "00";
else --this should never happen
bit10(1 downto 0) <= "00";
end if;
end if;
end process;
--without endian swap:
-- process ( pciewb_localreset_n, rxtlp_firstdw_be )
-- begin
-- if (pciewb_localreset_n = '0') then
-- bit10(1 downto 0) <="00";
-- else
-- if (rxtlp_firstdw_be ="0001") then
-- bit10(1 downto 0) <= "00";
-- elsif (rxtlp_firstdw_be ="0010") then
-- bit10(1 downto 0) <= "01";
-- elsif (rxtlp_firstdw_be ="0100") then
-- bit10(1 downto 0) <= "10";
-- elsif (rxtlp_firstdw_be ="1000") then
-- bit10(1 downto 0) <= "11";
-- elsif (rxtlp_firstdw_be ="0011") then
-- bit10(1 downto 0) <= "00";
-- elsif (rxtlp_firstdw_be ="1100") then
-- bit10(1 downto 0) <= "10";
-- elsif (rxtlp_firstdw_be ="1111") then
-- bit10(1 downto 0) <= "00";
-- else --this should never happen
-- bit10(1 downto 0) <= "00";
-- end if;
-- end if;
-- end process;
 
-- INTERRUPTS: -------------------------------------------------------------------------
--to assert an interrupt, use the cfg_interrupt_assert_n pin.
--datasheet text:
--As shown in Figure 6-30, the user application first asserts cfg_interrupt_n and
--cfg_interrupt_assert_n to assert the interrupt. The user application should select a
--specific interrupt (INTA, INTB, INTC, or INTD) using cfg_interrupt_di[7:0] as shown
--in Table 6-19.
-- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt has been accepted.
--On the following clock cycle, the user application deasserts cfg_interrupt_n and, if the
--Interrupt Disable bit in the PCI Command register is set to 0, the core sends an assert
--interrupt message (Assert_INTA, Assert_INTB, and so forth).
-- After the user application has determined that the interrupt has been serviced, it
--asserts cfg_interrupt_n while deasserting cfg_interrupt_assert_n to deassert the
--interrupt. The appropriate interrupt must be indicated via cfg_interrupt_di[7:0].
-- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt deassertion has
--been accepted. On the following clock cycle, the user application deasserts
--cfg_interrupt_n and the core sends a deassert interrupt message (Deassert_INTA,
--Deassert_INTB, and so forth).
--cfg_interrupt_di[7:0] value Legacy Interrupt
--00h INTA
--01h INTB
--02h INTC
--03h INTD
 
cfg_interrupt_di <= "00000000"; --intA used
 
process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
cfg_interrupt_rdy_n)
begin
if (pciewb_localreset_n='0') then
pcieirq_state <= "00000000";
cfg_interrupt_n <= '1';
cfg_interrupt_assert_n_1 <= '1';
else
if (trn_clk'event and trn_clk = '1') then
case ( pcieirq_state ) is
 
--********** idle STATE **********
when "00000000" => --state 0
if (pcie_irq = '1') then
pcieirq_state <= "00000001";
cfg_interrupt_n <= '0'; --active
else
cfg_interrupt_n <= '1'; --inactive
end if;
cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert
 
--********** assert STATE **********
when "00000001" => --state 1
if (cfg_interrupt_rdy_n ='0') then --ep accepted it
cfg_interrupt_n <= '1'; --deassert the request
pcieirq_state <= "00000010";
else
cfg_interrupt_n <= '0'; --request INTA assertion
end if;
 
--********** pcie_irq kept asserted STATE **********
when "00000010" => --state 2
if (pcie_irq = '0') then --pcie_irq gets deasserted
pcieirq_state <= "00000011";
end if;
cfg_interrupt_n <= '1'; --inactive
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
 
--********** DEassert STATE **********
when "00000011" => --state 3
if (cfg_interrupt_rdy_n ='0') then --ep accepted it
cfg_interrupt_n <= '1'; --deassert the request
pcieirq_state <= "00000000";
else
cfg_interrupt_n <= '0'; --request INTA DEassertion
end if;
 
when others => --error
pcieirq_state <= "00000000"; --go to state 0
end case;
end if;
end if;
end process;
--this (little delay) is to fix a hold time violation created inside the pcie-ep ip:
cfg_interrupt_assert_n <= cfg_interrupt_assert_n_1 or (not pciewb_localreset_n);
 
 
 
 
 
 
-- -------- END OF FILE -------------------------------------------------------------------------------------
end Behavioral;
 
 

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