Subversion Repositories pcie_mini_axi4s_wb

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/trunk/example_proejct/PCIe_mini_axi4s_wb_vivado_20191026.zip

trunk/example_proejct/PCIe_mini_axi4s_wb_vivado_20191026.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/example_proejct/when using this example, replace the sources within with latest version.txt =================================================================== Index: trunk/rtl/old/pcie_mini_axi4s_wb_v1.0.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/rtl/old/pcie_mini_axi4s_wb_v1.0.zip =================================================================== --- trunk/rtl/old/pcie_mini_axi4s_wb_v1.0.zip (nonexistent) +++ trunk/rtl/old/pcie_mini_axi4s_wb_v1.0.zip (revision 2)

trunk/rtl/old/pcie_mini_axi4s_wb_v1.0.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/rtl/example_device_top.vhd =================================================================== --- trunk/rtl/example_device_top.vhd (nonexistent) +++ trunk/rtl/example_device_top.vhd (revision 2) @@ -0,0 +1,203 @@ +---------------------------------------------------------------------------------- +-- Project name: pcie_mini_axi4s_wb, device top level file, EXAMPLE DESIGN +-- This is an example device top level file, where the pcie_mini_axi4s_wb is instantiated. +-- Functions: PCIe endpoint, a register block, 2 LED outputs. +-- +-- YOU don't need this file in your own custom design !!! This file is only demonstration. +-- +-- Engineer: Istvan Nagy, buenoshun@gmail.com +-- +-- Create Date: 10/10/2019 +-- Modify date: 10/10/2019 +-- Design Name: example_device_top encapsulating pcie_mini_axi4s_wb +-- Version: 1.0 +-- Tool versions: Vivado 2019.1 +-- +-- Target Devices: Xilinx usc+ FPGAs. +-------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--entity header ---------------------------------------------------------------- +entity example_device_top is +Port ( + pci_exp_txp : out std_logic; + pci_exp_txn : out std_logic; + pci_exp_rxp : in std_logic; + pci_exp_rxn : in std_logic; + sys_clk_n : in std_logic; + sys_clk_p : in std_logic; + sys_reset_n : in std_logic; + debug_pins : out std_logic_vector(31 downto 0); + scan_pins : in std_logic_vector(31 downto 0); + led_out_1 : out std_logic; + led_out_2 : out std_logic +); +end example_device_top; +--architecture start ------------------------------------------------------------ +architecture Behavioral of example_device_top is + +-- INTERNAL SIGNALS ------------------------------------------------------------- + SIGNAL dummy0: std_logic; + SIGNAL dummy1: std_logic_VECTOR(6 DOWNTO 0); + SIGNAL pcie_bar0_wb_data_o : std_logic_vector(31 downto 0); + SIGNAL pcie_bar0_wb_data_i : std_logic_vector(31 downto 0); + SIGNAL pcie_bar0_wb_addr_o : std_logic_vector(27 downto 0); + SIGNAL pcie_bar0_wb_cyc_o : std_logic; + SIGNAL pcie_bar0_wb_stb_o : std_logic; + SIGNAL pcie_bar0_wb_wr_o : std_logic; + SIGNAL pcie_bar0_wb_ack_i : std_logic; + SIGNAL pcie_bar0_wb_clk_o : std_logic; --62.5MHz + SIGNAL pcie_bar0_wb_sel_o : std_logic_vector(3 downto 0); + SIGNAL pcie_irq : std_logic; + SIGNAL pcie_msi_enabled : std_logic; + SIGNAL pcie_resetout : std_logic; + SIGNAL register_one : std_logic_vector(31 downto 0); + SIGNAL register_two : std_logic_vector(31 downto 0); + SIGNAL register_three : std_logic_vector(31 downto 0); + SIGNAL register_four : std_logic_vector(31 downto 0); + SIGNAL regxx_scratchpad : std_logic_vector(31 downto 0); + SIGNAL scan_pins_latched1 : std_logic_vector(31 downto 0); + SIGNAL scan_pins_latched2 : std_logic_vector(31 downto 0); + SIGNAL wb_config_state : std_logic_vector(7 downto 0); + SIGNAL ACK_copy : std_logic; + + + +--------- COMPONENT DECLARATIONS (introducing the IPs) -------------------------- +COMPONENT pcie_mini_axi4s_wb + PORT ( --FPGA PINS(EXTERNAL): + pci_exp_txp : out std_logic; + pci_exp_txn : out std_logic; + pci_exp_rxp : in std_logic; + pci_exp_rxn : in std_logic; + sys_clk_n : in std_logic; + sys_clk_p : in std_logic; + sys_reset_n : in std_logic; + --ON CHIP PORTS: + --DATA BUS for BAR0 (wishbone): + pcie_bar0_wb_data_o : out std_logic_vector(31 downto 0); + pcie_bar0_wb_data_i : in std_logic_vector(31 downto 0); + pcie_bar0_wb_addr_o : out std_logic_vector(27 downto 0); + pcie_bar0_wb_cyc_o : out std_logic; + pcie_bar0_wb_stb_o : out std_logic; + pcie_bar0_wb_wr_o : out std_logic; + pcie_bar0_wb_ack_i : in std_logic; + pcie_bar0_wb_clk_o : out std_logic; --62.5MHz + pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0); + --OTHER: + pcie_irq : in std_logic; + pcie_msi_enabled : out std_logic; -- added to monitor if MSI interrupt is enabled + pcie_resetout : out std_logic --active high + ); +END COMPONENT; + + +--architecture body start ------------------------------------------------------- +begin +--------- COMPONENT INSTALLATIONS (connecting the IPs to local signals) --------- +Inst_pcieaxiwbtop: pcie_mini_axi4s_wb + PORT MAP ( + pci_exp_txp => pci_exp_txp, + pci_exp_txn => pci_exp_txn, + pci_exp_rxp => pci_exp_rxp, + pci_exp_rxn => pci_exp_rxn, + sys_clk_n => sys_clk_n, + sys_clk_p => sys_clk_p, + sys_reset_n => sys_reset_n, + pcie_bar0_wb_data_o => pcie_bar0_wb_data_o, + pcie_bar0_wb_data_i => pcie_bar0_wb_data_i, + pcie_bar0_wb_addr_o => pcie_bar0_wb_addr_o, + pcie_bar0_wb_cyc_o => pcie_bar0_wb_cyc_o, + pcie_bar0_wb_stb_o => pcie_bar0_wb_stb_o, + pcie_bar0_wb_wr_o => pcie_bar0_wb_wr_o, + pcie_bar0_wb_ack_i => pcie_bar0_wb_ack_i, + pcie_bar0_wb_clk_o => pcie_bar0_wb_clk_o, + pcie_bar0_wb_sel_o => pcie_bar0_wb_sel_o, + pcie_irq => pcie_irq, + pcie_msi_enabled => pcie_msi_enabled, + pcie_resetout => pcie_resetout + ); + + +-- local Logic ------------------------------------------------------------------ +debug_pins <= register_one; --check register content with TopJtag_Probe. +led_out_1 <= register_one(1); +led_out_2 <= register_one(2); + +-- WISHB/SMB REGISTER SET +wishbone: process (pcie_resetout , pcie_bar0_wb_clk_o) is + begin + if (pcie_resetout ='0') then + --DAT_R(7 downto 0) <= (others => '0'); + register_one <= (OTHERS => '0'); + register_two <= (OTHERS => '0'); + register_three <= (OTHERS => '0'); + register_four <= (OTHERS => '0'); + wb_config_state <= (OTHERS => '0'); + regxx_scratchpad <= (OTHERS => '0'); + scan_pins_latched1 <= (OTHERS => '0'); + scan_pins_latched2 <= (OTHERS => '0'); + pcie_bar0_wb_data_i <= (OTHERS => '0'); + else + if (pcie_bar0_wb_clk_o'event and pcie_bar0_wb_clk_o = '1') then + scan_pins_latched1 <= scan_pins; + scan_pins_latched2 <= scan_pins_latched1; + + case ( wb_config_state ) is + + --********** IDLE STATE ********** + when "00000000" => --state 0 + --WAIT FOR WISHBONE TRANSACTION: + pcie_bar0_wb_ack_i <= '0'; + ACK_copy <= '0'; + --writes: + if (pcie_bar0_wb_cyc_o = '1' and pcie_bar0_wb_wr_o = '1' and ACK_copy='0') then + wb_config_state <= "00001001"; + --reads: + elsif (pcie_bar0_wb_cyc_o = '1' and pcie_bar0_wb_wr_o = '0' and ACK_copy='0') then --read + wb_config_state <= "00001010"; + end if; + + --********** write STATE ********** + when "00001001" => --state 1 + wb_config_state <= "00000000"; --no wait states, go back to idle + pcie_bar0_wb_ack_i <= '1'; + ACK_copy <= '1'; + case (pcie_bar0_wb_addr_o(7 downto 0)) is + when X"00" => register_one <= pcie_bar0_wb_data_o(31 downto 0); + when X"01" => register_two <= pcie_bar0_wb_data_o(31 downto 0); + when X"02" => register_three <= pcie_bar0_wb_data_o(31 downto 0); + when X"03" => register_four <= pcie_bar0_wb_data_o(31 downto 0); + when others => regxx_scratchpad <= pcie_bar0_wb_data_o(31 downto 0); + end case; + + + --********** read STATE ********** + when "00001010" => --state 2: registers read-out + wb_config_state <= "00000000"; --no wait states, go back to idle + pcie_bar0_wb_ack_i <= '1'; + ACK_copy <= '1'; + case (pcie_bar0_wb_addr_o(7 downto 0)) is + when X"00" => pcie_bar0_wb_data_i(31 downto 0) <= register_one ; + when X"01" => pcie_bar0_wb_data_i(31 downto 0) <= register_two ; + when X"02" => pcie_bar0_wb_data_i(31 downto 0) <= register_three ; + when X"03" => pcie_bar0_wb_data_i(31 downto 0) <= register_four ; + when X"04" => pcie_bar0_wb_data_i(31 downto 0) <= scan_pins_latched2 ; + when others => pcie_bar0_wb_data_i(31 downto 0) <= regxx_scratchpad ; + end case; + + when others => --error state + wb_config_state <= "00000000"; --go to state 0 + end case; + + end if; + end if; +end process wishbone; + + + +--end file ---------------------------------------------------------------------- +end Behavioral; \ No newline at end of file Index: trunk/rtl/pcie_axi4s2trn_wrapper.vhd =================================================================== --- trunk/rtl/pcie_axi4s2trn_wrapper.vhd (nonexistent) +++ trunk/rtl/pcie_axi4s2trn_wrapper.vhd (revision 2) @@ -0,0 +1,1374 @@ +------------------------------------------------------------------------------------ +-- AXI4STREAM TO TRN WRAPPER FOR PCIE +-- WRITTEN BY: ISTVAN NAGY, 2019 10 03 +-- +--THIS IS A WRAPPER FILE FOR CONENCTING THE AXI4STREAM BASED NEW XILINX PCIE-EP-IP +--TO THE OLD PCIE_MINI PROJECT THAT EXPECTS THE PCIE EP IP TO HAVE A TRN INTERFACE. +--LOGIC: AN AXI4STREAM INTERFACE, A TRN INTERFACE AND AN AXI4 DESCRIPTOR HANDLER. +-- +--Example design is 1-lane 5Gbps, status and eye capture ports enabled, +--device used was Ultrascale+ xcku3p-ffva676-3-e +-- Usage: +-- Thius file is a wrapper for converting the axi4s interface of the new Ultrascal+ +-- FPGA PCIE endpoint IP, to TRN, that works with the pcie_mini logic. The pcie_mini +-- is also modified to implement the new header encoding, while this file is just +-- for the bit timing signals conversion. +--How this works: from UG672-appendix-J the TRN-AXI4S bit signal conversion/migration. +--AXI4S does not provide original TLP header, only AXI4s header, handled in other file. +-- naming: m_axis_cq = TRN_RX, while s_axis_cc = TRN_RX, on completion EP interface. +------------------------------------------------------------------------------------ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--entity header ---------------------------------------------------------------- +entity pcie is + generic ( + TL_TX_RAM_RADDR_LATENCY : integer := 0; + TL_TX_RAM_RDATA_LATENCY : integer := 2; + TL_RX_RAM_RADDR_LATENCY : integer := 0; + TL_RX_RAM_RDATA_LATENCY : integer := 2; + TL_RX_RAM_WRITE_LATENCY : integer := 0; + VC0_TX_LASTPACKET : integer := 14; + VC0_RX_RAM_LIMIT : bit_vector := x"7FF"; + VC0_TOTAL_CREDITS_PH : integer := 32; + VC0_TOTAL_CREDITS_PD : integer := 211; + VC0_TOTAL_CREDITS_NPH : integer := 8; + VC0_TOTAL_CREDITS_CH : integer := 40; + VC0_TOTAL_CREDITS_CD : integer := 211; + VC0_CPL_INFINITE : boolean := TRUE; + BAR0 : bit_vector := x"F0000000"; + BAR1 : bit_vector := x"00000000"; + BAR2 : bit_vector := x"00000000"; + BAR3 : bit_vector := x"00000000"; + BAR4 : bit_vector := x"00000000"; + BAR5 : bit_vector := x"00000000"; + EXPANSION_ROM : bit_vector := "0000000000000000000000"; + DISABLE_BAR_FILTERING : boolean := FALSE; + DISABLE_ID_CHECK : boolean := FALSE; + TL_TFC_DISABLE : boolean := FALSE; + TL_TX_CHECKS_DISABLE : boolean := FALSE; + USR_CFG : boolean := FALSE; + USR_EXT_CFG : boolean := FALSE; + DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2; + CLASS_CODE : bit_vector := x"068000"; + CARDBUS_CIS_POINTER : bit_vector := x"00000000"; + PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1"; + PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"1"; + PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE; + PCIE_CAP_INT_MSG_NUM : bit_vector := "00000"; + DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0; + DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE; + DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7; + DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7; + SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE; + SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE; + SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE; + DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE; + LINK_CAP_ASPM_SUPPORT : integer := 1; + LINK_CAP_L0S_EXIT_LATENCY : integer := 7; + LINK_CAP_L1_EXIT_LATENCY : integer := 7; + LL_ACK_TIMEOUT : bit_vector := x"0000"; + LL_ACK_TIMEOUT_EN : boolean := FALSE; + LL_REPLAY_TIMEOUT : bit_vector := x"0000"; + LL_REPLAY_TIMEOUT_EN : boolean := FALSE; + MSI_CAP_MULTIMSGCAP : integer := 0; + MSI_CAP_MULTIMSG_EXTENSION : integer := 0; + LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE; + PLM_AUTO_CONFIG : boolean := FALSE; + FAST_TRAIN : boolean := FALSE; + ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE; + DISABLE_SCRAMBLING : boolean := FALSE; + PM_CAP_VERSION : integer := 3; + PM_CAP_PME_CLOCK : boolean := FALSE; + PM_CAP_DSI : boolean := FALSE; + PM_CAP_AUXCURRENT : integer := 0; + PM_CAP_D1SUPPORT : boolean := TRUE; + PM_CAP_D2SUPPORT : boolean := TRUE; + PM_CAP_PMESUPPORT : bit_vector := x"0F"; + PM_DATA0 : bit_vector := x"04"; + PM_DATA_SCALE0 : bit_vector := x"0"; + PM_DATA1 : bit_vector := x"00"; + PM_DATA_SCALE1 : bit_vector := x"0"; + PM_DATA2 : bit_vector := x"00"; + PM_DATA_SCALE2 : bit_vector := x"0"; + PM_DATA3 : bit_vector := x"00"; + PM_DATA_SCALE3 : bit_vector := x"0"; + PM_DATA4 : bit_vector := x"04"; + PM_DATA_SCALE4 : bit_vector := x"0"; + PM_DATA5 : bit_vector := x"00"; + PM_DATA_SCALE5 : bit_vector := x"0"; + PM_DATA6 : bit_vector := x"00"; + PM_DATA_SCALE6 : bit_vector := x"0"; + PM_DATA7 : bit_vector := x"00"; + PM_DATA_SCALE7 : bit_vector := x"0"; + PCIE_GENERIC : bit_vector := "000011101111"; + GTP_SEL : integer := 0; + CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE"; + CFG_DEV_ID : std_logic_vector(15 downto 0) := x"ABCD"; + CFG_REV_ID : std_logic_vector(7 downto 0) := x"00"; + CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE"; + CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234"; + REF_CLK_FREQ : integer := 0 + ); + port ( + -- PCI Express Fabric Interface + pci_exp_txp : out std_logic; + pci_exp_txn : out std_logic; + pci_exp_rxp : in std_logic; + pci_exp_rxn : in std_logic; + + -- Transaction (TRN) Interface + trn_lnk_up_n : out std_logic; + + -- Tx + trn_td : in std_logic_vector(63 downto 0); + trn_tsof_n : in std_logic; + trn_teof_n : in std_logic; + trn_tsrc_rdy_n : in std_logic; + trn_tdst_rdy_n : out std_logic; + trn_terr_drop_n : out std_logic; + trn_tsrc_dsc_n : in std_logic; + trn_terrfwd_n : in std_logic; + trn_tbuf_av : out std_logic_vector(5 downto 0); + trn_tstr_n : in std_logic; + trn_tcfg_req_n : out std_logic; + trn_tcfg_gnt_n : in std_logic; + --trn_trem_n : in std_logic; --this might be needed for correct number of bytes transfer ????????? + + -- Rx + trn_rd : out std_logic_vector(63 downto 0); + trn_rsof_n : out std_logic; + trn_reof_n : out std_logic; + trn_rsrc_rdy_n : out std_logic; + trn_rsrc_dsc_n : out std_logic; + trn_rdst_rdy_n : in std_logic; + trn_rerrfwd_n : out std_logic; + trn_rnp_ok_n : in std_logic; + trn_rbar_hit_n : out std_logic_vector(6 downto 0); + trn_fc_sel : in std_logic_vector(2 downto 0); + trn_fc_nph : out std_logic_vector(7 downto 0); + trn_fc_npd : out std_logic_vector(11 downto 0); + trn_fc_ph : out std_logic_vector(7 downto 0); + trn_fc_pd : out std_logic_vector(11 downto 0); + trn_fc_cplh : out std_logic_vector(7 downto 0); + trn_fc_cpld : out std_logic_vector(11 downto 0); + + -- Host (CFG) Interface + cfg_do : out std_logic_vector(31 downto 0); + cfg_rd_wr_done_n : out std_logic; + cfg_dwaddr : in std_logic_vector(9 downto 0); + cfg_rd_en_n : in std_logic; + cfg_err_ur_n : in std_logic; + cfg_err_cor_n : in std_logic; + cfg_err_ecrc_n : in std_logic; + cfg_err_cpl_timeout_n : in std_logic; + cfg_err_cpl_abort_n : in std_logic; + cfg_err_posted_n : in std_logic; + cfg_err_locked_n : in std_logic; + cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0); + cfg_err_cpl_rdy_n : out std_logic; + cfg_interrupt_n : in std_logic; + cfg_interrupt_rdy_n : out std_logic; + cfg_interrupt_assert_n : in std_logic; + cfg_interrupt_do : out std_logic_vector(7 downto 0); + cfg_interrupt_di : in std_logic_vector(7 downto 0); + cfg_interrupt_mmenable : out std_logic_vector(2 downto 0); + cfg_interrupt_msienable : out std_logic; + cfg_turnoff_ok_n : in std_logic; + cfg_to_turnoff_n : out std_logic; + cfg_pm_wake_n : in std_logic; + cfg_pcie_link_state_n : out std_logic_vector(2 downto 0); --new encoding: 1xx=down, x00=no_receivers, x01=linktraining, x10=DLLinit, 011=linkUP. Spartan6 encode was different. + cfg_trn_pending_n : in std_logic; + cfg_dsn : in std_logic_vector(63 downto 0); + cfg_bus_number : out std_logic_vector(7 downto 0); + cfg_device_number : out std_logic_vector(4 downto 0); + cfg_function_number : out std_logic_vector(2 downto 0); + cfg_status : out std_logic_vector(15 downto 0); + cfg_command : out std_logic_vector(15 downto 0); + cfg_dstatus : out std_logic_vector(15 downto 0); + cfg_dcommand : out std_logic_vector(15 downto 0); + cfg_lstatus : out std_logic_vector(15 downto 0); + cfg_lcommand : out std_logic_vector(15 downto 0); + + -- System Interface + sys_clk : in std_logic; --ref clock oscillator 100mhz + sys_clk2 : in std_logic; + sys_reset_n : in std_logic; + trn_clk : out std_logic; --parallel bus clock 52/125mhz + trn_reset_n : out std_logic; + received_hot_reset : out std_logic + ); +end pcie; + +architecture rtl of pcie is + + --attribute CORE_GENERATION_INFO : STRING; + --attribute CORE_GENERATION_INFO of rtl : architecture is + -- "pcie,s6_pcie_v1_2,{TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=14,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=211,VC0_TOTAL_CREDITS_NPH=8,VC0_TOTAL_CREDITS_CH=40,VC0_TOTAL_CREDITS_CD=211,VC0_CPL_INFINITE=TRUE,BAR0=F0000000,BAR1=00000000,BAR2=00000000,BAR3=00000000,BAR4=00000000,BAR5=00000000,EXPANSION_ROM=000000,USR_CFG=FALSE,USR_EXT_CFG=FALSE,DEV_CAP_MAX_PAYLOAD_SUPPORTED=2,CLASS_CODE=068000,CARDBUS_CIS_POINTER=00000000,PCIE_CAP_CAPABILITY_VERSION=1,PCIE_CAP_DEVICE_PORT_TYPE=1,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,DEV_CAP_ENDPOINT_L0S_LATENCY=7,DEV_CAP_ENDPOINT_L1_LATENCY=7,LINK_CAP_ASPM_SUPPORT=1,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,LINK_STATUS_SLOT_CLOCK_CONFIG=FALSE,ENABLE_RX_TD_ECRC_TRIM=FALSE,DISABLE_SCRAMBLING=FALSE,PM_CAP_DSI=FALSE,PM_CAP_D1SUPPORT=TRUE,PM_CAP_D2SUPPORT=TRUE,PM_CAP_PMESUPPORT=0F,PM_DATA0=04,PM_DATA_SCALE0=0,PM_DATA1=00,PM_DATA_SCALE1=0,PM_DATA2=00,PM_DATA_SCALE2=0,PM_DATA3=00,PM_DATA_SCALE3=0,PM_DATA4=04,PM_DATA_SCALE4=0,PM_DATA5=00,PM_DATA_SCALE5=0,PM_DATA6=00,PM_DATA_SCALE6=0,PM_DATA7=00,PM_DATA_SCALE7=0,PCIE_GENERIC=000010101111,GTP_SEL=0,CFG_VEN_ID=10EE,CFG_DEV_ID=ABCD,CFG_REV_ID=00,CFG_SUBSYS_VEN_ID=10EE,CFG_SUBSYS_ID=1234,REF_CLK_FREQ=0}"; + + +-- INTERNAL SIGNALS ------------------------------------------------------------- +SIGNAL pl_gen2_upstream_prefer_deemph : std_logic; +SIGNAL pl_redo_eq : std_logic; +SIGNAL pl_redo_eq_speed : std_logic; +SIGNAL s_axis_cc_tdata : std_logic_vector(63 downto 0); +SIGNAL s_axis_rq_tdata : std_logic_vector(63 downto 0); +SIGNAL s_axis_cc_tuser : std_logic_vector(32 downto 0); +SIGNAL s_axis_rq_tlast : std_logic; +SIGNAL s_axis_cc_tlast : std_logic; +SIGNAL pcie_cq_np_req : std_logic_vector(1 downto 0); +SIGNAL s_axis_rq_tuser : std_logic_vector(61 downto 0); +SIGNAL s_axis_cc_tkeep : std_logic_vector(1 downto 0); +SIGNAL s_axis_rq_tkeep : std_logic_vector(1 downto 0); +SIGNAL s_axis_cc_tvalid : std_logic; +SIGNAL s_axis_rq_tvalid : std_logic; +SIGNAL m_axis_cq_tready : std_logic; +SIGNAL m_axis_rc_tready : std_logic; +SIGNAL cfg_mgmt_addr : std_logic_vector(9 downto 0); +SIGNAL cfg_mgmt_function_number : std_logic_vector(7 downto 0); +SIGNAL cfg_mgmt_write : std_logic; +SIGNAL cfg_mgmt_write_data : std_logic_vector(31 downto 0); +SIGNAL cfg_mgmt_byte_enable : std_logic_vector(3 downto 0); +SIGNAL cfg_mgmt_read : std_logic; +SIGNAL cfg_mgmt_debug_access : std_logic; +SIGNAL cfg_msg_transmit : std_logic; +SIGNAL cfg_msg_transmit_type : std_logic_vector(2 downto 0); +SIGNAL cfg_msg_transmit_data : std_logic_vector(31 downto 0); +SIGNAL cfg_fc_sel : std_logic_vector(2 downto 0); +SIGNAL cfg_hot_reset_in : std_logic; +SIGNAL cfg_config_space_enable : std_logic; +--SIGNAL cfg_dsn : std_logic_vector(63 downto 0); +SIGNAL cfg_dev_id_pf0 : std_logic_vector(15 downto 0); +SIGNAL cfg_dev_id_pf1 : std_logic_vector(15 downto 0); +SIGNAL cfg_dev_id_pf2 : std_logic_vector(15 downto 0); +SIGNAL cfg_dev_id_pf3 : std_logic_vector(15 downto 0); +SIGNAL cfg_vend_id : std_logic_vector(15 downto 0); +SIGNAL cfg_rev_id_pf0 : std_logic_vector(7 downto 0); +SIGNAL cfg_rev_id_pf1 : std_logic_vector(7 downto 0); +SIGNAL cfg_rev_id_pf2 : std_logic_vector(7 downto 0); +SIGNAL cfg_rev_id_pf3 : std_logic_vector(7 downto 0); +SIGNAL cfg_subsys_id_pf0 : std_logic_vector(15 downto 0); +SIGNAL cfg_subsys_id_pf1 : std_logic_vector(15 downto 0); +SIGNAL cfg_subsys_id_pf2 : std_logic_vector(15 downto 0); +SIGNAL cfg_subsys_id_pf3 : std_logic_vector(15 downto 0); +SIGNAL cfg_subsys_vend_id : std_logic_vector(15 downto 0); +SIGNAL cfg_ds_port_number : std_logic_vector(7 downto 0); +SIGNAL cfg_ds_bus_number : std_logic_vector(7 downto 0); +SIGNAL cfg_ds_device_number : std_logic_vector(4 downto 0); +SIGNAL cfg_ds_function_number : std_logic_vector(2 downto 0); +SIGNAL cfg_power_state_change_ack : std_logic; +SIGNAL cfg_err_cor_in : std_logic; +SIGNAL cfg_err_uncor_in : std_logic; +SIGNAL cfg_flr_done : std_logic_vector(3 downto 0); +SIGNAL cfg_req_pm_transition_l23_ready : std_logic; +SIGNAL cfg_link_training_enable : std_logic; +SIGNAL cfg_interrupt_int : std_logic_vector(3 downto 0); +SIGNAL cfg_interrupt_pending : std_logic_vector(3 downto 0); +SIGNAL cfg_interrupt_msi_int : std_logic_vector(31 downto 0); +SIGNAL cfg_interrupt_msi_pending_status : std_logic_vector(31 downto 0); +SIGNAL cfg_interrupt_msi_pending_status_function_num : std_logic_vector(1 downto 0); +SIGNAL cfg_interrupt_msi_pending_status_data_enable : std_logic; +SIGNAL cfg_interrupt_msi_select : std_logic_vector(1 downto 0); +SIGNAL cfg_interrupt_msix_address : std_logic_vector(63 downto 0); +SIGNAL cfg_interrupt_msix_data : std_logic_vector(31 downto 0); +SIGNAL cfg_interrupt_msix_int : std_logic; +SIGNAL cfg_interrupt_msix_vec_pending : std_logic_vector(1 downto 0); +SIGNAL cfg_interrupt_msi_attr : std_logic_vector(2 downto 0); +SIGNAL cfg_interrupt_msi_tph_present : std_logic; +SIGNAL cfg_interrupt_msi_tph_type : std_logic_vector(1 downto 0); +SIGNAL cfg_interrupt_msi_tph_st_tag : std_logic_vector(7 downto 0); +SIGNAL cfg_interrupt_msi_function_number : std_logic_vector(7 downto 0); +SIGNAL cfg_ext_read_data : std_logic_vector(31 downto 0); +SIGNAL cfg_ext_read_data_valid : std_logic; +SIGNAL cfg_vf_flr_func_num : std_logic_vector(7 downto 0); +SIGNAL cfg_vf_flr_done : std_logic_VECTOR(0 DOWNTO 0); +SIGNAL cfg_pm_aspm_l1_entry_reject : std_logic; +SIGNAL cfg_pm_aspm_tx_l0s_entry_disable : std_logic; +SIGNAL conf_req_type : std_logic_vector(1 downto 0); +SIGNAL conf_req_reg_num : std_logic_vector(3 downto 0); +SIGNAL conf_req_data : std_logic_vector(31 downto 0); +SIGNAL conf_req_valid : std_logic; +SIGNAL cap_gnt : std_logic; +SIGNAL cap_rel : std_logic; +SIGNAL sys_clk_gt : std_logic; +SIGNAL ext_ch_gt_drpaddr : std_logic_vector(79 downto 0); +SIGNAL ext_ch_gt_drpen : std_logic_vector(7 downto 0); +SIGNAL ext_ch_gt_drpwe : std_logic_vector(7 downto 0); +SIGNAL ext_ch_gt_drpdi : std_logic_vector(127 downto 0); +SIGNAL drp_clk : std_logic; +SIGNAL drp_en : std_logic; +SIGNAL drp_we : std_logic; +SIGNAL drp_addr : std_logic_vector(9 downto 0); +SIGNAL drp_di : std_logic_vector(15 downto 0); +SIGNAL gt_pcieuserratedone : std_logic_vector(7 downto 0); +SIGNAL gt_loopback : std_logic_vector(23 downto 0); +SIGNAL gt_txprbsforceerr : std_logic_vector(7 downto 0); +SIGNAL gt_txinhibit : std_logic_vector(7 downto 0); +SIGNAL gt_txprbssel : std_logic_vector(31 downto 0); +SIGNAL gt_rxprbssel : std_logic_vector(31 downto 0); +SIGNAL gt_rxprbscntreset : std_logic_vector(7 downto 0); +SIGNAL gt_dmonfiforeset : std_logic_vector(7 downto 0); +SIGNAL gt_dmonitorclk : std_logic_vector(7 downto 0); +SIGNAL gt_txpmareset : std_logic_vector(7 downto 0); +SIGNAL gt_rxpmareset : std_logic_vector(7 downto 0); +SIGNAL gt_txpcsreset : std_logic_vector(7 downto 0); +SIGNAL gt_rxpcsreset : std_logic_vector(7 downto 0); +SIGNAL gt_rxbufreset : std_logic_vector(7 downto 0); +SIGNAL gt_rxcdrreset : std_logic_vector(7 downto 0); +SIGNAL gt_rxdfelpmreset : std_logic_vector(7 downto 0); +SIGNAL free_run_clock : std_logic; +SIGNAL common_commands_in : std_logic_vector(25 downto 0); +SIGNAL pipe_rx_0_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_1_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_2_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_3_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_4_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_5_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_6_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_7_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_8_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_9_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_10_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_11_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_12_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_13_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_14_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_rx_15_sigs : std_logic_vector(83 downto 0); +SIGNAL ext_qpll0lock_out : std_logic_vector(1 downto 0); +SIGNAL ext_qpll0outclk_out : std_logic_vector(1 downto 0); +SIGNAL ext_qpll0outrefclk_out : std_logic_vector(1 downto 0); +SIGNAL ext_qpll1lock_out : std_logic_vector(1 downto 0); +SIGNAL ext_qpll1outclk_out : std_logic_vector(1 downto 0); +SIGNAL ext_qpll1outrefclk_out : std_logic_vector(1 downto 0); +SIGNAL qpll0lock_out : std_logic_vector(1 downto 0); +SIGNAL qpll0outclk_out : std_logic_vector(1 downto 0); +SIGNAL qpll0outrefclk_out : std_logic_vector(1 downto 0); +SIGNAL qpll1lock_out : std_logic_vector(1 downto 0); +SIGNAL qpll1outclk_out : std_logic_vector(1 downto 0); +SIGNAL qpll1outrefclk_out : std_logic_vector(1 downto 0); +SIGNAL pcierateqpllpd_out : std_logic_vector(15 downto 0); +SIGNAL pcierateqpllreset_out : std_logic_vector(15 downto 0); +SIGNAL bufgtce_out : std_logic_vector(7 downto 0); +SIGNAL bufgtcemask_out : std_logic_vector(23 downto 0); +SIGNAL bufgtdiv_out : std_logic_vector(71 downto 0); +SIGNAL bufgtreset_out : std_logic_vector(7 downto 0); +SIGNAL bufgtrstmask_out : std_logic_vector(23 downto 0); +SIGNAL cplllock_out : std_logic_vector(7 downto 0); +SIGNAL dmonitorout_out : std_logic_vector(127 downto 0); +SIGNAL gtpowergood_out : std_logic_vector(7 downto 0); +SIGNAL pcierategen3_out : std_logic_vector(7 downto 0); +SIGNAL pcierateidle_out : std_logic_vector(7 downto 0); +SIGNAL pciesynctxsyncdone_out : std_logic_vector(7 downto 0); +SIGNAL pcieusergen3rdy_out : std_logic_vector(7 downto 0); +SIGNAL pcieuserphystatusrst_out : std_logic_vector(7 downto 0); +SIGNAL pcieuserratestart_out : std_logic_vector(7 downto 0); +SIGNAL phystatus_out : std_logic_vector(7 downto 0); +SIGNAL rxbufstatus_out : std_logic_vector(23 downto 0); +SIGNAL rxbyteisaligned_out : std_logic_vector(7 downto 0); +SIGNAL rxbyterealign_out : std_logic_vector(7 downto 0); +SIGNAL rxcdrlock_out : std_logic_vector(7 downto 0); +SIGNAL rxclkcorcnt_out : std_logic_vector(15 downto 0); +SIGNAL rxcommadet_out : std_logic_vector(7 downto 0); +SIGNAL rxctrl0_out : std_logic_vector(127 downto 0); +SIGNAL rxctrl1_out : std_logic_vector(127 downto 0); +SIGNAL rxctrl2_out : std_logic_vector(63 downto 0); +SIGNAL rxctrl3_out : std_logic_vector(63 downto 0); +SIGNAL rxdata_out : std_logic_vector(1023 downto 0); +SIGNAL rxdlysresetdone_out : std_logic_vector(7 downto 0); +SIGNAL rxelecidle_out : std_logic_vector(7 downto 0); +SIGNAL rxoutclk_out : std_logic_vector(7 downto 0); +SIGNAL rxoutclkfabric_out : std_logic_vector(7 downto 0); +SIGNAL rxoutclkpcs_out : std_logic_vector(7 downto 0); +SIGNAL rxphaligndone_out : std_logic_vector(7 downto 0); +SIGNAL rxpmaresetdone_out : std_logic_vector(7 downto 0); +SIGNAL rxprbserr_out : std_logic_vector(7 downto 0); +SIGNAL rxprbslocked_out : std_logic_vector(7 downto 0); +SIGNAL rxratedone_out : std_logic_vector(7 downto 0); +SIGNAL rxrecclkout_out : std_logic_vector(7 downto 0); +SIGNAL rxresetdone_out : std_logic_vector(7 downto 0); +SIGNAL rxstatus_out : std_logic_vector(23 downto 0); +SIGNAL rxsyncdone_out : std_logic_vector(7 downto 0); +SIGNAL rxvalid_out : std_logic_vector(7 downto 0); +SIGNAL txdlysresetdone_out : std_logic_vector(7 downto 0); +SIGNAL txoutclk_out : std_logic_vector(7 downto 0); +SIGNAL txoutclkfabric_out : std_logic_vector(7 downto 0); +SIGNAL txoutclkpcs_out : std_logic_vector(7 downto 0); +SIGNAL txphaligndone_out : std_logic_vector(7 downto 0); +SIGNAL txphinitdone_out : std_logic_vector(7 downto 0); +SIGNAL txpmaresetdone_out : std_logic_vector(7 downto 0); +SIGNAL txprgdivresetdone_out : std_logic_vector(7 downto 0); +SIGNAL txresetdone_out : std_logic_vector(7 downto 0); +SIGNAL txsyncdone_out : std_logic_vector(7 downto 0); +SIGNAL txsyncout_out : std_logic_vector(7 downto 0); +SIGNAL drprdy_out : std_logic_vector(7 downto 0); +SIGNAL drpdo_out : std_logic_vector(127 downto 0); +SIGNAL ext_phy_clk_pclk2_gt : std_logic; +SIGNAL ext_phy_clk_int_clock : std_logic; +SIGNAL ext_phy_clk_pclk : std_logic; +SIGNAL ext_phy_clk_phy_pclk2 : std_logic; +SIGNAL ext_phy_clk_phy_coreclk : std_logic; +SIGNAL ext_phy_clk_phy_userclk : std_logic; +SIGNAL ext_phy_clk_phy_mcapclk : std_logic; +SIGNAL prst_clk : std_logic; +SIGNAL pl_eq_in_progress : std_logic; +SIGNAL pl_eq_phase : std_logic_vector(1 downto 0); +SIGNAL pl_eq_mismatch : std_logic; +SIGNAL pl_redo_eq_pending : std_logic; +SIGNAL m_axis_cq_tdata : std_logic_vector(63 downto 0); +SIGNAL m_axis_rc_tdata : std_logic_vector(63 downto 0); +SIGNAL m_axis_cq_tuser : std_logic_vector(87 downto 0); +SIGNAL m_axis_cq_tlast : std_logic; +SIGNAL m_axis_rc_tlast : std_logic; +SIGNAL pcie_cq_np_req_count : std_logic_vector(5 downto 0); +SIGNAL m_axis_rc_tuser : std_logic_vector(74 downto 0); +SIGNAL m_axis_cq_tkeep : std_logic_vector(1 downto 0); +SIGNAL m_axis_rc_tkeep : std_logic_vector(1 downto 0); +SIGNAL m_axis_cq_tvalid : std_logic; +SIGNAL m_axis_rc_tvalid : std_logic; +SIGNAL s_axis_cc_tready : std_logic_vector(3 downto 0); +SIGNAL s_axis_rq_tready : std_logic_vector(3 downto 0); +SIGNAL pcie_rq_seq_num0 : std_logic_vector(5 downto 0); +SIGNAL pcie_rq_seq_num_vld0 : std_logic; +SIGNAL pcie_rq_seq_num1 : std_logic_vector(5 downto 0); +SIGNAL pcie_rq_seq_num_vld1 : std_logic; +SIGNAL pcie_rq_tag0 : std_logic_vector(7 downto 0); +SIGNAL pcie_rq_tag_vld0 : std_logic; +SIGNAL pcie_rq_tag1 : std_logic_vector(7 downto 0); +SIGNAL pcie_rq_tag_vld1 : std_logic; +SIGNAL pcie_tfc_nph_av : std_logic_vector(3 downto 0); +SIGNAL pcie_tfc_npd_av : std_logic_vector(3 downto 0); +SIGNAL pcie_rq_tag_av : std_logic_vector(3 downto 0); +SIGNAL cfg_mgmt_read_data : std_logic_vector(31 downto 0); +SIGNAL cfg_mgmt_read_write_done : std_logic; +SIGNAL cfg_phy_link_down : std_logic; +SIGNAL cfg_phy_link_status : std_logic_vector(1 downto 0); +SIGNAL cfg_negotiated_width : std_logic_vector(2 downto 0); +SIGNAL cfg_current_speed : std_logic_vector(1 downto 0); +SIGNAL cfg_max_payload : std_logic_vector(1 downto 0); +SIGNAL cfg_max_read_req : std_logic_vector(2 downto 0); +SIGNAL cfg_function_status : std_logic_vector(15 downto 0); +SIGNAL cfg_function_power_state : std_logic_vector(11 downto 0); +SIGNAL cfg_link_power_state : std_logic_vector(1 downto 0); +SIGNAL cfg_err_cor_out : std_logic; +SIGNAL cfg_err_nonfatal_out : std_logic; +SIGNAL cfg_err_fatal_out : std_logic; +SIGNAL cfg_local_error_valid : std_logic; +SIGNAL cfg_local_error_out : std_logic_vector(4 downto 0); +SIGNAL cfg_ltssm_state : std_logic_vector(5 downto 0); +SIGNAL cfg_rx_pm_state : std_logic_vector(1 downto 0); +SIGNAL cfg_tx_pm_state : std_logic_vector(1 downto 0); +SIGNAL cfg_rcb_status : std_logic_vector(3 downto 0); +SIGNAL cfg_obff_enable : std_logic_vector(1 downto 0); +SIGNAL cfg_pl_status_change : std_logic; +SIGNAL cfg_tph_requester_enable : std_logic_vector(3 downto 0); +SIGNAL cfg_tph_st_mode : std_logic_vector(11 downto 0); +SIGNAL cfg_msg_received : std_logic; +SIGNAL cfg_msg_received_data : std_logic_vector(7 downto 0); +SIGNAL cfg_msg_received_type : std_logic_vector(4 downto 0); +SIGNAL cfg_msg_transmit_done : std_logic; +SIGNAL cfg_fc_ph : std_logic_vector(7 downto 0); +SIGNAL cfg_fc_pd : std_logic_vector(11 downto 0); +SIGNAL cfg_fc_nph : std_logic_vector(7 downto 0); +SIGNAL cfg_fc_npd : std_logic_vector(11 downto 0); +SIGNAL cfg_fc_cplh : std_logic_vector(7 downto 0); +SIGNAL cfg_fc_cpld : std_logic_vector(11 downto 0); +SIGNAL cfg_hot_reset_out : std_logic; +--SIGNAL cfg_bus_number : std_logic_vector(7 downto 0); +SIGNAL cfg_power_state_change_interrupt : std_logic; +SIGNAL cfg_flr_in_process : std_logic_vector(3 downto 0); +SIGNAL cfg_interrupt_sent : std_logic; +SIGNAL cfg_interrupt_msi_enable : std_logic_vector(3 downto 0); +SIGNAL cfg_interrupt_msi_sent : std_logic; +SIGNAL cfg_interrupt_msi_fail : std_logic; +SIGNAL cfg_interrupt_msi_mmenable : std_logic_vector(11 downto 0); +SIGNAL cfg_interrupt_msi_mask_update : std_logic; +SIGNAL cfg_interrupt_msi_data : std_logic_vector(31 downto 0); +SIGNAL cfg_interrupt_msix_enable : std_logic_vector(3 downto 0); +SIGNAL cfg_interrupt_msix_mask : std_logic_vector(3 downto 0); +SIGNAL cfg_interrupt_msix_vec_pending_status : std_logic; +SIGNAL cfg_ext_read_received : std_logic; +SIGNAL cfg_ext_write_received : std_logic; +SIGNAL cfg_ext_register_number : std_logic_vector(9 downto 0); +SIGNAL cfg_ext_function_number : std_logic_vector(7 downto 0); +SIGNAL cfg_ext_write_data : std_logic_vector(31 downto 0); +SIGNAL cfg_ext_write_byte_enable : std_logic_vector(3 downto 0); +SIGNAL rbar_bar_size : std_logic_vector(5 downto 0); +SIGNAL rbar_function_number : std_logic_vector(7 downto 0); +SIGNAL rbar_write_enable_bar0 : std_logic; +SIGNAL rbar_write_enable_bar1 : std_logic; +SIGNAL rbar_write_enable_bar2 : std_logic; +SIGNAL rbar_write_enable_bar3 : std_logic; +SIGNAL rbar_write_enable_bar4 : std_logic; +SIGNAL rbar_write_enable_bar5 : std_logic; +SIGNAL cfg_vf_flr_in_process : std_logic_vector(251 downto 0); +SIGNAL cfg_vf_status : std_logic_vector(503 downto 0); +SIGNAL cfg_vf_power_state : std_logic_vector(755 downto 0); +SIGNAL cfg_vf_tph_requester_enable : std_logic_vector(251 downto 0); +SIGNAL cfg_vf_tph_st_mode : std_logic_vector(755 downto 0); +SIGNAL cfg_interrupt_msix_vf_enable : std_logic_vector(251 downto 0); +SIGNAL cfg_interrupt_msix_vf_mask : std_logic_vector(251 downto 0); +SIGNAL conf_req_ready : std_logic; +SIGNAL conf_resp_rdata : std_logic_vector(31 downto 0); +SIGNAL conf_resp_valid : std_logic; +SIGNAL cap_req : std_logic; +SIGNAL mcap_design_switch : std_logic; +SIGNAL user_clk : std_logic; +SIGNAL core_clk : std_logic; +SIGNAL gt_drp_clk : std_logic; +SIGNAL user_reset : std_logic; +SIGNAL user_lnk_up : std_logic; +SIGNAL sys_clk_ce_out : std_logic; +SIGNAL ext_ch_gt_drpclk : std_logic; +SIGNAL ext_ch_gt_drprdy : std_logic_vector(7 downto 0); +SIGNAL ext_ch_gt_drpdo : std_logic_vector(127 downto 0); +SIGNAL drp_rdy : std_logic; +SIGNAL drp_do : std_logic_vector(15 downto 0); +SIGNAL gt_txelecidle : std_logic_vector(7 downto 0); +SIGNAL gt_txresetdone : std_logic_vector(7 downto 0); +SIGNAL gt_rxresetdone : std_logic_vector(7 downto 0); +SIGNAL gt_rxpmaresetdone : std_logic_vector(7 downto 0); +SIGNAL gt_txphaligndone : std_logic_vector(7 downto 0); +SIGNAL gt_txphinitdone : std_logic_vector(7 downto 0); +SIGNAL gt_txdlysresetdone : std_logic_vector(7 downto 0); +SIGNAL gt_rxphaligndone : std_logic_vector(7 downto 0); +SIGNAL gt_rxdlysresetdone : std_logic_vector(7 downto 0); +SIGNAL gt_rxsyncdone : std_logic_vector(7 downto 0); +SIGNAL gt_eyescandataerror : std_logic_vector(7 downto 0); +SIGNAL gt_rxprbserr : std_logic_vector(7 downto 0); +SIGNAL gt_dmonitorout : std_logic_vector(127 downto 0); +SIGNAL gt_rxcommadet : std_logic_vector(7 downto 0); +SIGNAL gt_phystatus : std_logic_vector(7 downto 0); +SIGNAL gt_rxvalid : std_logic_vector(7 downto 0); +SIGNAL gt_rxcdrlock : std_logic_vector(7 downto 0); +SIGNAL gt_pcierateidle : std_logic_vector(7 downto 0); +SIGNAL gt_pcieuserratestart : std_logic_vector(7 downto 0); +SIGNAL gt_gtpowergood : std_logic_vector(7 downto 0); +SIGNAL gt_cplllock : std_logic_vector(7 downto 0); +SIGNAL gt_rxoutclk : std_logic_vector(7 downto 0); +SIGNAL gt_rxrecclkout : std_logic_vector(7 downto 0); +SIGNAL gt_qpll0lock : std_logic_vector(1 downto 0); +SIGNAL gt_qpll1lock : std_logic_vector(1 downto 0); +SIGNAL gt_rxstatus : std_logic_vector(23 downto 0); +SIGNAL gt_rxbufstatus : std_logic_vector(23 downto 0); +SIGNAL gt_bufgtdiv : std_logic_vector(8 downto 0); +SIGNAL phy_txeq_ctrl : std_logic_vector(15 downto 0); +SIGNAL phy_txeq_preset : std_logic_vector(31 downto 0); +SIGNAL phy_rst_fsm : std_logic_vector(3 downto 0); +SIGNAL phy_txeq_fsm : std_logic_vector(23 downto 0); +SIGNAL phy_rxeq_fsm : std_logic_vector(23 downto 0); +SIGNAL phy_rst_idle : std_logic; +SIGNAL phy_rrst_n : std_logic; +SIGNAL phy_prst_n : std_logic; +SIGNAL gt_gen34_eios_det : std_logic_vector(7 downto 0); +SIGNAL gt_txoutclk : std_logic_vector(7 downto 0); +SIGNAL gt_txoutclkfabric : std_logic_vector(7 downto 0); +SIGNAL gt_rxoutclkfabric : std_logic_vector(7 downto 0); +SIGNAL gt_txoutclkpcs : std_logic_vector(7 downto 0); +SIGNAL gt_rxoutclkpcs : std_logic_vector(7 downto 0); +SIGNAL gt_txprogdivresetdone : std_logic_vector(7 downto 0); +SIGNAL gt_txpmaresetdone : std_logic_vector(7 downto 0); +SIGNAL gt_txsyncdone : std_logic_vector(7 downto 0); +SIGNAL gt_rxprbslocked : std_logic_vector(7 downto 0); +SIGNAL common_commands_out : std_logic_vector(25 downto 0); +SIGNAL pipe_tx_0_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_1_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_2_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_3_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_4_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_5_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_6_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_7_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_8_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_9_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_10_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_11_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_12_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_13_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_14_sigs : std_logic_vector(83 downto 0); +SIGNAL pipe_tx_15_sigs : std_logic_vector(83 downto 0); +SIGNAL int_qpll0lock_out : std_logic_vector(1 downto 0); +SIGNAL int_qpll0outrefclk_out : std_logic_vector(1 downto 0); +SIGNAL int_qpll0outclk_out : std_logic_vector(1 downto 0); +SIGNAL int_qpll1lock_out : std_logic_vector(1 downto 0); +SIGNAL int_qpll1outrefclk_out : std_logic_vector(1 downto 0); +SIGNAL int_qpll1outclk_out : std_logic_vector(1 downto 0); +SIGNAL ext_qpllxrefclk : std_logic_vector(1 downto 0); +SIGNAL ext_qpllxrate : std_logic_vector(5 downto 0); +SIGNAL ext_qpllxrcalenb : std_logic; +SIGNAL ext_qpll0pd : std_logic_vector(1 downto 0); +SIGNAL ext_qpll0reset : std_logic_vector(1 downto 0); +SIGNAL ext_qpll1pd : std_logic_vector(1 downto 0); +SIGNAL ext_qpll1reset : std_logic_vector(1 downto 0); +SIGNAL gtrefclk01_in : std_logic_vector(1 downto 0); +SIGNAL gtrefclk00_in : std_logic_vector(1 downto 0); +SIGNAL pcierateqpll0_in : std_logic_vector(5 downto 0); +SIGNAL pcierateqpll1_in : std_logic_vector(5 downto 0); +SIGNAL qpll0pd_in : std_logic_vector(1 downto 0); +SIGNAL qpll0reset_in : std_logic_vector(1 downto 0); +SIGNAL qpll1pd_in : std_logic_vector(1 downto 0); +SIGNAL qpll1reset_in : std_logic_vector(1 downto 0); +SIGNAL qpll0freqlock_in : std_logic_vector(7 downto 0); +SIGNAL qpll1freqlock_in : std_logic_vector(7 downto 0); +SIGNAL rcalenb_in : std_logic_vector(1 downto 0); +SIGNAL txpisopd_in : std_logic_vector(7 downto 0); +SIGNAL cpllfreqlock_in : std_logic_vector(7 downto 0); +SIGNAL cpllpd_in : std_logic_vector(7 downto 0); +SIGNAL cpllreset_in : std_logic_vector(7 downto 0); +SIGNAL dmonfiforeset_in : std_logic_vector(7 downto 0); +SIGNAL dmonitorclk_in : std_logic_vector(7 downto 0); +SIGNAL eyescanreset_in : std_logic_vector(7 downto 0); +SIGNAL gtrefclk0_in : std_logic_vector(7 downto 0); +SIGNAL gtrxreset_in : std_logic_vector(7 downto 0); +SIGNAL gttxreset_in : std_logic_vector(7 downto 0); +SIGNAL gtwiz_reset_rx_done_in : std_logic; +SIGNAL gtwiz_reset_tx_done_in : std_logic; +SIGNAL gtwiz_userclk_rx_active_in : std_logic; +SIGNAL gtwiz_userclk_tx_active_in : std_logic; +SIGNAL loopback_in : std_logic_vector(23 downto 0); +SIGNAL pcieeqrxeqadaptdone_in : std_logic_vector(7 downto 0); +SIGNAL pcierstidle_in : std_logic_vector(7 downto 0); +SIGNAL pciersttxsyncstart_in : std_logic_vector(7 downto 0); +SIGNAL pcieuserratedone_in : std_logic_vector(7 downto 0); +SIGNAL resetovrd_in : std_logic_vector(7 downto 0); +SIGNAL rx8b10ben_in : std_logic_vector(7 downto 0); +SIGNAL rxbufreset_in : std_logic_vector(7 downto 0); +SIGNAL rxcdrfreqreset_in : std_logic_vector(7 downto 0); +SIGNAL rxcdrhold_in : std_logic_vector(7 downto 0); +SIGNAL rxcdrreset_in : std_logic_vector(7 downto 0); +SIGNAL rxcommadeten_in : std_logic_vector(7 downto 0); +SIGNAL rxdfeagchold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfecfokhold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfekhhold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfelfhold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfelpmreset_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap10hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap11hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap12hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap13hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap14hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap15hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap2hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap3hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap4hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap5hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap6hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap7hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap8hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfetap9hold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfeuthold_in : std_logic_vector(7 downto 0); +SIGNAL rxdfevphold_in : std_logic_vector(7 downto 0); +SIGNAL rxlpmen_in : std_logic_vector(7 downto 0); +SIGNAL rxlpmgchold_in : std_logic_vector(7 downto 0); +SIGNAL rxlpmhfhold_in : std_logic_vector(7 downto 0); +SIGNAL rxlpmlfhold_in : std_logic_vector(7 downto 0); +SIGNAL rxlpmoshold_in : std_logic_vector(7 downto 0); +SIGNAL rxmcommaalignen_in : std_logic_vector(7 downto 0); +SIGNAL rxoshold_in : std_logic_vector(7 downto 0); +SIGNAL rxpcommaalignen_in : std_logic_vector(7 downto 0); +SIGNAL rxpcsreset_in : std_logic_vector(7 downto 0); +SIGNAL rxpd_in : std_logic_vector(15 downto 0); +SIGNAL rxpmareset_in : std_logic_vector(7 downto 0); +SIGNAL rxpolarity_in : std_logic_vector(7 downto 0); +SIGNAL rxprbscntreset_in : std_logic_vector(7 downto 0); +SIGNAL rxprbssel_in : std_logic_vector(31 downto 0); +SIGNAL rxprogdivreset_in : std_logic_vector(7 downto 0); +SIGNAL rxrate_in : std_logic_vector(23 downto 0); +SIGNAL rxslide_in : std_logic_vector(7 downto 0); +SIGNAL rxtermination_in : std_logic_vector(7 downto 0); +SIGNAL rxuserrdy_in : std_logic_vector(7 downto 0); +SIGNAL rxusrclk2_in : std_logic_vector(7 downto 0); +SIGNAL rxusrclk_in : std_logic_vector(7 downto 0); +SIGNAL tx8b10ben_in : std_logic_vector(7 downto 0); +SIGNAL txctrl0_in : std_logic_vector(127 downto 0); +SIGNAL txctrl1_in : std_logic_vector(127 downto 0); +SIGNAL txctrl2_in : std_logic_vector(63 downto 0); +SIGNAL txdata_in : std_logic_vector(1023 downto 0); +SIGNAL txdeemph_in : std_logic_vector(15 downto 0); +SIGNAL txdetectrx_in : std_logic_vector(7 downto 0); +SIGNAL txdiffctrl_in : std_logic_vector(39 downto 0); +SIGNAL txdlybypass_in : std_logic_vector(7 downto 0); +SIGNAL txdlyen_in : std_logic_vector(7 downto 0); +SIGNAL txdlyhold_in : std_logic_vector(7 downto 0); +SIGNAL txdlyovrden_in : std_logic_vector(7 downto 0); +SIGNAL txdlysreset_in : std_logic_vector(7 downto 0); +SIGNAL txdlyupdown_in : std_logic_vector(7 downto 0); +SIGNAL txelecidle_in : std_logic_vector(7 downto 0); +SIGNAL txmaincursor_in : std_logic_vector(55 downto 0); +SIGNAL txmargin_in : std_logic_vector(23 downto 0); +SIGNAL txoutclksel_in : std_logic_vector(23 downto 0); +SIGNAL txpcsreset_in : std_logic_vector(7 downto 0); +SIGNAL txpd_in : std_logic_vector(15 downto 0); +SIGNAL txphalign_in : std_logic_vector(7 downto 0); +SIGNAL txphalignen_in : std_logic_vector(7 downto 0); +SIGNAL txphdlypd_in : std_logic_vector(7 downto 0); +SIGNAL txphdlyreset_in : std_logic_vector(7 downto 0); +SIGNAL txphdlytstclk_in : std_logic_vector(7 downto 0); +SIGNAL txphinit_in : std_logic_vector(7 downto 0); +SIGNAL txphovrden_in : std_logic_vector(7 downto 0); +SIGNAL rxratemode_in : std_logic_vector(7 downto 0); +SIGNAL txpmareset_in : std_logic_vector(7 downto 0); +SIGNAL txpostcursor_in : std_logic_vector(39 downto 0); +SIGNAL txprbsforceerr_in : std_logic_vector(7 downto 0); +SIGNAL txprbssel_in : std_logic_vector(31 downto 0); +SIGNAL txprecursor_in : std_logic_vector(39 downto 0); +SIGNAL txprogdivreset_in : std_logic_vector(7 downto 0); +SIGNAL txrate_in : std_logic_vector(23 downto 0); +SIGNAL txswing_in : std_logic_vector(7 downto 0); +SIGNAL txsyncallin_in : std_logic_vector(7 downto 0); +SIGNAL txsyncin_in : std_logic_vector(7 downto 0); +SIGNAL txsyncmode_in : std_logic_vector(7 downto 0); +SIGNAL txuserrdy_in : std_logic_vector(7 downto 0); +SIGNAL txusrclk2_in : std_logic_vector(7 downto 0); +SIGNAL txusrclk_in : std_logic_vector(7 downto 0); +SIGNAL drpclk_in : std_logic; +SIGNAL drpaddr_in : std_logic_vector(79 downto 0); +SIGNAL drpen_in : std_logic_vector(7 downto 0); +SIGNAL drprst_in : std_logic_vector(7 downto 0); +SIGNAL drpwe_in : std_logic_vector(7 downto 0); +SIGNAL drpdi_in : std_logic_vector(127 downto 0); +SIGNAL ext_phy_clk_bufg_gt_ce : std_logic; +SIGNAL ext_phy_clk_bufg_gt_reset : std_logic; +SIGNAL ext_phy_clk_rst_idle : std_logic; +SIGNAL ext_phy_clk_txoutclk : std_logic; +SIGNAL ext_phy_clk_bufgtcemask : std_logic; +SIGNAL ext_phy_clk_gt_bufgtrstmask : std_logic; +SIGNAL ext_phy_clk_bufgtdiv : std_logic_vector(8 downto 0); +SIGNAL phy_rdy_out : std_logic; +SIGNAL sys_reset : std_logic; +SIGNAL in_packet_reg : std_logic; +SIGNAL cfg_bus_number_sub : std_logic_vector(7 downto 0); +SIGNAL cfg_dsn_sub : std_logic_vector(63 downto 0); +SIGNAL cfg_flr_done_sub : std_logic_vector(3 downto 0); +SIGNAL cfg_vf_flr_done_sub : std_logic_vector(0 downto 0); +SIGNAL sys_clk_sub : std_logic; + + + + CONSTANT PL_LINK_CAP_MAX_LINK_WIDTH : integer := 1; -- 1- X1; 2 - X2; 4 - X4; 8 - X8; 16 - X16 + CONSTANT C_DATA_WIDTH : integer := 64; -- RX/TX interface data width + CONSTANT AXISTEN_IF_MC_RX_STRADDLE : integer := 0; + CONSTANT PL_LINK_CAP_MAX_LINK_SPEED : integer := 2; -- 1- GEN1; 2 - GEN2; 4 - GEN3; 8 - GEN4 + CONSTANT KEEP_WIDTH : integer := C_DATA_WIDTH / 32; + CONSTANT EXT_PIPE_SIM : BOOLEAN := FALSE; -- This CONSTANT has effect on selecting Enable External PIPE Interface in GUI. + CONSTANT AXISTEN_IF_CC_ALIGNMENT_MODE : BOOLEAN := FALSE; + CONSTANT AXISTEN_IF_CQ_ALIGNMENT_MODE : BOOLEAN := FALSE; + CONSTANT AXISTEN_IF_RQ_ALIGNMENT_MODE : BOOLEAN := FALSE; + CONSTANT AXISTEN_IF_RC_ALIGNMENT_MODE : BOOLEAN := FALSE; + CONSTANT AXI4_CQ_TUSER_WIDTH : integer := 88; + CONSTANT AXI4_CC_TUSER_WIDTH : integer := 33; + CONSTANT AXI4_RQ_TUSER_WIDTH : integer := 62; + CONSTANT AXI4_RC_TUSER_WIDTH : integer := 75; + CONSTANT AXISTEN_IF_ENABLE_CLIENT_TAG : integer := 0; + CONSTANT RQ_AVAIL_TAG_IDX : integer := 8; + CONSTANT RQ_AVAIL_TAG : integer := 256; + CONSTANT AXISTEN_IF_RQ_PARITY_CHECK : integer := 0; + CONSTANT AXISTEN_IF_CC_PARITY_CHECK : integer := 0; + CONSTANT AXISTEN_IF_RC_PARITY_CHECK : integer := 0; + CONSTANT AXISTEN_IF_CQ_PARITY_CHECK : integer := 0; + CONSTANT AXISTEN_IF_ENABLE_RX_MSG_INTFC : BOOLEAN := FALSE; + --CONSTANT AXISTEN_IF_ENABLE_MSG_ROUTE : std_logic_vector(17 downto 0) := X"2FFFF"; + + + + +--------- COMPONENT DECLARATIONS (introducing the IPs) -------------------------- +COMPONENT pcie4_uscale_plus_0 + PORT ( + pci_exp_txn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + pci_exp_txp : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + pci_exp_rxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + pci_exp_rxp : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + user_clk : OUT STD_LOGIC; + user_reset : OUT STD_LOGIC; + user_lnk_up : OUT STD_LOGIC; + s_axis_rq_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + s_axis_rq_tkeep : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axis_rq_tlast : IN STD_LOGIC; + s_axis_rq_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axis_rq_tuser : IN STD_LOGIC_VECTOR(61 DOWNTO 0); + s_axis_rq_tvalid : IN STD_LOGIC; + m_axis_rc_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + m_axis_rc_tkeep : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axis_rc_tlast : OUT STD_LOGIC; + m_axis_rc_tready : IN STD_LOGIC; + m_axis_rc_tuser : OUT STD_LOGIC_VECTOR(74 DOWNTO 0); + m_axis_rc_tvalid : OUT STD_LOGIC; + m_axis_cq_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + m_axis_cq_tkeep : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axis_cq_tlast : OUT STD_LOGIC; + m_axis_cq_tready : IN STD_LOGIC; + m_axis_cq_tuser : OUT STD_LOGIC_VECTOR(87 DOWNTO 0); + m_axis_cq_tvalid : OUT STD_LOGIC; + s_axis_cc_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + s_axis_cc_tkeep : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axis_cc_tlast : IN STD_LOGIC; + s_axis_cc_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axis_cc_tuser : IN STD_LOGIC_VECTOR(32 DOWNTO 0); + s_axis_cc_tvalid : IN STD_LOGIC; + pcie_rq_seq_num0 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + pcie_rq_seq_num_vld0 : OUT STD_LOGIC; + pcie_rq_seq_num1 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + pcie_rq_seq_num_vld1 : OUT STD_LOGIC; + pcie_rq_tag0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + pcie_rq_tag1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + pcie_rq_tag_av : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pcie_rq_tag_vld0 : OUT STD_LOGIC; + pcie_rq_tag_vld1 : OUT STD_LOGIC; + pcie_tfc_nph_av : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pcie_tfc_npd_av : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pcie_cq_np_req : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pcie_cq_np_req_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + cfg_phy_link_down : OUT STD_LOGIC; + cfg_phy_link_status : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + cfg_negotiated_width : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + cfg_current_speed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + cfg_max_payload : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + cfg_max_read_req : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + cfg_function_status : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + cfg_function_power_state : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + cfg_vf_status : OUT STD_LOGIC_VECTOR(503 DOWNTO 0); + cfg_vf_power_state : OUT STD_LOGIC_VECTOR(755 DOWNTO 0); + cfg_link_power_state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + cfg_mgmt_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + cfg_mgmt_function_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cfg_mgmt_write : IN STD_LOGIC; + cfg_mgmt_write_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + cfg_mgmt_byte_enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + cfg_mgmt_read : IN STD_LOGIC; + cfg_mgmt_read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + cfg_mgmt_read_write_done : OUT STD_LOGIC; + cfg_mgmt_debug_access : IN STD_LOGIC; + cfg_err_cor_out : OUT STD_LOGIC; + cfg_err_nonfatal_out : OUT STD_LOGIC; + cfg_err_fatal_out : OUT STD_LOGIC; + cfg_local_error_valid : OUT STD_LOGIC; + cfg_local_error_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + cfg_ltssm_state : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + cfg_rx_pm_state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + cfg_tx_pm_state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + cfg_rcb_status : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + cfg_obff_enable : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + cfg_pl_status_change : OUT STD_LOGIC; + cfg_tph_requester_enable : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + cfg_tph_st_mode : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + cfg_vf_tph_requester_enable : OUT STD_LOGIC_VECTOR(251 DOWNTO 0); + cfg_vf_tph_st_mode : OUT STD_LOGIC_VECTOR(755 DOWNTO 0); + cfg_msg_received : OUT STD_LOGIC; + cfg_msg_received_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + cfg_msg_received_type : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + cfg_msg_transmit : IN STD_LOGIC; + cfg_msg_transmit_type : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + cfg_msg_transmit_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + cfg_msg_transmit_done : OUT STD_LOGIC; + cfg_fc_ph : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + cfg_fc_pd : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + cfg_fc_nph : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + cfg_fc_npd : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + cfg_fc_cplh : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + cfg_fc_cpld : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + cfg_fc_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + cfg_dsn : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + cfg_bus_number : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + cfg_power_state_change_ack : IN STD_LOGIC; + cfg_power_state_change_interrupt : OUT STD_LOGIC; + cfg_err_cor_in : IN STD_LOGIC; + cfg_err_uncor_in : IN STD_LOGIC; + cfg_flr_in_process : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + cfg_flr_done : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + cfg_vf_flr_in_process : OUT STD_LOGIC_VECTOR(251 DOWNTO 0); + cfg_vf_flr_func_num : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cfg_vf_flr_done : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + cfg_link_training_enable : IN STD_LOGIC; + cfg_interrupt_int : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + cfg_interrupt_pending : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + cfg_interrupt_sent : OUT STD_LOGIC; + cfg_interrupt_msi_enable : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + cfg_interrupt_msi_mmenable : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + cfg_interrupt_msi_mask_update : OUT STD_LOGIC; + cfg_interrupt_msi_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + cfg_interrupt_msi_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + cfg_interrupt_msi_int : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + cfg_interrupt_msi_pending_status : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + cfg_interrupt_msi_pending_status_data_enable : IN STD_LOGIC; + cfg_interrupt_msi_pending_status_function_num : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + cfg_interrupt_msi_sent : OUT STD_LOGIC; + cfg_interrupt_msi_fail : OUT STD_LOGIC; + cfg_interrupt_msi_attr : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + cfg_interrupt_msi_tph_present : IN STD_LOGIC; + cfg_interrupt_msi_tph_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + cfg_interrupt_msi_tph_st_tag : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cfg_interrupt_msi_function_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cfg_pm_aspm_l1_entry_reject : IN STD_LOGIC; + cfg_pm_aspm_tx_l0s_entry_disable : IN STD_LOGIC; + cfg_hot_reset_out : OUT STD_LOGIC; + cfg_config_space_enable : IN STD_LOGIC; + cfg_req_pm_transition_l23_ready : IN STD_LOGIC; + cfg_hot_reset_in : IN STD_LOGIC; + cfg_ds_port_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cfg_ds_bus_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cfg_ds_device_number : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sys_clk : IN STD_LOGIC; + sys_clk_gt : IN STD_LOGIC; + sys_reset : IN STD_LOGIC; + gt_pcieuserratedone : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_loopback : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + gt_txprbsforceerr : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txinhibit : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txprbssel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + gt_rxprbssel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + gt_rxprbscntreset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txelecidle : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxpmaresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txphaligndone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txphinitdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txdlysresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxphaligndone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxdlysresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxsyncdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_eyescandataerror : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxprbserr : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_dmonfiforeset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_dmonitorclk : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_dmonitorout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + gt_rxcommadet : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_phystatus : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxvalid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxcdrlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_pcierateidle : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_pcieuserratestart : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_gtpowergood : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_cplllock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxoutclk : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxrecclkout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_qpll1lock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_qpll0lock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + gt_rxbufstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + gt_bufgtdiv : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); + phy_txeq_ctrl : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + phy_txeq_preset : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + phy_rst_fsm : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + phy_txeq_fsm : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + phy_rxeq_fsm : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + phy_rst_idle : OUT STD_LOGIC; + phy_rrst_n : OUT STD_LOGIC; + phy_prst_n : OUT STD_LOGIC; + gt_gen34_eios_det : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txoutclk : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txoutclkfabric : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxoutclkfabric : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txoutclkpcs : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxoutclkpcs : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txpmareset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxpmareset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txpcsreset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxpcsreset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxbufreset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxcdrreset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxdfelpmreset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txprogdivresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txpmaresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_txsyncdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_rxprbslocked : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + phy_rdy_out : OUT STD_LOGIC + ); +END COMPONENT; + + + +--architecture body start ------------------------------------------------------- +begin +--------- COMPONENT INSTALLATIONS (connecting the IPs to local signals) --------- +xilinx_pcie_ip : pcie4_uscale_plus_0 + PORT MAP ( + pci_exp_txn(0) => pci_exp_txn, + pci_exp_txp(0) => pci_exp_txp, + pci_exp_rxn(0) => pci_exp_rxn, + pci_exp_rxp(0) => pci_exp_rxp, + user_clk => user_clk , + user_reset => user_reset , + user_lnk_up => user_lnk_up , + phy_rdy_out => phy_rdy_out , + s_axis_rq_tlast => s_axis_rq_tlast , + s_axis_rq_tdata => s_axis_rq_tdata , + s_axis_rq_tuser => s_axis_rq_tuser , + s_axis_rq_tkeep => s_axis_rq_tkeep , + s_axis_rq_tready => s_axis_rq_tready , + s_axis_rq_tvalid => s_axis_rq_tvalid , + m_axis_rc_tdata => m_axis_rc_tdata , + m_axis_rc_tuser => m_axis_rc_tuser , + m_axis_rc_tlast => m_axis_rc_tlast , + m_axis_rc_tkeep => m_axis_rc_tkeep , + m_axis_rc_tvalid => m_axis_rc_tvalid , + m_axis_rc_tready => m_axis_rc_tready , + m_axis_cq_tdata => m_axis_cq_tdata , + m_axis_cq_tuser => m_axis_cq_tuser , + m_axis_cq_tlast => m_axis_cq_tlast , + m_axis_cq_tkeep => m_axis_cq_tkeep , + m_axis_cq_tvalid => m_axis_cq_tvalid , + m_axis_cq_tready => m_axis_cq_tready , + s_axis_cc_tdata => s_axis_cc_tdata , + s_axis_cc_tuser => s_axis_cc_tuser , + s_axis_cc_tlast => s_axis_cc_tlast , + s_axis_cc_tkeep => s_axis_cc_tkeep , + s_axis_cc_tvalid => s_axis_cc_tvalid , + s_axis_cc_tready => s_axis_cc_tready , + gt_pcieuserratedone => (OTHERS => '0'), + gt_loopback => (OTHERS => '0'), + gt_txprbsforceerr => (OTHERS => '0'), + gt_txinhibit => (OTHERS => '0'), + gt_txprbssel => (OTHERS => '0'), + gt_rxprbssel => (OTHERS => '0'), + gt_rxprbscntreset => (OTHERS => '0'), +-- gt_rxcdrlock => , +-- gt_pcierateidle => , +-- gt_pcieuserratestart => , +-- gt_gtpowergood => , +-- gt_rxoutclk => , +-- gt_rxrecclkout => , +-- gt_txresetdone => , +-- gt_rxpmaresetdone => , +-- gt_rxresetdone => , +-- gt_rxbufstatus => , +-- gt_txphaligndone => , +-- gt_txphinitdone => , +-- gt_txdlysresetdone => , +-- gt_rxphaligndone => , +-- gt_rxdlysresetdone => , +-- gt_rxsyncdone => , +-- gt_cplllock => , +-- gt_qpll0lock => , +-- gt_qpll1lock => , +-- gt_eyescandataerror => , +-- gt_rxprbserr => , +-- gt_dmonitorout => , + gt_dmonfiforeset => (OTHERS => '0'), + gt_dmonitorclk => (OTHERS => '0'), +-- gt_rxcommadet => , +-- gt_txelecidle => , +-- gt_rxvalid => , +-- gt_bufgtdiv => , +-- phy_rrst_n => , +-- phy_txeq_ctrl => , +-- phy_txeq_preset => , +-- phy_txeq_fsm => , +-- phy_rxeq_fsm => , +-- phy_rst_idle => , +-- gt_gen34_eios_det => , +-- gt_txoutclk => , +-- gt_txoutclkfabric => , +-- gt_rxoutclkfabric => , +-- gt_txoutclkpcs => , +-- gt_rxoutclkpcs => , + gt_txpmareset => (OTHERS => '0'), + gt_rxpmareset => (OTHERS => '0'), + gt_txpcsreset => (OTHERS => '0'), + gt_rxpcsreset => (OTHERS => '0'), + gt_rxbufreset => (OTHERS => '0'), + gt_rxcdrreset => (OTHERS => '0'), + gt_rxdfelpmreset => (OTHERS => '0'), +-- gt_txprogdivresetdone => , +-- gt_txpmaresetdone => , +-- gt_txsyncdone => , +-- gt_rxprbslocked => , +-- phy_prst_n => , +-- phy_rst_fsm => , +-- gt_phystatus => , +-- gt_rxstatus => , + pcie_tfc_nph_av => pcie_tfc_nph_av , + pcie_tfc_npd_av => pcie_tfc_npd_av , + pcie_rq_seq_num0 => pcie_rq_seq_num0 , + pcie_rq_seq_num_vld0 => pcie_rq_seq_num_vld0 , + pcie_rq_seq_num1 => pcie_rq_seq_num1 , + pcie_rq_seq_num_vld1 => pcie_rq_seq_num_vld1 , +-- pcie_rq_tag0 => , +-- pcie_rq_tag1 => , +-- pcie_rq_tag_av => , +-- pcie_rq_tag_vld0 => , +-- pcie_rq_tag_vld1 => , + pcie_cq_np_req => pcie_cq_np_req , + pcie_cq_np_req_count => pcie_cq_np_req_count , + cfg_phy_link_down => cfg_phy_link_down , +-- cfg_phy_link_status => , + cfg_negotiated_width => cfg_negotiated_width , + cfg_current_speed => cfg_current_speed , + cfg_max_payload => cfg_max_payload , + cfg_max_read_req => cfg_max_read_req , + cfg_function_status => cfg_function_status , + cfg_function_power_state => cfg_function_power_state , + cfg_vf_status => cfg_vf_status , +-- cfg_vf_power_state => , + cfg_link_power_state => cfg_link_power_state , + cfg_err_cor_out => cfg_err_cor_out , + cfg_err_nonfatal_out => cfg_err_nonfatal_out , + cfg_err_fatal_out => cfg_err_fatal_out , +-- cfg_local_error_out => , +-- cfg_local_error_valid => , + cfg_ltssm_state => cfg_ltssm_state , +-- cfg_rx_pm_state => , +-- cfg_tx_pm_state => , + cfg_rcb_status => cfg_rcb_status , + cfg_obff_enable => cfg_obff_enable , + cfg_pl_status_change => cfg_pl_status_change , +-- cfg_tph_requester_enable => , +-- cfg_tph_st_mode => , +-- cfg_vf_tph_requester_enable => , +-- cfg_vf_tph_st_mode => , + cfg_mgmt_addr => cfg_mgmt_addr , + cfg_mgmt_write => cfg_mgmt_write , + cfg_mgmt_write_data => cfg_mgmt_write_data , + cfg_mgmt_byte_enable => cfg_mgmt_byte_enable , + cfg_mgmt_read => cfg_mgmt_read , + cfg_mgmt_read_data => cfg_mgmt_read_data , + cfg_mgmt_read_write_done => cfg_mgmt_read_write_done , + cfg_mgmt_debug_access => '0', + cfg_mgmt_function_number => (OTHERS => '0'), + cfg_pm_aspm_l1_entry_reject => '0', + cfg_pm_aspm_tx_l0s_entry_disable => '1', + cfg_msg_received => cfg_msg_received , + cfg_msg_received_data => cfg_msg_received_data , + cfg_msg_received_type => cfg_msg_received_type , + cfg_msg_transmit => cfg_msg_transmit , + cfg_msg_transmit_type => cfg_msg_transmit_type , + cfg_msg_transmit_data => cfg_msg_transmit_data , + cfg_msg_transmit_done => cfg_msg_transmit_done , + cfg_fc_ph => cfg_fc_ph , + cfg_fc_pd => cfg_fc_pd , + cfg_fc_nph => cfg_fc_nph , + cfg_fc_npd => cfg_fc_npd , + cfg_fc_cplh => cfg_fc_cplh , + cfg_fc_cpld => cfg_fc_cpld , + cfg_fc_sel => cfg_fc_sel , + cfg_bus_number => cfg_bus_number_sub, + cfg_dsn => cfg_dsn_sub , + cfg_power_state_change_ack => cfg_power_state_change_ack , + cfg_power_state_change_interrupt => cfg_power_state_change_interrupt , + cfg_err_cor_in => cfg_err_cor_in , + cfg_err_uncor_in => cfg_err_uncor_in , + cfg_flr_in_process => cfg_flr_in_process , + cfg_flr_done => cfg_flr_done_sub , + cfg_vf_flr_in_process => cfg_vf_flr_in_process , + cfg_vf_flr_done => cfg_vf_flr_done_sub , + cfg_link_training_enable => cfg_link_training_enable , + cfg_hot_reset_out => cfg_hot_reset_out , + cfg_config_space_enable => cfg_config_space_enable , + cfg_req_pm_transition_l23_ready => cfg_req_pm_transition_l23_ready , + cfg_hot_reset_in => cfg_hot_reset_in , + cfg_ds_bus_number => cfg_ds_bus_number , + cfg_ds_device_number => cfg_ds_device_number , + cfg_ds_port_number => cfg_ds_port_number , + cfg_vf_flr_func_num => cfg_vf_flr_func_num, + cfg_interrupt_int => cfg_interrupt_int , + cfg_interrupt_pending => cfg_interrupt_pending , + cfg_interrupt_sent => cfg_interrupt_sent , + cfg_interrupt_msi_enable => cfg_interrupt_msi_enable , + cfg_interrupt_msi_mmenable => cfg_interrupt_msi_mmenable , + cfg_interrupt_msi_mask_update => cfg_interrupt_msi_mask_update , + cfg_interrupt_msi_data => cfg_interrupt_msi_data , + cfg_interrupt_msi_select => cfg_interrupt_msi_select , + cfg_interrupt_msi_int => cfg_interrupt_msi_int , + cfg_interrupt_msi_pending_status => cfg_interrupt_msi_pending_status (31 downto 0), + cfg_interrupt_msi_sent => cfg_interrupt_msi_sent , + cfg_interrupt_msi_fail => cfg_interrupt_msi_fail , + cfg_interrupt_msi_attr => cfg_interrupt_msi_attr , + cfg_interrupt_msi_tph_present => cfg_interrupt_msi_tph_present , + cfg_interrupt_msi_tph_type => cfg_interrupt_msi_tph_type , + cfg_interrupt_msi_tph_st_tag => cfg_interrupt_msi_tph_st_tag , + cfg_interrupt_msi_pending_status_function_num => "00", + cfg_interrupt_msi_pending_status_data_enable => '0', + cfg_interrupt_msi_function_number => cfg_interrupt_msi_function_number , + sys_clk => sys_clk_sub , + sys_clk_gt => sys_clk_gt , + sys_reset => sys_reset + ); + +-- local Logic ------------------------------------------------------------------ +sys_reset <= not sys_reset_n; + + + +--AXI4S-TRN conversions: +--start of frame, remainder-keep logic, data path DWORD-endian-reordering +--general rule: TRN_T* to S_AXIS_CC*, while TRN_R* to M_AXIS_CQ*, TRN_FC* to CFG_FC*. + +-- SIGNALS TO THIS FILE TOP OUTPUTS. + trn_lnk_up_n <= not user_lnk_up ; + -- Tx + trn_tdst_rdy_n <= not s_axis_cc_tready(0) ; + trn_terr_drop_n <= '1'; + trn_tbuf_av <= "000000"; + trn_tcfg_req_n <= '1'; + -- Rx + trn_rd(63 downto 32) <= m_axis_cq_tdata(31 downto 0); --endian swap + trn_rd(31 downto 0) <= m_axis_cq_tdata(63 downto 32); + trn_rsof_n <= not (m_axis_cq_tvalid and (not in_packet_reg)); + process ( sys_reset_n, user_clk) + begin + if (sys_reset_n = '0') then + in_packet_reg <='0'; + elsif (user_clk'event and user_clk = '1') then + if (m_axis_cq_tvalid='1' and m_axis_cq_tready='1') then + in_packet_reg <= not m_axis_cq_tlast; + end if; + end if; + end process; + trn_reof_n <= not m_axis_cq_tlast ; + trn_rsrc_rdy_n <= not m_axis_cq_tvalid; + trn_rsrc_dsc_n <= '0'; + trn_rerrfwd_n <= not m_axis_cq_tuser(1); + trn_rbar_hit_n <= not m_axis_cq_tuser(8 downto 2); + trn_fc_nph <= cfg_fc_nph ; + trn_fc_npd <= cfg_fc_npd ; + trn_fc_ph <= cfg_fc_ph ; + trn_fc_pd <= cfg_fc_pd ; + trn_fc_cplh <= cfg_fc_cplh; + trn_fc_cpld <= cfg_fc_cpld; + -- Host (CFG) Interface + cfg_do <= (OTHERS => '0'); + cfg_rd_wr_done_n <= not cfg_mgmt_read_write_done; + cfg_err_cpl_rdy_n <= '1'; + cfg_interrupt_rdy_n <= '1'; + cfg_interrupt_do <= (OTHERS => '0'); + cfg_interrupt_mmenable <= (OTHERS => '0'); + cfg_interrupt_msienable <= cfg_interrupt_msi_enable(0); + cfg_to_turnoff_n <= '1'; + cfg_pcie_link_state_n(1 downto 0) <= cfg_phy_link_status; + cfg_pcie_link_state_n(2) <= cfg_phy_link_down; + cfg_bus_number <= cfg_bus_number_sub; + cfg_device_number <= (OTHERS => '0'); --the new core doesnt provide this, so we assume 0. On PCI-express, each device is on a different bus, and device number=0. this core is simple, so func.num=0 too. + cfg_function_number <= (OTHERS => '0'); + cfg_status <= (OTHERS => '0'); + cfg_command <= (OTHERS => '0'); + cfg_dstatus <= (OTHERS => '0'); + cfg_dcommand <= (OTHERS => '0'); + cfg_lstatus <= (OTHERS => '0'); + cfg_lcommand <= (OTHERS => '0'); + -- System Interface + trn_clk <= user_clk; + trn_reset_n <= not user_reset; + received_hot_reset <= cfg_hot_reset_out; + + +--IP BELOW INPUTS: + s_axis_rq_tdata <= (OTHERS => '0'); + s_axis_rq_tkeep <= (OTHERS => '0'); + s_axis_rq_tlast <= '0'; + s_axis_rq_tuser <= (OTHERS => '0'); + s_axis_rq_tvalid <= '0'; + m_axis_rc_tready <= '0'; + m_axis_cq_tready <= not trn_rdst_rdy_n; --CQ=RX + s_axis_cc_tdata(63 downto 32) <= trn_td(31 downto 0); --endian swap. CC=TX + s_axis_cc_tdata(31 downto 0) <= trn_td(63 downto 32); + --since the trn_term signal is missing on TRN, I try to re-creste it here: + --s_axis_cc_tkeep <= "11"; --try to force this to all dwords always valid = "11" + --s_axis_cc_tkeep <= "01"; --try to force this to 32bit valid = "01" or "10" ??? + --it would be correct like this, but trn_term is missing, xilinx suggestion: + --process ( sys_reset_n, user_clk) + --begin + --if (sys_reset_n = '0') then + --s_axis_cc_tkeep <=(OTHERS => '0'); + --elsif (user_clk'event and user_clk = '1') then + --if (s_axis_cc_tlast ='1') then + --if (trn_trem_n='1') then --missing signal on TRN interface. signal last dword of burst + --s_axis_cc_tkeep <= "01"; + --else + --s_axis_cc_tkeep <= "11"; + --end if; + --else + --s_axis_cc_tkeep <= "11"; + --end if; + --end if; + --end process; + --or try another trick, using end of frame: (async, so slow timing, but should work at 62MHz) + process ( sys_reset_n, user_clk, s_axis_cc_tlast, trn_teof_n) + begin + if (sys_reset_n = '0') then + s_axis_cc_tkeep <=(OTHERS => '0'); + else --elsif (user_clk'event and user_clk = '1') then + if (s_axis_cc_tlast ='1') then + if (trn_teof_n='0') then + s_axis_cc_tkeep <= "01"; + else + s_axis_cc_tkeep <= "11"; + end if; + else + s_axis_cc_tkeep <= "11"; + end if; + end if; + end process; + s_axis_cc_tlast <= not trn_teof_n; + s_axis_cc_tuser(3) <= not trn_tsrc_dsc_n; + s_axis_cc_tuser(2) <= not trn_tstr_n; + s_axis_cc_tuser(1) <= not trn_terrfwd_n; + s_axis_cc_tuser(0) <= '0'; + s_axis_cc_tvalid <= not trn_tsrc_rdy_n; + pcie_cq_np_req <= "00"; + cfg_mgmt_addr <= (OTHERS => '0'); + cfg_mgmt_function_number <= (OTHERS => '0'); + cfg_mgmt_write <= '0'; + cfg_mgmt_write_data <= (OTHERS => '0'); + cfg_mgmt_byte_enable <= (OTHERS => '0'); + cfg_mgmt_read <= '0'; + cfg_mgmt_debug_access <= '0'; + cfg_msg_transmit <= '0'; + cfg_msg_transmit_type <= (OTHERS => '0'); + cfg_msg_transmit_data <= (OTHERS => '0'); + cfg_fc_sel <= trn_fc_sel; + cfg_dsn_sub <= (OTHERS => '0'); --or cfg_dsn; + cfg_power_state_change_ack <= '0'; + cfg_err_cor_in <= '0'; + cfg_err_uncor_in <= '0'; + cfg_flr_done_sub <= (OTHERS => '0'); --or cfg_flr_done; + cfg_vf_flr_func_num <= (OTHERS => '0'); + cfg_vf_flr_done_sub <= (OTHERS => '0'); --or cfg_vf_flr_done; + cfg_link_training_enable <= '1'; + cfg_interrupt_int <= (OTHERS => '0'); + cfg_interrupt_pending <= (OTHERS => '0'); + cfg_interrupt_msi_select <= (OTHERS => '0'); + cfg_interrupt_msi_int <= (OTHERS => '0'); + cfg_interrupt_msi_pending_status <= (OTHERS => '0'); + cfg_interrupt_msi_pending_status_data_enable <= '0'; + cfg_interrupt_msi_pending_status_function_num <= (OTHERS => '0'); + cfg_interrupt_msi_attr <= (OTHERS => '0'); + cfg_interrupt_msi_tph_present <= '0'; + cfg_interrupt_msi_tph_type <= (OTHERS => '0'); + cfg_interrupt_msi_tph_st_tag <= (OTHERS => '0'); + cfg_interrupt_msi_function_number <= (OTHERS => '0'); + cfg_pm_aspm_l1_entry_reject <= '0'; + cfg_pm_aspm_tx_l0s_entry_disable <= '0'; + cfg_config_space_enable <= '1'; + cfg_req_pm_transition_l23_ready <= '0'; + cfg_hot_reset_in <= '0'; + cfg_ds_port_number <= (OTHERS => '0'); + cfg_ds_bus_number <= (OTHERS => '0'); + cfg_ds_device_number <= (OTHERS => '0'); + sys_clk_sub <= sys_clk; --the 100/125/250M reference clock + sys_clk_gt <= sys_clk2; + sys_reset <= not sys_reset_n; + gt_pcieuserratedone <= (OTHERS => '0'); + gt_loopback <= (OTHERS => '0'); + gt_txprbsforceerr <= (OTHERS => '0'); + gt_txinhibit <= (OTHERS => '0'); + gt_txprbssel <= (OTHERS => '0'); + gt_rxprbssel <= (OTHERS => '0'); + gt_rxprbscntreset <= (OTHERS => '0'); + gt_dmonfiforeset <= (OTHERS => '0'); + gt_dmonitorclk <= (OTHERS => '0'); + gt_txpmareset <= (OTHERS => '0'); + gt_rxpmareset <= (OTHERS => '0'); + gt_txpcsreset <= (OTHERS => '0'); + gt_rxpcsreset <= (OTHERS => '0'); + gt_rxbufreset <= (OTHERS => '0'); + gt_rxcdrreset <= (OTHERS => '0'); + gt_rxdfelpmreset <= (OTHERS => '0'); + + + + + + +--end file ---------------------------------------------------------------------- +end rtl; \ No newline at end of file Index: trunk/rtl/pcie_mini_axi4s_wb.vhd =================================================================== --- trunk/rtl/pcie_mini_axi4s_wb.vhd (nonexistent) +++ trunk/rtl/pcie_mini_axi4s_wb.vhd (revision 2) @@ -0,0 +1,1546 @@ +---------------------------------------------------------------------------------- +-- Project name: pcie_mini_axi4s_wb +-- PCI-express EP to Wishbone master bridge, with AXI4S internal connection to the hard-IP. +-- +-- This design is based on the pcie_mini project that was tested on Xilinx Spartan-6 +-- FPGAs. This new one only works on newer FPGAs that have PCIe-EP-IP with AXI4-STREAM +-- interface, instead of the old TRN interface. For example Kintex/Virtex-7, +-- Ultrascale and Ultrascale-plus. The user logic will be a Wishbone-bus based system. +-- It is called "mini" because it is few lines of code, nothing to do with mini-pci form factor. +-- +-- Engineer: Istvan Nagy, buenoshun@gmail.com +-- Contributors (to the original pcie_mini spartan-6): Stephen Battazzo, Scott Cogan +-- +-- Create Date: 05/30/2010 +-- Modify date: 08/10/2019 +-- Design Name: pcie_mini_axi4s_wb (entity name, top of pcie module) +-- Version: 1.0 +-- Tool versions: Vivado 2019.1 +-- +-- Target Devices: Xilinx Series-7/usc/usc+ FPGAs. This pcie_mini_axi4s_wb no longer works on +-- Spartan-6, due to header format change. For spartan-6 use the pcie_mini version 1.4. +-- The original 1.4 wrapper-less pcie_mini was tested on Spartan-6 LX45T FPGA devices. +-- +-- Project files: pcie_mini_axi4s_wb.vhd (top), pcie_axi4s2trn_wrapper.vhd, plus several +-- Vivado-generated files that are not included on opencores, the user has to re-generate them. +-- Either generate these IPs inside the top Vivado project, or copy the folders (with all files) over. +-- Dependencies (vivado generated sources): +-- 1. PCIE-EP-IP: +-- Generate a PCIe Endpoint block IP core in the IP Catalog (used to be called The CoreGenerator). +-- In IP catalog > Standard Bus Interfaces > PCI Express > Ultrascale+ PCI Express Integrated Block. +-- Param: Axi-freq=125 or 62MHz, refclk=100MHz, Additional transceiver c/s ports enabled, width=x1, +-- max payload=128bytes, set IDs, 1 mem BAR at 256MB size, BaseClass=bridge, Axisten if width = 64bit., +-- last tab all additional interfaces most enabled by default (except config intergface, but may need it). +-- Also copy the generic section of the "pcie" from the file: pcie4_uscale_plus_0_pcie4_uscale_core_top.v +-- into pcie_axi4s2trn_wrapper.vhd. +-- Generated files/folders: +-- ...\proj_name\proj_name.srcs\sources_1\ip\pcie4_uscale_plus_0 +-- 2. Block ram: +-- Generate a new blockram IP core in the IP Catalog (used to be called The CoreGenerator). +-- In IP catalog > Basic Elements > Memory Elements > Block Memory Generator. +-- Param: Dual port block memory, type=True_dualp, a-w=32, a-depth=512, b-w=64, b-depth=256, +-- Ena=always, common clock, +-- Generated files/folders: +-- ..\proj_name\proj_name.srcs\sources_1\ip\blk_mem_gen_0 +-- 3. Device and pinout. The clock buffer primitive below IBUFDS_GTE4 depends on the FPGA family. +-- The pin assignment: When generating the core, the IP catalog wizard assigns a GT site number, +-- likely Y225. Check that number, then look up the device/package combination in UG575, to see which +-- pins are in that region. Then find lane-0, MGT-clokc-0 pins and assign the RX/TX/CLK signals to +-- these pins on the "I/O Ports" view pin assignment. In case of XCU3-FFVA676: Y1,Y2,AA3,AA4,T5,T6. +-- +-- Description: +-- PCI-express endpoint block, transaction layer logic and back-end logic. The main +-- purpose of this file is to make a useable back-end interface and handle flow control +-- for the xilinx auto-generated PCIe endpoint IP. +-- The PCIe endpoint implements one 256MByte memory BAR (Base Address Register). +-- This 256MBytes size is set up in the core config, and also hardcoded in this +-- file (search for: "256MBytes"). +-- This 1 BAR is implemented as a Wishbone master interface with byte addressing, +-- where address [x:2] shows DWORD address, while sel[3:0] decodes the 2 LSBs. +-- ADDRESSES ARE BYTE ADDRESSES. +-- The lower address bits are usually zero, so the slave (MCB) has to select bytes based +-- on the byte select signals: sel[3:0]. The output address of the core contails the 2 +-- LSBs as well. The core was only tested with 32-bit accesses, byte-wide might work or not. +-- The TLP logic is capable of handling up to 1k bytes (256 DWORDs) payload data in a +-- single PCIe transaction, and can handle only one request at a time. If a new request +-- is arriving while processing the previous one (e.g. getting the data from a wishbone +-- read), then the state machine will not process it immediately, or it will hang. So +-- the user software has to wait for the previous read completion before issueing a new +-- request. The multiple DWORDs are handled separately by the WB statemachine. +-- Performance: WishBone bus: 62.5MHz, 32bit, 2clk/access -> 125MBytes/sec. The maximum +-- data throughput can be achieved when using the maximum data payload (block). +-- The core uses INTA wirtual wire to signal interrupts. +-- +-- x1 PCIe, legacy endpoint, uses a 100MHz ref clock. +-- Synthesis: Set the "FSM Encoding Algorithm" to "user". +-- +-- Changes from the pcie_mini Spartan-6 project: works with PCIE-EP-IP that has Axi-4-stream +-- interface instead of TRN interface, the spartan-6 32/32 blockrams replaced with ultrascale+ +-- 64/32 (width conversion) true-blockram buffers, the PCIe TLP decoding bit field +-- replaced with axi4s header bit field decoding. 1 new file added for wrapping the PCIe-EP. +-- Less than 32bit transfers are no longer supported, since Xilinx was so kind and replaced the +-- PCIe TLP with this Axi4S header (descriptor) that does not have byte enables encoded in it. +-- +-- Revision: +-- Revision 1.0 - pcie_mini v1.5 sources copied over and header decoding logic edited. +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + + + +entity pcie_mini_axi4s_wb is + generic ( + -- BAR0_WIDTH = 28 sets address space for 2^28 bytes = 256MB, BARO = x"F0000000" + -- BAR0_WIDTH = 22 sets address space for 2^22 bytes = 4MB, BARO = x"FFC00000" + BAR0 : bit_vector := x"FFC00000"; + BAR0_WIDTH : integer := 22 + ); + Port ( --FPGA PINS(EXTERNAL): + pci_exp_txp : out std_logic; + pci_exp_txn : out std_logic; + pci_exp_rxp : in std_logic; + pci_exp_rxn : in std_logic; + sys_clk_n : in std_logic; + sys_clk_p : in std_logic; + sys_reset_n : in std_logic; + --ON CHIP PORTS: + --DATA BUS for BAR0 (wishbone): + pcie_bar0_wb_data_o : out std_logic_vector(31 downto 0); + pcie_bar0_wb_data_i : in std_logic_vector(31 downto 0); + pcie_bar0_wb_addr_o : out std_logic_vector(27 downto 0); + pcie_bar0_wb_cyc_o : out std_logic; + pcie_bar0_wb_stb_o : out std_logic; + pcie_bar0_wb_wr_o : out std_logic; + pcie_bar0_wb_ack_i : in std_logic; + pcie_bar0_wb_clk_o : out std_logic; --62.5MHz + pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0); + --OTHER: + pcie_irq : in std_logic; + pcie_msi_enabled : out std_logic; -- added to monitor if MSI interrupt is enabled + pcie_resetout : out std_logic --active high + ); +end pcie_mini_axi4s_wb; + + + + +architecture Behavioral of pcie_mini_axi4s_wb is + + + + + -- Internal Signals ------------------------------------------------------------ + --SIGNAL dummy : std_logic_vector(15 downto 0); --write data bus + SIGNAL cfg_do : std_logic_vector(31 downto 0); + SIGNAL cfg_rd_wr_done_n : std_logic; + SIGNAL cfg_dwaddr : std_logic_vector(9 downto 0); + SIGNAL cfg_rd_en_n : std_logic; + SIGNAL cfg_err_ur_n : std_logic; + SIGNAL cfg_err_cor_n : std_logic; + SIGNAL cfg_err_ecrc_n : std_logic; + SIGNAL cfg_err_cpl_timeout_n : std_logic; + SIGNAL cfg_err_cpl_abort_n : std_logic; + SIGNAL cfg_err_posted_n : std_logic; + SIGNAL cfg_err_locked_n : std_logic; + SIGNAL cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0); + SIGNAL cfg_err_cpl_rdy_n : std_logic; + SIGNAL cfg_interrupt_n : std_logic; + SIGNAL cfg_interrupt_rdy_n : std_logic; + SIGNAL cfg_interrupt_assert_n : std_logic; + SIGNAL cfg_interrupt_do : std_logic_vector(7 downto 0); + SIGNAL cfg_interrupt_di : std_logic_vector(7 downto 0); + SIGNAL cfg_interrupt_mmenable : std_logic_vector(2 downto 0); + SIGNAL cfg_interrupt_msienable : std_logic; + SIGNAL cfg_turnoff_ok_n : std_logic; + SIGNAL cfg_to_turnoff_n : std_logic; + SIGNAL cfg_pm_wake_n : std_logic; + SIGNAL cfg_pcie_link_state_n : std_logic_vector(2 downto 0); + SIGNAL cfg_trn_pending_n : std_logic; + SIGNAL cfg_dsn : std_logic_vector(63 downto 0); + SIGNAL cfg_bus_number : std_logic_vector(7 downto 0); + SIGNAL cfg_device_number : std_logic_vector(4 downto 0); + SIGNAL cfg_function_number : std_logic_vector(2 downto 0); + SIGNAL cfg_status : std_logic_vector(15 downto 0); + SIGNAL cfg_command : std_logic_vector(15 downto 0); + SIGNAL cfg_dstatus : std_logic_vector(15 downto 0); + SIGNAL cfg_dcommand : std_logic_vector(15 downto 0); + SIGNAL cfg_lstatus : std_logic_vector(15 downto 0); + SIGNAL cfg_lcommand : std_logic_vector(15 downto 0); + -- System Interface + SIGNAL sys_clk : std_logic; + SIGNAL trn_clk : std_logic; + SIGNAL trn_reset_n : std_logic; + SIGNAL received_hot_reset : std_logic; + -- Transaction (TRN) Interface + SIGNAL trn_lnk_up_n : std_logic; + -- data interface Tx + SIGNAL trn_td : std_logic_vector(63 downto 0); + SIGNAL trn_tsof_n : std_logic; + SIGNAL trn_teof_n : std_logic; + SIGNAL trn_tsrc_rdy_n : std_logic; + SIGNAL trn_tdst_rdy_n : std_logic; + SIGNAL trn_terr_drop_n : std_logic; + SIGNAL trn_tsrc_dsc_n : std_logic; + SIGNAL trn_terrfwd_n : std_logic; + SIGNAL trn_tbuf_av : std_logic_vector(5 downto 0); + SIGNAL trn_tstr_n : std_logic; + SIGNAL trn_tcfg_req_n : std_logic; + SIGNAL trn_tcfg_gnt_n : std_logic; + -- data interface Rx + SIGNAL trn_rd : std_logic_vector(63 downto 0); + SIGNAL trn_rsof_n : std_logic; + SIGNAL trn_reof_n : std_logic; + SIGNAL trn_rsrc_rdy_n : std_logic; + SIGNAL trn_rsrc_dsc_n : std_logic; + SIGNAL trn_rdst_rdy_n : std_logic; + SIGNAL trn_rerrfwd_n : std_logic; + SIGNAL trn_rnp_ok_n : std_logic; + SIGNAL trn_rbar_hit_n : std_logic_vector(6 downto 0); + -- flow control + SIGNAL trn_fc_sel : std_logic_vector(2 downto 0); + SIGNAL trn_fc_nph : std_logic_vector(7 downto 0); + SIGNAL trn_fc_npd : std_logic_vector(11 downto 0); + SIGNAL trn_fc_ph : std_logic_vector(7 downto 0); + SIGNAL trn_fc_pd : std_logic_vector(11 downto 0); + SIGNAL trn_fc_cplh : std_logic_vector(7 downto 0); + SIGNAL trn_fc_cpld : std_logic_vector(11 downto 0); + + SIGNAL start_read_wb0 : std_logic; + SIGNAL start_write_wb0 : std_logic; + SIGNAL wb_transaction_complete : std_logic; + SIGNAL pcie_bar0_wb_data_i_latched : std_logic_vector(31 downto 0); + SIGNAL pcie_bar0_wb_data_o_feed : std_logic_vector(31 downto 0); + SIGNAL pcie_bar0_wb_addr_o_feed : std_logic_vector(27 downto 0); + SIGNAL pcie_bar0_wb_sel_o_feed : std_logic_vector(3 downto 0); + SIGNAL start_read_wb1 : std_logic; + SIGNAL start_write_wb1 : std_logic; + SIGNAL rd_data_ready_wb1 : std_logic; + + SIGNAL pcie_just_received_a_new_tlp : std_logic ; + SIGNAL pcie_start_reading_rx_tlp : std_logic ; + SIGNAL pcie_there_is_a_new_tlp_to_transmit : std_logic ; + SIGNAL rxtlp_decodedaddress : std_logic_vector(31 downto 0); + SIGNAL tlp_payloadsize_dwords : std_logic_vector(7 downto 0); + SIGNAL rxtlp_firstdw_be : std_logic_vector(3 downto 0); + SIGNAL rxtlp_lastdw_be : std_logic_vector(3 downto 0); + SIGNAL rxtlp_requesterid : std_logic_vector(15 downto 0); + SIGNAL tlp_state : std_logic_vector(7 downto 0); + SIGNAL tlp_state_copy : std_logic_vector(7 downto 0); + SIGNAL rxtlp_data_0 : std_logic_vector(31 downto 0); + SIGNAL rxtlp_data_1 : std_logic_vector(31 downto 0); + SIGNAL rxtlp_data_2 : std_logic_vector(31 downto 0); + SIGNAL rxtlp_data_3 : std_logic_vector(31 downto 0); + SIGNAL rxtlp_data_4 : std_logic_vector(31 downto 0); + SIGNAL rxtlp_data_5 : std_logic_vector(31 downto 0); + SIGNAL rxtlp_data_6 : std_logic_vector(31 downto 0); + SIGNAL rxtlp_data_7 : std_logic_vector(31 downto 0); + SIGNAL txtlp_data_0 : std_logic_vector(31 downto 0); + SIGNAL txtlp_data_1 : std_logic_vector(31 downto 0); + SIGNAL txtlp_data_2 : std_logic_vector(31 downto 0); + SIGNAL txtlp_data_3 : std_logic_vector(31 downto 0); + SIGNAL txtlp_data_4 : std_logic_vector(31 downto 0); + SIGNAL txtlp_data_5 : std_logic_vector(31 downto 0); + SIGNAL txtlp_data_6 : std_logic_vector(31 downto 0); + SIGNAL txtlp_data_7 : std_logic_vector(31 downto 0); + SIGNAL pcie_tlp_tx_complete : std_logic; + + --this signal added by StBa, AAC Microtec + SIGNAL irq_prohibit : std_logic; + + SIGNAL pcieirq_state : std_logic_vector(2 downto 0); + SIGNAL txtrn_counter : std_logic_vector(7 downto 0); + SIGNAL trn_rx_counter : std_logic_vector(7 downto 0); + SIGNAL cfg_completer_id : std_logic_vector(15 downto 0); + SIGNAL wb0_state : std_logic_vector(7 downto 0); + SIGNAL epif_tx_state : std_logic_vector(7 downto 0); + SIGNAL epif_rx_state : std_logic_vector(7 downto 0); + SIGNAL bit10 : std_logic_vector(1 downto 0); + + SIGNAL bram_rxtlp_we : std_logic_vector(0 downto 0); + SIGNAL bram_rxtlp_writeaddress : std_logic_vector(31 downto 0); + SIGNAL bram_rxtlp_writedata : std_logic_vector(63 downto 0); + SIGNAL bram_rxtlp_readaddress : std_logic_vector(31 downto 0); + SIGNAL bram_rxtlp_readdata : std_logic_vector(31 downto 0); + SIGNAL bram_txtlp_we : std_logic_vector(0 downto 0); + SIGNAL bram_txtlp_writeaddress : std_logic_vector(8 downto 0); + SIGNAL bram_txtlp_writedata : std_logic_vector(31 downto 0); + SIGNAL bram_txtlp_readaddress : std_logic_vector(31 downto 0); + SIGNAL bram_txtlp_readdata : std_logic_vector(63 downto 0); + + SIGNAL tlp_datacount : std_logic_vector(7 downto 0); + --SIGNAL bram_rxtlp_firstdata_address : std_logic_vector(8 downto 0); + SIGNAL rxtlp_header_dw0 : std_logic_vector(31 downto 0); + SIGNAL rxtlp_header_dw1 : std_logic_vector(31 downto 0); + SIGNAL rxtlp_header_dw2 : std_logic_vector(31 downto 0); + SIGNAL rxtlp_header_dw3 : std_logic_vector(31 downto 0); + SIGNAL flag1 : std_logic; + SIGNAL rxdw1_23_0 : std_logic_vector(23 downto 0); + SIGNAL pcie_rxtlp_tag : std_logic_vector(7 downto 0); + SIGNAL rxtlp_attr_tc : std_logic_vector(5 downto 0); + SIGNAL rxtlp_at : std_logic_vector(1 downto 0); + SIGNAL pciewb_localreset_n : std_logic; + SIGNAL cfg_interrupt_assert_n_1 : std_logic; + SIGNAL trn_tsrc_rdy_n_1 : std_logic; + SIGNAL trn_tsof_n1 : std_logic; + SIGNAL rcompl_bytecount_field : std_logic_vector(9 downto 0); + SIGNAL rxstm_readytoroll : std_logic; + SIGNAL tlpstm_isin_idle : std_logic; + + SIGNAL dummy_dina_bram : std_logic_vector(31 downto 0); + SIGNAL dummy_doutb_bram : std_logic_vector(63 downto 0); + SIGNAL dummy_douta_bram : std_logic_vector(31 downto 0); + SIGNAL dummy_dinb_bram : std_logic_vector(63 downto 0); + SIGNAL sys_clk2 : std_logic; + + + + -- COMPONENT DECLARATIONS (introducing the IPs) -------------------------------- + + --this is the pcie endpoint core from coregenerator. + --Core name: Xilinx Spartan-6 Integrated + --Block for PCI Express + --Version: 1.2 + --Release Date: September 16, 2009. ISE DS 11.4 + component pcie is + generic ( + TL_TX_RAM_RADDR_LATENCY : integer := 0; + TL_TX_RAM_RDATA_LATENCY : integer := 2; + TL_RX_RAM_RADDR_LATENCY : integer := 0; + TL_RX_RAM_RDATA_LATENCY : integer := 2; + TL_RX_RAM_WRITE_LATENCY : integer := 0; + VC0_TX_LASTPACKET : integer := 14; + VC0_RX_RAM_LIMIT : bit_vector := x"7FF"; + VC0_TOTAL_CREDITS_PH : integer := 32; + VC0_TOTAL_CREDITS_PD : integer := 211; + VC0_TOTAL_CREDITS_NPH : integer := 8; + VC0_TOTAL_CREDITS_CH : integer := 40; + VC0_TOTAL_CREDITS_CD : integer := 211; + VC0_CPL_INFINITE : boolean := TRUE; + BAR0 : bit_vector := BAR0; --x"F0000000"; + BAR1 : bit_vector := x"00000000"; + BAR2 : bit_vector := x"00000000"; + BAR3 : bit_vector := x"00000000"; + BAR4 : bit_vector := x"00000000"; + BAR5 : bit_vector := x"00000000"; + EXPANSION_ROM : bit_vector := "0000000000000000000000"; + DISABLE_BAR_FILTERING : boolean := FALSE; + DISABLE_ID_CHECK : boolean := FALSE; + TL_TFC_DISABLE : boolean := FALSE; + TL_TX_CHECKS_DISABLE : boolean := FALSE; + USR_CFG : boolean := FALSE; + USR_EXT_CFG : boolean := FALSE; + DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2; + CLASS_CODE : bit_vector := x"068000"; + CARDBUS_CIS_POINTER : bit_vector := x"00000000"; + PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1"; + PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"1"; + PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE; + PCIE_CAP_INT_MSG_NUM : bit_vector := "00000"; + DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0; + DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE; + DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7; + DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7; + SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE; + SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE; + SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE; + DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE; + LINK_CAP_ASPM_SUPPORT : integer := 1; + --LINK_CAP_L0S_EXIT_LATENCY : integer := 7; + --LINK_CAP_L1_EXIT_LATENCY : integer := 7; + LL_ACK_TIMEOUT : bit_vector := x"0000"; + LL_ACK_TIMEOUT_EN : boolean := FALSE; + --LL_REPLAY_TIMEOUT : bit_vector := x"0204"; + LL_REPLAY_TIMEOUT : bit_vector := x"0000"; + LL_REPLAY_TIMEOUT_EN : boolean := FALSE; + MSI_CAP_MULTIMSGCAP : integer := 0; + MSI_CAP_MULTIMSG_EXTENSION : integer := 0; + LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE; + PLM_AUTO_CONFIG : boolean := FALSE; + FAST_TRAIN : boolean := FALSE; + ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE; + DISABLE_SCRAMBLING : boolean := FALSE; + PM_CAP_VERSION : integer := 3; + PM_CAP_PME_CLOCK : boolean := FALSE; + PM_CAP_DSI : boolean := FALSE; + PM_CAP_AUXCURRENT : integer := 0; + PM_CAP_D1SUPPORT : boolean := TRUE; + PM_CAP_D2SUPPORT : boolean := TRUE; + PM_CAP_PMESUPPORT : bit_vector := x"0F"; + PM_DATA0 : bit_vector := x"04"; + PM_DATA_SCALE0 : bit_vector := x"0"; + PM_DATA1 : bit_vector := x"00"; + PM_DATA_SCALE1 : bit_vector := x"0"; + PM_DATA2 : bit_vector := x"00"; + PM_DATA_SCALE2 : bit_vector := x"0"; + PM_DATA3 : bit_vector := x"00"; + PM_DATA_SCALE3 : bit_vector := x"0"; + PM_DATA4 : bit_vector := x"04"; + PM_DATA_SCALE4 : bit_vector := x"0"; + PM_DATA5 : bit_vector := x"00"; + PM_DATA_SCALE5 : bit_vector := x"0"; + PM_DATA6 : bit_vector := x"00"; + PM_DATA_SCALE6 : bit_vector := x"0"; + PM_DATA7 : bit_vector := x"00"; + PM_DATA_SCALE7 : bit_vector := x"0"; + PCIE_GENERIC : bit_vector := "000011101111"; + GTP_SEL : integer := 0; + CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE"; + CFG_DEV_ID : std_logic_vector(15 downto 0) := x"BADD"; + CFG_REV_ID : std_logic_vector(7 downto 0) := x"00"; + CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE"; + CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234"; + REF_CLK_FREQ : integer := 0 + ); + port ( + -- PCI Express Fabric Interface + pci_exp_txp : out std_logic; + pci_exp_txn : out std_logic; + pci_exp_rxp : in std_logic; + pci_exp_rxn : in std_logic; + + -- Transaction (TRN) Interface + trn_lnk_up_n : out std_logic; + + -- Tx + trn_td : in std_logic_vector(63 downto 0); + trn_tsof_n : in std_logic; + trn_teof_n : in std_logic; + trn_tsrc_rdy_n : in std_logic; + trn_tdst_rdy_n : out std_logic; + trn_terr_drop_n : out std_logic; + trn_tsrc_dsc_n : in std_logic; + trn_terrfwd_n : in std_logic; + trn_tbuf_av : out std_logic_vector(5 downto 0); + trn_tstr_n : in std_logic; + trn_tcfg_req_n : out std_logic; + trn_tcfg_gnt_n : in std_logic; + + -- Rx + trn_rd : out std_logic_vector(63 downto 0); + trn_rsof_n : out std_logic; + trn_reof_n : out std_logic; + trn_rsrc_rdy_n : out std_logic; + trn_rsrc_dsc_n : out std_logic; + trn_rdst_rdy_n : in std_logic; + trn_rerrfwd_n : out std_logic; + trn_rnp_ok_n : in std_logic; + trn_rbar_hit_n : out std_logic_vector(6 downto 0); + trn_fc_sel : in std_logic_vector(2 downto 0); + trn_fc_nph : out std_logic_vector(7 downto 0); + trn_fc_npd : out std_logic_vector(11 downto 0); + trn_fc_ph : out std_logic_vector(7 downto 0); + trn_fc_pd : out std_logic_vector(11 downto 0); + trn_fc_cplh : out std_logic_vector(7 downto 0); + trn_fc_cpld : out std_logic_vector(11 downto 0); + + -- Host (CFG) Interface + cfg_do : out std_logic_vector(31 downto 0); + cfg_rd_wr_done_n : out std_logic; + cfg_dwaddr : in std_logic_vector(9 downto 0); + cfg_rd_en_n : in std_logic; + cfg_err_ur_n : in std_logic; + cfg_err_cor_n : in std_logic; + cfg_err_ecrc_n : in std_logic; + cfg_err_cpl_timeout_n : in std_logic; + cfg_err_cpl_abort_n : in std_logic; + cfg_err_posted_n : in std_logic; + cfg_err_locked_n : in std_logic; + cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0); + cfg_err_cpl_rdy_n : out std_logic; + cfg_interrupt_n : in std_logic; + cfg_interrupt_rdy_n : out std_logic; + cfg_interrupt_assert_n : in std_logic; + cfg_interrupt_do : out std_logic_vector(7 downto 0); + cfg_interrupt_di : in std_logic_vector(7 downto 0); + cfg_interrupt_mmenable : out std_logic_vector(2 downto 0); + cfg_interrupt_msienable : out std_logic; + cfg_turnoff_ok_n : in std_logic; + cfg_to_turnoff_n : out std_logic; + cfg_pm_wake_n : in std_logic; + cfg_pcie_link_state_n : out std_logic_vector(2 downto 0); + cfg_trn_pending_n : in std_logic; + cfg_dsn : in std_logic_vector(63 downto 0); + cfg_bus_number : out std_logic_vector(7 downto 0); + cfg_device_number : out std_logic_vector(4 downto 0); + cfg_function_number : out std_logic_vector(2 downto 0); + cfg_status : out std_logic_vector(15 downto 0); + cfg_command : out std_logic_vector(15 downto 0); + cfg_dstatus : out std_logic_vector(15 downto 0); + cfg_dcommand : out std_logic_vector(15 downto 0); + cfg_lstatus : out std_logic_vector(15 downto 0); + cfg_lcommand : out std_logic_vector(15 downto 0); + + -- System Interface + sys_clk : in std_logic; + sys_clk2 : in std_logic; + sys_reset_n : in std_logic; + trn_clk : out std_logic; + trn_reset_n : out std_logic; + received_hot_reset : out std_logic + ); + end component pcie; + + + +COMPONENT blk_mem_gen_0 + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + clkb : IN STD_LOGIC; + web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; + + + +---- ------- SYNTHESIS ATTRIBUTES: -------------------------------------------------- +--attribute keep_hierarchy : string; +--attribute keep_hierarchy of pcie_mini_axi4s_wb: entity is "yes"; +attribute keep : string; +attribute keep of cfg_dstatus : signal is "true"; +attribute keep of tlp_state : signal is "true"; + + +-- --------ARCHITECTURE BODY BEGINS ----------------------------------------------- +begin + + +cfg_turnoff_ok_n <= '1'; + + -- COMPONENT INSTALLATIONS (connecting the IPs to local signals) --------------- + + + -- COMPONENT INSTALLATIONS (connecting the IPs to local signals) --------------- + + inst_pcie : pcie + port map ( + pci_exp_txp => pci_exp_txp, + pci_exp_txn => pci_exp_txn, + pci_exp_rxp => pci_exp_rxp, + pci_exp_rxn => pci_exp_rxn, + trn_lnk_up_n => trn_lnk_up_n, + trn_td => trn_td, -- Bus [63 : 0] + trn_tsof_n => trn_tsof_n, + trn_teof_n => trn_teof_n, + trn_tsrc_rdy_n => trn_tsrc_rdy_n, + trn_tdst_rdy_n => trn_tdst_rdy_n, + trn_terr_drop_n => trn_terr_drop_n, + trn_tsrc_dsc_n => trn_tsrc_dsc_n, + trn_terrfwd_n => trn_terrfwd_n, + trn_tbuf_av => trn_tbuf_av, -- Bus [31 : 0] + trn_tstr_n => trn_tstr_n, + trn_tcfg_req_n => trn_tcfg_req_n, + trn_tcfg_gnt_n => trn_tcfg_gnt_n, + trn_rd => trn_rd, -- Bus [63 : 0] + trn_rsof_n => trn_rsof_n, + trn_reof_n => trn_reof_n, + trn_rsrc_rdy_n => trn_rsrc_rdy_n, + trn_rsrc_dsc_n => trn_rsrc_dsc_n, + trn_rdst_rdy_n => trn_rdst_rdy_n, + trn_rerrfwd_n => trn_rerrfwd_n, + trn_rnp_ok_n => trn_rnp_ok_n, + trn_rbar_hit_n => trn_rbar_hit_n, -- Bus [31 : 0] + trn_fc_sel => trn_fc_sel, -- Bus [31 : 0] + trn_fc_nph => trn_fc_nph, -- Bus [31 : 0] + trn_fc_npd => trn_fc_npd, -- Bus [31 : 0] + trn_fc_ph => trn_fc_ph, -- Bus [31 : 0] + trn_fc_pd => trn_fc_pd, -- Bus [31 : 0] + trn_fc_cplh => trn_fc_cplh, -- Bus [31 : 0] + trn_fc_cpld => trn_fc_cpld, -- Bus [31 : 0] + cfg_do => cfg_do, -- Bus [31 : 0] + cfg_rd_wr_done_n => cfg_rd_wr_done_n, + cfg_dwaddr => cfg_dwaddr, -- Bus [31 : 0] + cfg_rd_en_n => cfg_rd_en_n, + cfg_err_ur_n => cfg_err_ur_n, + cfg_err_cor_n => cfg_err_cor_n, + cfg_err_ecrc_n => cfg_err_ecrc_n, + cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n, + cfg_err_cpl_abort_n => cfg_err_cpl_abort_n, + cfg_err_posted_n => cfg_err_posted_n, + cfg_err_locked_n => cfg_err_locked_n, + cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header, -- Bus [31 : 0] + cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n, + cfg_interrupt_n => cfg_interrupt_n, + cfg_interrupt_rdy_n => cfg_interrupt_rdy_n, + cfg_interrupt_assert_n => cfg_interrupt_assert_n, + cfg_interrupt_do => cfg_interrupt_do, -- Bus [31 : 0] + cfg_interrupt_di => cfg_interrupt_di, -- Bus [31 : 0] + cfg_interrupt_mmenable => cfg_interrupt_mmenable, -- Bus [31 : 0] + cfg_interrupt_msienable => cfg_interrupt_msienable, + cfg_turnoff_ok_n => cfg_turnoff_ok_n, + cfg_to_turnoff_n => cfg_to_turnoff_n, + cfg_pm_wake_n => cfg_pm_wake_n, + cfg_pcie_link_state_n => cfg_pcie_link_state_n, -- Bus [2 : 0] + cfg_trn_pending_n => cfg_trn_pending_n, + cfg_dsn => cfg_dsn, -- Bus [31 : 0] + cfg_bus_number => cfg_bus_number, -- Bus [31 : 0] + cfg_device_number => cfg_device_number, -- Bus [31 : 0] + cfg_function_number => cfg_function_number, -- Bus [31 : 0] + cfg_status => cfg_status, -- Bus [31 : 0] + cfg_command => cfg_command, -- Bus [31 : 0] + cfg_dstatus => cfg_dstatus, -- Bus [31 : 0] + cfg_dcommand => cfg_dcommand, -- Bus [31 : 0] + cfg_lstatus => cfg_lstatus, -- Bus [31 : 0] + cfg_lcommand => cfg_lcommand, -- Bus [31 : 0] + sys_clk => sys_clk, + sys_clk2 => sys_clk2, + sys_reset_n => sys_reset_n, + trn_clk => trn_clk, + trn_reset_n => trn_reset_n, + received_hot_reset => received_hot_reset + ); + + + +--block ram for RX TLP: +Inst_bram_rxtlp: blk_mem_gen_0 + PORT MAP ( + -- 32bit user side port: + clka => trn_clk, + wea => "0", + addra => bram_rxtlp_readaddress(8 downto 0), + dina => dummy_dina_bram, + douta => bram_rxtlp_readdata, + -- 64bit PCIe side port: + clkb => trn_clk, + web => bram_rxtlp_we, + addrb => bram_rxtlp_writeaddress(7 downto 0), + dinb => bram_rxtlp_writedata, + doutb => dummy_doutb_bram + ); + +--block ram for TX TLP: +Inst_bram_txtlp: blk_mem_gen_0 + PORT MAP ( + -- 32bit user side port: + clka => trn_clk, + wea => bram_txtlp_we, + addra => bram_txtlp_writeaddress(8 downto 0), + dina => bram_txtlp_writedata, + douta => dummy_douta_bram, + -- 64bit PCIe side port: + clkb => trn_clk, + web => "0", + addrb => bram_txtlp_readaddress(7 downto 0), + dinb => dummy_dinb_bram, + doutb => bram_txtlp_readdata + ); + + + + -- MAIN LOGIC: --------------------------------------------------------------------------------------------- + +dummy_dina_bram <= (OTHERS => '0'); +dummy_dinb_bram <= (OTHERS => '0'); + + --System Signals:-------------------------------- + + --Clock Input Buffer for differential system clock + --IBUFDS_GTE3/4 is the gigabit transceiver input pad buffer component. The REFCLK signal should be routed to the dedicated referenceclock input pins + --on the serial transceiver, and the user design should instantiate the IBUFDS_GTE3 primitive in the user design. + IBUFDS_inst : IBUFDS_GTE4 --IBUFDS_GTE3 for Ultrascale (use ODIV2), GTE4 for ultrascale+ (use ODIV2), GTE2 for Virtex7 (swap O with ODIV2) + generic map ( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00") + port map ( + O => sys_clk2, -- Buffer output 1 (use on Virtex 7 only) + I => sys_clk_p, -- Diff_p buffer input (connect directly to top-level port) + CEB => '0', + ODIV2 => sys_clk, --Buffer output 2 (use on ultrascale/+) + IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port) + ); + + --wishbone clock output: + pcie_bar0_wb_clk_o <= trn_clk; + --pcie_bar1_wb_clk_o <= trn_clk; + + + --use one of these for resetting logic in this file: + pciewb_localreset_n <= sys_reset_n; --dont wait for the PCIE-EP to finish its init. + --pciewb_localreset_n <= trn_reset_n; + --pciewb_localreset_n <= trn_reset_n and (not trn_lnk_up_n) and (not received_hot_reset); + --reset to the core: + --sys_reset_n comes from toplevel directly to the core. same name + --reset output to other cores: + pcie_resetout <= not pciewb_localreset_n; + + --trn_lnk_up_n --not used. + + + --pcie ep ip config port: ---------------------------------------------------------- + + --trn_fc_sel <= "000"; + + trn_rnp_ok_n <= '0'; + --trn_terrfwd_n <= '1'; + + --trn_tcfg_gnt_n <= '0'; + + cfg_err_cor_n <= '1'; + cfg_err_ur_n <= '1'; + cfg_err_ecrc_n <= '1'; + cfg_err_cpl_timeout_n <= '1'; + cfg_err_cpl_abort_n <= '1'; + cfg_err_posted_n <= '0'; + cfg_err_locked_n <= '1'; + cfg_pm_wake_n <= '1'; + cfg_trn_pending_n <= '1'; + + --trn_tstr_n <= '0'; + --cfg_interrupt_assert_n <= '1'; --used in a process at the bottom of this file + --cfg_interrupt_n <= '1'; + --cfg_interrupt_di <= x"00"; --intA used + + cfg_err_tlp_cpl_header <= (OTHERS => '0'); + cfg_dwaddr <= (OTHERS => '0'); + cfg_rd_en_n <= '1'; + --serial number: + cfg_dsn <= (OTHERS => '0'); + + -- AT THE BOTTOM OF THIS FILE: + -- --some fix values: + -- trn_tsrc_dsc_n <= '1'; --no errors on trn bus + -- trn_tstr_n <= '0'; --pipelining (0= link may begin before the entire packet has been written) + -- trn_tcfg_gnt_n <= '0'; --no tlp priorities + -- trn_terrfwd_n <= '1'; --no errors on trn + -- --nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n + + + + --use this in read completion packets: + cfg_completer_id <= cfg_bus_number & cfg_device_number & cfg_function_number; + + + + + + + -- WISBONE BACK-end INTERFACE ---------------------------------------------------- + + --main state machine: set states, capture inputs, set addr/data outputs + --minimum 2 clock cycles / transaction. writes are posted, reads have wait states. + process (pciewb_localreset_n, trn_clk, wb0_state, start_read_wb0, start_write_wb0, + pcie_bar0_wb_addr_o_feed, pcie_bar0_wb_data_o_feed, pcie_bar0_wb_sel_o_feed) + begin + if (pciewb_localreset_n='0') then + wb0_state <= "00000000"; + wb_transaction_complete <= '0'; + pcie_bar0_wb_addr_o <= "0000000000000000000000000000"; + pcie_bar0_wb_sel_o <= "0000"; + pcie_bar0_wb_data_o <= "00000000000000000000000000000000"; + wb_transaction_complete <='0'; + else + if (trn_clk'event and trn_clk = '1') then + case ( wb0_state ) is + + --********** IDLE STATE ********** + when "00000000" => --state 0 + wb_transaction_complete <='0'; + pcie_bar0_wb_sel_o <= pcie_bar0_wb_sel_o_feed; + pcie_bar0_wb_addr_o <= pcie_bar0_wb_addr_o_feed; + if (start_read_wb0 ='1') then --go to read + wb0_state <= "00000001"; + elsif (start_write_wb0 ='1') then --go to write + wb0_state <= "00000010"; + --no endian swap: pcie_bar0_wb_data_o <= pcie_bar0_wb_data_o_feed; + pcie_bar0_wb_data_o (7 downto 0) <= pcie_bar0_wb_data_o_feed(31 downto 24); --swap endianism + pcie_bar0_wb_data_o (15 downto 8) <= pcie_bar0_wb_data_o_feed(23 downto 16); --swap endianism + pcie_bar0_wb_data_o (23 downto 16) <= pcie_bar0_wb_data_o_feed(15 downto 8); --swap endianism + pcie_bar0_wb_data_o (31 downto 24) <= pcie_bar0_wb_data_o_feed(7 downto 0); --swap endianism + end if; + + --********** READ STATE ********** + --set the outputs, + --if ACK asserted, sample the data input + --The hold requirements are oversatisfyed by going back to idle, and by the fact that the slave uses the cyc/stb/wr strobes synchronously. + when "00000001" => --state 1 + if (pcie_bar0_wb_ack_i='1') then + --no endian swap: pcie_bar0_wb_data_i_latched <= pcie_bar0_wb_data_i; --sample the incoming data + pcie_bar0_wb_data_i_latched (7 downto 0) <= pcie_bar0_wb_data_i(31 downto 24); --swap endianism + pcie_bar0_wb_data_i_latched (15 downto 8) <= pcie_bar0_wb_data_i(23 downto 16); --swap endianism + pcie_bar0_wb_data_i_latched (23 downto 16) <= pcie_bar0_wb_data_i(15 downto 8); --swap endianism + pcie_bar0_wb_data_i_latched (31 downto 24) <= pcie_bar0_wb_data_i(7 downto 0); --swap endianism + wb_transaction_complete <='1'; --signalling ready, but only for one clock cycle + wb0_state <= "00000000"; --go to state 0 + else + wb_transaction_complete <='0'; + end if; + + --********** WRITE STATE ********** + --if ACK asserted, go back to idle + --The hold requirements are oversatisfyed by waiting for ACK to remove write data + when "00000010" => --state 2 + if (pcie_bar0_wb_ack_i='1') then + wb0_state <= "00000000"; --go to state 0 + wb_transaction_complete <='1'; + else + wb_transaction_complete <='0'; + end if; + + when others => --error + wb0_state <= "00000000"; --go to state 0 + end case; + end if; + end if; + end process; + --sync control on wb-control signals: + process (pciewb_localreset_n, wb0_state) + begin + if (pciewb_localreset_n='0') then + pcie_bar0_wb_cyc_o <= '0'; + pcie_bar0_wb_stb_o <= '0'; + pcie_bar0_wb_wr_o <= '0'; + else + if (wb0_state = "00000000") then --idle + pcie_bar0_wb_cyc_o <= '0'; + pcie_bar0_wb_stb_o <= '0'; + pcie_bar0_wb_wr_o <= '0'; + elsif (wb0_state = "00000001") then --read + pcie_bar0_wb_cyc_o <= '1'; + pcie_bar0_wb_stb_o <= '1'; + pcie_bar0_wb_wr_o <= '0'; + elsif (wb0_state = "00000010") then --write + pcie_bar0_wb_cyc_o <= '1'; + pcie_bar0_wb_stb_o <= '1'; + pcie_bar0_wb_wr_o <= '1'; + else + pcie_bar0_wb_cyc_o <= '0'; + pcie_bar0_wb_stb_o <= '0'; + pcie_bar0_wb_wr_o <= '0'; + end if; + end if; + end process; + + + + + + + + + -- INTERFACE TO THE PCIE-EP IP -------------------------------------------------------- + --trn_clk and trn_reset_n are the same as the pcie_resetout and pcie_bar0_wb_clk_o, + --so it is not a clock domain crossing. + + + -- TX: INTERFACE TO THE PCIE-EP: TRANSMIT TLP PACKETS:----- + --Read completion is 3DW header. This core only transmits read completion or Unbsupported request packets. + process (pciewb_localreset_n, trn_clk, epif_tx_state, bram_txtlp_readdata , bram_txtlp_readaddress, + pcie_there_is_a_new_tlp_to_transmit, tlp_payloadsize_dwords, txtrn_counter) + begin + if (pciewb_localreset_n='0') then + epif_tx_state <= "00000000"; + trn_tsrc_rdy_n_1 <='1'; + trn_tsof_n1 <= '1'; + trn_teof_n <= '1'; + trn_td <= (OTHERS => '0'); + pcie_tlp_tx_complete <= '0'; + txtrn_counter <= "00000001"; + bram_txtlp_readaddress <= (OTHERS => '0'); + else + if (trn_clk'event and trn_clk = '1') then + case ( epif_tx_state ) is + + --********** idle STATE ********** + when "00000000" => --state 0 + --if there is a new TLP assembled and the EP is ready, + --start the tx-trn bus transaction. + if (pcie_there_is_a_new_tlp_to_transmit='1') then + epif_tx_state <= "00000001"; --next state + end if; + trn_tsrc_rdy_n_1 <='1'; + trn_tsof_n1 <= '1'; + trn_teof_n <= '1'; + trn_td <= (OTHERS => '0'); + pcie_tlp_tx_complete <= '0'; + txtrn_counter <= "00000001"; + bram_txtlp_readaddress <= (OTHERS => '0'); + + --********** ready-wait STATE ********** + when "00000001" => --state 1 + --if there is a new TLP assembled and the EP is ready, + --start the tx-trn bus transaction. + if (trn_tdst_rdy_n='0') then + epif_tx_state <= "00000010"; --next state + end if; + trn_tsrc_rdy_n_1 <='1'; + trn_tsof_n1 <= '1'; + trn_teof_n <= '1'; + trn_td <= (OTHERS => '0'); + pcie_tlp_tx_complete <= '0'; + txtrn_counter <= "00000001"; + bram_txtlp_readaddress <= (OTHERS => '0'); + + --********** transfer STATE ********** + when "00000010" => --state 2 + trn_tsrc_rdy_n_1 <='0'; + trn_td <= bram_txtlp_readdata; + if (trn_tdst_rdy_n='0') then + txtrn_counter <= txtrn_counter +1; + bram_txtlp_readaddress <= bram_txtlp_readaddress +1; + end if; + if (txtrn_counter = "00000010") then + trn_tsof_n1 <= '0'; --start + else + trn_tsof_n1 <= '1'; + end if; + --test number of dwords: + if (txtrn_counter = tlp_payloadsize_dwords +4) then -- "+3" is the header and "+1" is for the delay + --this is the last dword, next clk is next state + epif_tx_state <= "00000000"; --back to idle, since finished + trn_teof_n <= '0'; --end + pcie_tlp_tx_complete <= '1'; --assert for 1 clk + else + trn_teof_n <= '1'; --not end yet + pcie_tlp_tx_complete <= '0'; --not complete yet + end if; + + when others => --error + epif_tx_state <= "00000000"; --back to idle + trn_tsrc_rdy_n_1 <='1'; + trn_tsof_n1 <= '1'; + trn_teof_n <= '1'; + trn_td <= (OTHERS => '0'); + pcie_tlp_tx_complete <= '0'; + txtrn_counter <= "00000001"; + + end case; + end if; + end if; + end process; + + --this (little delay) is to fix a hold time violation created inside the pcie-ep ip: + trn_tsrc_rdy_n <= trn_tsrc_rdy_n_1 or (not pciewb_localreset_n); + trn_tsof_n <= trn_tsof_n1 or (not pciewb_localreset_n); + + + + --some fix values: + trn_tsrc_dsc_n <= '1'; --no errors on trn bus + trn_tstr_n <= '0'; --pipelining + trn_tcfg_gnt_n <= '0'; --no tlp priorities + trn_terrfwd_n <= '1'; --no errors on trn + --nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n + + + + + + -- RX: INTERFACE TO THE PCIE-EP: GET the received TLP PACKETS:- ---- + process (pciewb_localreset_n, trn_clk, epif_rx_state, tlp_state, trn_rx_counter, + bram_rxtlp_writeaddress, rxstm_readytoroll, trn_rsof_n, tlpstm_isin_idle, trn_rdst_rdy_n) + begin + if (pciewb_localreset_n='0') then + pcie_just_received_a_new_tlp <= '0'; + epif_rx_state <= "00000000"; + trn_rdst_rdy_n <= '1'; + trn_rx_counter <= (OTHERS => '0'); + bram_rxtlp_we <= "0"; + bram_rxtlp_writeaddress <= (OTHERS => '0'); + bram_rxtlp_writedata <= (OTHERS => '0'); + rxstm_readytoroll <= '0'; + else + if (trn_clk'event and trn_clk = '1') then + + case ( epif_rx_state ) is + + --********** idle STATE ********** + when "00000000" => --state 0 + pcie_just_received_a_new_tlp <= '0'; + bram_rxtlp_writedata <= trn_rd; + if (trn_rsrc_rdy_n='0' and trn_rsof_n='0' and tlpstm_isin_idle = '1' and trn_rdst_rdy_n='0') then + trn_rx_counter <= trn_rx_counter +1; + bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1; + epif_rx_state <= "00000001"; + else + trn_rx_counter <= (OTHERS => '0'); + bram_rxtlp_writeaddress <= (OTHERS => '0'); + end if; + --destination ready: + if (tlpstm_isin_idle = '1')then + trn_rdst_rdy_n <= '0'; + else + trn_rdst_rdy_n <= '1'; + end if; + --write into buffer: + if (trn_rsrc_rdy_n='0' and trn_rsof_n='0' and tlpstm_isin_idle = '1') then + bram_rxtlp_we <= "1"; + rxstm_readytoroll <= '1'; + else + bram_rxtlp_we <= "0"; + rxstm_readytoroll <= '0'; + end if; + + --********** read STATE ********** + when "00000001" => --state 1 + rxstm_readytoroll <= '0'; + if (trn_reof_n ='0') then --last dw + epif_rx_state <= "00000010"; --for the next clk cycle + trn_rdst_rdy_n <= '1'; --ok, dont send more yet + end if; + if (trn_rsrc_rdy_n='0') then --only act if the EP was ready + trn_rx_counter <= trn_rx_counter +1; + bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1; + bram_rxtlp_writedata <= trn_rd; + end if; + --in an early stage of this transfer, the scheduler can already + --start working on the data, this way its pipelined, so the latency is lower. + if (trn_rx_counter = "00000010") then + pcie_just_received_a_new_tlp <= '1';--assert for one clk only + else + pcie_just_received_a_new_tlp <= '0'; + end if; + + --********** finished filling up RX TLP STATE ********** + when "00000010" => --state 2 + epif_rx_state <= "00000000"; + trn_rx_counter <= (OTHERS => '0'); + + when others => --error + epif_rx_state <= "00000000"; --go to state 0 + end case; + end if; + end if; + end process; + + --fixed connections: + --trn_rnp_ok_ntrn_rnp_ok_n <= '0'; --ready to receive non-posted + --not connected: trn_rerrfwd_n, trn_rsrc_dsc_n, trn_rbar_hit_n + + + + + + -- flow control: INTERFACE TO THE PCIE-EP: - ---- + --not used. pcie-ep provides information about credit status. + --unconnected: trn_fc_nph, trn_fc_npd, trn_fc_ph, trn_fc_pd, trn_fc_cplh, trn_fc_cpld + trn_fc_sel <= "000"; + + + + + + -- --- GLUE LOGIC BETWEEN THE PCIE CORE-IF AND THE WB INTERFACES ----------------------- + -- --- ALSO TLP PACKET PROCESSING. + --Theory of operation: + --RX: If we receive a TLP (pcie_just_received_a_new_tlp goes high for one clock cycle), + --then store it (pcie_received_tlp), decode it (to figure out if its read request, + --posted write or non-supported request), then assert a flag (start_write_wb0 or + --start_read_wb0)to initiate a wishbone cycle. + --TX: At the completion of a wishbone read, the wishbone statemachine asserts the + --wb_transaction_complete flag, so we can assemble the TX TLP packet (pcie_to_transmit_tlp) + --and assert the flag named pcie_there_is_a_new_tlp_to_transmit. This packet will be + --a read completion packet on the PCIe link. + -- + --This core can handle 1...8 DWORD accesses in one request (max 256bit payload ), + --and can handle only one request at a time. If a new request is arriving while + --processing the previous one (e.g. getting the data from a wishbone read), then + --the state machine will not process it immediately, or it will hang. So the user + --software has to wait for the previous read completion before issueing a new request. + --The multiple DWORDs are handled separately by the WB statemachine. + --Performance: WishBone bus: 62.5MHz, 32bit, 3clk/access -> 83MBytes/sec + -- + --TLP decoding: + --Header+Payload_data+TLP_DIGEST(ECRC). + --received Header: + --First Dword: bit.30/29=format: 00=3DW-header+no_data, 01=4DW-header+no_data, + --10=3DW-header+data, 11=4DW-header+data. bit.28:24=type: 00000 or 00001 are memory + --read requests, 00000 or 00001 are memory write request if type=1x. read request + --completion is 01010 and type=10. bit.9:0 is payload size [DW]. + --Second Dword: bit.31:16 is requester ID. bit3:0 is first dword byte enable, bit.7:4 is + --byte enable for last dword data. intermediate dwords have all bytes enabled. + --Third DWORD: address, where bit.1:0=00b. 4DW headers are for 64bit. 64bit adressing + --uses 3rd-dword for addre63:32, 4th dword for addr31:0. + -- + --The TLP variables in this core: BRAM memory used store TLP, up to 1-2kBytes + -- + --Read completion is 3DW header and routed by completer-ID and requester-ID, not address. + --The core has to store the requester ID and feed it back in the completion packet. + --Completion status: 000=successful, 100=completer_abort, 001=unsupported request. byte + --count is N.of bytes left. lower_address is the first enabled byte of data returned + --with the Completion. + -- + -- Completion packet header (descriptor): new, axi4-stream format used!!!!!!!!!!!! + -- + -- 63 32 31 0 + -- /---------DW1--------------\/-----------DW0---------------\ + -- ------------------------address63:2----------------------AT (address type) + -- + -- 63 32 31 0 + -- /---------DW3--------------\/-----------DW2---------------\ + -- R attr TC BAR-ap BAR-id tar-funct, tag, bus dev, funct, R, req type, dword count + -- + + + --TLP-protocol statemachine: + process (pciewb_localreset_n, trn_clk, tlp_state, + pcie_just_received_a_new_tlp, tlp_datacount, + bram_rxtlp_readdata, bram_txtlp_writeaddress, bram_rxtlp_readaddress, + tlp_state_copy, rxtlp_decodedaddress, + rxtlp_header_dw0, rxtlp_header_dw1, rxtlp_header_dw2, rxtlp_header_dw3, + bit10, rxtlp_firstdw_be, wb_transaction_complete, flag1, rxdw1_23_0, pcie_rxtlp_tag, + tlp_payloadsize_dwords, pcie_bar0_wb_data_i_latched, cfg_completer_id, + rxtlp_requesterid) + begin + if (pciewb_localreset_n='0') then + start_read_wb0 <= '0'; + start_write_wb0 <= '0'; + pcie_bar0_wb_data_o_feed <= (others => '0'); + pcie_bar0_wb_addr_o_feed <= (others => '0'); + pcie_bar0_wb_sel_o_feed <= (others => '0'); + pcie_there_is_a_new_tlp_to_transmit <= '0'; + rxtlp_decodedaddress<= (others => '0'); + tlp_payloadsize_dwords <= (others => '0'); + rxtlp_firstdw_be <= (others => '0'); + rxtlp_lastdw_be <= (others => '0'); + rxtlp_requesterid <= (others => '0'); + tlp_state <= (others => '0'); + tlp_state_copy <= (others => '0'); + bram_txtlp_we <= "0"; + bram_txtlp_writeaddress <= (others => '0'); + bram_txtlp_writedata <= (others => '0'); + bram_rxtlp_readaddress <= (others => '0'); + rxtlp_header_dw0 <= "01111111000000000000000000000000"; + rxtlp_header_dw1 <= (others => '0'); + rxtlp_header_dw2 <= (others => '0'); + rxtlp_header_dw3 <= (others => '0'); + flag1 <= '0'; + rxdw1_23_0 <= (others => '0'); + pcie_rxtlp_tag <= (others => '0'); + rcompl_bytecount_field <= (others => '0'); + tlpstm_isin_idle <= '1'; + else + if (trn_clk'event and trn_clk = '1') then + case ( tlp_state ) is + + --********** IDLE STATE ********** + --also re-initialize signals... + when "00000000" => --state 0 + if (pcie_just_received_a_new_tlp='1') then + tlp_state <= "00000001"; --to tlp decoding state + tlpstm_isin_idle <= '0'; + else + tlpstm_isin_idle <= '1'; + end if; + start_write_wb0 <= '0'; + start_read_wb0 <= '0'; + tlp_state_copy <= tlp_state; + bram_txtlp_we <= "0"; + bram_txtlp_writeaddress <= (others => '0'); + bram_txtlp_writedata <= (others => '0'); + bram_rxtlp_readaddress <= (others => '0'); + tlp_datacount <= "00000001"; + rxtlp_header_dw0 <= "01111111000000000000000000000000"; --this is to prevent false decode + pcie_bar0_wb_data_o_feed <= (others => '0'); + pcie_bar0_wb_addr_o_feed <= (others => '0'); + pcie_bar0_wb_sel_o_feed <= (others => '0'); + rxtlp_header_dw1 <= (others => '0'); + rxtlp_header_dw2 <= (others => '0'); + rxtlp_header_dw3 <= (others => '0'); + rxdw1_23_0 <= (others => '0'); + pcie_rxtlp_tag <= (others => '0'); + pcie_there_is_a_new_tlp_to_transmit <= '0'; + rxtlp_decodedaddress<= (others => '0'); + tlp_payloadsize_dwords <= (others => '0'); + rxtlp_firstdw_be <= (others => '0'); + rxtlp_lastdw_be <= (others => '0'); + rxtlp_requesterid <= (others => '0'); + rcompl_bytecount_field <= (others => '0'); + + + --********** TLP ARRIVED STATE ********** + --read TLP out of EP, decode and decide, + --latch address/sel/wr_data + --All the "IF"-statements use address+1, because the BRAM read side has data available 1clk late!!! + --Added an ectra clock delay, based on testing, since the data is one more CLK late. + when "00000001" => --state 1 + --latch the header: + bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1; + if (bram_rxtlp_readaddress = "000000010") then + rxtlp_header_dw0 <= bram_rxtlp_readdata; + elsif (bram_rxtlp_readaddress = "000000011") then + rxtlp_header_dw1 <= bram_rxtlp_readdata; + elsif (bram_rxtlp_readaddress = "000000100") then + rxtlp_header_dw2 <= bram_rxtlp_readdata; + elsif (bram_rxtlp_readaddress = "000000101") then + rxtlp_header_dw3 <= bram_rxtlp_readdata; + end if; + --decode some parameters: + tlp_payloadsize_dwords <= rxtlp_header_dw2(7 downto 0); + rxtlp_firstdw_be <= "1111"; --rxtlp_header_dw1(3 downto 0); no longer supported + rxtlp_lastdw_be <= "1111"; --rxtlp_header_dw1(7 downto 4); no longer supported + rxtlp_requesterid <= rxtlp_header_dw2(31 downto 16); + rxtlp_attr_tc <= rxtlp_header_dw3(30 downto 25); + pcie_rxtlp_tag <= rxtlp_header_dw3(7 downto 0) ; --tag + rxtlp_at <= rxtlp_header_dw0(1 downto 0); + --decide based on header: + if (rxtlp_header_dw2(14 downto 8)="0000") then --32bit read + if (bram_rxtlp_readaddress = "000000100") then + --rxtlp_decodedaddress <= bram_rxtlp_readdata; + rxtlp_decodedaddress(29 downto 0) <= rxtlp_header_dw0(31 downto 2); --byte address or dword address????? + bram_txtlp_writeaddress(8 downto 0) <= "000000011"; --point after the 3dw readcompl header + tlp_state <= "00000011"; + end if; + elsif (rxtlp_header_dw2(14 downto 8)="0001") then --32bit write + if (bram_rxtlp_readaddress = "000000100") then + --rxtlp_decodedaddress <= bram_rxtlp_readdata; + rxtlp_decodedaddress(29 downto 0) <= rxtlp_header_dw0(31 downto 2); + tlp_state <= "00000010"; + end if; + elsif (rxtlp_header_dw0(30 downto 24)="1111111") then --just wait until this gets a real value (not ready yet) + rxtlp_decodedaddress <= bram_rxtlp_readdata; + else --unsupported request + if (bram_rxtlp_readaddress = "000000100") then + tlp_state <= "00000101"; + bram_txtlp_writeaddress <= "111111111"; + end if; + end if; + + + --********** WRITE STATE ********** + --initiate WB write(s) (1...N DWORD accesses) + when "00000010" => --state 2 + pcie_bar0_wb_addr_o_feed(BAR0_WIDTH-1 downto 2) <= rxtlp_decodedaddress(BAR0_WIDTH-1 downto 2) + tlp_datacount -1; -- BAR0 size is hardcoded here, by cutting MSB's off + pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0); + pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be; + pcie_bar0_wb_data_o_feed <= bram_rxtlp_readdata; + tlp_state_copy <= tlp_state; + if (tlp_state_copy = tlp_state) then + start_write_wb0 <= '0'; + else --generate just one pulse, at the first clk cycle in this state + start_write_wb0 <= '1'; + end if; + if (wb_transaction_complete='1') then --one DW transfer completed + + if (tlp_payloadsize_dwords = tlp_datacount) then --all data completed + tlp_state <= "00000000"; --to idle + else + tlp_state <= "00010100"; --restart wb transaction with new data + bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1; + tlp_datacount <= tlp_datacount +1; + end if; + end if; + --* Write restart state * + when "00010100" => --state 20 + tlp_state <= "00000010"; + + + --********** READ STATE ********** + --initiate WB read, store all data, starting from address=2, then go to completion state + when "00000011" => --state 3 + pcie_bar0_wb_addr_o_feed(BAR0_WIDTH-1 downto 2) <= rxtlp_decodedaddress(BAR0_WIDTH-1 downto 2) + tlp_datacount -1; + pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0); + pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be; + tlp_state_copy <= tlp_state; + if (tlp_state_copy = tlp_state) then + start_read_wb0 <= '0'; + else --generate just one pulse + start_read_wb0 <= '1'; + end if; + if (wb_transaction_complete='1') then + bram_txtlp_writedata <= pcie_bar0_wb_data_i_latched; + bram_txtlp_we <= "1"; + if (tlp_payloadsize_dwords = tlp_datacount)then + tlp_state <= "01111110"; --read completion + --bram_txtlp_writeaddress remains the same to capture data in next clock cycle + --Calculate completion header's "rcompl_bytecount_field" from rxtlp_firstdw_be, rxtlp_lastdw_be, tlp_payloadsize_dwords + if (rxtlp_lastdw_be="0000") then --max 1DW + if (rxtlp_firstdw_be="1111") then --4bytes + rcompl_bytecount_field <= "0000000100"; + bram_txtlp_writedata (25 downto 16) <= "0000000100"; + elsif (rxtlp_firstdw_be="0111" or rxtlp_firstdw_be="1110") then + rcompl_bytecount_field <= "0000000011"; + bram_txtlp_writedata (25 downto 16) <= "0000000011"; + elsif (rxtlp_firstdw_be="0011" or rxtlp_firstdw_be="1100" or rxtlp_firstdw_be="0110") then + rcompl_bytecount_field <= "0000000010"; + bram_txtlp_writedata (25 downto 16) <= "0000000010"; + else + rcompl_bytecount_field <= "0000000001"; + bram_txtlp_writedata (25 downto 16) <= "0000000001"; + end if; + else --more than 1DW: right now we dont support non-aligned multi-Dword accesses + rcompl_bytecount_field(9 downto 2) <= tlp_payloadsize_dwords; + rcompl_bytecount_field(1 downto 0) <= "00"; + end if; + else + tlp_state <= "00011110"; --one more wb read + tlp_datacount <= tlp_datacount +1; + end if; + else + bram_txtlp_we <= "0"; + end if; + --* read restart STATE * + when "00011110" => --state 30 + tlp_state_copy <= tlp_state; -- SC: required to re-trigger additional reads, start_read_wb0 <= '1' + bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1; -- SC: increment address here (moved) + tlp_state <= "00000011"; + bram_txtlp_we <= "0"; + + --intermediate state before completion (to ensure data latch at address-4) + --for additional data bytes/dwords + when "01111110" => --state 126 + tlp_state <= "00000100"; + bram_txtlp_writeaddress <= (OTHERS => '0'); --reset address to zero, for the TLP header latching!!!! + --pre-write header-DW0: *** + bram_txtlp_writedata (31) <= '0'; --flag1; --reserved + bram_txtlp_writedata (30) <= '0'; --not locked read + bram_txtlp_writedata (29 downto 26) <= "0000"; --byte count upper + bram_txtlp_writedata (25 downto 16) <= rcompl_bytecount_field; + bram_txtlp_writedata (15 downto 10) <= "000000"; + bram_txtlp_writedata (9 downto 8) <= rxtlp_at; + bram_txtlp_writedata (7) <= '0'; + bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(4 downto 0); --lower address - decoding correct, 32bit or 8bit addressing??? + case (rxtlp_firstdw_be) is + when "0000" => bram_txtlp_writedata (1 downto 0) <= "00"; --lower address + when "1000" => bram_txtlp_writedata (1 downto 0) <= "11"; --lower address + when "0100" => bram_txtlp_writedata (1 downto 0) <= "10"; --lower address + when "1100" => bram_txtlp_writedata (1 downto 0) <= "10"; --lower address + when "0010" => bram_txtlp_writedata (1 downto 0) <= "01"; --lower address + when "0110" => bram_txtlp_writedata (1 downto 0) <= "01"; --lower address + when "1010" => bram_txtlp_writedata (1 downto 0) <= "01"; --lower address + when "1110" => bram_txtlp_writedata (1 downto 0) <= "01"; --lower address + when others => bram_txtlp_writedata (1 downto 0) <= "00"; --lower address + end case; + + + + --********** READ COMPLETION STATE ********** + --assemble the tx TLP header, starting from position-0, and initiate the transmit + --buffer signals bram_txtlp_we, bram_txtlp_writeaddress, bram_txtlp_writedata + when "00000100" => --state 4 + tlp_state_copy <= tlp_state; + bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1; + --header-1.dw *** + if (bram_txtlp_writeaddress="000000000") then --if address is 0: launch data for next lock/address(1): + bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; + bram_txtlp_writedata (15) <= '0'; + bram_txtlp_writedata (14) <= '0'; + bram_txtlp_writedata (13 downto 12) <= "00"; --completion status 000=successful, 001=unsupported, 100=abort + bram_txtlp_writedata (11 downto 8) <= "0000"; --tlp_payloadsize_dwords; + bram_txtlp_writedata (7 downto 0) <= tlp_payloadsize_dwords; + bram_txtlp_we <= "1"; + --header-2.dw *** + elsif (bram_txtlp_writeaddress="000000001") then --if address is 1: launch data for next lock/address(2): + bram_txtlp_writedata (31) <= '0'; + bram_txtlp_writedata (30 downto 25) <= rxtlp_attr_tc; + bram_txtlp_writedata (24) <= '1'; --completer id enable + bram_txtlp_writedata (23 downto 8) <= cfg_completer_id; + bram_txtlp_writedata (7 downto 0) <= pcie_rxtlp_tag; + else --data dwords, disable writes from next clock cycle + bram_txtlp_we <= "0"; + end if; + --one pulse to start the ep-if statemachine, upon arriving to this state + if (tlp_state_copy = tlp_state) then + pcie_there_is_a_new_tlp_to_transmit <= '0'; + else + pcie_there_is_a_new_tlp_to_transmit <= '1'; + end if; + --back to idle when the ep-if tx is finished: (wait to avoid overwrite) + if (pcie_tlp_tx_complete='1') then + tlp_state <= "00000000"; + end if; + + + --********** UNSUPPORTED REQUEST STATE ********** + --completion response with status=001 + when "00000101" => --state 5 + tlp_state_copy <= tlp_state; + tlp_payloadsize_dwords <= "00000000"; + bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1; + --assembling the TLP packet: ) + if (bram_txtlp_writeaddress="111111111") then --header 0.dw + bram_txtlp_we <= "1"; + bram_txtlp_writedata (31) <= flag1; --reserved + bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion + bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0); + elsif (bram_txtlp_writeaddress="000000000") then --header 1.dw + bram_txtlp_we <= "1"; + bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID + bram_txtlp_writedata (15 downto 13) <= "000"; --status= UNSUPPORTED REQUEST *** + bram_txtlp_writedata (12) <= '0'; --reserved + bram_txtlp_writedata (11 downto 0) <= "000000000000"; --remaining byte count + elsif (bram_txtlp_writeaddress="000000001") then --header 2.dw + bram_txtlp_we <= "1"; + bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID + bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag + bram_txtlp_writedata (7) <= '0'; --reserved + bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address + bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0); --lower address + else --data dwords + bram_txtlp_we <= "0"; + end if; + --one pulse to start the ep-if statemachine, upon arriving to this state + if (tlp_state_copy = tlp_state) then + pcie_there_is_a_new_tlp_to_transmit <= '0'; + else + pcie_there_is_a_new_tlp_to_transmit <= '1'; + end if; + --back to idle when finished: + if (pcie_tlp_tx_complete='1') then + tlp_state <= "00000000"; + end if; + + when others => --error + tlp_state <= "00000000"; --go to state 0 + end case; + + end if; + end if; + end process; --end tlp statemachine + + + + + --byte enable encoding to wb_address bit1:0 + --this does not swap the endian, since only the data is swapped in the pcie packets. + process ( pciewb_localreset_n, rxtlp_firstdw_be ) + begin + if (pciewb_localreset_n = '0') then + bit10(1 downto 0) <="00"; + else + if (rxtlp_firstdw_be ="0001") then + bit10(1 downto 0) <= "00"; + elsif (rxtlp_firstdw_be ="0010") then + bit10(1 downto 0) <= "01"; + elsif (rxtlp_firstdw_be ="0100") then + bit10(1 downto 0) <= "10"; + elsif (rxtlp_firstdw_be ="1000") then + bit10(1 downto 0) <= "11"; + elsif (rxtlp_firstdw_be ="0011") then + bit10(1 downto 0) <= "00"; + elsif (rxtlp_firstdw_be ="1100") then + bit10(1 downto 0) <= "10"; + elsif (rxtlp_firstdw_be ="1111") then + bit10(1 downto 0) <= "00"; + else --this should never happen + bit10(1 downto 0) <= "00"; + end if; + end if; + end process; + + + + + + -- INTERRUPTS: ------------------------------------------------------------------------- + --to assert an interrupt, use the cfg_interrupt_assert_n pin. + --datasheet text: + --As shown in Figure 6-30, the user application first asserts cfg_interrupt_n and + --cfg_interrupt_assert_n to assert the interrupt. The user application should select a + --specific interrupt (INTA, INTB, INTC, or INTD) using cfg_interrupt_di[7:0] as shown + --in Table 6-19. + -- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt has been accepted. + --On the following clock cycle, the user application deasserts cfg_interrupt_n and, if the + --Interrupt Disable bit in the PCI Command register is set to 0, the core sends an assert + --interrupt message (Assert_INTA, Assert_INTB, and so forth). + -- After the user application has determined that the interrupt has been serviced, it + --asserts cfg_interrupt_n while deasserting cfg_interrupt_assert_n to deassert the + --interrupt. The appropriate interrupt must be indicated via cfg_interrupt_di[7:0]. + -- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt deassertion has + --been accepted. On the following clock cycle, the user application deasserts + --cfg_interrupt_n and the core sends a deassert interrupt message (Deassert_INTA, + --Deassert_INTB, and so forth). + --cfg_interrupt_di[7:0] value Legacy Interrupt + --00h INTA + --01h INTB + --02h INTC + --03h INTD + + cfg_interrupt_di <= "00000000"; --intA used + + --prohibit IRQ assert when TLP state machine not idle. + -- if an IRQ is asserted between a read request and completion, it causes an error in the endpoint block. + -- added by StBa, AAC Microtec, 2012 + irq_prohibit <= not tlpstm_isin_idle; + + -- fixed compatibility with both MSI interrupts and legacy interrupts + -- added by SC, FRIB, 2016 + pcie_msi_enabled <= cfg_interrupt_msienable; + + process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state, + cfg_interrupt_rdy_n) + begin + if (pciewb_localreset_n='0') then + pcieirq_state <= "000"; + cfg_interrupt_n <= '1'; + cfg_interrupt_assert_n_1 <= '1'; + else + if (trn_clk'event and trn_clk = '1') then + case ( pcieirq_state ) is + --********** idle STATE ********** + when "000" => --state 0 + cfg_interrupt_n <= '1'; --inactive + cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert + if (pcie_irq = '1') then + pcieirq_state <= "001"; + end if; + --********** wait for not irq_prohibit ********** + when "001" => --state 1 + if (irq_prohibit = '0') then + pcieirq_state <= "010"; + cfg_interrupt_n <= '0'; --active + cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert + end if; + --********** assert STATE ********** + when "010" => --state 2 + cfg_interrupt_n <= '0'; --request INTA assertion + if (cfg_interrupt_rdy_n ='0') then --ep accepted it + cfg_interrupt_n <= '1'; --deassert the request + cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert + pcieirq_state <= "011"; -- wait for IRQ deassert + end if; + --********** (LEGACY) pcie_irq kept asserted STATE ********** + when "011" => --state 3 + if (pcie_irq='0' and irq_prohibit='0' and cfg_interrupt_msienable='0') then + pcieirq_state <= "100"; -- LEGACY, pcie_irq gets deasserted + end if; + if (pcie_irq='0' and cfg_interrupt_msienable='1') then + pcieirq_state <= "000"; -- MSI IRQ, back to IDLE when pcie_irq deasserted + end if; + cfg_interrupt_n <= '1'; --inactive + cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert + --********** DEassert STATE ********** + -- below state only used for legacy interrupts + when "100" => --state 4 + cfg_interrupt_n <= '0'; --request INTA DEassertion + if (cfg_interrupt_rdy_n ='0') then --ep accepted it + cfg_interrupt_n <= '1'; --deassert the request + pcieirq_state <= "000"; + end if; + + when others => --error + pcieirq_state <= "000"; --go to state 0 + end case; + end if; + end if; + end process; + + --this (little delay) is to fix a hold time violation created inside the pcie-ep ip: + cfg_interrupt_assert_n <= cfg_interrupt_assert_n_1 or (not pciewb_localreset_n); + + + + + + +-- -------- END OF FILE ------------------------------------------------------------------------------------- +end Behavioral; + +