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Rev 4 → Rev 5

/trunk/ibniz/ibniz.v
0,0 → 1,99
 
 
module Ibniz_adapter ( clk, rst,
iX_video, iY_video,
// T_in, X_in, Y_in,
// V_out,
oR_video, oG_video, oB_video,
tumblers, endFrame, dbg_val );
 
parameter RES_X_H= 1240;
parameter RES_Y_H= 1024;
parameter XY_STEP_H= 7;
parameter RES_X_L= 640;
parameter RES_Y_L= 480;
parameter XY_STEP_L= 8;
 
parameter ENABLE_HEAVIES= 1;
 
input clk;
input rst;
 
input signed [11:0] iX_video;
input signed [11:0] iY_video;
output reg [7:0] oR_video;
output reg [7:0] oG_video;
output reg [7:0] oB_video;
input [9:0] tumblers;
input endFrame;
output wire [63:0] dbg_val;
 
wire signed [31:0] T_in;
wire signed [31:0] X_in;
wire signed [31:0] Y_in;
 
wire [31:0] V_out2;
 
wire high_res= 1;
 
reg [15:0] count;
 
assign T_in[15:0]=0;
assign T_in[31:16]=count;
 
wire signed [11:0] x;
wire signed [11:0] y;
assign x= (iX_video- (high_res ? RES_X_H/2 :RES_X_L/2 ));
assign y= (iY_video- (high_res ? RES_Y_H/2 :RES_Y_L/2 ));
 
assign X_in= x<<<(high_res ? XY_STEP_H :XY_STEP_L );
assign Y_in= y<<<(high_res ? XY_STEP_H :XY_STEP_L );
 
wire [31:0] V_out [0:7];
 
 
assign V_out2 = //1? V_out[7] :
tumblers[0] ?
(tumblers[1] ?
(tumblers[2] ? V_out[7] : V_out[3]) :
(tumblers[2] ? V_out[5] : V_out[1]) ) :
((tumblers[1]&&ENABLE_HEAVIES==1) ?
( tumblers[2] ? V_out[6] : V_out[2]) :
(tumblers[2] ? V_out[4] : V_out[0]) );
Ibniz_generator1 ig0( clk, rst, tumblers[2:0]==0, T_in, X_in, Y_in, V_out[0] );
Ibniz_generator4 ig1( clk, rst, tumblers[2:0]==1, T_in, X_in, Y_in, V_out[1] );
Ibniz_generator2 ig2( clk, rst, tumblers[2:0]==2, T_in, X_in, Y_in, V_out[2] );
Ibniz_generator3 ig3( clk, rst, tumblers[2:0]==3, T_in, X_in, Y_in, V_out[3] );
Ibniz_generator6 ig4( clk, rst, tumblers[2:0]==4, T_in, X_in, Y_in, V_out[4] );
Ibniz_generator5 ig5( clk, rst, tumblers[2:0]==5, T_in, X_in, Y_in, V_out[5] );
Ibniz_generator7 ig6( clk, rst, tumblers[2:0]==6, T_in, X_in, Y_in, V_out[6] );
Ibniz_generator0 ig7( clk, rst, tumblers[2:0]==7, T_in, X_in, Y_in, V_out[7] );
 
wire signed [15:0] bright= V_out2[15:8];
wire signed [7:0] hue2= V_out2[23:16];
wire signed [7:0] hue1= V_out2[31:24];
wire signed [15:0] C= bright;// -16;
wire signed [15:0] D= (hue1^8'h80) -128;
wire signed [15:0] E= (hue2^8'h80) -128;
wire signed [11:0] B_video= (( 298*C + 409*E + 128) >>> 8);
wire signed [11:0] G_video= (( 298*C - 100*D - 208*E + 128) >>> 8);
wire signed [11:0] R_video= (( 298*C + 516*D + 128) >>> 8);
 
always@(posedge clk or posedge rst)
begin
if ( rst )
begin
count= 0;
end
else
begin
if ( endFrame )
count<= count +1;
// Y'UV ->RGB
oR_video= R_video<0 ? 0 : ( R_video>255 ? 255 : R_video);
oG_video= G_video<0 ? 0 : ( G_video>255 ? 255 : G_video);
oB_video= B_video<0 ? 0 : ( B_video>255 ? 255 : B_video);
end
end
endmodule
 
/trunk/ibniz/ibniz_units_old.v
0,0 → 1,179
 
`define MAX(a,b) ( (a)>(b)? (a):(b) )
`define ABS(a) ( (a)>0? (a):(-(a)) )
 
//============================= XOR VARIATION ===================================
 
//module Ibniz_generator7z ( clk, rst, ena, T_in, X_in, Y_in, V_out );
//
//input clk;
//input rst;
//input ena;
//input wire signed [31:0] T_in;
//input wire signed [31:0] X_in;
//input wire signed [31:0] Y_in;
//output reg [31:0] V_out;
//
//wire [31:0] XxY= ( X_in+ (X_in <<T_in[28:24] ) )^ ( Y_in + T_in[26:10] ) ;
//wire [31:0] V0= XxY+ (T_in>>7);
//
//always@(posedge clk or posedge rst)
//begin
// if ( rst )
// begin
// end
// else if ( ena )
// begin
// // **
//// XY <=((XX_in * YY_in)>>>16);
//// V_out<= ( XY * (TT_in))>>>16;
// // ^x7r+Md8r& (xor exch ror(7) + )
// V_out= V0 + ((V0<<(T_in[29:25])) & 32'hFFFF0000 );
// end
//end
//endmodule
 
module Ibniz_Stars ( clk, rst, ena, T_in, X_in, Y_in, V_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] T_in;
input wire signed [31:0] X_in;
input wire signed [31:0] Y_in;
output reg [31:0] V_out;
 
reg [31:0] R1;
reg [31:0] R2;
reg [31:0] R3;
reg [31:0] G1;
reg [31:0] G2;
reg [31:0] G3;
 
always@(posedge clk or posedge rst)
begin
if ( rst )
begin
end
else if ( ena )
begin
R1 <= (((X_in+T_in[31:12])>>>7)) * 11713 + ((Y_in>>>8)+(Y_in)) * 5422133;
R2 <= R1 * 7 + (R1>>8)*1817 ;
R3 <= { R2[7:0],R2[15:8],R2[23:16], R2[7:0] ^ R2[15:8] ^ R2[23:16] ^ R2[31:24] };
// **
V_out <= R3[7:0] ? 0 : R3[8] ? -1 : R3;
end
end
endmodule
 
//============================= ATAN2 ===================================
module Ibniz_generator0 ( clk, rst, ena, T_in, _X_in, _Y_in, V_out, dbg_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] T_in;
input wire signed [31:0] _X_in;
input wire signed [31:0] _Y_in;
output reg [31:0] V_out;
output reg signed [63:0] dbg_out;
 
wire signed [31:0] X_in= _X_in/2;
wire signed [31:0] Y_in= _Y_in/2;
 
always@(posedge clk or posedge rst)
begin
if ( rst )
begin
end
else if ( ena )
begin
// &*
// V_out= ((d_out<<<4)+(T_in>>>6))^(s_out>>6);
V_out=
// `ABS(_X_in) > 32'hF800 ? 0:
V0;// + ((V0<<(T_in[29:25])) & 32'hFFFF0000 );
end
end
 
//wire [31:0] V0= ((d_out-(T_in>>>14)) *20) ^((div_out>>>12)+(T_in>>>8));//((a_out[23:16]==Y_in[15:8])? -1:0);
 
wire [31:0] V0;
 
wire signed [31:0] T_sin;
PseudoSin ( clk, rst, ena, T_in>>>7, T_sin, _ );
 
 
Psin_Texture ( clk, rst, ena, T_in, ((d_out-(T_sin>>>7)-(T_in>>>13)) *20), ((div_out>>>12)+(T_sin)+(T_in>>>5)), V0 );
//Psin_Texture ( clk, rst, ena, T_in, ((d_out-(T_in>>>13)) *20), ((div_out>>>12)+(T_in>>>7)), V0 );
 
wire signed [31:0] s_out;
wire signed [31:0] a_out;
wire signed [31:0] a_outm;
wire signed [31:0] d_out;
wire signed [31:0] XX= ( (X_in) *(X_in) )>>12;
wire signed [31:0] YY= ( Y_in*Y_in)>>12;
wire signed [31:0] XXYY= XX+YY;
 
atan2_pipelined atan( clk, X_in, Y_in, a_out, _ );
 
defparam atan.IS_IBNIZ= 1;
//div_pipelined mydiv( clk, a_out<<12, pix2, d_out );
id_pipelined id( clk, a_out, d_out );
defparam id.DELAY= 16;
sqrt_pipelined sqrt1( clk, XXYY, s_out, _ );
 
wire signed [31:0] sin_a;
wire signed [31:0] cos_a;
wire signed [31:0] sin_q;
wire signed [31:0] div_out;
 
div_pipelined div1( clk, 48'h400000000000, XXYY, div_out );
defparam div1.BITS= 48;
 
endmodule
 
 
 
//============================= CIRCLES ===================================
//module Ibniz_generator7y ( clk, rst, ena, T_in, X_in, Y_in, V_out, dbg_out );
//
//input clk;
//input rst;
//input ena;
//input wire signed [31:0] T_in;
//input wire signed [35:0] X_in;
//input wire signed [35:0] Y_in;
//output reg [31:0] V_out;
//output reg signed [63:0] dbg_out;
//
//always@(posedge clk or posedge rst)
//begin
// if ( rst )
// begin
// end
// else if ( ena )
// begin
// // &*
// V_out= s_out*(T_in>>16);
// end
//end
//
//wire signed [31:0] s_out;
//wire signed [31:0] d_out;
//sqrt_pipelined sqrt1( clk, (X_in*X_in+Y_in*Y_in)>>>16, s_out, d_out );
//
//wire signed [31:0] XXX = X_in<<16;
//wire signed [31:0] XXX2 = (X_in-16*128);
//wire signed [31:0] YYY = Y_in<<16;
//wire signed [31:0] YYY_p = (YYY-256);
//wire signed [31:0] g_out = (YYY==0 || XXX==0 || X_in==32'h8000 || Y_in==(-32'h8000) ) ? -16'sh1 :
// ((YYY >= s_out /*&& YYY_p<-s_out*/) ? 32'h33338000 : 32'h0)
//// +( (YYY >= d_out /*&& YYY_p<-d_out*/) ? 32'hCC008000 : 32'h0)
//// +( (YYY >= -c_out && YYY_p<-c_out) ? 32'h88888000 : 32'h0)
// ;
//
//endmodule
 
//
 
/trunk/ibniz/ibniz_units.v
0,0 → 1,328
 
`define MAX(a,b) ( (a)>(b)? (a):(b) )
 
module Ibniz_generator1 ( clk, rst, ena, T_in, X_in, Y_in, V_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] T_in;
input wire signed [31:0] X_in;
input wire signed [31:0] Y_in;
output reg [31:0] V_out;
 
wire [31:0] XxY= X_in^Y_in;
 
always@(posedge clk or posedge rst)
begin
if ( rst )
begin
end
else if ( ena )
begin
// **
// XY <=((XX_in * YY_in)>>>16);
// V_out<= ( XY * (TT_in))>>>16;
// ^x7r+Md8r& (xor exch ror(7) + )
V_out= XxY+ (T_in>>7) + (T_in<<(32-7));
end
end
endmodule
 
module Ibniz_generator2 ( clk, rst, ena, T_in, X_in, Y_in, V_out, dbg_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] T_in;
input wire signed [31:0] X_in;
input wire signed [31:0] Y_in;
output reg [31:0] V_out;
output reg [63:0] dbg_out;
 
wire signed [47:0] XY= Y_in+X_in+(X_in>>>6);
wire signed [31:0] d_out;
 
wire done;
 
div_pipelined div1( clk, {T_in, 16'h0}, (/*XY[31]?-XY:*/XY), d_out );
 
//defparam div1.BITS= 48;
 
always@(posedge clk or posedge rst)
begin
if ( rst )
begin
end
else if ( ena )
begin
// if (done)
begin
// +/
V_out<= d_out;
dbg_out[31:0]<= X_in+Y_in;
dbg_out[63:32]<= T_in>>>16;
end
// else
// V_out<= V_out>>>1;
end
end
endmodule
 
////============================= PERLIN NOISE ===================================
 
 
//module Ibniz_generator7d ( clk, rst, ena, T_in, X_in, Y_in, V_out, dbg_out );
//
//`define NSCALE 14
//
//input clk;
//input rst;
//input ena;
//input wire signed [31:0] T_in;
//input wire signed [31:0] X_in;
//input wire signed [31:0] Y_in;
//output reg [31:0] V_out;
//output reg [63:0] dbg_out;
//
//wire signed [31:0] XX= (X_in>>>`NSCALE);
//wire signed [31:0] YY= (Y_in>>>`NSCALE);
//reg signed [31:0] GX00;
//reg signed [31:0] GY00;
//reg signed [31:0] GX01;
//reg signed [31:0] GY01;
//reg signed [31:0] GX10;
//reg signed [31:0] GY10;
//reg signed [31:0] GX11;
//reg signed [31:0] GY11;
//reg signed [31:0] rx00;
//reg signed [31:0] ry00;
//reg signed [31:0] rx01;
//reg signed [31:0] ry01;
//reg signed [31:0] rx10;
//reg signed [31:0] ry10;
//reg signed [31:0] rx11;
//reg signed [31:0] ry11;
//reg signed [31:0] r00;
//reg signed [31:0] r10;
//reg signed [31:0] r01;
//reg signed [31:0] r11;
//wire signed [31:0] _MX= (X_in - (XX<<<`NSCALE));//& (T_in[24]?(-1):((32'h1<<<`NSCALE) - 1));
//wire signed [31:0] _MY= (Y_in - (YY<<<`NSCALE));//& (T_in[24]?(-1):((32'h1<<<`NSCALE) - 1));
//reg signed [31:0] __MX;
//reg signed [31:0] __MY;
//reg signed [31:0] MX;
//reg signed [31:0] MY;
//reg signed [31:0] v1;
//reg signed [31:0] v2;
//reg signed [31:0] v3;
//reg signed [31:0] v4;
//wire signed [31:0] d_out;
//
//wire done;
//
////defparam div1.BITS= 48;
//
//always@(posedge clk or posedge rst)
//begin
// if ( rst )
// begin
// end
// else if ( ena )
// begin
//// if (done)
// begin
// // +/
// GX00<= XX * 16'h7353 + YY * 16'hacd7 ;
//// GY00<= XX * 16'ha689 + YY * 16'h7335;
// GX01<= XX * 16'h7353 + (YY+1) * 16'hacd7 ;
//// GY01<= XX * 16'ha689 + (YY+1) * 16'h7335;
// GX10<= (XX+1) * 16'h7353 + YY * 16'hacd7 ;
//// GY10<= (XX+1) * 16'ha689 + YY * 16'h7335;
// GX11<= (XX+1) * 16'h7353 + (YY+1) * 16'hacd7 ;
//// GY11<= (XX+1) * 16'ha689 + (YY+1) * 16'h7335;
// rx00 <= GX00[15] ? 0 : GX00[14] ? 1 : -1;
// ry00 <= ~GX00[15] ? 0 : GX00[14] ? 1 : -1;
// r00 <= rx00*(_MX) + ry00*_MY;
// rx01 <= GX01[15] ? 0 : GX01[14] ? 1 : -1;
// ry01 <= ~GX01[15] ? 0 : GX01[14] ? 1 : -1;
// r01 <= rx01*_MX + ry01*(_MY - (32'sh1<<<(`NSCALE)) );
// rx10 <= GX10[15] ? 0 : GX10[14] ? 1 : -1;
// ry10 <= ~GX10[15] ? 0 : GX10[14] ? 1 : -1;
// r10 <= rx10*(_MX - (32'sh1<<<(`NSCALE)) ) + ry10*_MY;
// rx11 <= GX11[15] ? 0 : GX11[14] ? 1 : -1;
// ry11 <= ~GX11[15] ? 0 : GX11[14] ? 1 : -1;
// r11 <= rx11*(_MX - (32'sh1<<<(`NSCALE)) ) + ry11*(_MY - (32'sh1<<<(`NSCALE)) );
//
// __MX<= (_MX*_MX);
// __MY<= (_MY*_MY);
// MX<= (3*__MX - 2*_MX*(__MX>>>`NSCALE))>>>`NSCALE;
// MY<= (3*__MY - 2*_MY*(__MY>>>`NSCALE))>>>`NSCALE;
//
// v1 <= (r10 * MX + r00 * ((32'sh1<<<(`NSCALE)) - MX))>>>`NSCALE;
// v2 <= (r11 * MX + r01 * ((32'sh1<<<(`NSCALE)) - MX))>>>`NSCALE;
//// V_out <= (((32'sh1<<<(`NSCALE))+v1)<<<(15-`NSCALE) );
// V_out <= (((32'sh1<<<(`NSCALE))+v2 * MY + v1 * ((32'sh1<<<(`NSCALE)) - MY))>>>`NSCALE)<<<(15-`NSCALE);
//
// // v1<= rx00 * MX + ry00 * MY;
//// v2<= rx01 * (16'h0040 - MX) + ry01 * MY;
//// v3<= rx10 * MX + ry10 * (16'h0040 - MY);
//// v4<= rx11 * (16'h0040 - MX) + ry11 * (16'h0040 - MY);
//// V_out<= (v1+v2+v3+v4);
// end
// end
//end
//endmodule
 
module Ibniz_generator3 ( clk, rst, ena, T_in, X_in, Y_in, V_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] T_in;
input wire signed [31:0] X_in;
input wire signed [31:0] Y_in;
output reg [31:0] V_out;
 
always@(posedge clk or posedge rst)
begin
if ( rst )
begin
end
else if ( ena )
begin
// **
V_out= ((((X_in>>>4) * (Y_in>>>4))>>>8) * (T_in>>>16));
end
end
endmodule
 
module Ibniz_generator4 ( clk, rst, ena, T_in, X_in, Y_in, V_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] T_in;
input wire signed [31:0] X_in;
input wire signed [31:0] Y_in;
output reg [31:0] V_out;
 
always@(posedge clk or posedge rst)
begin
if ( rst )
begin
end
else if ( ena )
begin
// &*
V_out= (X_in & Y_in) * (T_in>>>16);
end
end
endmodule
 
 
 
//
 
 
//
////============================= FLOOR+CEIL ===================================
module Ibniz_generator7 ( clk, rst, ena, T_in, _X_in, Y_in, V_out, dbg_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] T_in;
input wire signed [31:0] _X_in;
wire signed [31:0] X_in= _X_in/2;
input wire signed [31:0] Y_in;
output reg [31:0] V_out;
output reg [63:0] dbg_out;
 
wire signed [31:0] d_out;
wire signed [31:0] d_del;
wire signed [31:0] Y_pos_del;
wire signed [31:0] s_out;
 
wire done;
 
wire signed [47:0] XY= X_in+Y_in;
//wire signed [47:0] X_pos= { {48{X_in[31]}}, X_in, 16'h0};
//wire signed [48:0] Y_pos= Y_in;
wire signed [47:0] X_pos= `ABS(X_in)>`ABS(Y_in) ? { {48{X_in[31]}}, X_in, 16'h0} : { {48{Y_in[31]}}, Y_in, 16'h0};
wire signed [48:0] Y_pos= `ABS(X_in)>`ABS(Y_in) ? Y_in : X_in;
 
div_pipelined div1( clk, X_pos, Y_pos, d_out );
//div_pipelined div1( clk, X_in+T_in, Y_in, d_out );
defparam div1.BITS= 24;
 
id_pipelined id2( clk, Y_pos, Y_pos_del );
defparam id2.DELAY= 24;
//defparam div2.BITS= 24;
 
//wire signed [31:0] ys_out;
//sin_pipelined sin1( clk, Y_pos, ys_out, _, _ );
//wire signed [31:0] ds_out;
//sin_pipelined sin2( clk, d_out, ds_out, _, _ );
 
wire signed [31:0] hor= -((Y_pos_del>>>5)* (T_in>>>14));
wire signed [31:0] _bright= `ABS(Y_pos_del)*2-32'hffff;
wire signed [31:0] bright= (_bright>>>8)*(_bright>>>8);
reg signed [31:0] bright2;
 
always@(posedge clk or posedge rst)
begin
if ( rst )
begin
end
else if ( ena )
begin
// if (done)
begin
// //
bright2 <= (bright>>>8)*(bright>>>8);
// V_out<= d_out^(Y_pos+ ((X_in+Y_in<0) ? (T_in>>>10):-(T_in>>>10)));//( (X_in<<<16 <0 != (Y_in<<<16 <0)) ) ? 0 : 32'haaaaaaaa;
V_out<= (bright*(d_out[15:0]^hor[18:3])>>16)
| (d_out[16]^hor[20] ? 32'h80000000:0)
| (d_out[17]^hor[21] ? 32'h00800000:0)
| (d_out[18]^hor[22] ? 32'h40000000:0)
| (Y_pos_del==Y_in ? 32'h00400000:0);//( (X_in<<<16 <0 != (Y_in<<<16 <0)) ) ? 0 : 32'haaaaaaaa;
dbg_out[31:0]<= X_in+Y_in;
dbg_out[63:32]<= T_in>>>16;
end
// else
// V_out<= V_out>>>1;
end
end
endmodule
 
//============================= MATH TEST ===================================
//module Ibniz_generator7h ( clk, rst, ena, T_in, X_in, Y_in, V_out, dbg_out );
//
//input clk;
//input rst;
//input ena;
//input wire signed [31:0] T_in;
//input wire signed [31:0] X_in;
//input wire signed [31:0] Y_in;
//output reg [31:0] V_out;
//output reg [63:0] dbg_out;
//
//wire signed [31:0] d_out;
//exp_pipelined exp1( clk, (X_in)<<<4, d_out );
//
//
//always@(posedge clk or posedge rst)
//begin
// if ( rst )
// begin
// end
// else if ( ena )
// begin
// begin
// V_out<= ( (d_out > (Y_in<<<10)) ) ? 0 : 32'haaaaaaaa;
// dbg_out[63:32]<= T_in>>>16;
// end
// end
//end
//endmodule
/trunk/ibniz/jupiter.v
0,0 → 1,297
 
`define MAX(a,b) ( (a)>(b)? (a):(b) )
`define ABS(a) ( (a)>0? (a):(-(a)) )
 
 
//============================= ATAN2 ===================================
module Ibniz_generator5 ( clk, rst, ena, T_in, _X_in, _Y_in, V_out, dbg_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] T_in;
input wire signed [31:0] _X_in;
input wire signed [31:0] _Y_in;
output reg [31:0] V_out;
output reg signed [63:0] dbg_out;
reg signed [31:0] V_out2;
 
wire signed [31:0] X_in =_X_in;//+_Y_in)*3/4;
wire signed [31:0] Y_in =_Y_in;//-_Y_in)*3/4;
 
reg [31:0] R1;
reg [31:0] R2;
reg [31:0] R3;
 
always@(posedge clk or posedge rst)
begin
if ( rst )
begin
end
else if ( ena )
begin
R1 <= (((X_in+T_in[31:12])>>>7)) * 11713 + ((Y_in>>>8)+(Y_in)) * 5422133;
R2 <= R1 * 7 + (R1>>8)*1817 ;
R3 <= { R2[7:0],R2[15:8],R2[23:16], R2[7:0] ^ R2[15:8] ^ R2[23:16] ^ R2[31:24] };
// &*
// V_out2= ((d_out1*Z_D)>>>16 );//32'h00408000 +
// V_out= ( (V3<<16)+(V2<<8)+((V1*Z_D)>>>16));
// V_out= ( T_in[24] ? (a_T^(a_out1<<<2)) : ( a_out1<<<2 )+16'h8000 );
V_out= Z_D<5 ? (R3[7:0] ? 0 : R3[8] ? -1 : R3) :
// (((( d_out1&32'hff000000 )*Z_D)>>>16)&32'hff000000)|
// (((( d_out1&32'h00ff0000 )*Z_D)>>>16)&32'h00ff0000)|
(((( d_out1&32'hffff0000 ))))|
(((( d_out1&32'h0000ffff )*Z_D)>>>16)&32'h0000ffff);//(a_out2<<<3) ^(( a_out1<<<3 ) );//+16'h8000
end
end
 
wire signed [47:0] XY= ((a_out1)<<<2)+(a_out2)-48'h00010000;
wire signed [31:0] d_out1= (_d_out1)>>>8;
wire signed [47:0] _d_out1;
 
div_pipelined div1( clk, {T_in, 22'h0}, (/*XY[31]?-XY:*/XY), _d_out1 );
 
 
wire signed [31:0] X_D;
wire signed [31:0] Y_D;
wire signed [31:0] Z_D;
wire signed [31:0] s_out1;
wire signed [31:0] s_out2;
wire signed [47:0] a_out2 =_a_out2>>>3;
wire signed [47:0] a_out1 =`ABS(_a_out1);
wire signed [17:0] _a_out2;
wire signed [17:0] _a_out1;
wire signed [31:0] d_out;
wire signed [31:0] XX= ( (X_in>>>1)*(X_in>>>1) ); // 30
wire signed [31:0] YY= ( (Y_in>>>1)*(Y_in>>>1) ); // 30
wire signed [31:0] MXXYY1= 32'h40000000 - (XX+YY); // 30
wire signed [31:0] MXXYY= (MXXYY1[31]) ? 0:(MXXYY1<<1) ; // 31
wire signed [31:0] MYY= (MXXYY1[31]) ? 0:(-YY<<1) ; // 31
//wire signed [31:0] MXXYY= 32'h00010000 - (XX+YY);
//wire signed [31:0] MYY= 32'h00010000 - YY;
 
atan2_pipelined atan1( clk, s_out1[31:14], Y_in, _a_out1, dummy1 );
atan2_pipelined atan2( clk, X_in, s_out2[28:13], _a_out2, dummy2 );
//atan2_pipelined atan1( clk, s_out1, Y_D, a_out1, dummy1 );
//atan2_pipelined atan2( clk, X_D, s_out2, a_out2, dummy2 );
 
defparam atan1.IS_IBNIZ= 1;
defparam atan2.IS_IBNIZ= 1;
//div_pipelined mydiv( clk, a_out<<12, pix2, d_out );
//id_pipelined id1( clk, X_in, X_D );
//defparam id1.DELAY= 32;
//id_pipelined id2( clk, Y_in, Y_D );
//defparam id2.DELAY= 32;
id_pipelined id3( clk, s_out2[28:13], Z_D );
defparam id3.DELAY= 64;
 
sqrt_pipelined sqrt1( clk, MYY[31:4], s_out1[31:0], _ );
sqrt_pipelined sqrt2( clk, MXXYY[31:4], s_out2[31:0], _ );
//sqrt_pipelined sqrt2( clk, MXXYY[16:1], s_out2[15:0], _ );
//defparam sqrt2.BITS= 20;
//defparam sqrt1.BITS= 20;
 
endmodule
 
 
//============================= ATAN2 ===================================
module PseudoSin ( clk, rst, ena, _X_in, S_out, R_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] _X_in;
output reg [31:0] S_out;
output reg [15:0] R_out;
 
wire signed [31:0] XX_in= 32'h00007fff-{ {16{1'b0}}, {_X_in[15:0]} };
wire signed [31:0] X_in=
`ABS(XX_in) < 32'h00000100 ? 32'h00000100 :
XX_in;
reg signed [31:0] X1;
reg signed [31:0] X2;
reg signed [31:0] X2d;
reg signed [31:0] X3;
reg sgn_x;
reg _sgn_x;
reg [15:0]rgn_x;
reg [15:0]_rgn_x;
 
always@(posedge clk or posedge rst)
begin
if ( rst )
begin
end
else if ( ena )
begin
// 1 ступень конвеера
X1<= `ABS(X_in);
X2<= ((X_in) * (X_in))>>>16;
_sgn_x<= _X_in[16];
_rgn_x<= _X_in[31:16];
// 2 ступень конвеера
X2d<= X2;
X3<= (X1 * X2)>>>16;
sgn_x<= _sgn_x;
rgn_x<=_rgn_x;
// 3 ступень конвеера
R_out<=rgn_x;
S_out<= (((1<<15)-(3*X2d-2*X3)) ) * (sgn_x ? -2:2);//
end
end
 
endmodule
 
 
 
 
module Psin_Texture ( clk, rst, ena, T_in, _X_in, _Y_in, V_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] T_in;
input wire signed [31:0] _X_in;
input wire signed [31:0] _Y_in;
output reg [31:0] V_out;
 
reg signed [31:0] SXSY;
wire signed [31:0] _SSS;
wire signed [31:0] MSSS= -_SSS;
wire signed [31:0] etalon;
 
wire signed [31:0] RX;
wire signed [31:0] RY;
 
wire signed [15:0] NX;
wire signed [15:0] NY;
wire signed [15:0] NXd;
wire signed [15:0] NYd;
wire signed [15:0] PXY= NXd+NYd;
wire signed [15:0] MXY= NXd-NYd;
wire signed [31:0] NXY= _SSS>0 ? (PXY[3]?{ PXY[3:0], 4'b0, PXY[3:0]*PXY[7:4], 4'b0, (_SSS[15:0]) } :0) :
(MXY[3]?{ MXY[4:1], 4'b0, MXY[3:0]*MXY[7:4], 4'b0, (MSSS[15:0]) } :0);
 
 
always@(posedge clk or posedge rst)
begin
if ( rst )
begin
end
else if ( ena )
begin
SXSY<= ( ((( RX>>>7)*( RY>>>7))) )/2;
V_out<=
// _X_in==0 && _Y_in[8]==0 ? 32'haaaaaaaa :
// _Y_in<32'h00008000 ? SXSY :
NXY;
// V_out= _Y_in==0 || _X_in==0 ? 32'haaaaaaaa : (((RX)>_Y_in ? -1:0) ^ ((etalon)>_Y_in ? 32'h33333333:0) );//+32'sh00008000;
end
end
 
sin_pipelined sin1( clk, _X_in, etalon, _, _ );
 
PseudoSin psinX( clk, rst, ena, _X_in*8, RX, NX );
PseudoSin psinY( clk, rst, ena, _Y_in*8, RY, NY );
 
PseudoSin psinV( clk, rst, ena, SXSY*2, _SSS, _ );
id_pipelined idnx( clk, NX, NXd );
id_pipelined idny( clk, NY, NYd );
defparam idnx.DELAY= 4;
defparam idny.DELAY= 4;
 
endmodule
 
 
//============================= rotate sphere ===================================
module Ibniz_generator6 ( clk, rst, ena, T_in, _X_in, _Y_in, V_out, dbg_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] T_in;
input wire signed [31:0] _X_in;
input wire signed [31:0] _Y_in;
output reg [31:0] V_out;
output reg signed [63:0] dbg_out;
reg signed [31:0] V_out2;
 
wire signed [31:0] __X_in= _X_in+(48<<7);
 
reg signed [31:0] X_in;
wire signed [31:0] Y_in =_Y_in>0 ? (_Y_in - 32'h8008)*2 : (_Y_in + 32'h8008)*2;//-_Y_in)*3/4;
 
reg [31:0] R1;
reg [31:0] R2;
reg [31:0] R3;
 
always@(posedge clk or posedge rst)
begin
if ( rst )
begin
end
else if ( ena )
begin
X_in =__X_in>(32'sd16<<<8) ? (__X_in - 32'h9000)*2 : (__X_in + 32'h8000)*2;//+_Y_in)*3/4;
//R1 <= (((X_in+T_in[31:12])>>>7)) * 11713 + ((Y_in>>>8)+(Y_in)) * 5422133;
//R2 <= R1 * 7 + (R1>>8)*1817 ;
//R3 <= { R2[7:0],R2[15:8],R2[23:16], R2[7:0] ^ R2[15:8] ^ R2[23:16] ^ R2[31:24] };
// &*
// V_out2= ((d_out1*Z_D)>>>16 );//32'h00408000 +
// V_out= ( (V3<<16)+(V2<<8)+((V1*Z_D)>>>16));
// V_out= ( T_in[24] ? (a_out2^(a_out1<<<2)) : ( a_out1<<<2 )+16'h8000 );
V_out= Z_D<5 ? 0://(R3[7:0] ? 0 : R3[8] ? -1 : R3) :
d_out1;//(a_out2<<<3) ^(( a_out1<<<3 ) );//+16'h8000
end
end
 
//wire signed [47:0] XY= ((a_out1)<<<3)+(a_out2)-48'h00010000;
wire signed [31:0] d_out1= ((a_out1<<<4)+( _X_in>0 ? (T_in>>>10):0 ))^((a_out2<<<4)+( _Y_in>0 ? (T_in>>>10):0 ));
//wire signed [47:0] _d_out1;
 
//div_pipelined div1( clk, {T_in, 22'h0}, (/*XY[31]?-XY:*/XY), _d_out1 );
 
 
wire signed [31:0] X_D;
wire signed [31:0] Y_D;
wire signed [31:0] Z_D;
wire signed [31:0] s_out1;
wire signed [31:0] s_out2;
wire signed [47:0] a_out2 =_a_out2>>>3;
wire signed [47:0] a_out1 =`ABS(_a_out1>>>1);
wire signed [31:0] _a_out2;
wire signed [17:0] _a_out1;
wire signed [31:0] d_out;
wire signed [31:0] XX= ( (X_in>>>2)*(X_in>>>2) ); // 30
wire signed [31:0] YY= ( (Y_in>>>2)*(Y_in>>>2) ); // 30
wire signed [31:0] MXXYY1= 32'h10000000 - (XX+YY); // 30
wire signed [31:0] MXXYY= (MXXYY1[31]) ? 0:(MXXYY1<<3) ; // 31
wire signed [31:0] MYY= (MXXYY1[31]) ? 0:(-YY<<1) ; // 31
//wire signed [31:0] MXXYY= 32'h00010000 - (XX+YY);
//wire signed [31:0] MYY= 32'h00010000 - YY;
 
atan2_pipelined atan1( clk, s_out1[31:14], Y_in, _a_out1, dummy1 ); //16
atan2_pipelined atan2( clk, X_in-(32'sd32<<<8), s_out2[31:13], _a_out2, dummy2 );
//atan2_pipelined atan1( clk, s_out1, Y_D, a_out1, dummy1 );
//atan2_pipelined atan2( clk, X_D, s_out2, a_out2, dummy2 );
 
defparam atan1.IS_IBNIZ= 1;
defparam atan2.IS_IBNIZ= 1;
//div_pipelined mydiv( clk, a_out<<12, pix2, d_out );
//id_pipelined id1( clk, X_in, X_D );
//defparam id1.DELAY= 32;
//id_pipelined id2( clk, Y_in, Y_D );
//defparam id2.DELAY= 32;
id_pipelined id3( clk, s_out2[28:13], Z_D );
defparam id3.DELAY= 16;
 
sqrt_pipelined sqrt1( clk, MYY[31:4], s_out1[31:0], _ ); //32
sqrt_pipelined sqrt2( clk, MXXYY[31:4], s_out2[31:0], _ );
//sqrt_pipelined sqrt2( clk, MXXYY[16:1], s_out2[15:0], _ );
//defparam sqrt2.BITS= 20;
//defparam sqrt1.BITS= 20;
 
endmodule
 

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