URL
https://opencores.org/ocsvn/plb2wbbridge/plb2wbbridge/trunk
Subversion Repositories plb2wbbridge
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Rev 1 → Rev 2
/trunk/coregen/fifo_generator/plb2wb_bridge.setup
0,0 → 1,28
Device_Family = virtex5 |
Device = xc5vlx50 |
Package = ff676 |
Speedgrade = -2 |
|
|
# Path to the vhdl and implementation directory |
PLB2WB_Bridge_VHDL_DIR = ../../systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/ |
PLB2WB_Bridge_NGC_DIR = ../../systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/ise/work/ |
|
Address_Buffer_Size = 16 # valid values: 16, 32, ... 4194304 |
Read_Buffer_Size = 16 # valid values: 16, 32, ... 4194304 |
Write_Buffer_Size = 16 # valid values: 16, 32, ... 4194304 |
Stat2WB_Buffer_Size = 16 # valid values: 16, 32, ... 4194304 |
Stat2PLB_Buffer_Size = 16 # valid values: 16, 32, ... 4194304 |
WB_Clk_Frequency = 66 # MHz |
PLB_Clk_Frequency = 100 # MHz |
|
|
################################ |
# Do not change below unless |
# you know what you are doing |
|
Address_Buffer_minDWidth = 42 # 32 bit address, 4 bit BE, 4 bit size, 1 RNW, minimum 1 bit master-id |
Read_Buffer_DWidth = 33 # 32 bit datum and 1 bit error |
Write_Buffer_DWidth = 32 |
Stat2PLB_Buffer_minDWidth = 100 # 32 bit address, 32 bit datum, 3 bit status info, 1-4 bit master-id, 32 bit irq-info |
Stat2WB_Buffer_DWidth = 1 |
/trunk/coregen/fifo_generator/fifo_generator.rb
0,0 → 1,723
#!/usr/bin/ruby |
|
# Usage: ruby fifo_generator [OPTIONS]... setup-file |
# |
# OPTIONS: |
# |
# -c --no-coregen do not run coregen (Only creates *.xco command_files) |
# -v --cp-vhdl-to-lib copy vhdl-files to library folder |
# (path is set in 'setup-file') |
# -n --cp-ngc-to_imp copy netlist-files to implementation folder |
# (path is set in 'setup_file') |
# -? --help display this message |
# |
require 'pp' |
require 'getoptlong' |
require 'rdoc/usage' |
#======================================================================= |
# |
# _____ _ __ ____ _ |
# | ___(_)/ _| ___ / ___| ___ _ __ ___ _ __ __ _| |_ ___ _ __ |
# | |_ | | |_ / _ \ _____| | _ / _ \ '_ \ / _ \ '__/ _` | __/ _ \| '__| |
# | _| | | _| (_) |_____| |_| | __/ | | | __/ | | (_| | || (_) | | |
# |_| |_|_| \___/ \____|\___|_| |_|\___|_| \__,_|\__\___/|_| |
# _______________________________________________ |
# _________________________________________________________ |
# |
# |
# |
# |
# |
# |
# |
# |
#======================================================================= |
# |
# |
# Global constants/strings |
# |
#======================================================================= |
|
BASE_INFO=" |
###################### |
# |
# Auto generated by 'fifo_generator.rb'. |
# Please modify only 'plb2wb_bridge.setup', |
# modifications to this file will be overwritten! |
# |
#### |
" |
BASE_SELECT=" |
SELECT Fifo_Generator family Xilinx,_Inc. 5.3 |
" |
# CSET use_extra_logic=false ?? |
#======================================================================= |
# |
# |
# Global variables |
# |
#======================================================================= |
$plb2wb_bridge_vhdl_dir = nil |
$plb2wb_bridge_ngc_dir = nil |
$address_buffer_size = nil |
$read_buffer_size = nil |
$write_buffer_size = nil |
$device = nil |
$device_family = nil |
$package = nil |
$speedgrade = nil |
$address_buffer_mindwidth = nil |
$read_buffer_dwidth = nil |
$write_buffer_dwidth = nil |
$wb_clk_frequency = nil |
$plb_clk_frequency = nil |
$mid2plb_buffer_size = nil |
$stat2plb_buffer_size = nil |
$stat2plb_buffer_mindwidth = nil |
$stat2wb_buffer_size = nil |
$stat2wb_buffer_dwidth = nil |
$opt_no_coregen = false |
$opt_cp_vhdl = false |
$opt_cp_ngc = false |
|
#======================================================================= |
# |
# |
# functions to set and check gloval variables |
# |
#======================================================================= |
def all_items_set? |
|
all_items_set = true; |
|
if $address_buffer_size == nil |
all_items_set = false; |
print "'Address_Buffer_Size' is not set in setup file\n" |
end |
if $read_buffer_size == nil |
all_items_set = false; |
print "'Read_Buffer_Size' is not set in setup file\n" |
end |
if $write_buffer_size == nil |
all_items_set = false; |
print "'Write_Buffer_Size' is not set in setup file\n" |
end |
if $device == nil |
all_items_set = false; |
print "'Device' is not set in setup file\n" |
end |
if $device_family == nil |
all_items_set = false; |
print "'Device_Family' is not set in setup file\n" |
end |
if $package == nil |
all_items_set = false; |
print "'Package' is not set in setup file\n" |
end |
if $speedgrade == nil |
all_items_set = false; |
print "'Speedgrade' is not set in setup file\n" |
end |
if $address_buffer_mindwidth == nil |
all_items_set = false; |
print "'Address_Buffer_minDWidth' is not set in setup file\n" |
end |
if $read_buffer_dwidth == nil |
all_items_set = false; |
print "'Read_Buffer_DWidth' is not set in setup file\n" |
end |
if $write_buffer_dwidth == nil |
all_items_set = false; |
print "'Write_Buffer_DWidth' is not set in setup file\n" |
end |
if $wb_clk_frequency == nil |
all_items_set = false; |
print "'PLB_Clk_Frequency' is not set in setup file\n" |
end |
if $plb_clk_frequency == nil |
all_items_set = false; |
print "'WB_Clk_Frequency' is not set in setup file\n" |
end |
if $stat2plb_buffer_size == nil |
all_items_set = false; |
print "'Stat2PLB_Buffer_Size' is not set in setup file\n" |
end |
if $stat2plb_buffer_mindwidth == nil |
all_items_set = false; |
print "'Stat2PLB_Buffer_minDWidth' is not set in setup file\n" |
end |
if $stat2wb_buffer_size == nil |
all_items_set = false; |
print "'Stat2WB_Buffer_Size' is not set in setup file\n" |
end |
if $stat2wb_buffer_dwidth == nil |
all_items_set = false; |
print "'Stat2WB_Buffer_DWidth' is not set in setup file\n" |
end |
return all_items_set |
end |
|
|
def set_item( item, value ) |
|
|
case item |
when "PLB2WB_Bridge_VHDL_DIR" |
$plb2wb_bridge_vhdl_dir = value |
when "Address_Buffer_Size" |
if value =~ /^[0-9]*$/ |
$address_buffer_size = value |
else |
print "Invalid format for `Address_Buffer_Size` in setup file\n";exit |
end |
when "Read_Buffer_Size" |
if value =~ /^[0-9]*$/ |
$read_buffer_size = value |
else |
print "Invalid format for `Read_Buffer_Size` in setup file\n";exit |
end |
when "Write_Buffer_Size" |
if value =~ /^[0-9]*$/ |
$write_buffer_size = value |
else |
print "Invalid format for `Write_Buffer_Size` in setup file\n";exit |
end |
when "Device_Family" |
$device_family = value |
when "Device" |
$device = value |
when "Package" |
$package = value |
when "Speedgrade" |
if value =~ /^\-[0-9]*$/ |
$speedgrade = value |
end |
when "Address_Buffer_minDWidth" |
if value =~ /^[0-9]*$/ |
$address_buffer_mindwidth = value |
else |
print "Invalid format for `Address_Buffer_minDWidth` in setup file\n";exit |
end |
when "Read_Buffer_DWidth" |
if value =~ /^[0-9]*$/ |
$read_buffer_dwidth = value |
else |
print "Invalid format for `Read_Buffer_DWidth` in setup file\n";exit |
end |
when "Write_Buffer_DWidth" |
if value =~ /^[0-9]*$/ |
$write_buffer_dwidth = value |
else |
print "Invalid format for `Write_Buffer_DWidth` in setup file\n";exit |
end |
when "WB_Clk_Frequency" |
if value =~ /^[0-9]*$/ |
$wb_clk_frequency = value |
else |
print "Invalid format for `WB_Clk_Frequency` in setup file\n";exit |
end |
when "PLB_Clk_Frequency" |
if value =~ /^[0-9]*$/ |
$plb_clk_frequency = value |
else |
print "Invalid format for `PLB_Clk_Frequency` in setup file\n";exit |
end |
when "PLB2WB_Bridge_NGC_DIR" |
$plb2wb_bridge_ngc_dir = value |
|
when "Stat2PLB_Buffer_Size" |
if value =~ /^[0-9]*$/ |
$stat2plb_buffer_size = value |
else |
print "Invalid format for `Stat2PLB_Buffer_Size` in setup file\n";exit |
end |
|
when "Stat2PLB_Buffer_minDWidth" |
if value =~ /^[0-9]*$/ |
$stat2plb_buffer_mindwidth = value |
else |
print "Invalid format for `Stat2PLB_Buffer_minDWidth` in setup file\n";exit |
end |
|
when "Stat2WB_Buffer_Size" |
if value =~ /^[0-9]*$/ |
$stat2wb_buffer_size = value |
else |
print "Invalid format for `Stat2WB_Buffer_Size` in setup file\n";exit |
end |
|
when "Stat2WB_Buffer_DWidth" |
if value =~ /^[0-9]*$/ |
$stat2wb_buffer_dwidth = value |
else |
print "Invalid format for `Stat2WB_Buffer_DWidth` in setup file\n";exit |
end |
|
end |
|
end |
#======================================================================= |
# |
# |
# *.XCO-File generation helpers |
# |
#======================================================================= |
def print_project_header( file ) |
|
file.puts( "SET addpads = False" ) |
file.puts( "SET asysymbol = True" ) |
file.puts( "SET busformat = BusFormatParenNotRipped") |
file.puts( "SET createndf = False" ) |
file.puts( "SET designentry = VHDL" ) |
file.puts( "SET device = " + $device ) |
file.puts( "SET devicefamily = " + $device_family ) |
file.puts( "SET flowvendor = Other" ) |
file.puts( "SET formalverification = False" ) |
file.puts( "SET foundationsym = False" ) |
file.puts( "SET implementationfiletype = Ngc" ) |
file.puts( "SET package = " + $package ) |
file.puts( "SET removerpms = False" ) |
file.puts( "SET simulationfiles = Structural" ) |
file.puts( "SET speedgrade = " + $speedgrade ) |
file.puts( "SET verilogsim = False" ) |
file.puts( "SET vhdlsim = True" ) |
|
|
|
|
end |
|
|
def print_fifo_parameters( file, independet_clocks, component_name, deepth, width, r_clk_frq, w_clk_frq, with_almost_empty ) |
|
data_count_width = Math.log( deepth ) / Math.log( 2 ) |
|
if with_almost_empty |
file.puts( "CSET almost_empty_flag=true" ) |
else |
file.puts( "CSET almost_empty_flag=false" ) |
end |
file.puts( "CSET almost_full_flag=false" ) |
file.puts( "CSET component_name=#{component_name}" ) |
file.puts( "CSET data_count=false" ) |
file.puts( "CSET data_count_width=#{data_count_width.to_i}" ) |
file.puts( "CSET disable_timing_violations=false" ) |
file.puts( "CSET dout_reset_value=0" ) |
file.puts( "CSET empty_threshold_assert_value=1" ) |
file.puts( "CSET empty_threshold_negate_value=1" ) |
file.puts( "CSET enable_ecc=false" ) |
file.puts( "CSET enable_int_clk=false" ) |
file.puts( "CSET enable_reset_synchronization=true" ) |
if independet_clocks == false |
#common clocks |
if deepth.to_i < 512 |
file.puts( "CSET fifo_implementation=Common_Clock_Distributed_RAM" ) |
else |
if with_almost_empty |
file.puts( "CSET fifo_implementation=Common_Clock_Block_RAM" ) |
else |
file.puts( "CSET fifo_implementation=Common_Clock_Builtin_FIFO" ) |
end |
end |
else |
#independet clocks |
if deepth.to_i < 512 |
file.puts( "CSET fifo_implementation=Independent_Clocks_Distributed_RAM" ) |
else |
if with_almost_empty |
file.puts( "CSET fifo_implementation=Independent_Clocks_Block_RAM" ) |
else |
file.puts( "CSET fifo_implementation=Independent_Clocks_Builtin_FIFO" ) |
end |
end |
end |
file.puts( "CSET full_flags_reset_value=0" ) |
file.puts( "CSET full_threshold_assert_value=1" ) |
file.puts( "CSET full_threshold_negate_value=1" ) |
file.puts( "CSET inject_dbit_error=false" ) |
file.puts( "CSET inject_sbit_error=false" ) |
file.puts( "CSET input_data_width=#{width}" ) |
file.puts( "CSET input_depth=#{deepth}" ) |
file.puts( "CSET output_data_width=#{width}" ) |
file.puts( "CSET output_depth=#{deepth}" ) |
file.puts( "CSET overflow_flag=false" ) |
file.puts( "CSET overflow_sense=Active_High" ) |
file.puts( "CSET performance_options=First_Word_Fall_Through" ) |
file.puts( "CSET programmable_empty_type=No_Programmable_Empty_Threshold" ) |
file.puts( "CSET programmable_full_type=No_Programmable_Full_Threshold" ) |
if deepth.to_i < 512 or independet_clocks == false |
file.puts( "CSET read_clock_frequency=1" ) |
else |
file.puts( "CSET read_clock_frequency=#{r_clk_frq}" ) |
end |
file.puts( "CSET read_data_count=false" ) |
file.puts( "CSET read_data_count_width=#{data_count_width.to_i}" ) |
file.puts( "CSET reset_pin=true" ) |
file.puts( "CSET reset_type=Asynchronous_Reset" ) |
file.puts( "CSET underflow_flag=false" ) |
file.puts( "CSET underflow_sense=Active_High" ) |
file.puts( "CSET use_dout_reset=false" ) |
file.puts( "CSET use_embedded_registers=false" ) |
file.puts( "CSET valid_flag=false" ) |
file.puts( "CSET valid_sense=Active_High" ) |
file.puts( "CSET write_acknowledge_flag=false" ) |
file.puts( "CSET write_acknowledge_sense=Active_High" ) |
if deepth.to_i < 512 or independet_clocks == false |
file.puts( "CSET write_clock_frequency=1" ) |
else |
file.puts( "CSET write_clock_frequency=#{w_clk_frq}" ) |
end |
file.puts( "CSET write_data_count=false" ) |
file.puts( "CSET write_data_count_width=#{data_count_width.to_i}" ) |
|
|
end |
#====================================================================== |
# |
# XCO-File generation and syntehsis functions |
# |
# |
#====================================================================== |
|
|
|
def generate_adr_fifos( independet_clocks ) |
|
cc_or_ic = (independet_clocks == true)? "ic" : "cc" |
|
open( "fifo_adr_#{cc_or_ic}_1.xco", "w" ) do |file| |
file.puts( BASE_INFO ) |
print_project_header( file ) |
file.puts( BASE_SELECT ) |
print_fifo_parameters( file, |
independet_clocks, |
"fifo_adr_#{cc_or_ic}_1", |
$address_buffer_size, |
$address_buffer_mindwidth.to_i, |
$wb_clk_frequency, |
$plb_clk_frequency, |
false ) |
file.puts( "GENERATE" ) |
file.close |
end |
|
|
|
open( "fifo_adr_#{cc_or_ic}_2.xco", "w" ) do |file| |
file.puts( BASE_INFO ) |
print_project_header( file ) |
file.puts( BASE_SELECT ) |
print_fifo_parameters( file, |
independet_clocks, |
"fifo_adr_#{cc_or_ic}_2", |
$address_buffer_size, |
$address_buffer_mindwidth.to_i + 1, |
$wb_clk_frequency, |
$plb_clk_frequency, |
false ) |
file.puts( "GENERATE" ) |
file.close |
end |
|
|
|
|
open( "fifo_adr_#{cc_or_ic}_3.xco", "w" ) do |file| |
file.puts( BASE_INFO ) |
print_project_header( file ) |
file.puts( BASE_SELECT ) |
print_fifo_parameters( file, |
independet_clocks, |
"fifo_adr_#{cc_or_ic}_3", |
$address_buffer_size, |
$address_buffer_mindwidth.to_i + 2, |
$wb_clk_frequency, |
$plb_clk_frequency, |
false ) |
file.puts( "GENERATE" ) |
file.close |
end |
|
|
|
|
open( "fifo_adr_#{cc_or_ic}_4.xco", "w" ) do |file| |
file.puts( BASE_INFO ) |
print_project_header( file ) |
file.puts( BASE_SELECT ) |
print_fifo_parameters( file, |
independet_clocks, |
"fifo_adr_#{cc_or_ic}_4", |
$address_buffer_size, |
$address_buffer_mindwidth.to_i + 3, |
$wb_clk_frequency, |
$plb_clk_frequency, |
false ) |
file.puts( "GENERATE" ) |
file.close |
end |
|
|
system( "coregen -b fifo_adr_#{cc_or_ic}_1.xco" ) if $opt_no_coregen == false |
system( "coregen -b fifo_adr_#{cc_or_ic}_2.xco" ) if $opt_no_coregen == false |
system( "coregen -b fifo_adr_#{cc_or_ic}_3.xco" ) if $opt_no_coregen == false |
system( "coregen -b fifo_adr_#{cc_or_ic}_4.xco" ) if $opt_no_coregen == false |
|
end |
|
|
def generate_wdat_fifos( independet_clocks ) |
|
|
cc_or_ic = (independet_clocks == true)? "ic" : "cc" |
|
open( "fifo_wdat_#{cc_or_ic}_32.xco", "w" ) do |file| |
file.puts( BASE_INFO ) |
print_project_header( file ) |
file.puts( BASE_SELECT ) |
print_fifo_parameters( file, |
independet_clocks, |
"fifo_wdat_#{cc_or_ic}_32", |
$write_buffer_size, |
$write_buffer_dwidth.to_i, |
$wb_clk_frequency, |
$plb_clk_frequency, |
false ) |
file.puts( "GENERATE" ) |
file.close |
end |
|
system( "coregen -b fifo_wdat_#{cc_or_ic}_32.xco" ) if $opt_no_coregen == false |
|
end |
|
|
def generate_rdat_fifos( independet_clocks ) |
|
|
cc_or_ic = (independet_clocks == true)? "ic" : "cc" |
|
open( "fifo_rdat_#{cc_or_ic}_32.xco", "w" ) do |file| |
file.puts( BASE_INFO ) |
print_project_header( file ) |
file.puts( BASE_SELECT ) |
print_fifo_parameters( file, |
independet_clocks, |
"fifo_rdat_#{cc_or_ic}_32", |
$read_buffer_size, |
$read_buffer_dwidth.to_i, |
$plb_clk_frequency, |
$wb_clk_frequency, |
true ) |
file.puts( "GENERATE" ) |
file.close |
end |
|
system( "coregen -b fifo_rdat_#{cc_or_ic}_32.xco" ) if $opt_no_coregen == false |
|
end |
|
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def generate_stat2plb_fifos( independet_clocks ) |
|
cc_or_ic = (independet_clocks == true)? "ic" : "cc" |
|
|
|
open( "fifo_stat2plb_#{cc_or_ic}_1.xco", "w" ) do |file| |
file.puts( BASE_INFO ) |
print_project_header( file ) |
file.puts( BASE_SELECT ) |
print_fifo_parameters( file, |
independet_clocks, |
"fifo_stat2plb_#{cc_or_ic}_1", |
$stat2plb_buffer_size, |
$stat2plb_buffer_mindwidth.to_i, |
$plb_clk_frequency, |
$wb_clk_frequency, |
false ) |
file.puts( "GENERATE" ) |
file.close |
end |
|
|
|
open( "fifo_stat2plb_#{cc_or_ic}_2.xco", "w" ) do |file| |
file.puts( BASE_INFO ) |
print_project_header( file ) |
file.puts( BASE_SELECT ) |
print_fifo_parameters( file, |
independet_clocks, |
"fifo_stat2plb_#{cc_or_ic}_2", |
$stat2plb_buffer_size, |
$stat2plb_buffer_mindwidth.to_i + 1, |
$plb_clk_frequency, |
$wb_clk_frequency, |
false ) |
file.puts( "GENERATE" ) |
file.close |
end |
|
|
|
open( "fifo_stat2plb_#{cc_or_ic}_3.xco", "w" ) do |file| |
file.puts( BASE_INFO ) |
print_project_header( file ) |
file.puts( BASE_SELECT ) |
print_fifo_parameters( file, |
independet_clocks, |
"fifo_stat2plb_#{cc_or_ic}_3", |
$stat2plb_buffer_size, |
$stat2plb_buffer_mindwidth.to_i + 2, |
$plb_clk_frequency, |
$wb_clk_frequency, |
false ) |
file.puts( "GENERATE" ) |
file.close |
end |
|
|
|
open( "fifo_stat2plb_#{cc_or_ic}_4.xco", "w" ) do |file| |
file.puts( BASE_INFO ) |
print_project_header( file ) |
file.puts( BASE_SELECT ) |
print_fifo_parameters( file, |
independet_clocks, |
"fifo_stat2plb_#{cc_or_ic}_4", |
$stat2plb_buffer_size, |
$stat2plb_buffer_mindwidth.to_i + 3, |
$plb_clk_frequency, |
$wb_clk_frequency, |
false ) |
file.puts( "GENERATE" ) |
file.close |
end |
|
system( "coregen -b fifo_stat2plb_#{cc_or_ic}_1.xco" ) if $opt_no_coregen == false |
system( "coregen -b fifo_stat2plb_#{cc_or_ic}_2.xco" ) if $opt_no_coregen == false |
system( "coregen -b fifo_stat2plb_#{cc_or_ic}_3.xco" ) if $opt_no_coregen == false |
system( "coregen -b fifo_stat2plb_#{cc_or_ic}_4.xco" ) if $opt_no_coregen == false |
|
end |
|
def generate_stat2wb_fifos( independet_clocks ) |
|
cc_or_ic = (independet_clocks == true)? "ic" : "cc" |
|
open( "fifo_stat2wb_#{cc_or_ic}.xco", "w" ) do |file| |
file.puts( BASE_INFO ) |
print_project_header( file ) |
file.puts( BASE_SELECT ) |
print_fifo_parameters( file, |
independet_clocks, |
"fifo_stat2wb_#{cc_or_ic}", |
$stat2wb_buffer_size, |
$stat2wb_buffer_dwidth.to_i, |
$plb_clk_frequency, |
$wb_clk_frequency, |
false ) |
file.puts( "GENERATE" ) |
file.close |
end |
|
system( "coregen -b fifo_stat2wb_#{cc_or_ic}.xco" ) if $opt_no_coregen == false |
|
end |
|
|
|
#================================================================= |
# |
# Main-script starts here: |
# |
#================================================================= |
opts= GetoptLong.new( |
['--no-coregen', '-c', GetoptLong::NO_ARGUMENT], |
['--cp-vhdl-to-lib', '-v', GetoptLong::NO_ARGUMENT], |
['--cp-ngc-to-imp', '-n', GetoptLong::NO_ARGUMENT], |
['--help', '-?', GetoptLong::NO_ARGUMENT] |
) |
|
|
opts.each do |opt, arg| |
case opt |
when '--no-coregen' |
$opt_no_coregen = true |
when '--cp-vhdl-to-lib' |
$opt_cp_vhdl = true |
when '--cp-ngc-to-imp' |
$opt_cp_ngc = true |
when '--help' |
RDoc::usage |
end |
end |
|
if ARGV.length != 1 |
RDoc::usage |
end |
|
|
|
if File.exists? ARGV[0] |
|
|
open( 'plb2wb_bridge.setup' ) do |file| |
file.each { |line| |
|
# check, if this is a valid setup-line |
if line =~ /[\s]*([a-zA-Z0-9_]+)[\s]*=[\s]*([\-0-9a-zA-Z\.\/_]+)/ |
set_item( $1, $2 ) |
end |
} |
end |
else |
print "#{ARGV[0]} not found!\n\n" |
RDoc::usage |
end |
|
|
|
|
if all_items_set? |
|
generate_stat2plb_fifos ( true ) |
generate_stat2plb_fifos ( false ) |
generate_adr_fifos ( true ) |
generate_adr_fifos ( false ) |
generate_wdat_fifos ( true ) |
generate_wdat_fifos ( false ) |
generate_rdat_fifos ( true ) |
generate_rdat_fifos ( false ) |
generate_stat2wb_fifos ( true ) |
generate_stat2wb_fifos ( false ) |
|
|
|
if $opt_cp_vhdl |
if $plb2wb_bridge_vhdl_dir == nil |
print "'PLB2WB_Bridge_VHDL_Dir' is not set in plb2wb_bridge.setup\n" |
else |
system( "cp *.vhd #{$plb2wb_bridge_vhdl_dir }" ) |
print "Copy vhdl-files to '#{$plb2wb_bridge_vhdl_dir}'\n" |
end |
end |
|
if $opt_cp_ngc |
if $plb2wb_bridge_ngc_dir == nil |
print "'PLB2WB_Bridge_NGC_Dir' is not set in plb2wb_bridge.setup\n" |
else |
print "Copy netlists to '#{$plb2wb_bridge_ngc_dir}'\n" |
system( "cp *.ngc #{$plb2wb_bridge_ngc_dir }" ) |
end |
end |
|
else |
print "Please complete 'plb2wb_bridge.setup'\n" |
exit |
end |
|
|
|
|
#================================================================= |
trunk/coregen/fifo_generator/fifo_generator.rb
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/doc/plb2wb_bridge_spec.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/plb2wb_bridge_spec.pdf
===================================================================
--- trunk/doc/plb2wb_bridge_spec.pdf (nonexistent)
+++ trunk/doc/plb2wb_bridge_spec.pdf (revision 2)
trunk/doc/plb2wb_bridge_spec.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/systems/dev_system_sim/simulation/testbench/system_tb.vhd
===================================================================
--- trunk/systems/dev_system_sim/simulation/testbench/system_tb.vhd (nonexistent)
+++ trunk/systems/dev_system_sim/simulation/testbench/system_tb.vhd (revision 2)
@@ -0,0 +1,161 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+entity system_tb is
+end system_tb;
+
+architecture STRUCTURE of system_tb is
+
+ constant sys_clk_period : time := 10.000000 ns;
+ constant wb_clk_period : time := 13.333333 ns;
+ constant sys_rst_length : time := 160 ns;
+
+ constant SYNCH_PART : integer := 1;
+ constant SYNCH_SUBPART : integer := 2;
+ constant SYNCH_SUBSUBPART : integer := 3;
+
+ constant SUBSUBPART_LENGTH : integer := 15; -- 10 clock cycles
+ constant SUBPART_LENGTH : integer := 5; -- 7 times SUBSUBPART_LENGTH
+ constant PART_LENGTH : integer := 5; -- 6 times SUBPART_LENGTH
+
+ component system is
+ port (
+ sys_clk_pin : in std_logic;
+ sys_rst_pin : in std_logic;
+ to_synch_in_pin : in std_logic_vector( 0 to 31 );
+ from_synch_out_pin : out std_logic_vector( 0 to 31 );
+ wb_clk_pin : in std_logic;
+ wb_rst_pin : in std_logic
+ );
+ end component;
+
+
+ signal sys_clk : std_logic;
+ signal sys_rst : std_logic := '1';
+ signal wb_clk : std_logic;
+ signal wb_rst : std_logic;
+
+
+ signal to_synch_in : std_logic_vector( 0 to 31 );
+ signal from_synch_out : std_logic_vector( 0 to 31 );
+ signal tb_synch_out : std_logic_vector( 0 to 31 ) := ( others => '0' );
+
+ procedure SendSynch( signal synch_out : OUT std_logic_vector;
+ COMMAND : integer ) is
+ begin
+ synch_out( COMMAND ) <= '1';
+ wait for sys_clk_period*1;
+ synch_out( COMMAND ) <= '0';
+ end procedure SendSynch;
+
+
+begin
+
+ to_synch_in <= from_synch_out or tb_synch_out;
+
+
+
+ dut : system
+ port map (
+ sys_clk_pin => sys_clk,
+ sys_rst_pin => sys_rst,
+ to_synch_in_pin => to_synch_in,
+ from_synch_out_pin => from_synch_out,
+ wb_clk_pin => wb_clk,
+ wb_rst_pin => wb_rst
+ );
+
+
+ --
+ -- generate plb-clk
+ --
+ process
+ begin
+ sys_clk <= '0';
+ loop
+ wait for (sys_clk_period/2);
+ sys_clk <= not sys_clk;
+ end loop;
+ end process;
+
+
+ --
+ --
+ --
+ process
+ begin
+ wb_clk <= '0';
+ loop
+ wait for (wb_clk_period/2);
+ wb_clk <= not wb_clk;
+ end loop;
+ end process;
+
+
+
+
+ process
+ begin
+ sys_rst <= '1';
+ wait for ( sys_rst_length );
+ sys_rst <= not sys_rst;
+ wait;
+ end process;
+
+
+
+
+
+
+ process
+ begin
+ wb_rst <= '1';
+ wait for ( sys_rst_length );
+ wb_rst <= '0';
+ wait for 7500 ns;
+ wb_rst <= '1';
+ wait for wb_clk_period*5;
+ wb_rst <= '0';
+ wait;
+ end process;
+
+
+ process
+ begin
+
+ wait until sys_rst = '0';
+ -- wait until masters a ready
+ wait for sys_clk_period * 10;
+
+
+ while true loop
+ for i in 0 to PART_LENGTH-1 loop
+ SendSynch( tb_synch_out, SYNCH_PART );
+
+ for j in 0 to SUBPART_LENGTH-1 loop
+ SendSynch( tb_synch_out, SYNCH_SUBPART );
+
+ for k in 0 to SUBSUBPART_LENGTH loop
+ SendSynch( tb_synch_out, SYNCH_SUBSUBPART );
+ wait for (SUBSUBPART_LENGTH * sys_clk_period );
+ end loop;
+
+
+ end loop;
+
+
+ end loop;
+
+ end loop;
+
+ end process;
+
+
+
+
+end architecture STRUCTURE;
+
Index: trunk/systems/dev_system_sim/simulation/scripts/wave.do
===================================================================
--- trunk/systems/dev_system_sim/simulation/scripts/wave.do (nonexistent)
+++ trunk/systems/dev_system_sim/simulation/scripts/wave.do (revision 2)
@@ -0,0 +1,286 @@
+
+#
+# Display top-level ports
+#
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+set tbpath {sim:/system_tb/dut}
+
+eval add wave -color DarkGreen -noupdate -divider {"top-level ports"}
+eval add wave -color DarkGreen -noupdate $binopt sim:/system_tb/sys_clk
+eval add wave -color DarkGreen -noupdate $binopt sim:/system_tb/sys_rst
+eval add wave -color DarkGreen -noupdate $binopt sim:/system_tb/dut/plb_bfm_slave/synch_in
+
+
+ # Master signals
+ proc add_master { num color } {
+ global binopt hexopt tbpath
+ eval add wave -color ${color} -noupdate -group Master_${num}
+ eval add wave -color ${color} -label ${num}_m_request -group Master_${num} -noupdate $binopt $tbpath/plb_bfm_master_${num}/m_request
+ eval add wave -color ${color} -label ${num}_m_abus -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_abus
+ eval add wave -color ${color} -label ${num}_m_be -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_be
+ eval add wave -color ${color} -label ${num}_m_rnw -group Master_${num} -noupdate $binopt $tbpath/plb_bfm_master_${num}/m_rnw
+ eval add wave -color ${color} -label ${num}_m_size -group Master_${num} -noupdate $binopt $tbpath/plb_bfm_master_${num}/m_size
+ eval add wave -color ${color} -label ${num}_m_priority -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_priority
+ eval add wave -color ${color} -label ${num}_plb_mrddbus -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/plb_mrddbus
+ eval add wave -color ${color} -label ${num}_m_wrdbus -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_wrdbus
+ }
+ add_master 32 White
+ add_master 64 AliceBlue
+ add_master 128 Seashell
+
+
+
+
+
+# do ../behavioral/mb_plb_wave.do
+# do ../behavioral/plb_bfm_monitor_wave.do
+# do ../behavioral/plb_bfm_slave_wave.do
+
+
+ proc add_ocram { num color } {
+ global binopt hexopt tbpath
+ eval add wave -color ${color} -noupdate -group ocram${num}
+ eval add wave -color ${color} -label wb_stb_i -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_stb_i
+ eval add wave -color ${color} -label wb_ack_o -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_ack_o
+ eval add wave -color ${color} -label wb_err_o -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_err_o
+ eval add wave -color ${color} -label wb_rty_o -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_rty_o
+ eval add wave -color ${color} -label w_ack -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/w_ack
+ eval add wave -color ${color} -label err_rty_count_r -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/err_rty_count_r
+ eval add wave -color ${color} -label err_rty_count_w -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/err_rty_count_w
+ eval add wave -color ${color} -label r_delay_count -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/r_delay_count
+ eval add wave -color ${color} -label w_delay_count -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/w_delay_count
+
+ eval add wave -color ${color} -label ram(0) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(0)
+ eval add wave -color ${color} -label ram(1) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(1)
+ eval add wave -color ${color} -label ram(2) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(2)
+ eval add wave -color ${color} -label ram(3) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(3)
+ eval add wave -color ${color} -label ram(4) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(4)
+ eval add wave -color ${color} -label ram(5) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(5)
+ eval add wave -color ${color} -label ram(6) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(6)
+ eval add wave -color ${color} -label ram(7) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(7)
+ }
+
+
+
+
+ #
+ # General bridge signals
+ #
+ eval add wave -color purple -group bridge_general -noupdate
+ eval add wave -color purple -label sl_addrack -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_addrack
+ eval add wave -color purple -label plb_abus -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb_abus
+ eval add wave -color purple -label plb_be -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb_be
+ eval add wave -color purple -label plb_pavalid -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_pavalid
+ eval add wave -color purple -label plb_savalid -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_savalid
+ eval add wave -color purple -label plb_rnw -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_rnw
+ eval add wave -color purple -label plb_msize -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_msize
+ eval add wave -color purple -label plb_type -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_type
+ eval add wave -color purple -label plb_wrdbus -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb_wrdbus
+ eval add wave -color purple -label sl_rddbus -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/sl_rddbus
+
+ eval add wave -color purple -label sl_wrdack -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_wrdack
+ eval add wave -color maroon -label sl_wrcomp -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_wrcomp
+ eval add wave -color purple -label sl_rddack -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_rddack
+ eval add wave -color maroon -label sl_rdcomp -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_rdcomp
+
+ eval add wave -color maroon -label sl_rdprim -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_rdprim
+ eval add wave -color maroon -label sl_wrprim -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_wrprim
+
+
+ eval add wave -color maroon -label wb_adr_o -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_adr_o
+ eval add wave -color maroon -label wb_cyc_o -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_cyc_o
+ eval add wave -color maroon -label wb_dat_i -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_dat_i
+ eval add wave -color maroon -label wb_dat_o -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_dat_o
+ eval add wave -color maroon -label wb_err_i -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_err_i
+ eval add wave -color maroon -label wb_rst_i -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_rst_i
+ eval add wave -color maroon -label wb_sel_o -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_sel_o
+ eval add wave -color maroon -label wb_stb_o -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_stb_o
+ eval add wave -color maroon -label wb_we_o -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_we_o
+ eval add wave -color maroon -label sl_mbusy -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mbusy
+ eval add wave -color maroon -label sl_mwrerr -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mwrerr
+ eval add wave -color maroon -label sl_mrderr -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mrderr
+
+
+ #
+ # Bridge - Transfer Control Unit
+ #
+ eval add wave -color aquamarine -group bridge_TCU -noupdate
+ eval add wave -color aquamarine -label c_plb_wstate -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/c_plb_wstate
+ eval add wave -color aquamarine -label c_plb_rstate -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/c_plb_rstate
+ eval add wave -color aquamarine -label c_wb_state -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/c_wb_state
+ eval add wave -color aquamarine -label wb_ack -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_ack
+ eval add wave -color aquamarine -label wb_err -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_err
+ eval add wave -color aquamarine -label wb_rty -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_rty
+ eval add wave -color aquamarine -label wb_rst_i -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_rst_i
+ eval add wave -color aquamarine -label wb_rst_short -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_rst_short
+
+ eval add wave -color aquamarine -label tcu_addrack -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_addrack
+ eval add wave -color aquamarine -label sl_rdwdaddr -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/sl_rdwdaddr
+
+ eval add wave -color aquamarine -label tcu_adr_offset -group bridge_TCU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_adr_offset
+ eval add wave -color aquamarine -label tcu_adrbufren -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_adrbufren
+ eval add wave -color aquamarine -label tcu_adrbufwen -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_adrbufwen
+ eval add wave -color aquamarine -label tcu_rpiperden -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_rpiperden
+ eval add wave -color aquamarine -label tcu_wpiperden -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_wpiperden
+
+ eval add wave -color aquamarine -label tcu_enrddbus -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_enrddbus
+ eval add wave -color aquamarine -label tcu_rbufren -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_rbufren
+ eval add wave -color aquamarine -label tcu_rbufwen -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_rbufwen
+ eval add wave -color aquamarine -label tcu_wbufren -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_wbufren
+ eval add wave -color aquamarine -label tcu_wbufwen -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_wbufwen
+
+ eval add wave -color aquamarine -label tcu_enStuRDDbus -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_ensturddbus
+ eval add wave -color aquamarine -label tcu_stuWritePA -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_stuwritepa
+ eval add wave -color aquamarine -label tcu_stuWriteSA -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_stuwritesa
+ eval add wave -color aquamarine -label tcu_stat2plb_en -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_stat2plb_en
+ eval add wave -color aquamarine -label tcu_wb_status_info -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/tcu_wb_status_info
+
+ eval add wave -color aquamarine -label tcu_mrbusy -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_mrbusy
+ eval add wave -color aquamarine -label mbusy_read_out -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/mbusy_read_out
+ eval add wave -color aquamarine -label mbusy_write_out -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/mbusy_write_out
+ eval add wave -color aquamarine -label SL_MWrErr -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/SL_MWrErr
+ eval add wave -color aquamarine -label SL_MRdErr -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/SL_MRdErr
+ eval add wave -color aquamarine -label sl_wrbterm -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/sl_wrbterm
+ eval add wave -color aquamarine -label sl_rdbterm -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/sl_rdbterm
+
+
+ eval add wave -color aquamarine -label wb_tout_reset -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_tout_reset
+ eval add wave -color aquamarine -label wb_tout_count -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_tout_count
+ eval add wave -color aquamarine -label wb_tout_counter -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_tout_counter
+ eval add wave -color aquamarine -label wb_tout_alarm -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_tout_alarm
+
+
+
+ eval add wave -color aquamarine -label start_plb_r -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/start_plb_r
+ eval add wave -color aquamarine -label start_plb_sec_r -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/start_plb_sec_r
+ eval add wave -color aquamarine -label start_plb_sec_stat_r -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/start_plb_sec_stat_r
+ eval add wave -color aquamarine -label start_plb_sec_stat_w -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/start_plb_sec_stat_w
+ eval add wave -color aquamarine -label start_plb_sec_w -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/start_plb_sec_w
+ eval add wave -color aquamarine -label start_plb_stat_r -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/start_plb_stat_r
+ eval add wave -color aquamarine -label start_plb_stat_w -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/start_plb_stat_w
+ eval add wave -color aquamarine -label start_plb_w -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/start_plb_w
+ eval add wave -color aquamarine -label start_wb_r -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/start_wb_r
+ eval add wave -color aquamarine -label start_wb_w -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/start_wb_w
+
+
+
+
+
+
+
+ #
+ # Bridge - Status Unit
+ #
+ eval add wave -color DarkSalmon -group bridge_STU -noupdate
+ eval add wave -color DarkSalmon -label STU_full -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_full
+ eval add wave -color DarkSalmon -label STU_softReset -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_softReset
+ eval add wave -color DarkSalmon -label STU_continue -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_continue
+ eval add wave -color DarkSalmon -label STU_abort -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_abort
+ eval add wave -color DarkSalmon -label amu_masterid -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/amu_masterid
+ eval add wave -color DarkSalmon -label plb_masterid -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/plb_masterid
+
+ eval add wave -color DarkSalmon -label stat2plb_empty -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2plb_empty
+ eval add wave -color DarkSalmon -label stat2plb_rd_en -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2plb_rd_en
+ eval add wave -color DarkSalmon -label stat2wb_rd_en -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_rd_en
+ eval add wave -color DarkSalmon -label stat2wb_wr_en -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_wr_en
+ eval add wave -color DarkSalmon -label stat2wb_full -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_full
+ eval add wave -color DarkSalmon -label stat2wb_empty -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_empty
+ eval add wave -color DarkSalmon -label stat2wb_dout -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_dout
+ eval add wave -color DarkSalmon -label stat2wb_din -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_din
+
+ eval add wave -color DarkSalmon -label tcu_stuLatchPA -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/tcu_stulatchpa
+ eval add wave -color DarkSalmon -label tcu_stuLatchSA -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/tcu_stulatchsa
+
+
+ eval add wave -color DarkSalmon -label soft_reset_count -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/soft_reset_count
+ eval add wave -color DarkSalmon -label address_reg -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/address_reg
+ eval add wave -color DarkSalmon -label status_reg0 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(0)
+ eval add wave -color DarkSalmon -label status_reg1 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(1)
+ eval add wave -color DarkSalmon -label status_reg2 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(2)
+ eval add wave -color DarkSalmon -label status_reg3 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(3)
+ eval add wave -color DarkSalmon -label status_reg_out -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_reg_out
+
+
+
+
+ #
+ # Bridge - Adress Management Unit
+ #
+ eval add wave -color RosyBrown -group bridge_AMU -noupdate
+ eval add wave -color RosyBrown -label amu_addrack -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_addrack
+ eval add wave -color RosyBrown -label plb_savalid -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/plb_savalid
+ eval add wave -color RosyBrown -label amu_buf_rnw -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_rnw
+ eval add wave -color RosyBrown -label amu_bufempty -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_bufempty
+ eval add wave -color RosyBrown -label amu_buffull -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buffull
+ eval add wave -color RosyBrown -label amu_deviceselect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_deviceselect
+ eval add wave -color RosyBrown -label amu_statusselect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_statusselect
+ eval add wave -color RosyBrown -label amu_pipe_rmID -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_rmID
+ eval add wave -color RosyBrown -label amu_pipe_wmID -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_wmID
+ eval add wave -color rosyBrown -label amu_buf_size -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_size
+ eval add wave -color rosyBrown -label amu_buf_BE -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_BE
+ eval add wave -color rosyBrown -label amu_pipe_size -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_size
+ eval add wave -color rosyBrown -label amu_pipe_size -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_BE
+ eval add wave -color RosyBrown -label amu_buf_adr -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_adr
+ eval add wave -color RosyBrown -label wb_sel_o -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/wb_sel_o
+ eval add wave -color RosyBrown -label rpipe_out -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/rpipe_out
+ eval add wave -color RosyBrown -label wpipe_out -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/wpipe_out
+ eval add wave -color RosyBrown -label pipeline_in -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/pipeline_in
+ eval add wave -color RosyBrown -label AMU_pipe_adr -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_adr
+ eval add wave -color RosyBrown -label AMU_pipe_rStatusSelect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_rStatusSelect
+ eval add wave -color RosyBrown -label AMU_pipe_wStatusSelect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_wStatusSelect
+
+
+ #
+ # Read buffer
+ #
+ eval add wave -color SpringGreen -group bridge_RBF -noupdate
+ eval add wave -color SpringGreen -label rbuf_din -group bridge_RBF -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbuf_din
+ eval add wave -color SpringGreen -label rbuf_dout -group bridge_RBF -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbuf_dout
+ eval add wave -color SpringGreen -label tcu_rbufren -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/tcu_rbufren
+ eval add wave -color SpringGreen -label tcu_rbufwen -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/tcu_rbufwen
+ eval add wave -color SpringGreen -label rbf_empty -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbf_empty
+ eval add wave -color SpringGreen -label rbf_full -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbf_full
+ eval add wave -color SpringGreen -label rbf_almostempty -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbf_almostempty
+
+ #
+ # Write buffer
+ #
+ eval add wave -color LimeGreen -group bridge_WBF -noupdate
+ eval add wave -color LimeGreen -label plb_size -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/plb_size
+ eval add wave -color LimeGreen -label wbf_empty -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/wbf_empty
+ eval add wave -color LimeGreen -label wbf_full -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/wbf_full
+ eval add wave -color LimeGreen -label wbf_wbus -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/wbf_wbus
+ eval add wave -color LimeGreen -label tcu_wbufren -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/tcu_wbufren
+ eval add wave -color LimeGreen -label tcu_wbufwen -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/tcu_wbufwen
+
+
+
+ #
+ # Whishbone signals
+ #
+ eval add wave -color Orange -noupdate -group Wishbone
+
+ eval add wave -color Orange -label wb_m_dat_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_dat_o
+ eval add wave -color Orange -label wb_m_ack_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_ack_o
+ eval add wave -color Orange -label wb_m_err_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_err_o
+ eval add wave -color Orange -label wb_m_rty_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_rty_o
+ eval add wave -color Orange -label wb_s_dat_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_dat_o
+ eval add wave -color Orange -label wb_s_adr_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_adr_o
+ eval add wave -color Orange -label wb_s_sel_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_sel_o
+ eval add wave -color Orange -label wb_s_we_o -group Wishbone -noupdate $binopt $tbpath/wb_conbus_0/wb_s_we_o
+ eval add wave -color Orange -label wb_s_cyc_o -group Wishbone -noupdate $binopt $tbpath/wb_conbus_0/wb_s_cyc_o
+ eval add wave -color Orange -label wb_s_stb_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_stb_o
+ eval add wave -color Orange -label wb_clk_i -group Wishbone -noupdate $binopt $tbpath/wb_conbus_0/wb_clk_i
+
+
+ add_ocram 0 OrangeRed
+ add_ocram 1 OrangeRed
+ add_ocram 2 OrangeRed
+ add_ocram 3 OrangeRed
+
+ configure wave -namecolwidth 347
+ configure wave -valuecolwidth 252
+ configure wave -timeline 0
+ configure wave -timelineunits ns
Index: trunk/systems/dev_system_sim/simulation/scripts/slave_init.bin
===================================================================
Index: trunk/systems/dev_system_sim/simulation/scripts/modelsim_proj.mpf
===================================================================
--- trunk/systems/dev_system_sim/simulation/scripts/modelsim_proj.mpf (nonexistent)
+++ trunk/systems/dev_system_sim/simulation/scripts/modelsim_proj.mpf (revision 2)
@@ -0,0 +1,1377 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+secureip = c:/compxlib/secureip/
+simprim = c:/compxlib/simprim/
+simprims_ver = c:/compxlib/simprims_ver/
+unisim = c:/compxlib/unisim/
+unisims_ver = c:/compxlib/unisims_ver/
+xilinxcorelib = c:/compxlib/xilinxcorelib/
+xilinxcorelib_ver = c:/compxlib/xilinxcorelib_ver/
+microblaze_v7_20_d = /opt/Xilinx/11.1/compxlib/edk/microblaze_v7_20_d/
+proc_common_v3_00_a = c:/compxlib/edk/proc_common_v3_00_a/
+plb_v46_v1_04_a = c:/compxlib/edk/plb_v46_v1_04_a/
+lmb_v10_v1_00_a = /opt/Xilinx/11.1/compxlib/edk/lmb_v10_v1_00_a/
+lmb_bram_if_cntlr_v2_10_b = /opt/Xilinx/11.1/compxlib/edk/lmb_bram_if_cntlr_v2_10_b/
+lmb_bram_elaborate_v1_00_a = lmb_bram_elaborate_v1_00_a
+plbv46_slave_single_v1_01_a = c:/compxlib/edk/plbv46_slave_single_v1_01_a/
+interrupt_control_v2_01_a = /opt/Xilinx/11.1/compxlib/edk/interrupt_control_v2_01_a/
+xps_gpio_v2_00_a = /opt/Xilinx/11.1/compxlib/edk/xps_gpio_v2_00_a/
+xps_timer_v1_01_b = /opt/Xilinx/11.1/compxlib/edk/xps_timer_v1_01_b/
+clock_generator_v3_02_a = /opt/Xilinx/11.1/compxlib/edk/clock_generator_v3_02_a/
+mdm_v1_00_g = /opt/Xilinx/11.1/compxlib/edk/mdm_v1_00_g/
+proc_sys_reset_v2_00_a = /opt/Xilinx/11.1/compxlib/edk/proc_sys_reset_v2_00_a/
+xps_intc_v2_00_a = /opt/Xilinx/11.1/compxlib/edk/xps_intc_v2_00_a/
+work = work
+plbv46_master_bfm_v1_00_a = c:/compxlib/edk/plbv46_master_bfm_v1_00_a/
+plbv46_monitor_bfm_v1_00_a = c:/compxlib/edk/plbv46_monitor_bfm_v1_00_a/
+plbv46_slave_bfm_v1_00_a = c:/compxlib/edk/plbv46_slave_bfm_v1_00_a/
+bfm_synch_v1_00_a = c:/compxlib/edk/bfm_synch_v1_00_a/
+plbv46_bfm = c:/compxlib/edk/plbv46_bfm/
+plb2wb_bridge_v1_00_a = plb2wb_bridge_v1_00_a
+onchip_ram_v1_00_a = onchip_ram_v1_00_a
+wb_conbus_v1_00_a = wb_conbus_v1_00_a
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn off detection of FSMs having single bit current state variable.
+; FsmSingle = 0
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Do not show immediate assertions with constant expressions in
+; GUI/report/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect ;
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a Verilog condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules and modules included
+; using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 1 to 4, with the following
+; meanings (the default is 3):
+; 1 -- Turn off all optimizations that affect coverage reports.
+; 2 -- Allow optimizations that allow large performance improvements
+; by invoking sequential processes only when the data changes.
+; This may make major reductions in coverage counts.
+; 3 -- In addition, allow optimizations that may change expressions or
+; remove some statements. Allow constant propagation. Allow VHDL
+; subprogram inlining and VHDL FF recognition.
+; 4 -- In addition, allow optimizations that may remove major regions of
+; code by changing assignments to built-ins or removing unused
+; signals. Change Verilog gates to continuous assignments.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => _
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces
+; "merge_instances" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = [ ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn off detection of FSMs having single bit current state variable.
+; FsmSingle = 0
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a vopt condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; vopt automatic SDF
+; If automatic design optimization is on, enables automatic compilation
+; of SDF files.
+; Default is on, uncomment to turn off.
+; VoptAutoSDFCompile = 0
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+resolution = 1ps
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 10 sec
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL/Verilog immediate assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+; from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not defined for assertion level:
+; - and if failure occurs during elaboration, use MessageFormatBreakLine;
+; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
+; level), use MessageFormatBreak;
+; - otherwise, use MessageFormat.
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops do to a breakpoint or fatal error.
+; Example w/function name: # Break in Process ctr at counter.vhd line 44
+; Example wo/function name: # Break at counter.vhd line 44
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable System Verilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type). Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be indexed during
+; simulation. If set to 0, the WLF file will not be indexed.
+; The default is 1, indexed the WLF file.
+; WLFIndex = 0
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: these ini variables can be overriden by the vsim command
+; line switch "-onfinish ".
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result at the end of simulation before shutdown.
+; If this is enabled, the simstats result will be printed out before shutdown.
+; The default is off.
+; PrintSimStats = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA concurrent assertion pass enable.
+; For SVA, Default is on when the assertion has a pass action block, or
+; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
+; For PSL, Default is on only when vsim switch "-assertdebug" is used
+; and the vopt "+acc=a" flag is active.
+; AssertionPassEnable = 0
+
+; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
+; AssertionFailEnable = 0
+
+; Set PSL/SVA concurrent assertion pass limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionPassLimit = 1
+
+; Set PSL/SVA concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionFailLimit = 1
+
+; Turn on/off PSL concurrent assertion pass log. Default is off.
+; The flag does not affect SVA
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that
+; are included for toggle coverage. This leads to a longer simulation time with bigger
+; arrays covered with toggle coverage. Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable is 1
+; SVCovergroup63Compatibility = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator.
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
+; Sv_Seed = 0
+
+; Specify if the solver should attempt to ignore overflow/underflow semantics
+; for arithmetic constraints (multiply, addition, subtraction) in order to
+; improve performance. The "solveignoreoverflow" attribute can be specified on
+; a per-call basis to randomize() to override this setting.
+; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
+; ignore overflow/underflow.
+; SolveIgnoreOverflow = 0
+
+; Maximum size of dynamic arrays that are resized during randomize().
+; The default is 1000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 1000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; The default is 0 (no error).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures (SystemVerilog).
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; Maximum size of the solution graph that may be generated during randomize().
+; This value can be used to force randomize() to abort if the memory
+; requirements of the constraint scenario exceeds the specified limit. This
+; value is specified in 1000s of nodes.
+; The default is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Maximum number of evaluations that may be performed on the solution graph
+; generated during randomize(). This value can be used to force randomize() to
+; abort if the complexity of the constraint scenario (in time) exceeds the
+; specified limit. This value is specified in 10000s of evaluations.
+; The default is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of
+; the constraint solver for others.
+; The default value is "" (no options).
+;
+; Valid flags are:
+; i = disable bit interleaving for >, >=, <, <= constraints
+; n = disable bit interleaving for all constraints
+; r = reverse bit interleaving
+;
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; Note: To achieve the same random sequences, solver optimizations and/or
+; bug fixes introduced since the specified release may be disabled -
+; yielding the performance / behavior of the prior release.
+; Default value set to "" (random compatibility not required).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+; MvcHome = $MODEL_TECH/...
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = /lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = /lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = /lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = /lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = /lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: = [,...]
+; suppress can be used to achieve +nowarn
functionality
+; The format is: suppress = ,,[,,...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; The command verror can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear in the transcript and recorded in the wlf
+; file (messages that are recorded in the wlf file can be viewed
+; in the MsgViewer). The other settings are to send messages
+; only to the transcript or only to the wlf file. The valid
+; values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
+[Project]
+; Warning -- Do not edit the project properties directly.
+; Property names are dynamic in nature and property
+; values have special syntax. Changing property data directly
+; can result in a corrupt MPF file. All project properties
+; can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick =
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick =
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick =
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick =
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick =
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick =
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick =
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick =
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick =
+XML_DoubleClick = Edit
+XML_CustomDoubleClick =
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick =
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick =
+Project_Major_Version = 6
+Project_Minor_Version = 5
Index: trunk/systems/dev_system_sim/simulation/scripts/onchip_ram.bin
===================================================================
Index: trunk/systems/dev_system_sim/simulation/scripts/sim.do
===================================================================
--- trunk/systems/dev_system_sim/simulation/scripts/sim.do (nonexistent)
+++ trunk/systems/dev_system_sim/simulation/scripts/sim.do (revision 2)
@@ -0,0 +1,11 @@
+
+
+
+vsim -novopt -t ps system_tb
+
+do wave.do
+
+do transfers.do
+run 9000 ns
+
+
Index: trunk/systems/dev_system_sim/simulation/scripts/transfers.bfl
===================================================================
--- trunk/systems/dev_system_sim/simulation/scripts/transfers.bfl (nonexistent)
+++ trunk/systems/dev_system_sim/simulation/scripts/transfers.bfl (revision 2)
@@ -0,0 +1,21 @@
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+
+ mem_update( addr=f2000000, data=01112233 )
+ mem_update( addr=f2000004, data=44556677 )
+ mem_update( addr=f2000008, data=8899aabb )
+ mem_update( addr=f200000c, data=ccddeeff )
+
+ mem_update( addr=f3000000, data=01112233 )
+ mem_update( addr=f3000004, data=44556677 )
+ mem_update( addr=f3000008, data=8899aabb )
+ mem_update( addr=f300000c, data=ccddeeff )
+
+ write ( addr=f3000000, size=0000, be=1111 )
+ read ( addr=f3000000, size=0000, be=1111 )
+ read ( addr=f3000000, size=0000, be=1111 )
+
Index: trunk/systems/dev_system_sim/simulation/scripts/Makefile
===================================================================
--- trunk/systems/dev_system_sim/simulation/scripts/Makefile (nonexistent)
+++ trunk/systems/dev_system_sim/simulation/scripts/Makefile (revision 2)
@@ -0,0 +1,240 @@
+
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/..
+XPS_PROJ_DIR=$(CUR_DIR)/../..
+LIB_DIR=$(CUR_DIR)/../../../EDK_Libs
+
+PLB2WB_LIB_DIR=$(LIB_DIR)/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a
+OCRAM_LIB_DIR=$(LIB_DIR)/WishboneIPLib/pcores/testram_v1_00_a
+WB_LIB_DIR=$(LIB_DIR)/WishboneIPLib/pcores/wb_conbus_v1_00_a
+
+# VHDL compile flags
+VHDL_CFLAGS=-novopt -93 -error -check_synthesis -defercheck -deferSubpgmCheck -rangecheck
+
+## Uncomment this, if you are at hochschule pforzheim in a pc-pool.
+# (Check the paths in common/Makefile ->> vmap entries)
+#ENVIRONMENT=HSP
+
+
+ifeq ( $(ENVIRONMENT), "HSP" )
+VMAP= \
+ vmap -c; \
+ vmap secureip 'c:/Programme/CAEE/ISE_Lib/secureip/'; \
+ vmap simprim 'c:/Programme/CAEE/ISE_Lib/simprim/'; \
+ vmap simprims_ver 'c:/Programme/CAEE/ISE_Lib/simprims_ver/'; \
+ vmap unisim 'c:/Programme/CAEE/ISE_Lib/unisim/'; \
+ vmap unisims_ver 'c:/Programme/CAEE/ISE_Lib/unisims_ver/'; \
+ vmap xilinxcorelib 'c:/Programme/CAEE/ISE_Lib/XilinxCoreLib/'; \
+ vmap xilinxcorelib_ver 'c:/Programme/CAEE/ISE_Lib/XilinxCoreLib_ver/'; \
+ vmap proc_common_v3_00_a 'c:/Programme/CAEE/EDK_Lib/edk/proc_common_v3_00_a/'; \
+ vmap plb_v46_v1_04_a 'c:/Programme/CAEE/EDK_Lib/edk/plb_v46_v1_04_a/'; \
+ vmap bfm_synch_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/bfm_synch_v1_00_a/'; \
+ vmap plbv46_bfm 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_bfm/'; \
+ vmap plbv46_master_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_master_bfm_v1_00_a/'; \
+ vmap plbv46_monitor_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_monitor_bfm_v1_00_a/'; \
+ vmap plbv46_slave_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_slave_bfm_v1_00_a/'; \
+ vmap plbv46_slave_single_v1_01_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_slave_single_v1_01_a/';
+
+else
+VMAP= \
+ vmap -c; \
+ vmap unisim '/opt/Xilinx/11.1/compxlib/unisim/'; \
+ vmap unisims_ver '/opt/Xilinx/11.1/compxlib/unisims_ver/'; \
+ vmap proc_common_v3_00_a '/opt/Xilinx/11.1/compxlib/edk/proc_common_v3_00_a/'; \
+ vmap plb_v46_v1_04_a '/opt/Xilinx/11.1/compxlib/edk/plb_v46_v1_04_a/'; \
+ vmap bfm_synch_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/bfm_synch_v1_00_a/'; \
+ vmap plbv46_bfm '/opt/Xilinx/11.1/compxlib/edk/plbv46_bfm/'; \
+ vmap plbv46_master_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_master_bfm_v1_00_a/'; \
+ vmap plbv46_monitor_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_monitor_bfm_v1_00_a/'; \
+ vmap plbv46_slave_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_slave_bfm_v1_00_a/'; \
+ vlib work; \
+ vmap work work; \
+ vlib plb2wb_bridge_v1_00_a; \
+ vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;
+endif
+
+
+###########
+ONCHIP_RAM_TARGET=$(CUR_DIR)/testram_*/testram/_primary.dat
+WB_TARGET=$(CUR_DIR)/wb_conbus_*/wb_conbus_*/_primary.dat
+WORK_TARGET=$(CUR_DIR)/work/system/_primary.dat
+PLB2WB_BRIDGE_TARGET=$(CUR_DIR)/plb2wb_bridge_*/plb2wb_bridge/_primary.dat
+###########
+
+
+
+###########
+PLB2WB_BRIDGE_SRC=$(PLB2WB_LIB_DIR)/hdl/vhdl/*.vhd \
+ ../testbench/plb2wb_amu_tb.vhd
+
+ONCHIP_RAM_SRC=$(OCRAM_LIB_DIR)/hdl/vhdl/testram.vhd
+WB_SRC=$(WB_LIB_DIR)/hdl/verilog/*.v
+###########
+
+
+
+
+
+WORK_SRC= $(SIM_DIR)/behavioral/mb_plb_wrapper.vhd \
+ $(SIM_DIR)/behavioral/plb_bfm_master_32_wrapper.vhd \
+ $(SIM_DIR)/behavioral/plb_bfm_monitor_wrapper.vhd \
+ $(SIM_DIR)/behavioral/plb_bfm_slave_wrapper.vhd \
+ $(SIM_DIR)/behavioral/plb_bfm_synch_wrapper.vhd \
+ $(SIM_DIR)/behavioral/system.vhd \
+ $(SIM_DIR)/testbench/system_tb.vhd
+
+VHDL_BRIDGE_SRC=$(SIM_DIR)/behavioral/plb2wb_bridge_0_wrapper.vhd
+
+
+#
+# Generate Simulation HDL Files
+# (This is the same than XPS-Gui->Simulation->Generate Simulation HDL Files)
+#
+$(WORK_SRC): $(XPS_PROJ_DIR)/system.mhs
+ simgen $(XPS_PROJ_DIR)/system.mhs -lang vhdl \
+ -p virtex5 \
+ -m beh \
+ -od $(XPS_PROJ_DIR)/ \
+ -s mti \
+ -lp $(LIB_DIR)
+
+#
+#
+# Generate the modelsim.ini file and working directory
+# after this, modelsim.ini contains the library mappings
+#
+modelsim.ini:
+ $(VMAP)
+
+
+
+#
+# Compile the Bus Functional Model script file
+# transfers.bfl: is written in PLB Bus Functional Language
+# (see $XILINX_EDK/third_party/doc/PlbToolkit.pdf )
+# xilbfc: Bus functional compiler (perl script)
+#
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+#
+# Compile the vhdl-sources with modelsim vhdl compiler
+#
+$(WORK_TARGET): $(WORK_SRC)
+ vlib work; \
+ vmap work work; \
+ vlog -novopt -93 -work work "../behavioral/wb_conbus_0_wrapper.v"; \
+ vcom $(VHDL_CFLAGS) -work work \
+ "../behavioral/onchip_ram_0_wrapper.vhd" \
+ "../behavioral/onchip_ram_1_wrapper.vhd" \
+ "../behavioral/onchip_ram_2_wrapper.vhd" \
+ "../behavioral/onchip_ram_3_wrapper.vhd" \
+ "../behavioral/mb_plb_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_32_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_64_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_128_wrapper.vhd" \
+ "../behavioral/plb_bfm_monitor_wrapper.vhd" \
+ "../behavioral/plb_bfm_slave_wrapper.vhd" \
+ "../behavioral/plb_bfm_synch_wrapper.vhd" \
+ "../behavioral/plb2wb_bridge_0_wrapper.vhd" \
+ "../behavioral/system.vhd" \
+ "../testbench/system_tb.vhd"
+
+
+$(PLB2WB_BRIDGE_TARGET): $(PLB2WB_BRIDGE_SRC)
+ vlib plb2wb_bridge_v1_00_a;
+ vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;
+ vcom $(VHDL_CFLAGS) -work plb2wb_bridge_v1_00_a \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_pkg.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_short_impulse.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_cc_4.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_ic_4.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_cc_3.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_ic_3.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_cc_2.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_ic_2.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_cc_1.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_ic_1.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_rdat_cc_32.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_rdat_ic_32.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_rdat.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_wdat_cc_32.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_wdat_ic_32.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_wdat.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_ic_4.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_cc_4.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_ic_3.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_cc_3.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_ic_2.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_cc_2.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_ic_1.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_cc_1.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2wb.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2wb_ic.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2wb_cc.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_fifo.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_stu.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_tcu.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_amu.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_rbuf.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_wbuf.vhd" \
+ "$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_bridge.vhd"
+
+
+
+$(ONCHIP_RAM_TARGET): $(ONCHIP_RAM_SRC)
+ vlib testram_v1_00_a;
+ vmap testram_v1_00_a testram_v1_00_a;
+ vcom $(VHDL_CFLAGS) -work testram_v1_00_a $(OCRAM_LIB_DIR)/hdl/vhdl/testram.vhd
+
+
+$(WB_TARGET): $(WB_SRC)
+ vlib wb_conbus_v1_00_a;
+ vmap wb_conbus_v1_00_a wb_conbus_v1_00_a;
+ vlog -novopt -93 -work wb_conbus_v1_00_a "$(WB_LIB_DIR)/hdl/verilog/wb_conbus_arb.v" \
+ "$(WB_LIB_DIR)/hdl/verilog/wb_conbus_top.v" \
+ "$(WB_LIB_DIR)/hdl/verilog/wb_conbus_wrapper.v"
+
+
+
+compile: modelsim.ini $(ONCHIP_RAM_TARGET) $(WORK_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET)
+
+sim: modelsim.ini transfers.do $(ONCHIP_RAM_TARGET) $(WORK_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET)
+ vsim -quiet -l simulation.log -do sim.do
+
+
+sim_fifo: ./plb2wb_bridge_*/plb2wb_bridge/_primary.dat
+ vsim -quiet -do sim_fifo.do
+
+sim_amu : ./plb2wb_bridge_*/plb2wb_bridge/_primary.dat
+ vsim -quiet -do sim_amu.do
+
+sim_clk_trans: ./plb2wb_bridge_*/plb2wb_bridge/_primary.dat
+ vsim -quiet -do sim_clk_trans.do
+
+clean:
+ rm -rf work \
+simgen.log \
+simgen.opt \
+transcript \
+vsim.wlf \
+modelsim.ini \
+../behavioral \
+xilbfc.log \
+plb2wb_bridge_v1_00_a \
+wb_conbus_v1_00_a \
+testram_v1_00_a \
+wb_conbus_v1_00_a \
+bfm_synch_v1_00_a \
+plb_v46_v1_04_a \
+plbv46_bfm \
+plbv46_master_bfm_v1_00_a \
+plbv46_monitor_bfm_v1_00_a \
+plbv46_slave_bfm_v1_00_a \
+plbv46_slave_single_v1_01_a \
+proc_common_v3_00_a \
+modelsim_proj.cr.mti \
+transfers.do
Index: trunk/systems/dev_system_sim/system.mss
===================================================================
--- trunk/systems/dev_system_sim/system.mss (nonexistent)
+++ trunk/systems/dev_system_sim/system.mss (revision 2)
@@ -0,0 +1,43 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = plb_bfm_slave
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = plb2wb_bridge_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_3
+END
+
+
Index: trunk/systems/dev_system_sim/system.xmp
===================================================================
--- trunk/systems/dev_system_sim/system.xmp (nonexistent)
+++ trunk/systems/dev_system_sim/system.xmp (revision 2)
@@ -0,0 +1,25 @@
+#Please do not modify this file by hand
+XmpVersion: 11.4
+VerMgmt: 11.4
+IntStyle: default
+ModuleSearchPath: ../EDK_Libs/
+MHS File: system.mhs
+MSS File: system.mss
+Architecture: virtex5
+Device: xc5vlx50
+Package: ff676
+SpeedGrade: -1
+UserCmd1:
+UserCmd1Type: 0
+UserCmd2:
+UserCmd2Type: 0
+GenSimTB: 0
+SdkExportBmmBit: 1
+SdkExportDir: SDK/SDK_Export
+InsertNoPads: 0
+WarnForEAArch: 1
+HdlLang: VHDL
+SimModel: BEHAVIORAL
+UcfFile: data/system.ucf
+EnableParTimingError: 1
+ShowLicenseDialog: 1
Index: trunk/systems/dev_system_sim/data/system.ucf
===================================================================
--- trunk/systems/dev_system_sim/data/system.ucf (nonexistent)
+++ trunk/systems/dev_system_sim/data/system.ucf (revision 2)
@@ -0,0 +1,6 @@
+# Virtex 5 ML501 Evaluation Platform
+Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
+TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
+Net fpga_0_clk_1_sys_clk_pin LOC = AD8 | IOSTANDARD=LVCMOS33;
+Net fpga_0_rst_1_sys_rst_pin TIG;
+Net fpga_0_rst_1_sys_rst_pin LOC = T23 | IOSTANDARD=LVCMOS33 | PULLUP;
Index: trunk/systems/dev_system_sim/system.mhs
===================================================================
--- trunk/systems/dev_system_sim/system.mhs (nonexistent)
+++ trunk/systems/dev_system_sim/system.mhs (revision 2)
@@ -0,0 +1,191 @@
+
+# ##############################################################################
+# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
+# Fri Mar 5 18:02:26 2010
+# Target Board: Xilinx Virtex 5 ML501 Evaluation Platform Rev 1
+# Family: virtex5
+# Device: xc5vlx50
+# Package: ff676
+# Speed Grade: -1
+# Processor number: 1
+# Processor 1: microblaze_0
+# System clock frequency: 125.0
+# Debug Interface: On-Chip HW Debug Module
+# ##############################################################################
+ PARAMETER VERSION = 2.1.0
+
+
+ PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
+ PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
+ PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]
+ PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]
+ PORT wb_clk_pin = wb_clk, DIR = I, SIGIS = CLK
+ PORT wb_rst_pin = wb_rst, DIR = I, SIGIS = RST
+
+
+BEGIN plb_v46
+ PARAMETER INSTANCE = mb_plb
+ PARAMETER HW_VER = 1.04.a
+ PARAMETER C_EXT_RESET_HIGH = 1
+ PARAMETER C_DCR_INTFCE = 1
+ PARAMETER C_BASEADDR = 0b0000000000
+ PARAMETER C_HIGHADDR = 0b1111111111
+ PORT PLB_Clk = clk_100MHz
+ PORT SYS_Rst = sys_rst_s
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_32
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_SIZE = 0b10
+ PARAMETER PLB_MASTER_NUM = 0b0000
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_0
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_64
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ PARAMETER PLB_MASTER_SIZE = 0b10
+ PARAMETER PLB_MASTER_NUM = 0b0001
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_1
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_128
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ PARAMETER PLB_MASTER_NUM = 0b0010
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_2
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_monitor_bfm
+ PARAMETER INSTANCE = plb_bfm_monitor
+ PARAMETER HW_VER = 1.00.a
+ BUS_INTERFACE MON_PLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_3
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_slave_bfm
+ PARAMETER INSTANCE = plb_bfm_slave
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_SLAVE_ADDR_LO_0 = 0x00020000
+ PARAMETER PLB_SLAVE_ADDR_HI_0 = 0x0002ffff
+ PARAMETER C_SPLB_NATIVE_DWIDTH = 32
+ PARAMETER PLB_SLAVE_SIZE = 0b00
+ BUS_INTERFACE SPLB = mb_plb
+ PORT SYNCH_IN = synch_in
+ PORT SYNCH_OUT = bfm_synch_out_4
+END
+
+BEGIN bfm_synch
+ PARAMETER INSTANCE = plb_bfm_synch
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_NUM_SYNCH = 5
+ PORT TO_SYNCH_IN = synch_out
+ PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_1 & bfm_synch_out_2 & bfm_synch_out_3 & bfm_synch_out_4
+END
+
+BEGIN plb2wb_bridge
+ PARAMETER INSTANCE = plb2wb_bridge_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_BASEADDR = 0xf0000000
+ PARAMETER C_HIGHADDR = 0xf7ffffff
+ PARAMETER WB_ADR_OFFSET = 0xf0000000
+ PARAMETER WB_ADR_OFFSET_NEG = 1
+ PARAMETER SYNCHRONY = false
+ PARAMETER C_STATUS_BASEADDR = 0x00010000
+ PARAMETER C_STATUS_HIGHADDR = 0x0001FFFF
+ PARAMETER WB_PIC_INTS = 1
+ PARAMETER WB_SUPPORT_BLOCK = 0
+ PARAMETER C_SPLB_SUPPORT_BUR_LINE = 0
+ PARAMETER C_SPLB_SUPPORT_ADR_PIPE = 0
+ BUS_INTERFACE SPLB = mb_plb
+ BUS_INTERFACE MWB = wb_conbus_0
+ PORT SPLB_Clk = clk_100MHz
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+ PORT wb_pic_int_i = net_gnd
+END
+
+BEGIN wb_conbus
+ PARAMETER INSTANCE = wb_conbus_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER wb_s0_addr = 0x00
+ PARAMETER wb_s27_addr_w = 8
+ PARAMETER wb_s1_addr = 0x01
+ PARAMETER wb_s2_addr = 0x02
+ PARAMETER wb_s3_addr = 0x03
+ PARAMETER wb_s4_addr = 0x04
+ PARAMETER wb_s5_addr = 0x05
+ PARAMETER wb_s6_addr = 0x06
+ PARAMETER wb_s7_addr = 0x07
+ PARAMETER wb_s0_addr_w = 8
+ PARAMETER wb_s1_addr_w = 8
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 0
+ PARAMETER WR_DELAY = 0
+# PARAMETER WITH_ERR_OR_RTY = 0b01
+ PARAMETER WITH_ERR_OR_RTY = 0b00
+ PARAMETER ERR_RTY_INTERVAL = 2
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_1
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 1
+ PARAMETER WR_DELAY = 1
+# PARAMETER WITH_ERR_OR_RTY = 0b01
+ PARAMETER WITH_ERR_OR_RTY = 0b00
+ PARAMETER ERR_RTY_INTERVAL = 3
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_2
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 3
+ PARAMETER WR_DELAY = 3
+# PARAMETER WITH_ERR_OR_RTY = 0b01
+ PARAMETER WITH_ERR_OR_RTY = 0b00
+ PARAMETER ERR_RTY_INTERVAL = 4
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_3
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 11
+ PARAMETER WR_DELAY = 5
+# PARAMETER WITH_ERR_OR_RTY = 0b01
+ PARAMETER WITH_ERR_OR_RTY = 0b00
+ PARAMETER ERR_RTY_INTERVAL = 2
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
Index: trunk/systems/dev_system_sim/etc/bitgen.ut
===================================================================
--- trunk/systems/dev_system_sim/etc/bitgen.ut (nonexistent)
+++ trunk/systems/dev_system_sim/etc/bitgen.ut (revision 2)
@@ -0,0 +1,14 @@
+-g TdoPin:PULLNONE
+-g DriveDone:No
+-g StartUpClk:JTAGCLK
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g TckPin:PULLUP
+-g TdiPin:PULLUP
+-g TmsPin:PULLUP
+-g DonePipe:No
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:NONE
+-g Persist:No
+
Index: trunk/systems/dev_system_sim/etc/fast_runtime.opt
===================================================================
--- trunk/systems/dev_system_sim/etc/fast_runtime.opt (nonexistent)
+++ trunk/systems/dev_system_sim/etc/fast_runtime.opt (revision 2)
@@ -0,0 +1,84 @@
+FLOWTYPE = FPGA;
+###############################################################
+## Filename: fast_runtime.opt
+##
+## Option File For Xilinx FPGA Implementation Flow for Fast
+## Runtime.
+##
+## Version: 4.1.1
+###############################################################
+#
+# Options for Translator
+#
+# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
+#
+Program ngdbuild
+-p ; # Partname to use - picked from xflow commandline
+-nt timestamp; # NGO File generation. Regenerate only when
+ # source netlist is newer than existing
+ # NGO file (default)
+-bm .bmm # Block RAM memory map file
+; # User design - pick from xflow command line
+-uc .ucf; # ucf constraints
+.ngd; # Name of NGD file. Filebase same as design filebase
+End Program ngdbuild
+
+#
+# Options for Mapper
+#
+# Type "map -h " for a detailed list of map command line options
+#
+Program map
+-o _map.ncd; # Output Mapped ncd file
+-w; # Overwrite output files.
+-pr b; # Pack internal FF/latches into IOBs
+#-fp .mfp; # Floorplan file
+-ol high;
+-timing;
+-detail;
+.ngd; # Input NGD file
+.pcf; # Physical constraints file
+END Program map
+
+#
+# Options for Post Map Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_map_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o _map.twr; # Output trace report file
+-xml _map.twx; # Output XML version of the timing report
+#-tsi _map.tsi; # Produce Timing Specification Interaction report
+_map.ncd; # Input mapped ncd
+.pcf; # Physical constraints file
+END Program post_map_trce
+
+#
+# Options for Place and Route
+#
+# Type "par -h" for a detailed list of par command line options
+#
+Program par
+-w; # Overwrite existing placed and routed ncd
+-ol high; # Overall effort level
+_map.ncd; # Input mapped NCD file
+.ncd; # Output placed and routed NCD
+.pcf; # Input physical constraints file
+END Program par
+
+#
+# Options for Post Par Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_par_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o .twr; # Output trace report file
+-xml .twx; # Output XML version of the timing report
+#-tsi .tsi; # Produce Timing Specification Interaction report
+.ncd; # Input placed and routed ncd
+.pcf; # Physical constraints file
+END Program post_par_trce
+
+
Index: trunk/systems/dev_system_sim/etc/download.cmd
===================================================================
--- trunk/systems/dev_system_sim/etc/download.cmd (nonexistent)
+++ trunk/systems/dev_system_sim/etc/download.cmd (revision 2)
@@ -0,0 +1,6 @@
+setMode -bscan
+setCable -p auto
+identify
+assignfile -p 4 -file implementation/download.bit
+program -p 4
+quit
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/testbench/system_tb.vhd
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/testbench/system_tb.vhd (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/testbench/system_tb.vhd (revision 2)
@@ -0,0 +1,118 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+entity system_tb is
+end system_tb;
+
+architecture STRUCTURE of system_tb is
+
+ constant sys_clk_period : time := 10.000000 ns;
+ constant sys_rst_length : time := 160 ns;
+
+ constant SYNCH_PART : integer := 1;
+ constant SYNCH_SUBPART : integer := 2;
+ constant SYNCH_SUBSUBPART : integer := 3;
+
+ constant SUBSUBPART_LENGTH : integer := 10; -- 10 clock cycles
+ constant SUBPART_LENGTH : integer := 5; -- 7 times SUBSUBPART_LENGTH
+ constant PART_LENGTH : integer := 5; -- 6 times SUBPART_LENGTH
+
+ component system is
+ port (
+ sys_clk_pin : in std_logic;
+ sys_rst_pin : in std_logic;
+ to_synch_in_pin : in std_logic_vector( 0 to 31 );
+ from_synch_out_pin : out std_logic_vector( 0 to 31 )
+ );
+ end component;
+
+
+ signal sys_clk : std_logic;
+ signal sys_rst : std_logic := '1';
+
+ signal to_synch_in : std_logic_vector( 0 to 31 );
+ signal from_synch_out : std_logic_vector( 0 to 31 );
+ signal tb_synch_out : std_logic_vector( 0 to 31 ) := ( others => '0' );
+
+ procedure SendSynch( signal synch_out : OUT std_logic_vector;
+ COMMAND : integer ) is
+ begin
+ synch_out( COMMAND ) <= '1';
+ wait for sys_clk_period*1;
+ synch_out( COMMAND ) <= '0';
+ end procedure SendSynch;
+
+
+begin
+
+ to_synch_in <= from_synch_out or tb_synch_out;
+
+
+
+ dut : system
+ port map (
+ sys_clk_pin => sys_clk,
+ sys_rst_pin => sys_rst,
+ to_synch_in_pin => to_synch_in,
+ from_synch_out_pin => from_synch_out
+ );
+
+
+ process
+ begin
+ sys_clk <= '0';
+ loop
+ wait for (sys_clk_period/2);
+ sys_clk <= not sys_clk;
+ end loop;
+ end process;
+
+
+ process
+ begin
+ sys_rst <= '1';
+ wait for ( sys_rst_length );
+ sys_rst <= not sys_rst;
+ wait;
+ end process;
+
+
+ process
+ begin
+
+ wait until sys_rst = '0';
+ -- wait until masters a ready
+ wait for sys_clk_period * 10;
+
+
+ while true loop
+ for i in 0 to PART_LENGTH-1 loop
+ SendSynch( tb_synch_out, SYNCH_PART );
+
+ for j in 0 to SUBPART_LENGTH-1 loop
+ SendSynch( tb_synch_out, SYNCH_SUBPART );
+
+ for k in 0 to SUBSUBPART_LENGTH loop
+ SendSynch( tb_synch_out, SYNCH_SUBSUBPART );
+ wait for (SUBSUBPART_LENGTH * sys_clk_period );
+ end loop;
+
+
+ end loop;
+
+
+ end loop;
+
+ end loop;
+
+ end process;
+
+
+
+
+end architecture STRUCTURE;
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/wave.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/wave.do (revision 2)
@@ -0,0 +1,54 @@
+
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+
+eval add wave -noupdate $binopt -label Clock -color SteelBlue /system_tb/sys_clk
+eval add wave -noupdate $binopt -label Reset -color SteelBlue /system_tb/sys_rst
+eval add wave -noupdate $hexopt -label synch_in -color Yellow /system_tb/dut/synch_in
+
+
+
+eval add wave -noupdate $binopt -label Mn_request -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_request
+
+eval add wave -noupdate $binopt -label Mn_RNW -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_rnw
+eval add wave -noupdate $binopt -label Mn_BE -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_be
+eval add wave -noupdate $binopt -label Mn_size -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_size
+eval add wave -noupdate $binopt -label Mn_type -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_type
+eval add wave -noupdate $hexopt -label Mn_ABus -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_abus
+eval add wave -noupdate $binopt -label PLB_PAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_pavalid
+eval add wave -noupdate $binopt -label PLB_SAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_savalid
+eval add wave -noupdate $binopt -label PLB_rdPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_rdprim
+eval add wave -noupdate $binopt -label PLB_wrPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_wrprim
+
+eval add wave -noupdate $hexopt -label Sl_rdDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddbus
+eval add wave -noupdate $binopt -label Sl_rdDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddack
+eval add wave -noupdate $binopt -label Sl_rdComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rdcomp
+
+
+eval add wave -noupdate $hexopt -label Sl_wrDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/plb_wrdbus
+eval add wave -noupdate $binopt -label Sl_wrDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrdack
+eval add wave -noupdate $binopt -label Sl_wrComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrcomp
+
+
+eval add wave -noupdate $binopt -label WB_CLK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_clk_i
+eval add wave -noupdate $binopt -label WB_RST_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rst_i
+eval add wave -noupdate $hexopt -label WB_ADR_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_adr_o
+eval add wave -noupdate $hexopt -label WB_DAT_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_o
+eval add wave -noupdate $hexopt -label WB_DAT_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_i
+eval add wave -noupdate $binopt -label WB_ACK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_ack_i
+eval add wave -noupdate $binopt -label WB_SEL_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_sel_o
+eval add wave -noupdate $binopt -label WB_STB_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_stb_o
+eval add wave -noupdate $binopt -label WB_LOCK_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_lock_o
+eval add wave -noupdate $binopt -label WB_WE_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_we_o
+
+
+
+eval add wave -noupdate $binopt -label bram0_ack_o -color Orange /system_tb/dut/onchip_ram_0/wb_ack_o
+eval add wave -noupdate $binopt -label bram1_ack_o -color Orange /system_tb/dut/onchip_ram_1/wb_ack_o
+eval add wave -noupdate $binopt -label bram2_ack_o -color Orange /system_tb/dut/onchip_ram_2/wb_ack_o
+eval add wave -noupdate $binopt -label bram3_ack_o -color Orange /system_tb/dut/onchip_ram_3/wb_ack_o
+
+
+configure wave -gridperiod 1
+configure wave -namecolwidth 200
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/transfers.bfl (revision 2)
@@ -0,0 +1,247 @@
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+
+ mem_update(addr=f0000000,data=11223344_22223344_33223344_44223344)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f0000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f0000030,data=01333311_02333311_03333311_04333311)
+ mem_update(addr=f1000000,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000010,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000020,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000030,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f2000000,data=11abcdef_22abcdef_33abcdef_44abcdef)
+ mem_update(addr=f3000000,data=11222222_22222222_33222222_44222222)
+ mem_update(addr=f3000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f3000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f3000030,data=01333311_02333311_03333311_04333311)
+
+ wait( level=SUBPART )
+
+
+
+ write ( addr=f0000000, size=0000, be=1111 )
+ write ( addr=f1000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0001, be=1111 )
+ write ( addr=f3000000, size=1010, be=1000 )
+ write ( addr=f2000000, size=0001, be=1111 )
+ write ( addr=f3000000, size=1010, be=1000 )
+ write ( addr=f1000000, size=0000, be=1111 )
+ write ( addr=f0000000, size=1010, be=0111 )
+ write ( addr=f1000000, size=1010, be=1000 )
+
+
+
+ -- this causes several address-pipelining situations
+ read ( addr=f1000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0001, be=1111 )
+ read ( addr=f1000000, size=0000, be=1111 )
+ read ( addr=f1000000, size=1010, be=0011 )
+ read ( addr=f2000000, size=1010, be=0011 )
+ read ( addr=f2000000, size=0001, be=1111 )
+ read ( addr=f1000000, size=1010, be=0100 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=1010, be=0001 )
+
+
+ wait( level = SUBSUBPART )
+ wait( level = SUBSUBPART )
+ wait( level = SUBSUBPART )
+
+ write ( addr=f0000000, size=0000, be=1111 )
+ read ( addr=f0000000, size=0000, be=1111 )
+ write ( addr=f1000000, size=0001, be=1111 )
+ read ( addr=f1000000, size=0001, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f3000000, size=0001, be=1111 )
+ read ( addr=f3000000, size=0001, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0001, be=1111 )
+ read ( addr=f2000000, size=0001, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=1010, be=0011 )
+ write ( addr=f3000000, size=0001, be=1111 )
+ read ( addr=f3000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=1010, be=0001 )
+ read ( addr=f2000000, size=0001, be=1111 )
+ read ( addr=f2000000, size=1010, be=0011 )
+ write ( addr=f2000000, size=0000, be=1111 )
+
+
+
+
+
+ ---------------------------------
+ -- 64-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_64/plb_bfm_master_64/master,device_type=plb_master)
+ configure(msize=01)
+
+
+ mem_update(addr=f0000000,data=11223344_22223344_33223344_44223344)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f0000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f0000030,data=01333311_02333311_03333311_04333311)
+ mem_update(addr=f1000000,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000010,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000020,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000030,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f2000000,data=11abcdef_22abcdef_33abcdef_44abcdef)
+ mem_update(addr=f3000000,data=11222222_22222222_33222222_44222222)
+ mem_update(addr=f3000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f3000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f3000030,data=01333311_02333311_03333311_04333311)
+
+ wait( level=PART )
+ wait( level=PART )
+
+
+
+
+
+ write ( addr=f0000000, size=0000, be=11111111 )
+ write ( addr=f1000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0001, be=11111111 )
+ write ( addr=f3000000, size=1010, be=10000000 )
+ write ( addr=f2000000, size=0001, be=11111111 )
+ write ( addr=f3000000, size=1010, be=10000000 )
+ write ( addr=f1000000, size=0000, be=11111111 )
+ write ( addr=f0000000, size=1010, be=01110000 )
+ write ( addr=f1000000, size=1010, be=10000000 )
+
+
+
+ -- this causes several address-pipelining situations
+ read ( addr=f1000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0001, be=11111111 )
+ read ( addr=f1000000, size=0000, be=11111111 )
+ read ( addr=f1000000, size=1010, be=00110000 )
+ read ( addr=f3000000, size=1010, be=00110000 )
+ read ( addr=f2000000, size=0001, be=11111111 )
+ read ( addr=f1000000, size=1010, be=00100000 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=1010, be=00010000 )
+
+
+ wait( level = SUBSUBPART )
+ wait( level = SUBSUBPART )
+ wait( level = SUBSUBPART )
+
+ write ( addr=f0000000, size=0000, be=11111111 )
+ read ( addr=f0000000, size=0000, be=11111111 )
+ write ( addr=f1000000, size=0001, be=11111111 )
+ read ( addr=f1000000, size=0001, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f3000000, size=0001, be=11111111 )
+ read ( addr=f3000000, size=0001, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0001, be=11111111 )
+ read ( addr=f2000000, size=0001, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=1010, be=00110000 )
+ write ( addr=f3000000, size=0001, be=11111111 )
+ read ( addr=f3000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=1010, be=00010000 )
+ read ( addr=f2000000, size=0001, be=11111111 )
+ read ( addr=f2000000, size=1010, be=00110000 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+
+
+
+
+
+
+ ---------------------------------
+ -- 128-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_128/plb_bfm_master_128/master,device_type=plb_master)
+ configure(msize=10)
+
+
+
+
+ mem_update(addr=f0000000,data=11223344_22223344_33223344_44223344)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f0000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f0000030,data=01333311_02333311_03333311_04333311)
+ mem_update(addr=f1000000,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000010,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000020,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000030,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f2000000,data=11abcdef_22abcdef_33abcdef_44abcdef)
+ mem_update(addr=f3000000,data=11222222_22222222_33222222_44222222)
+ mem_update(addr=f3000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f3000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f3000030,data=01333311_02333311_03333311_04333311)
+
+ wait( level=PART )
+ wait( level=PART )
+ wait( level=PART )
+ wait( level=PART )
+
+
+
+ write ( addr=f0000000, size=0000, be=1111111111111111 )
+ write ( addr=f1000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0001, be=1111111111111111 )
+ write ( addr=f3000000, size=1010, be=1000000000000000 )
+ write ( addr=f2000000, size=0001, be=1111111111111111 )
+ write ( addr=f3000000, size=1010, be=1000000000000000 )
+ write ( addr=f1000000, size=0000, be=1111111111111111 )
+ write ( addr=f0000000, size=1010, be=0111000000000000 )
+
+
+
+ -- this causes several address-pipelining situations
+ read ( addr=f1000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0001, be=1111111111111111 )
+ read ( addr=f1000000, size=0000, be=1111111111111111 )
+ read ( addr=f1000000, size=1010, be=0011000000000000 )
+ read ( addr=f3000000, size=1010, be=0011000000000000 )
+ read ( addr=f2000000, size=0001, be=1111111111111111 )
+ read ( addr=f1000000, size=1010, be=0100000000000000 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=1010, be=0001000000000000 )
+
+
+ wait( level = SUBSUBPART )
+
+ write ( addr=f0000000, size=0000, be=1111111111111111 )
+ read ( addr=f0000000, size=0000, be=1111111111111111 )
+ write ( addr=f1000000, size=0001, be=1111111111111111 )
+ read ( addr=f1000000, size=0001, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f3000000, size=0001, be=1111111111111111 )
+ read ( addr=f3000000, size=0001, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0001, be=1111111111111111 )
+ read ( addr=f2000000, size=0001, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=1010, be=0011000000000000 )
+ write ( addr=f3000000, size=0001, be=1111111111111111 )
+ read ( addr=f3000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=1010, be=0001000000000000 )
+ read ( addr=f2000000, size=0001, be=1111111111111111 )
+ read ( addr=f2000000, size=1010, be=0011000000000000 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+
+
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/sim.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 40000 ns
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/Makefile
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/wave.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/wave.do (revision 2)
@@ -0,0 +1,54 @@
+
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+
+eval add wave -noupdate $binopt -label Clock -color SteelBlue /system_tb/sys_clk
+eval add wave -noupdate $binopt -label Reset -color SteelBlue /system_tb/sys_rst
+eval add wave -noupdate $hexopt -label synch_in -color Yellow /system_tb/dut/synch_in
+
+
+
+eval add wave -noupdate $binopt -label Mn_request -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_request
+
+eval add wave -noupdate $binopt -label Mn_RNW -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_rnw
+eval add wave -noupdate $binopt -label Mn_BE -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_be
+eval add wave -noupdate $binopt -label Mn_size -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_size
+eval add wave -noupdate $binopt -label Mn_type -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_type
+eval add wave -noupdate $hexopt -label Mn_ABus -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_abus
+eval add wave -noupdate $binopt -label PLB_PAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_pavalid
+eval add wave -noupdate $binopt -label PLB_SAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_savalid
+eval add wave -noupdate $binopt -label PLB_rdPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_rdprim
+eval add wave -noupdate $binopt -label PLB_wrPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_wrprim
+
+eval add wave -noupdate $hexopt -label Sl_rdDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddbus
+eval add wave -noupdate $binopt -label Sl_rdDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddack
+eval add wave -noupdate $binopt -label Sl_rdComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rdcomp
+
+eval add wave -noupdate $hexopt -label Sl_wrDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/plb_wrdbus
+eval add wave -noupdate $binopt -label Sl_wrDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrdack
+eval add wave -noupdate $binopt -label Sl_wrComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrcomp
+
+
+
+eval add wave -noupdate $binopt -label WB_CLK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_clk_i
+eval add wave -noupdate $binopt -label WB_RST_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rst_i
+eval add wave -noupdate $hexopt -label WB_ADR_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_adr_o
+eval add wave -noupdate $hexopt -label WB_DAT_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_o
+eval add wave -noupdate $hexopt -label WB_DAT_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_i
+eval add wave -noupdate $binopt -label WB_ACK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_ack_i
+eval add wave -noupdate $binopt -label WB_SEL_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_sel_o
+eval add wave -noupdate $binopt -label WB_STB_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_stb_o
+eval add wave -noupdate $binopt -label WB_LOCK_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_lock_o
+eval add wave -noupdate $binopt -label WB_WE_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_we_o
+
+
+
+eval add wave -noupdate $binopt -label bram0_ack_o -color Orange /system_tb/dut/onchip_ram_0/wb_ack_o
+eval add wave -noupdate $binopt -label bram1_ack_o -color Orange /system_tb/dut/onchip_ram_1/wb_ack_o
+eval add wave -noupdate $binopt -label bram2_ack_o -color Orange /system_tb/dut/onchip_ram_2/wb_ack_o
+eval add wave -noupdate $binopt -label bram3_ack_o -color Orange /system_tb/dut/onchip_ram_3/wb_ack_o
+
+
+configure wave -gridperiod 1
+configure wave -namecolwidth 200
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/transfers.bfl (revision 2)
@@ -0,0 +1,140 @@
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+
+ mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
+ mem_update(addr=f0000010,data=01111100_02111100_03111100_04111100)
+ mem_update(addr=f0000020,data=01222200_02222200_03222200_04222200)
+ mem_update(addr=f0000030,data=01333300_02333300_03333300_04333300)
+
+ mem_update(addr=f1000000,data=01000011_02000011_03000011_04000011)
+ mem_update(addr=f1000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f1000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f1000030,data=01333311_02333311_03333311_04333311)
+
+-- mem_update(addr=f2000000,data=01000022_02000022_03000022_04000022)
+-- mem_update(addr=f2000010,data=01111122_02111122_03111122_04111122)
+-- mem_update(addr=f2000020,data=01222222_02222222_03222222_04222222)
+-- mem_update(addr=f2000030,data=01333322_02333322_03333322_04333322)
+--
+-- mem_update(addr=f3000000,data=01000033_02000033_03000033_04000033)
+-- mem_update(addr=f3000010,data=01111133_02111133_03111133_04111133)
+-- mem_update(addr=f3000020,data=01222233_02222233_03222233_04222233)
+-- mem_update(addr=f3000030,data=01333333_02333333_03333333_04333333)
+
+
+
+ wait( level=PART )
+
+ write ( addr=f0000000, size=1010, be=1111 )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ write ( addr=f1000000, size=1010, be=1000 )
+
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=1010, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=1010, be=1000 )
+
+
+
+ ---------------------------------
+ -- 64-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_64/plb_bfm_master_64/master,device_type=plb_master)
+ configure(msize=01)
+
+ mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
+ mem_update(addr=f0000010,data=01111100_02111100_03111100_04111100)
+ mem_update(addr=f0000020,data=01222200_02222200_03222200_04222200)
+ mem_update(addr=f0000030,data=01333300_02333300_03333300_04333300)
+
+ mem_update(addr=f1000000,data=01000011_02000011_03000011_04000011)
+ mem_update(addr=f1000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f1000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f1000030,data=01333311_02333311_03333311_04333311)
+
+
+
+ wait( level=PART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+
+ write ( addr=f0000000, size=1010, be=1101 )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ write ( addr=f1000000, size=1010, be=0100 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=1010, be=1101 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=1010, be=0100 )
+
+
+
+
+ ---------------------------------
+ -- 128-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_128/plb_bfm_master_128/master,device_type=plb_master)
+ configure(msize=10)
+
+ mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
+ mem_update(addr=f0000010,data=01111100_02111100_03111100_04111100)
+ mem_update(addr=f0000020,data=01222200_02222200_03222200_04222200)
+ mem_update(addr=f0000030,data=01333300_02333300_03333300_04333300)
+
+ mem_update(addr=f1000000,data=01000011_02000011_03000011_04000011)
+ mem_update(addr=f1000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f1000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f1000030,data=01333311_02333311_03333311_04333311)
+
+
+
+
+
+ wait( level=PART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+
+ write ( addr=f0000000, size=1010, be=0001 )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ write ( addr=f1000000, size=1010, be=1110 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=1010, be=0001 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=1010, be=1110 )
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/sim.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 6000 ns
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/Makefile
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/wave.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/wave.do (revision 2)
@@ -0,0 +1,54 @@
+
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+
+eval add wave -noupdate $binopt -label Clock -color SteelBlue /system_tb/sys_clk
+eval add wave -noupdate $binopt -label Reset -color SteelBlue /system_tb/sys_rst
+eval add wave -noupdate $hexopt -label synch_in -color Yellow /system_tb/dut/synch_in
+
+
+
+eval add wave -noupdate $binopt -label Mn_request -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_request
+
+eval add wave -noupdate $binopt -label Mn_RNW -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_rnw
+eval add wave -noupdate $binopt -label Mn_BE -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_be
+eval add wave -noupdate $binopt -label Mn_size -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_size
+eval add wave -noupdate $binopt -label Mn_type -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_type
+eval add wave -noupdate $hexopt -label Mn_ABus -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_abus
+eval add wave -noupdate $binopt -label PLB_PAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_pavalid
+eval add wave -noupdate $binopt -label PLB_SAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_savalid
+eval add wave -noupdate $binopt -label PLB_rdPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_rdprim
+eval add wave -noupdate $binopt -label PLB_wrPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_wrprim
+
+eval add wave -noupdate $hexopt -label Sl_rdDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddbus
+eval add wave -noupdate $binopt -label Sl_rdDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddack
+eval add wave -noupdate $binopt -label Sl_rdComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rdcomp
+
+eval add wave -noupdate $hexopt -label Sl_wrDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/plb_wrdbus
+eval add wave -noupdate $binopt -label Sl_wrDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrdack
+eval add wave -noupdate $binopt -label Sl_wrComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrcomp
+
+
+
+eval add wave -noupdate $binopt -label WB_CLK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_clk_i
+eval add wave -noupdate $binopt -label WB_RST_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rst_i
+eval add wave -noupdate $hexopt -label WB_ADR_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_adr_o
+eval add wave -noupdate $hexopt -label WB_DAT_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_o
+eval add wave -noupdate $hexopt -label WB_DAT_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_i
+eval add wave -noupdate $binopt -label WB_ACK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_ack_i
+eval add wave -noupdate $binopt -label WB_SEL_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_sel_o
+eval add wave -noupdate $binopt -label WB_STB_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_stb_o
+eval add wave -noupdate $binopt -label WB_LOCK_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_lock_o
+eval add wave -noupdate $binopt -label WB_WE_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_we_o
+
+
+
+eval add wave -noupdate $binopt -label bram0_ack_o -color Orange /system_tb/dut/onchip_ram_0/wb_ack_o
+eval add wave -noupdate $binopt -label bram1_ack_o -color Orange /system_tb/dut/onchip_ram_1/wb_ack_o
+eval add wave -noupdate $binopt -label bram2_ack_o -color Orange /system_tb/dut/onchip_ram_2/wb_ack_o
+eval add wave -noupdate $binopt -label bram3_ack_o -color Orange /system_tb/dut/onchip_ram_3/wb_ack_o
+
+
+configure wave -gridperiod 1
+configure wave -namecolwidth 200
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/transfers.bfl (revision 2)
@@ -0,0 +1,92 @@
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+ mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+
+ mem_update(addr=f1000000,data=01000000_02000000_03000000_04000000)
+
+
+ wait( level=PART )
+
+ write ( addr=f0000000, size=0010, be=1111111111111111 )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ write ( addr=f1000000, size=0001, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0010, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0001, be=1111111111111111 )
+
+
+
+ ---------------------------------
+ -- 64-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_64/plb_bfm_master_64/master,device_type=plb_master)
+ configure(msize=01)
+ mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+
+ mem_update(addr=f1000000,data=01000000_02000000_03000000_04000000)
+
+
+ wait( level=PART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+ write ( addr=f0000000, size=0010, be=1111111111111111 )
+ wait ( level=SUBSUBPART )
+ write ( addr=f1000000, size=0001, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0010, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0001, be=1111111111111111 )
+
+
+ ---------------------------------
+ -- 128-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_128/plb_bfm_master_128/master,device_type=plb_master)
+ configure(msize=10)
+
+ mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+
+ mem_update(addr=f1000000,data=01000000_02000000_03000000_04000000)
+
+
+
+ wait( level=PART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+ write ( addr=f0000000, size=0010, be=1111111111111111 )
+ wait ( level=SUBSUBPART )
+ write ( addr=f1000000, size=0001, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0010, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0001, be=1111111111111111 )
+
+
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/sim.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 6000 ns
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/Makefile
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/wave.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/wave.do (revision 2)
@@ -0,0 +1,54 @@
+
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+
+eval add wave -noupdate $binopt -label Clock -color SteelBlue /system_tb/sys_clk
+eval add wave -noupdate $binopt -label Reset -color SteelBlue /system_tb/sys_rst
+eval add wave -noupdate $hexopt -label synch_in -color Yellow /system_tb/dut/synch_in
+
+
+
+eval add wave -noupdate $binopt -label Mn_request -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_request
+
+eval add wave -noupdate $binopt -label Mn_RNW -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_rnw
+eval add wave -noupdate $binopt -label Mn_BE -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_be
+eval add wave -noupdate $binopt -label Mn_size -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_size
+eval add wave -noupdate $binopt -label Mn_type -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_type
+eval add wave -noupdate $hexopt -label Mn_ABus -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_abus
+eval add wave -noupdate $binopt -label PLB_PAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_pavalid
+eval add wave -noupdate $binopt -label PLB_SAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_savalid
+eval add wave -noupdate $binopt -label PLB_rdPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_rdprim
+eval add wave -noupdate $binopt -label PLB_wrPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_wrprim
+
+eval add wave -noupdate $hexopt -label Sl_rdDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddbus
+eval add wave -noupdate $binopt -label Sl_rdDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddack
+eval add wave -noupdate $binopt -label Sl_rdComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rdcomp
+
+
+eval add wave -noupdate $hexopt -label Sl_wrDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/plb_wrdbus
+eval add wave -noupdate $binopt -label Sl_wrDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrdack
+eval add wave -noupdate $binopt -label Sl_wrComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrcomp
+
+
+eval add wave -noupdate $binopt -label WB_CLK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_clk_i
+eval add wave -noupdate $binopt -label WB_RST_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rst_i
+eval add wave -noupdate $hexopt -label WB_ADR_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_adr_o
+eval add wave -noupdate $hexopt -label WB_DAT_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_o
+eval add wave -noupdate $hexopt -label WB_DAT_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_i
+eval add wave -noupdate $binopt -label WB_ACK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_ack_i
+eval add wave -noupdate $binopt -label WB_SEL_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_sel_o
+eval add wave -noupdate $binopt -label WB_STB_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_stb_o
+eval add wave -noupdate $binopt -label WB_LOCK_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_lock_o
+eval add wave -noupdate $binopt -label WB_WE_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_we_o
+
+
+
+eval add wave -noupdate $binopt -label bram0_ack_o -color Orange /system_tb/dut/onchip_ram_0/wb_ack_o
+eval add wave -noupdate $binopt -label bram1_ack_o -color Orange /system_tb/dut/onchip_ram_1/wb_ack_o
+eval add wave -noupdate $binopt -label bram2_ack_o -color Orange /system_tb/dut/onchip_ram_2/wb_ack_o
+eval add wave -noupdate $binopt -label bram3_ack_o -color Orange /system_tb/dut/onchip_ram_3/wb_ack_o
+
+
+configure wave -gridperiod 1
+configure wave -namecolwidth 200
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/transfers.bfl (revision 2)
@@ -0,0 +1,164 @@
+
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+
+
+ mem_update(addr=f0000000,data=11223344)
+ mem_update(addr=f1000000,data=ffeeffee)
+ mem_update(addr=f2000000,data=98765432)
+ mem_update(addr=f3000000,data=12341234)
+
+ wait( level=PART )
+
+ write ( addr=f0000000, size=0000, be=1111 )
+ write ( addr=f1000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f3000000, size=0000, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0000, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0000, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f2000000, size=0000, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f3000000, size=0000, be=1111 )
+
+
+
+
+ --
+ -- byte-enable test
+ --
+ mem_update(addr=f0000000,data=feefbaab_cddcbbaa_12212112_54437643)
+
+ write ( addr=f0000000, size=0000, be=1000 )
+ write ( addr=f0000001, size=0000, be=0100 )
+ write ( addr=f0000002, size=0000, be=0010 )
+ write ( addr=f0000003, size=0000, be=0001 )
+
+ read ( addr=f0000000, size=0000, be=1111 )
+
+ read ( addr=f0000000, size=0000, be=1000 )
+ read ( addr=f0000001, size=0000, be=0100 )
+ read ( addr=f0000002, size=0000, be=0010 )
+ read ( addr=f0000003, size=0000, be=0001 )
+
+
+
+
+ write ( addr=f0000004, size=0000, be=1100 )
+ write ( addr=f0000006, size=0000, be=0011 )
+
+ read ( addr=f0000004, size=0000, be=1111 )
+ read ( addr=f0000004, size=0000, be=1100 )
+ read ( addr=f0000006, size=0000, be=0011 )
+
+
+
+
+
+
+ ---------------------------------
+ -- 64-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_64/plb_bfm_master_64/master,device_type=plb_master)
+ configure(msize=01)
+
+
+ mem_update(addr=f0000000,data=11223344_55446677)
+ mem_update(addr=f1000000,data=ffeeffee_eeffeeff)
+ mem_update(addr=f2000000,data=98765432_10000000)
+ mem_update(addr=f3000000,data=12341234_43214321)
+
+ wait( level=PART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+ write ( addr=f0000000, size=0000, be=11111111 )
+ write ( addr=f1000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f3000000, size=0000, be=11111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0000, be=11111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0000, be=11111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f2000000, size=0000, be=11111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f3000000, size=0000, be=11111111 )
+
+
+
+
+
+
+
+
+ ---------------------------------
+ -- 128-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_128/plb_bfm_master_128/master,device_type=plb_master)
+ configure(msize=10)
+
+
+ mem_update(addr=f0000000,data=11223344_55446677_8899aabb_ccddeeff)
+ mem_update(addr=f1000000,data=ffeeffee_eeffeeff_efefefef_fefefefe)
+ mem_update(addr=f2000000,data=98765432_10000000_00110011_23456789)
+ mem_update(addr=f3000000,data=12341234_43214321_14251425_63524152)
+
+ wait( level=PART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+ write ( addr=f0000000, size=0000, be=1111111111111111 )
+ write ( addr=f1000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f3000000, size=0000, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0000, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0000, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f3000000, size=0000, be=1111111111111111 )
+
+
+
+
+
+
+
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/sim.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 11000 ns
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/Makefile
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/Makefile
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/simulation/Makefile (revision 2)
@@ -0,0 +1,112 @@
+SIM_DIR=$(shell pwd)
+
+XPS_PROJ_DIR=$(SIM_DIR)/..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+COMMON_DIR=$(SIM_DIR)/../../common
+LOG_DIR=$(SIM_DIR)/log
+PLB_BFM_SETUP_DIR=$(SIM_DIR)/../../plb_bfm_setup
+
+
+include $(COMMON_DIR)/Makefile
+
+
+
+all: sim
+
+
+TEST_CASES += test_cases/simple_read_write
+
+WORK_TARGET=$(SIM_BIN_DIR)/work/system/_primary.dat
+
+
+
+###
+#
+# note: WORK_TARGET is defined some lines above, the rest in ../../common/Makefile
+#
+COMPILE_COMPONENTS=$(TESTRAM_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET) $(PLB_BFM_TARGET) $(WORK_TARGET)
+
+
+
+#
+# Generate Simulation HDL Files
+# (This is the same than XPS-Gui->Simulation->Generate Simulation HDL Files)
+#
+$(SIM_DIR)/behavioral: $(XPS_PROJ_DIR)/system.mhs
+ @mkdir -p $(LOG_DIR)
+ simgen $(XPS_PROJ_DIR)/system.mhs -lang vhdl \
+ -p virtex5 \
+ -m beh \
+ -od $(XPS_PROJ_DIR)/ \
+ -s mti \
+ -lp $(LIB_DIR) \
+ -log $(LOG_DIR)/simgen
+ @mv simgen.opt log # there is no simgen-flag for this!
+
+
+
+
+
+# PLB_BFM_TARGET=$(SIM_BIN_DIR)/plbv46_bfm/system/_primary.dat
+# #BFM_SOURCE=$() TODO
+# $(PLB_BFM_TARGET):
+# cd $(SIM_BIN_DIR); \
+# vlib plbv46_bfm; \
+# vmap plbv46_bfm plbv46_bfm; \
+# vlib plbv46_master_bfm_v1_00_a; \
+# vmap plbv46_master_bfm_v1_00_a plbv46_master_bfm_v1_00_a; \
+# vlib plbv46_monitor_bfm_v1_00_a; \
+# vmap plbv46_monitor_bfm_v1_00_a plbv46_monitor_bfm_v1_00_a; \
+# vlib plbv46_slave_bfm_v1_00_a; \
+# vmap plbv46_slave_bfm_v1_00_a plbv46_slave_bfm_v1_00_a; \
+# vcom $(VHDL_CFLAGS) -work plbv46_bfm \
+# "$(PLB_BFM_SETUP_DIR)/plb_dcl_128.vhd"; \
+# vcom $(VHDL_CFLAGS) -work plbv46_master_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_master_bfm_v1_00_a/hdl/vhdl/plbv46_master_bfm.vhd" ; \
+# vcom $(VHDL_CFLAGS) -work plbv46_monitor_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_monitor_bfm_v1_00_a/hdl/vhdl/plbv46_monitor_bfm.vhd";\
+# vcom $(VHDL_CFLAGS) -work plbv46_slave_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_slave_bfm_v1_00_a/hdl/vhdl/plbv46_slave_bfm.vhd";
+
+
+
+
+
+$(WORK_TARGET): $(SIM_DIR)/behavioral $(SIM_BIN_DIR)/../testbench/system_tb.vhd
+ cd $(SIM_BIN_DIR); \
+ vlib work; \
+ vmap work work; \
+ vlog -novopt -93 -work work "../behavioral/wb_conbus_0_wrapper.v"; \
+ vcom $(VHDL_CFLAGS) -work work \
+ "../behavioral/onchip_ram_0_wrapper.vhd" \
+ "../behavioral/onchip_ram_1_wrapper.vhd" \
+ "../behavioral/onchip_ram_2_wrapper.vhd" \
+ "../behavioral/onchip_ram_3_wrapper.vhd" \
+ "../behavioral/mb_plb_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_32_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_64_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_128_wrapper.vhd" \
+ "../behavioral/plb_bfm_monitor_wrapper.vhd" \
+ "../behavioral/plb_bfm_slave_wrapper.vhd" \
+ "../behavioral/plb_bfm_synch_wrapper.vhd" \
+ "../behavioral/plb2wb_bridge_0_wrapper.vhd" \
+ "../behavioral/system.vhd" \
+ "../testbench/system_tb.vhd"
+
+
+
+
+
+
+compile: $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS)
+
+
+
+
+
+clean:
+ rm -rf \
+ $(SIM_DIR)/behavioral \
+ $(SIM_BIN_DIR) \
+ $(LOG_DIR)
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/system.mss
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/system.mss (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/system.mss (revision 2)
@@ -0,0 +1,43 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = plb_bfm_slave
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = plb2wb_bridge_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_3
+END
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/system.xmp
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/system.xmp (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/system.xmp (revision 2)
@@ -0,0 +1,25 @@
+#Please do not modify this file by hand
+XmpVersion: 11.4
+VerMgmt: 11.4
+IntStyle: default
+ModuleSearchPath: ../../EDK_Libs/
+MHS File: system.mhs
+MSS File: system.mss
+Architecture: virtex5
+Device: xc5vlx50
+Package: ff676
+SpeedGrade: -1
+UserCmd1:
+UserCmd1Type: 0
+UserCmd2:
+UserCmd2Type: 0
+GenSimTB: 0
+SdkExportBmmBit: 1
+SdkExportDir: SDK/SDK_Export
+InsertNoPads: 0
+WarnForEAArch: 1
+HdlLang: VHDL
+SimModel: BEHAVIORAL
+UcfFile: data/system.ucf
+EnableParTimingError: 1
+ShowLicenseDialog: 1
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/data/system.ucf
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/data/system.ucf (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/data/system.ucf (revision 2)
@@ -0,0 +1,6 @@
+# Virtex 5 ML501 Evaluation Platform
+Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
+TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
+Net fpga_0_clk_1_sys_clk_pin LOC = AD8 | IOSTANDARD=LVCMOS33;
+Net fpga_0_rst_1_sys_rst_pin TIG;
+Net fpga_0_rst_1_sys_rst_pin LOC = T23 | IOSTANDARD=LVCMOS33 | PULLUP;
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/system.mhs
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/system.mhs (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/system.mhs (revision 2)
@@ -0,0 +1,171 @@
+
+# ##############################################################################
+# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
+# Fri Mar 5 18:02:26 2010
+# Target Board: Xilinx Virtex 5 ML501 Evaluation Platform Rev 1
+# Family: virtex5
+# Device: xc5vlx50
+# Package: ff676
+# Speed Grade: -1
+# Processor number: 1
+# Processor 1: microblaze_0
+# System clock frequency: 125.0
+# Debug Interface: On-Chip HW Debug Module
+# ##############################################################################
+ PARAMETER VERSION = 2.1.0
+
+
+ PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
+ PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
+ PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]
+ PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]
+
+
+BEGIN plb_v46
+ PARAMETER INSTANCE = mb_plb
+ PARAMETER HW_VER = 1.04.a
+ PARAMETER C_EXT_RESET_HIGH = 1
+ PARAMETER C_DCR_INTFCE = 1
+ PARAMETER C_BASEADDR = 0b0000000000
+ PARAMETER C_HIGHADDR = 0b1111111111
+ PORT PLB_Clk = clk_100MHz
+ PORT SYS_Rst = sys_rst_s
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_32
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_SIZE = 0b10
+ PARAMETER PLB_MASTER_NUM = 0b0000
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_0
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_64
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ PARAMETER PLB_MASTER_SIZE = 0b10
+ PARAMETER PLB_MASTER_NUM = 0b0001
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_1
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_128
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ PARAMETER PLB_MASTER_NUM = 0b0010
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_2
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_monitor_bfm
+ PARAMETER INSTANCE = plb_bfm_monitor
+ PARAMETER HW_VER = 1.00.a
+ BUS_INTERFACE MON_PLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_3
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_slave_bfm
+ PARAMETER INSTANCE = plb_bfm_slave
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_SLAVE_ADDR_LO_0 = 0xF8000000
+ PARAMETER PLB_SLAVE_ADDR_HI_0 = 0xFFFFfFFF
+ PARAMETER C_SPLB_NATIVE_DWIDTH = 32
+ PARAMETER PLB_SLAVE_SIZE = 0b00
+ BUS_INTERFACE SPLB = mb_plb
+ PORT SYNCH_IN = synch_in
+ PORT SYNCH_OUT = bfm_synch_out_4
+END
+
+BEGIN bfm_synch
+ PARAMETER INSTANCE = plb_bfm_synch
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_NUM_SYNCH = 5
+ PORT TO_SYNCH_IN = synch_out
+ PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_1 & bfm_synch_out_2 & bfm_synch_out_3 & bfm_synch_out_4
+END
+
+BEGIN plb2wb_bridge
+ PARAMETER INSTANCE = plb2wb_bridge_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_BASEADDR = 0xf0000000
+ PARAMETER C_HIGHADDR = 0xf7ffffff
+ PARAMETER WB_ADR_OFFSET = 0xf0000000
+ PARAMETER WB_ADR_OFFSET_NEG = 1
+ PARAMETER WB_PIC_INTS = 1
+ BUS_INTERFACE SPLB = mb_plb
+ BUS_INTERFACE MWB = wb_conbus_0
+ PORT SPLB_Clk = clk_100MHz
+ PORT wb_clk_i = clk_100MHz
+ PORT wb_rst_i = sys_rst_s
+ PORT wb_pic_int_i = net_gnd
+END
+
+BEGIN wb_conbus
+ PARAMETER INSTANCE = wb_conbus_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER wb_s0_addr = 0x00
+ PARAMETER wb_s27_addr_w = 8
+ PARAMETER wb_s1_addr = 0x01
+ PARAMETER wb_s2_addr = 0x02
+ PARAMETER wb_s3_addr = 0x03
+ PARAMETER wb_s4_addr = 0x04
+ PARAMETER wb_s5_addr = 0x05
+ PARAMETER wb_s6_addr = 0x06
+ PARAMETER wb_s7_addr = 0x07
+ PARAMETER wb_s0_addr_w = 8
+ PARAMETER wb_s1_addr_w = 8
+ PORT wb_rst_i = sys_rst_s
+ PORT wb_clk_i = clk_100MHz
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 0
+ PARAMETER WR_DELAY = 0
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_rst_i = sys_rst_s
+ PORT wb_clk_i = clk_100MHz
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_1
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 1
+ PARAMETER WR_DELAY = 1
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = clk_100MHz
+ PORT wb_rst_i = sys_rst_s
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_2
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 3
+ PARAMETER WR_DELAY = 3
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = clk_100MHz
+ PORT wb_rst_i = sys_rst_s
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_3
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 5
+ PARAMETER WR_DELAY = 5
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = clk_100MHz
+ PORT wb_rst_i = sys_rst_s
+END
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/etc/bitgen.ut
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/etc/bitgen.ut (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/etc/bitgen.ut (revision 2)
@@ -0,0 +1,14 @@
+-g TdoPin:PULLNONE
+-g DriveDone:No
+-g StartUpClk:JTAGCLK
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g TckPin:PULLUP
+-g TdiPin:PULLUP
+-g TmsPin:PULLUP
+-g DonePipe:No
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:NONE
+-g Persist:No
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/etc/fast_runtime.opt
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/etc/fast_runtime.opt (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/etc/fast_runtime.opt (revision 2)
@@ -0,0 +1,84 @@
+FLOWTYPE = FPGA;
+###############################################################
+## Filename: fast_runtime.opt
+##
+## Option File For Xilinx FPGA Implementation Flow for Fast
+## Runtime.
+##
+## Version: 4.1.1
+###############################################################
+#
+# Options for Translator
+#
+# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
+#
+Program ngdbuild
+-p ; # Partname to use - picked from xflow commandline
+-nt timestamp; # NGO File generation. Regenerate only when
+ # source netlist is newer than existing
+ # NGO file (default)
+-bm .bmm # Block RAM memory map file
+; # User design - pick from xflow command line
+-uc .ucf; # ucf constraints
+.ngd; # Name of NGD file. Filebase same as design filebase
+End Program ngdbuild
+
+#
+# Options for Mapper
+#
+# Type "map -h " for a detailed list of map command line options
+#
+Program map
+-o _map.ncd; # Output Mapped ncd file
+-w; # Overwrite output files.
+-pr b; # Pack internal FF/latches into IOBs
+#-fp .mfp; # Floorplan file
+-ol high;
+-timing;
+-detail;
+.ngd; # Input NGD file
+.pcf; # Physical constraints file
+END Program map
+
+#
+# Options for Post Map Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_map_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o _map.twr; # Output trace report file
+-xml _map.twx; # Output XML version of the timing report
+#-tsi _map.tsi; # Produce Timing Specification Interaction report
+_map.ncd; # Input mapped ncd
+.pcf; # Physical constraints file
+END Program post_map_trce
+
+#
+# Options for Place and Route
+#
+# Type "par -h" for a detailed list of par command line options
+#
+Program par
+-w; # Overwrite existing placed and routed ncd
+-ol high; # Overall effort level
+_map.ncd; # Input mapped NCD file
+.ncd; # Output placed and routed NCD
+.pcf; # Input physical constraints file
+END Program par
+
+#
+# Options for Post Par Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_par_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o .twr; # Output trace report file
+-xml .twx; # Output XML version of the timing report
+#-tsi .tsi; # Produce Timing Specification Interaction report
+.ncd; # Input placed and routed ncd
+.pcf; # Physical constraints file
+END Program post_par_trce
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/etc/download.cmd
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/etc/download.cmd (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_syn/etc/download.cmd (revision 2)
@@ -0,0 +1,6 @@
+setMode -bscan
+setCable -p auto
+identify
+assignfile -p 4 -file implementation/download.bit
+program -p 4
+quit
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/testbench/system_tb.vhd
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/testbench/system_tb.vhd (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/testbench/system_tb.vhd (revision 2)
@@ -0,0 +1,146 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+entity system_tb is
+end system_tb;
+
+architecture STRUCTURE of system_tb is
+
+ constant sys_clk_period : time := 10.000000 ns;
+ constant wb_clk_period : time := 13.333333 ns;
+ constant sys_rst_length : time := 160 ns;
+
+ constant SYNCH_PART : integer := 1;
+ constant SYNCH_SUBPART : integer := 2;
+ constant SYNCH_SUBSUBPART : integer := 3;
+
+ constant SUBSUBPART_LENGTH : integer := 15; -- 10 clock cycles
+ constant SUBPART_LENGTH : integer := 5; -- 7 times SUBSUBPART_LENGTH
+ constant PART_LENGTH : integer := 5; -- 6 times SUBPART_LENGTH
+
+ component system is
+ port (
+ sys_clk_pin : in std_logic;
+ sys_rst_pin : in std_logic;
+ to_synch_in_pin : in std_logic_vector( 0 to 31 );
+ from_synch_out_pin : out std_logic_vector( 0 to 31 );
+ wb_clk_pin : in std_logic;
+ wb_rst_pin : in std_logic
+ );
+ end component;
+
+
+ signal sys_clk : std_logic;
+ signal sys_rst : std_logic := '1';
+ signal wb_clk : std_logic;
+ signal wb_rst : std_logic;
+
+
+ signal to_synch_in : std_logic_vector( 0 to 31 );
+ signal from_synch_out : std_logic_vector( 0 to 31 );
+ signal tb_synch_out : std_logic_vector( 0 to 31 ) := ( others => '0' );
+
+ procedure SendSynch( signal synch_out : OUT std_logic_vector;
+ COMMAND : integer ) is
+ begin
+ synch_out( COMMAND ) <= '1';
+ wait for sys_clk_period*1;
+ synch_out( COMMAND ) <= '0';
+ end procedure SendSynch;
+
+
+begin
+
+ to_synch_in <= from_synch_out or tb_synch_out;
+
+
+
+ dut : system
+ port map (
+ sys_clk_pin => sys_clk,
+ sys_rst_pin => sys_rst,
+ to_synch_in_pin => to_synch_in,
+ from_synch_out_pin => from_synch_out,
+ wb_clk_pin => wb_clk,
+ wb_rst_pin => wb_rst
+ );
+
+
+ --
+ -- generate plb-clk
+ --
+ process
+ begin
+ sys_clk <= '0';
+ loop
+ wait for (sys_clk_period/2);
+ sys_clk <= not sys_clk;
+ end loop;
+ end process;
+
+
+ --
+ --
+ --
+ process
+ begin
+ wb_clk <= '0';
+ loop
+ wait for (wb_clk_period/2);
+ wb_clk <= not wb_clk;
+ end loop;
+ end process;
+
+
+
+
+ process
+ begin
+ sys_rst <= '1';
+ wb_rst <= '1';
+ wait for ( sys_rst_length );
+ wb_rst <= not wb_rst;
+ sys_rst <= not sys_rst;
+ wait;
+ end process;
+
+
+ process
+ begin
+
+ wait until sys_rst = '0';
+ -- wait until masters a ready
+ wait for sys_clk_period * 10;
+
+
+ while true loop
+ for i in 0 to PART_LENGTH-1 loop
+ SendSynch( tb_synch_out, SYNCH_PART );
+
+ for j in 0 to SUBPART_LENGTH-1 loop
+ SendSynch( tb_synch_out, SYNCH_SUBPART );
+
+ for k in 0 to SUBSUBPART_LENGTH loop
+ SendSynch( tb_synch_out, SYNCH_SUBSUBPART );
+ wait for (SUBSUBPART_LENGTH * sys_clk_period );
+ end loop;
+
+
+ end loop;
+
+
+ end loop;
+
+ end loop;
+
+ end process;
+
+
+
+
+end architecture STRUCTURE;
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/wave.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/wave.do (revision 2)
@@ -0,0 +1,54 @@
+
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+
+eval add wave -noupdate $binopt -label Clock -color SteelBlue /system_tb/sys_clk
+eval add wave -noupdate $binopt -label Reset -color SteelBlue /system_tb/sys_rst
+eval add wave -noupdate $hexopt -label synch_in -color Yellow /system_tb/dut/synch_in
+
+
+
+eval add wave -noupdate $binopt -label Mn_request -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_request
+
+eval add wave -noupdate $binopt -label Mn_RNW -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_rnw
+eval add wave -noupdate $binopt -label Mn_BE -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_be
+eval add wave -noupdate $binopt -label Mn_size -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_size
+eval add wave -noupdate $binopt -label Mn_type -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_type
+eval add wave -noupdate $hexopt -label Mn_ABus -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_abus
+eval add wave -noupdate $binopt -label PLB_PAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_pavalid
+eval add wave -noupdate $binopt -label PLB_SAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_savalid
+eval add wave -noupdate $binopt -label PLB_rdPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_rdprim
+eval add wave -noupdate $binopt -label PLB_wrPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_wrprim
+
+eval add wave -noupdate $hexopt -label Sl_rdDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddbus
+eval add wave -noupdate $binopt -label Sl_rdDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddack
+eval add wave -noupdate $binopt -label Sl_rdComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rdcomp
+
+
+eval add wave -noupdate $hexopt -label Sl_wrDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/plb_wrdbus
+eval add wave -noupdate $binopt -label Sl_wrDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrdack
+eval add wave -noupdate $binopt -label Sl_wrComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrcomp
+
+
+eval add wave -noupdate $binopt -label WB_CLK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_clk_i
+eval add wave -noupdate $binopt -label WB_RST_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rst_i
+eval add wave -noupdate $hexopt -label WB_ADR_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_adr_o
+eval add wave -noupdate $hexopt -label WB_DAT_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_o
+eval add wave -noupdate $hexopt -label WB_DAT_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_i
+eval add wave -noupdate $binopt -label WB_ACK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_ack_i
+eval add wave -noupdate $binopt -label WB_SEL_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_sel_o
+eval add wave -noupdate $binopt -label WB_STB_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_stb_o
+eval add wave -noupdate $binopt -label WB_LOCK_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_lock_o
+eval add wave -noupdate $binopt -label WB_WE_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_we_o
+
+
+
+eval add wave -noupdate $binopt -label bram0_ack_o -color Orange /system_tb/dut/onchip_ram_0/wb_ack_o
+eval add wave -noupdate $binopt -label bram1_ack_o -color Orange /system_tb/dut/onchip_ram_1/wb_ack_o
+eval add wave -noupdate $binopt -label bram2_ack_o -color Orange /system_tb/dut/onchip_ram_2/wb_ack_o
+eval add wave -noupdate $binopt -label bram3_ack_o -color Orange /system_tb/dut/onchip_ram_3/wb_ack_o
+
+
+configure wave -gridperiod 1
+configure wave -namecolwidth 200
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/transfers.bfl (revision 2)
@@ -0,0 +1,247 @@
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+
+ mem_update(addr=f0000000,data=11223344_22223344_33223344_44223344)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f0000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f0000030,data=01333311_02333311_03333311_04333311)
+ mem_update(addr=f1000000,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000010,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000020,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000030,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f2000000,data=11abcdef_22abcdef_33abcdef_44abcdef)
+ mem_update(addr=f3000000,data=11222222_22222222_33222222_44222222)
+ mem_update(addr=f3000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f3000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f3000030,data=01333311_02333311_03333311_04333311)
+
+ wait( level=SUBPART )
+
+
+
+ write ( addr=f0000000, size=0000, be=1111 )
+ write ( addr=f1000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0001, be=1111 )
+ write ( addr=f3000000, size=1010, be=1000 )
+ write ( addr=f2000000, size=0001, be=1111 )
+ write ( addr=f3000000, size=1010, be=1000 )
+ write ( addr=f1000000, size=0000, be=1111 )
+ write ( addr=f0000000, size=1010, be=0111 )
+ write ( addr=f1000000, size=1010, be=1000 )
+
+
+
+ -- this causes several address-pipelining situations
+ read ( addr=f1000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0001, be=1111 )
+ read ( addr=f1000000, size=0000, be=1111 )
+ read ( addr=f1000000, size=1010, be=0011 )
+ read ( addr=f2000000, size=1010, be=0011 )
+ read ( addr=f2000000, size=0001, be=1111 )
+ read ( addr=f1000000, size=1010, be=0100 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=1010, be=0001 )
+
+
+ wait( level = SUBSUBPART )
+ wait( level = SUBSUBPART )
+ wait( level = SUBSUBPART )
+
+ write ( addr=f0000000, size=0000, be=1111 )
+ read ( addr=f0000000, size=0000, be=1111 )
+ write ( addr=f1000000, size=0001, be=1111 )
+ read ( addr=f1000000, size=0001, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f3000000, size=0001, be=1111 )
+ read ( addr=f3000000, size=0001, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0001, be=1111 )
+ read ( addr=f2000000, size=0001, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=1010, be=0011 )
+ write ( addr=f3000000, size=0001, be=1111 )
+ read ( addr=f3000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=1010, be=0001 )
+ read ( addr=f2000000, size=0001, be=1111 )
+ read ( addr=f2000000, size=1010, be=0011 )
+ write ( addr=f2000000, size=0000, be=1111 )
+
+
+
+
+
+ ---------------------------------
+ -- 64-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_64/plb_bfm_master_64/master,device_type=plb_master)
+ configure(msize=01)
+
+
+ mem_update(addr=f0000000,data=11223344_22223344_33223344_44223344)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f0000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f0000030,data=01333311_02333311_03333311_04333311)
+ mem_update(addr=f1000000,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000010,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000020,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000030,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f2000000,data=11abcdef_22abcdef_33abcdef_44abcdef)
+ mem_update(addr=f3000000,data=11222222_22222222_33222222_44222222)
+ mem_update(addr=f3000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f3000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f3000030,data=01333311_02333311_03333311_04333311)
+
+ wait( level=PART )
+ wait( level=PART )
+
+
+
+
+
+ write ( addr=f0000000, size=0000, be=11111111 )
+ write ( addr=f1000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0001, be=11111111 )
+ write ( addr=f3000000, size=1010, be=10000000 )
+ write ( addr=f2000000, size=0001, be=11111111 )
+ write ( addr=f3000000, size=1010, be=10000000 )
+ write ( addr=f1000000, size=0000, be=11111111 )
+ write ( addr=f0000000, size=1010, be=01110000 )
+ write ( addr=f1000000, size=1010, be=10000000 )
+
+
+
+ -- this causes several address-pipelining situations
+ read ( addr=f1000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0001, be=11111111 )
+ read ( addr=f1000000, size=0000, be=11111111 )
+ read ( addr=f1000000, size=1010, be=00110000 )
+ read ( addr=f3000000, size=1010, be=00110000 )
+ read ( addr=f2000000, size=0001, be=11111111 )
+ read ( addr=f1000000, size=1010, be=00100000 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=1010, be=00010000 )
+
+
+ wait( level = SUBSUBPART )
+ wait( level = SUBSUBPART )
+ wait( level = SUBSUBPART )
+
+ write ( addr=f0000000, size=0000, be=11111111 )
+ read ( addr=f0000000, size=0000, be=11111111 )
+ write ( addr=f1000000, size=0001, be=11111111 )
+ read ( addr=f1000000, size=0001, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f3000000, size=0001, be=11111111 )
+ read ( addr=f3000000, size=0001, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0001, be=11111111 )
+ read ( addr=f2000000, size=0001, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=1010, be=00110000 )
+ write ( addr=f3000000, size=0001, be=11111111 )
+ read ( addr=f3000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=1010, be=00010000 )
+ read ( addr=f2000000, size=0001, be=11111111 )
+ read ( addr=f2000000, size=1010, be=00110000 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+
+
+
+
+
+
+ ---------------------------------
+ -- 128-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_128/plb_bfm_master_128/master,device_type=plb_master)
+ configure(msize=10)
+
+
+
+
+ mem_update(addr=f0000000,data=11223344_22223344_33223344_44223344)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f0000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f0000030,data=01333311_02333311_03333311_04333311)
+ mem_update(addr=f1000000,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000010,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000020,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000030,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f2000000,data=11abcdef_22abcdef_33abcdef_44abcdef)
+ mem_update(addr=f3000000,data=11222222_22222222_33222222_44222222)
+ mem_update(addr=f3000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f3000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f3000030,data=01333311_02333311_03333311_04333311)
+
+ wait( level=PART )
+ wait( level=PART )
+ wait( level=PART )
+ wait( level=PART )
+
+
+
+ write ( addr=f0000000, size=0000, be=1111111111111111 )
+ write ( addr=f1000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0001, be=1111111111111111 )
+ write ( addr=f3000000, size=1010, be=1000000000000000 )
+ write ( addr=f2000000, size=0001, be=1111111111111111 )
+ write ( addr=f3000000, size=1010, be=1000000000000000 )
+ write ( addr=f1000000, size=0000, be=1111111111111111 )
+ write ( addr=f0000000, size=1010, be=0111000000000000 )
+
+
+
+ -- this causes several address-pipelining situations
+ read ( addr=f1000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0001, be=1111111111111111 )
+ read ( addr=f1000000, size=0000, be=1111111111111111 )
+ read ( addr=f1000000, size=1010, be=0011000000000000 )
+ read ( addr=f3000000, size=1010, be=0011000000000000 )
+ read ( addr=f2000000, size=0001, be=1111111111111111 )
+ read ( addr=f1000000, size=1010, be=0100000000000000 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=1010, be=0001000000000000 )
+
+
+ wait( level = SUBSUBPART )
+
+ write ( addr=f0000000, size=0000, be=1111111111111111 )
+ read ( addr=f0000000, size=0000, be=1111111111111111 )
+ write ( addr=f1000000, size=0001, be=1111111111111111 )
+ read ( addr=f1000000, size=0001, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f3000000, size=0001, be=1111111111111111 )
+ read ( addr=f3000000, size=0001, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0001, be=1111111111111111 )
+ read ( addr=f2000000, size=0001, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=1010, be=0011000000000000 )
+ write ( addr=f3000000, size=0001, be=1111111111111111 )
+ read ( addr=f3000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=1010, be=0001000000000000 )
+ read ( addr=f2000000, size=0001, be=1111111111111111 )
+ read ( addr=f2000000, size=1010, be=0011000000000000 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+
+
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/sim.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 80000 ns
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/Makefile
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/wave.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/wave.do (revision 2)
@@ -0,0 +1,53 @@
+
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+
+eval add wave -noupdate $binopt -label Clock -color SteelBlue /system_tb/sys_clk
+eval add wave -noupdate $binopt -label Reset -color SteelBlue /system_tb/sys_rst
+eval add wave -noupdate $hexopt -label synch_in -color Yellow /system_tb/dut/synch_in
+
+
+
+eval add wave -noupdate $binopt -label Mn_request -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_request
+
+eval add wave -noupdate $binopt -label Mn_RNW -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_rnw
+eval add wave -noupdate $binopt -label Mn_BE -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_be
+eval add wave -noupdate $binopt -label Mn_size -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_size
+eval add wave -noupdate $binopt -label Mn_type -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_type
+eval add wave -noupdate $hexopt -label Mn_ABus -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_abus
+eval add wave -noupdate $binopt -label PLB_PAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_pavalid
+eval add wave -noupdate $binopt -label PLB_SAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_savalid
+eval add wave -noupdate $binopt -label PLB_rdPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_rdprim
+eval add wave -noupdate $binopt -label PLB_wrPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_wrprim
+
+eval add wave -noupdate $hexopt -label Sl_rdDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddbus
+eval add wave -noupdate $binopt -label Sl_rdDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddack
+eval add wave -noupdate $binopt -label Sl_rdComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rdcomp
+
+eval add wave -noupdate $hexopt -label Sl_wrDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/plb_wrdbus
+eval add wave -noupdate $binopt -label Sl_wrDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrdack
+eval add wave -noupdate $binopt -label Sl_wrComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrcomp
+
+
+eval add wave -noupdate $binopt -label WB_CLK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_clk_i
+eval add wave -noupdate $binopt -label WB_RST_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rst_i
+eval add wave -noupdate $hexopt -label WB_ADR_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_adr_o
+eval add wave -noupdate $hexopt -label WB_DAT_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_o
+eval add wave -noupdate $hexopt -label WB_DAT_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_i
+eval add wave -noupdate $binopt -label WB_ACK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_ack_i
+eval add wave -noupdate $binopt -label WB_SEL_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_sel_o
+eval add wave -noupdate $binopt -label WB_STB_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_stb_o
+eval add wave -noupdate $binopt -label WB_LOCK_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_lock_o
+eval add wave -noupdate $binopt -label WB_WE_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_we_o
+
+
+
+eval add wave -noupdate $binopt -label bram0_ack_o -color Orange /system_tb/dut/onchip_ram_0/wb_ack_o
+eval add wave -noupdate $binopt -label bram1_ack_o -color Orange /system_tb/dut/onchip_ram_1/wb_ack_o
+eval add wave -noupdate $binopt -label bram2_ack_o -color Orange /system_tb/dut/onchip_ram_2/wb_ack_o
+eval add wave -noupdate $binopt -label bram3_ack_o -color Orange /system_tb/dut/onchip_ram_3/wb_ack_o
+
+
+configure wave -gridperiod 1
+configure wave -namecolwidth 200
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/sim.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 9000 ns
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/transfers.bfl (revision 2)
@@ -0,0 +1,140 @@
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+
+ mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
+ mem_update(addr=f0000010,data=01111100_02111100_03111100_04111100)
+ mem_update(addr=f0000020,data=01222200_02222200_03222200_04222200)
+ mem_update(addr=f0000030,data=01333300_02333300_03333300_04333300)
+
+ mem_update(addr=f1000000,data=01000011_02000011_03000011_04000011)
+ mem_update(addr=f1000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f1000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f1000030,data=01333311_02333311_03333311_04333311)
+
+-- mem_update(addr=f2000000,data=01000022_02000022_03000022_04000022)
+-- mem_update(addr=f2000010,data=01111122_02111122_03111122_04111122)
+-- mem_update(addr=f2000020,data=01222222_02222222_03222222_04222222)
+-- mem_update(addr=f2000030,data=01333322_02333322_03333322_04333322)
+--
+-- mem_update(addr=f3000000,data=01000033_02000033_03000033_04000033)
+-- mem_update(addr=f3000010,data=01111133_02111133_03111133_04111133)
+-- mem_update(addr=f3000020,data=01222233_02222233_03222233_04222233)
+-- mem_update(addr=f3000030,data=01333333_02333333_03333333_04333333)
+
+
+
+ wait( level=PART )
+
+ write ( addr=f0000000, size=1010, be=1111 )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ write ( addr=f1000000, size=1010, be=1000 )
+
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=1010, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=1010, be=1000 )
+
+
+
+ ---------------------------------
+ -- 64-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_64/plb_bfm_master_64/master,device_type=plb_master)
+ configure(msize=01)
+
+ mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
+ mem_update(addr=f0000010,data=01111100_02111100_03111100_04111100)
+ mem_update(addr=f0000020,data=01222200_02222200_03222200_04222200)
+ mem_update(addr=f0000030,data=01333300_02333300_03333300_04333300)
+
+ mem_update(addr=f1000000,data=01000011_02000011_03000011_04000011)
+ mem_update(addr=f1000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f1000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f1000030,data=01333311_02333311_03333311_04333311)
+
+
+
+ wait( level=PART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+
+ write ( addr=f0000000, size=1010, be=1101 )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ write ( addr=f1000000, size=1010, be=0100 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=1010, be=1101 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=1010, be=0100 )
+
+
+
+
+ ---------------------------------
+ -- 128-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_128/plb_bfm_master_128/master,device_type=plb_master)
+ configure(msize=10)
+
+ mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
+ mem_update(addr=f0000010,data=01111100_02111100_03111100_04111100)
+ mem_update(addr=f0000020,data=01222200_02222200_03222200_04222200)
+ mem_update(addr=f0000030,data=01333300_02333300_03333300_04333300)
+
+ mem_update(addr=f1000000,data=01000011_02000011_03000011_04000011)
+ mem_update(addr=f1000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f1000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f1000030,data=01333311_02333311_03333311_04333311)
+
+
+
+
+
+ wait( level=PART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+
+ write ( addr=f0000000, size=1010, be=0001 )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ write ( addr=f1000000, size=1010, be=1110 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=1010, be=0001 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=1010, be=1110 )
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/Makefile
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/wave.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/wave.do (revision 2)
@@ -0,0 +1,53 @@
+
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+
+eval add wave -noupdate $binopt -label Clock -color SteelBlue /system_tb/sys_clk
+eval add wave -noupdate $binopt -label Reset -color SteelBlue /system_tb/sys_rst
+eval add wave -noupdate $hexopt -label synch_in -color Yellow /system_tb/dut/synch_in
+
+
+
+eval add wave -noupdate $binopt -label Mn_request -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_request
+
+eval add wave -noupdate $binopt -label Mn_RNW -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_rnw
+eval add wave -noupdate $binopt -label Mn_BE -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_be
+eval add wave -noupdate $binopt -label Mn_size -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_size
+eval add wave -noupdate $binopt -label Mn_type -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_type
+eval add wave -noupdate $hexopt -label Mn_ABus -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_abus
+eval add wave -noupdate $binopt -label PLB_PAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_pavalid
+eval add wave -noupdate $binopt -label PLB_SAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_savalid
+eval add wave -noupdate $binopt -label PLB_rdPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_rdprim
+eval add wave -noupdate $binopt -label PLB_wrPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_wrprim
+
+eval add wave -noupdate $hexopt -label Sl_rdDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddbus
+eval add wave -noupdate $binopt -label Sl_rdDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddack
+eval add wave -noupdate $binopt -label Sl_rdComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rdcomp
+
+eval add wave -noupdate $hexopt -label Sl_wrDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/plb_wrdbus
+eval add wave -noupdate $binopt -label Sl_wrDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrdack
+eval add wave -noupdate $binopt -label Sl_wrComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrcomp
+
+
+eval add wave -noupdate $binopt -label WB_CLK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_clk_i
+eval add wave -noupdate $binopt -label WB_RST_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rst_i
+eval add wave -noupdate $hexopt -label WB_ADR_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_adr_o
+eval add wave -noupdate $hexopt -label WB_DAT_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_o
+eval add wave -noupdate $hexopt -label WB_DAT_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_i
+eval add wave -noupdate $binopt -label WB_ACK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_ack_i
+eval add wave -noupdate $binopt -label WB_SEL_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_sel_o
+eval add wave -noupdate $binopt -label WB_STB_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_stb_o
+eval add wave -noupdate $binopt -label WB_LOCK_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_lock_o
+eval add wave -noupdate $binopt -label WB_WE_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_we_o
+
+
+
+eval add wave -noupdate $binopt -label bram0_ack_o -color Orange /system_tb/dut/onchip_ram_0/wb_ack_o
+eval add wave -noupdate $binopt -label bram1_ack_o -color Orange /system_tb/dut/onchip_ram_1/wb_ack_o
+eval add wave -noupdate $binopt -label bram2_ack_o -color Orange /system_tb/dut/onchip_ram_2/wb_ack_o
+eval add wave -noupdate $binopt -label bram3_ack_o -color Orange /system_tb/dut/onchip_ram_3/wb_ack_o
+
+
+configure wave -gridperiod 1
+configure wave -namecolwidth 200
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/sim.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 10000 ns
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/transfers.bfl (revision 2)
@@ -0,0 +1,92 @@
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+ mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+
+ mem_update(addr=f1000000,data=01000000_02000000_03000000_04000000)
+
+
+ wait( level=PART )
+
+ write ( addr=f0000000, size=0010, be=1111111111111111 )
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ write ( addr=f1000000, size=0001, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0010, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0001, be=1111111111111111 )
+
+
+
+ ---------------------------------
+ -- 64-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_64/plb_bfm_master_64/master,device_type=plb_master)
+ configure(msize=01)
+ mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+
+ mem_update(addr=f1000000,data=01000000_02000000_03000000_04000000)
+
+
+ wait( level=PART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+ write ( addr=f0000000, size=0010, be=1111111111111111 )
+ wait ( level=SUBSUBPART )
+ write ( addr=f1000000, size=0001, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0010, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0001, be=1111111111111111 )
+
+
+ ---------------------------------
+ -- 128-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_128/plb_bfm_master_128/master,device_type=plb_master)
+ configure(msize=10)
+
+ mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+
+ mem_update(addr=f1000000,data=01000000_02000000_03000000_04000000)
+
+
+
+ wait( level=PART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+ write ( addr=f0000000, size=0010, be=1111111111111111 )
+ wait ( level=SUBSUBPART )
+ write ( addr=f1000000, size=0001, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0010, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0001, be=1111111111111111 )
+
+
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/Makefile
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/wave.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/wave.do (revision 2)
@@ -0,0 +1,54 @@
+
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+
+eval add wave -noupdate $binopt -label Clock -color SteelBlue /system_tb/sys_clk
+eval add wave -noupdate $binopt -label Reset -color SteelBlue /system_tb/sys_rst
+eval add wave -noupdate $hexopt -label synch_in -color Yellow /system_tb/dut/synch_in
+
+
+
+eval add wave -noupdate $binopt -label Mn_request -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_request
+
+eval add wave -noupdate $binopt -label Mn_RNW -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_rnw
+eval add wave -noupdate $binopt -label Mn_BE -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_be
+eval add wave -noupdate $binopt -label Mn_size -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_size
+eval add wave -noupdate $binopt -label Mn_type -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_type
+eval add wave -noupdate $hexopt -label Mn_ABus -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_abus
+eval add wave -noupdate $binopt -label PLB_PAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_pavalid
+eval add wave -noupdate $binopt -label PLB_SAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_savalid
+eval add wave -noupdate $binopt -label PLB_rdPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_rdprim
+eval add wave -noupdate $binopt -label PLB_wrPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_wrprim
+
+eval add wave -noupdate $hexopt -label Sl_rdDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddbus
+eval add wave -noupdate $binopt -label Sl_rdDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddack
+eval add wave -noupdate $binopt -label Sl_rdComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rdcomp
+
+
+eval add wave -noupdate $hexopt -label Sl_wrDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/plb_wrdbus
+eval add wave -noupdate $binopt -label Sl_wrDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrdack
+eval add wave -noupdate $binopt -label Sl_wrComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrcomp
+
+
+eval add wave -noupdate $binopt -label WB_CLK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_clk_i
+eval add wave -noupdate $binopt -label WB_RST_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rst_i
+eval add wave -noupdate $hexopt -label WB_ADR_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_adr_o
+eval add wave -noupdate $hexopt -label WB_DAT_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_o
+eval add wave -noupdate $hexopt -label WB_DAT_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_i
+eval add wave -noupdate $binopt -label WB_ACK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_ack_i
+eval add wave -noupdate $binopt -label WB_SEL_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_sel_o
+eval add wave -noupdate $binopt -label WB_STB_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_stb_o
+eval add wave -noupdate $binopt -label WB_LOCK_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_lock_o
+eval add wave -noupdate $binopt -label WB_WE_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_we_o
+
+
+
+eval add wave -noupdate $binopt -label bram0_ack_o -color Orange /system_tb/dut/onchip_ram_0/wb_ack_o
+eval add wave -noupdate $binopt -label bram1_ack_o -color Orange /system_tb/dut/onchip_ram_1/wb_ack_o
+eval add wave -noupdate $binopt -label bram2_ack_o -color Orange /system_tb/dut/onchip_ram_2/wb_ack_o
+eval add wave -noupdate $binopt -label bram3_ack_o -color Orange /system_tb/dut/onchip_ram_3/wb_ack_o
+
+
+configure wave -gridperiod 1
+configure wave -namecolwidth 200
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/transfers.bfl (revision 2)
@@ -0,0 +1,160 @@
+
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+
+
+ mem_update(addr=f0000000,data=11223344)
+ mem_update(addr=f1000000,data=ffeeffee)
+ mem_update(addr=f2000000,data=98765432)
+ mem_update(addr=f3000000,data=12341234)
+
+ wait( level=PART )
+
+ write ( addr=f0000000, size=0000, be=1111 )
+ write ( addr=f1000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f3000000, size=0000, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0000, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0000, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f2000000, size=0000, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f3000000, size=0000, be=1111 )
+
+
+ --
+ -- byte-enable test
+ --
+ mem_update(addr=f0000000,data=feefbaab_cddcbbaa_12212112_54437643)
+
+ write ( addr=f0000000, size=0000, be=1000 )
+ write ( addr=f0000001, size=0000, be=0100 )
+ write ( addr=f0000002, size=0000, be=0010 )
+ write ( addr=f0000003, size=0000, be=0001 )
+
+ read ( addr=f0000000, size=0000, be=1111 )
+
+ read ( addr=f0000000, size=0000, be=1000 )
+ read ( addr=f0000001, size=0000, be=0100 )
+ read ( addr=f0000002, size=0000, be=0010 )
+ read ( addr=f0000003, size=0000, be=0001 )
+
+
+
+
+ write ( addr=f0000004, size=0000, be=1100 )
+ write ( addr=f0000006, size=0000, be=0011 )
+
+ read ( addr=f0000004, size=0000, be=1111 )
+ read ( addr=f0000004, size=0000, be=1100 )
+ read ( addr=f0000006, size=0000, be=0011 )
+
+
+
+
+
+
+
+
+
+ ---------------------------------
+ -- 64-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_64/plb_bfm_master_64/master,device_type=plb_master)
+ configure(msize=01)
+
+
+ mem_update(addr=f0000000,data=11223344_55446677)
+ mem_update(addr=f1000000,data=ffeeffee_eeffeeff)
+ mem_update(addr=f2000000,data=98765432_10000000)
+ mem_update(addr=f3000000,data=12341234_43214321)
+
+ wait( level=PART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+ write ( addr=f0000000, size=0000, be=11111111 )
+ write ( addr=f1000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f3000000, size=0000, be=11111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0000, be=11111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0000, be=11111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f2000000, size=0000, be=11111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f3000000, size=0000, be=11111111 )
+
+
+
+
+
+
+
+
+ ---------------------------------
+ -- 128-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_128/plb_bfm_master_128/master,device_type=plb_master)
+ configure(msize=10)
+
+
+ mem_update(addr=f0000000,data=11223344_55446677_8899aabb_ccddeeff)
+ mem_update(addr=f1000000,data=ffeeffee_eeffeeff_efefefef_fefefefe)
+ mem_update(addr=f2000000,data=98765432_10000000_00110011_23456789)
+ mem_update(addr=f3000000,data=12341234_43214321_14251425_63524152)
+
+ wait( level=PART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+ write ( addr=f0000000, size=0000, be=1111111111111111 )
+ write ( addr=f1000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f3000000, size=0000, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0000, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0000, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f3000000, size=0000, be=1111111111111111 )
+
+
+
+
+
+
+
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/sim.do
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 15000 ns
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/Makefile
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/Makefile
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/simulation/Makefile (revision 2)
@@ -0,0 +1,113 @@
+SIM_DIR=$(shell pwd)
+
+XPS_PROJ_DIR=$(SIM_DIR)/..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+COMMON_DIR=$(SIM_DIR)/../../common
+LOG_DIR=$(SIM_DIR)/log
+PLB_BFM_SETUP_DIR=$(SIM_DIR)/../../plb_bfm_setup
+
+
+include $(COMMON_DIR)/Makefile
+
+
+
+all: sim
+
+
+TEST_CASES += test_cases/simple_read_write
+
+WORK_TARGET=$(SIM_BIN_DIR)/work/system/_primary.dat
+
+
+
+###
+#
+# note: WORK_TARGET is defined some lines above, the rest in ../../common/Makefile
+#
+COMPILE_COMPONENTS=$(TESTRAM_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET) $(PLB_BFM_TARGET) $(WORK_TARGET)
+
+
+
+#
+# Generate Simulation HDL Files
+# (This is the same than XPS-Gui->Simulation->Generate Simulation HDL Files)
+#
+$(SIM_DIR)/behavioral: $(XPS_PROJ_DIR)/system.mhs
+ @mkdir -p $(LOG_DIR)
+ simgen $(XPS_PROJ_DIR)/system.mhs -lang vhdl \
+ -p virtex5 \
+ -m beh \
+ -od $(XPS_PROJ_DIR)/ \
+ -s mti \
+ -lp $(LIB_DIR) \
+ -log $(LOG_DIR)/simgen
+ @mv simgen.opt log # there is no simgen-flag for this!
+
+
+
+
+
+# PLB_BFM_TARGET=$(SIM_BIN_DIR)/plbv46_bfm/system/_primary.dat
+# #BFM_SOURCE=$() TODO
+# $(PLB_BFM_TARGET):
+# cd $(SIM_BIN_DIR); \
+# vlib plbv46_bfm; \
+# vmap plbv46_bfm plbv46_bfm; \
+# vlib plbv46_master_bfm_v1_00_a; \
+# vmap plbv46_master_bfm_v1_00_a plbv46_master_bfm_v1_00_a; \
+# vlib plbv46_monitor_bfm_v1_00_a; \
+# vmap plbv46_monitor_bfm_v1_00_a plbv46_monitor_bfm_v1_00_a; \
+# vlib plbv46_slave_bfm_v1_00_a; \
+# vmap plbv46_slave_bfm_v1_00_a plbv46_slave_bfm_v1_00_a; \
+# vcom $(VHDL_CFLAGS) -work plbv46_bfm \
+# "$(PLB_BFM_SETUP_DIR)/plb_dcl_128.vhd"; \
+# vcom $(VHDL_CFLAGS) -work plbv46_master_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_master_bfm_v1_00_a/hdl/vhdl/plbv46_master_bfm.vhd" ; \
+# vcom $(VHDL_CFLAGS) -work plbv46_monitor_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_monitor_bfm_v1_00_a/hdl/vhdl/plbv46_monitor_bfm.vhd";\
+# vcom $(VHDL_CFLAGS) -work plbv46_slave_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_slave_bfm_v1_00_a/hdl/vhdl/plbv46_slave_bfm.vhd";
+
+
+
+
+
+$(WORK_TARGET): $(SIM_DIR)/behavioral $(SIM_BIN_DIR)/../testbench/system_tb.vhd
+ cd $(SIM_BIN_DIR); \
+ vlib work; \
+ vmap work work; \
+ vlog -novopt -93 -work work "../behavioral/wb_conbus_0_wrapper.v"; \
+ vcom $(VHDL_CFLAGS) -work work \
+ "../behavioral/onchip_ram_0_wrapper.vhd" \
+ "../behavioral/onchip_ram_1_wrapper.vhd" \
+ "../behavioral/onchip_ram_2_wrapper.vhd" \
+ "../behavioral/onchip_ram_3_wrapper.vhd" \
+ "../behavioral/mb_plb_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_32_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_64_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_128_wrapper.vhd" \
+ "../behavioral/plb_bfm_monitor_wrapper.vhd" \
+ "../behavioral/plb_bfm_slave_wrapper.vhd" \
+ "../behavioral/plb_bfm_synch_wrapper.vhd" \
+ "../behavioral/plb2wb_bridge_0_wrapper.vhd" \
+ "../behavioral/system.vhd" \
+ "../testbench/system_tb.vhd"
+
+
+
+
+
+
+compile: $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS)
+
+
+
+
+
+
+clean:
+ rm -rf \
+ $(SIM_DIR)/behavioral \
+ $(SIM_BIN_DIR) \
+ $(LOG_DIR)
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/system.mss
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/system.mss (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/system.mss (revision 2)
@@ -0,0 +1,43 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = plb_bfm_slave
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = plb2wb_bridge_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_3
+END
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/system.xmp
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/system.xmp (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/system.xmp (revision 2)
@@ -0,0 +1,25 @@
+#Please do not modify this file by hand
+XmpVersion: 11.4
+VerMgmt: 11.4
+IntStyle: default
+ModuleSearchPath: ../../EDK_Libs/
+MHS File: system.mhs
+MSS File: system.mss
+Architecture: virtex5
+Device: xc5vlx50
+Package: ff676
+SpeedGrade: -1
+UserCmd1:
+UserCmd1Type: 0
+UserCmd2:
+UserCmd2Type: 0
+GenSimTB: 0
+SdkExportBmmBit: 1
+SdkExportDir: SDK/SDK_Export
+InsertNoPads: 0
+WarnForEAArch: 1
+HdlLang: VHDL
+SimModel: BEHAVIORAL
+UcfFile: data/system.ucf
+EnableParTimingError: 1
+ShowLicenseDialog: 1
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/data/system.ucf
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/data/system.ucf (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/data/system.ucf (revision 2)
@@ -0,0 +1,6 @@
+# Virtex 5 ML501 Evaluation Platform
+Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
+TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
+Net fpga_0_clk_1_sys_clk_pin LOC = AD8 | IOSTANDARD=LVCMOS33;
+Net fpga_0_rst_1_sys_rst_pin TIG;
+Net fpga_0_rst_1_sys_rst_pin LOC = T23 | IOSTANDARD=LVCMOS33 | PULLUP;
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/system.mhs
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/system.mhs (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/system.mhs (revision 2)
@@ -0,0 +1,174 @@
+
+# ##############################################################################
+# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
+# Fri Mar 5 18:02:26 2010
+# Target Board: Xilinx Virtex 5 ML501 Evaluation Platform Rev 1
+# Family: virtex5
+# Device: xc5vlx50
+# Package: ff676
+# Speed Grade: -1
+# Processor number: 1
+# Processor 1: microblaze_0
+# System clock frequency: 125.0
+# Debug Interface: On-Chip HW Debug Module
+# ##############################################################################
+ PARAMETER VERSION = 2.1.0
+
+
+ PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
+ PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
+ PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]
+ PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]
+ PORT wb_clk_pin = wb_clk, DIR = I, SIGIS = CLK
+ PORT wb_rst_pin = wb_rst, DIR = I, SIGIS = RST
+
+
+BEGIN plb_v46
+ PARAMETER INSTANCE = mb_plb
+ PARAMETER HW_VER = 1.04.a
+ PARAMETER C_EXT_RESET_HIGH = 1
+ PARAMETER C_DCR_INTFCE = 1
+ PARAMETER C_BASEADDR = 0b0000000000
+ PARAMETER C_HIGHADDR = 0b1111111111
+ PORT PLB_Clk = clk_100MHz
+ PORT SYS_Rst = sys_rst_s
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_32
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_SIZE = 0b10
+ PARAMETER PLB_MASTER_NUM = 0b0000
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_0
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_64
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ PARAMETER PLB_MASTER_SIZE = 0b10
+ PARAMETER PLB_MASTER_NUM = 0b0001
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_1
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_128
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ PARAMETER PLB_MASTER_NUM = 0b0010
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_2
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_monitor_bfm
+ PARAMETER INSTANCE = plb_bfm_monitor
+ PARAMETER HW_VER = 1.00.a
+ BUS_INTERFACE MON_PLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_3
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_slave_bfm
+ PARAMETER INSTANCE = plb_bfm_slave
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_SLAVE_ADDR_LO_0 = 0xF8000000
+ PARAMETER PLB_SLAVE_ADDR_HI_0 = 0xFFFFfFFF
+ PARAMETER C_SPLB_NATIVE_DWIDTH = 32
+ PARAMETER PLB_SLAVE_SIZE = 0b00
+ BUS_INTERFACE SPLB = mb_plb
+ PORT SYNCH_IN = synch_in
+ PORT SYNCH_OUT = bfm_synch_out_4
+END
+
+BEGIN bfm_synch
+ PARAMETER INSTANCE = plb_bfm_synch
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_NUM_SYNCH = 5
+ PORT TO_SYNCH_IN = synch_out
+ PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_1 & bfm_synch_out_2 & bfm_synch_out_3 & bfm_synch_out_4
+END
+
+BEGIN plb2wb_bridge
+ PARAMETER INSTANCE = plb2wb_bridge_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_BASEADDR = 0xf0000000
+ PARAMETER C_HIGHADDR = 0xf7ffffff
+ PARAMETER WB_ADR_OFFSET = 0xf0000000
+ PARAMETER WB_ADR_OFFSET_NEG = 1
+ PARAMETER SYNCHRONY = false
+ PARAMETER WB_PIC_INTS = 1
+ BUS_INTERFACE SPLB = mb_plb
+ BUS_INTERFACE MWB = wb_conbus_0
+ PORT SPLB_Clk = clk_100MHz
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+ PORT wb_pic_int_i = net_gnd
+END
+
+BEGIN wb_conbus
+ PARAMETER INSTANCE = wb_conbus_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER wb_s0_addr = 0x00
+ PARAMETER wb_s27_addr_w = 8
+ PARAMETER wb_s1_addr = 0x01
+ PARAMETER wb_s2_addr = 0x02
+ PARAMETER wb_s3_addr = 0x03
+ PARAMETER wb_s4_addr = 0x04
+ PARAMETER wb_s5_addr = 0x05
+ PARAMETER wb_s6_addr = 0x06
+ PARAMETER wb_s7_addr = 0x07
+ PARAMETER wb_s0_addr_w = 8
+ PARAMETER wb_s1_addr_w = 8
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 0
+ PARAMETER WR_DELAY = 0
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_1
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 1
+ PARAMETER WR_DELAY = 1
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_2
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 3
+ PARAMETER WR_DELAY = 3
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_3
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 5
+ PARAMETER WR_DELAY = 5
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/etc/bitgen.ut
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/etc/bitgen.ut (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/etc/bitgen.ut (revision 2)
@@ -0,0 +1,14 @@
+-g TdoPin:PULLNONE
+-g DriveDone:No
+-g StartUpClk:JTAGCLK
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g TckPin:PULLUP
+-g TdiPin:PULLUP
+-g TmsPin:PULLUP
+-g DonePipe:No
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:NONE
+-g Persist:No
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/etc/fast_runtime.opt
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/etc/fast_runtime.opt (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/etc/fast_runtime.opt (revision 2)
@@ -0,0 +1,84 @@
+FLOWTYPE = FPGA;
+###############################################################
+## Filename: fast_runtime.opt
+##
+## Option File For Xilinx FPGA Implementation Flow for Fast
+## Runtime.
+##
+## Version: 4.1.1
+###############################################################
+#
+# Options for Translator
+#
+# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
+#
+Program ngdbuild
+-p ; # Partname to use - picked from xflow commandline
+-nt timestamp; # NGO File generation. Regenerate only when
+ # source netlist is newer than existing
+ # NGO file (default)
+-bm .bmm # Block RAM memory map file
+; # User design - pick from xflow command line
+-uc .ucf; # ucf constraints
+.ngd; # Name of NGD file. Filebase same as design filebase
+End Program ngdbuild
+
+#
+# Options for Mapper
+#
+# Type "map -h " for a detailed list of map command line options
+#
+Program map
+-o _map.ncd; # Output Mapped ncd file
+-w; # Overwrite output files.
+-pr b; # Pack internal FF/latches into IOBs
+#-fp .mfp; # Floorplan file
+-ol high;
+-timing;
+-detail;
+.ngd; # Input NGD file
+.pcf; # Physical constraints file
+END Program map
+
+#
+# Options for Post Map Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_map_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o _map.twr; # Output trace report file
+-xml _map.twx; # Output XML version of the timing report
+#-tsi _map.tsi; # Produce Timing Specification Interaction report
+_map.ncd; # Input mapped ncd
+.pcf; # Physical constraints file
+END Program post_map_trce
+
+#
+# Options for Place and Route
+#
+# Type "par -h" for a detailed list of par command line options
+#
+Program par
+-w; # Overwrite existing placed and routed ncd
+-ol high; # Overall effort level
+_map.ncd; # Input mapped NCD file
+.ncd; # Output placed and routed NCD
+.pcf; # Input physical constraints file
+END Program par
+
+#
+# Options for Post Par Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_par_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o .twr; # Output trace report file
+-xml .twx; # Output XML version of the timing report
+#-tsi .tsi; # Produce Timing Specification Interaction report
+.ncd; # Input placed and routed ncd
+.pcf; # Physical constraints file
+END Program post_par_trce
+
+
Index: trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/etc/download.cmd
===================================================================
--- trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/etc/download.cmd (nonexistent)
+++ trunk/systems/test_system_sim/32bit_on_128bitPLB_asyn/etc/download.cmd (revision 2)
@@ -0,0 +1,6 @@
+setMode -bscan
+setCable -p auto
+identify
+assignfile -p 4 -file implementation/download.bit
+program -p 4
+quit
Index: trunk/systems/test_system_sim/wb_retries/system.make
===================================================================
--- trunk/systems/test_system_sim/wb_retries/system.make (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/system.make (revision 2)
@@ -0,0 +1,248 @@
+#################################################################
+# Makefile generated by Xilinx Platform Studio
+# Project:/home/christian/share/semesterproject/trunk/systems/test_system_sim/wb_retries/system.xmp
+#
+# WARNING : This file will be re-generated every time a command
+# to run a make target is invoked. So, any changes made to this
+# file manually, will be lost when make is invoked next.
+#################################################################
+
+# Name of the Microprocessor system
+# The hardware specification of the system is in file :
+# /home/christian/share/semesterproject/trunk/systems/test_system_sim/wb_retries/system.mhs
+# The software specification of the system is in file :
+# /home/christian/share/semesterproject/trunk/systems/test_system_sim/wb_retries/system.mss
+
+include system_incl.make
+
+#################################################################
+# PHONY TARGETS
+#################################################################
+.PHONY: dummy
+.PHONY: netlistclean
+.PHONY: bitsclean
+.PHONY: simclean
+.PHONY: exporttosdk
+
+#################################################################
+# EXTERNAL TARGETS
+#################################################################
+all:
+ @echo "Makefile to build a Microprocessor system :"
+ @echo "Run make with any of the following targets"
+ @echo " "
+ @echo " netlist : Generates the netlist for the given MHS "
+ @echo " bits : Runs Implementation tools to generate the bitstream"
+ @echo " exporttosdk: Export files to SDK"
+ @echo " "
+ @echo " libs : Configures the sw libraries for this system"
+ @echo " program : Compiles the program sources for all the processor instances"
+ @echo " "
+ @echo " init_bram: Initializes bitstream with BRAM data"
+ @echo " ace : Generate ace file from bitstream and elf"
+ @echo " download : Downloads the bitstream onto the board"
+ @echo " "
+ @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"
+ @echo " simmodel : Generates HDL simulation models for chosen simulation mode"
+ @echo " behavioral_model : Generates behavioral HDL models with BRAM initialization"
+ @echo " structural_model : Generates structural simulation HDL models with BRAM initialization"
+ @echo " timing : Generates timing simulation HDL models with BRAM initialization"
+ @echo " "
+ @echo " netlistclean: Deletes netlist"
+ @echo " bitsclean: Deletes bit, ncd, bmm files"
+ @echo " hwclean : Deletes implementation dir"
+ @echo " libsclean: Deletes sw libraries"
+ @echo " programclean: Deletes compiled ELF files"
+ @echo " swclean : Deletes sw libraries and ELF files"
+ @echo " simclean : Deletes simulation dir"
+ @echo " clean : Deletes all generated files/directories"
+ @echo " "
+ @echo " make : (Default)"
+ @echo " Creates a Microprocessor system using default initializations"
+ @echo " specified for each processor in MSS file"
+
+
+bits: $(SYSTEM_BIT)
+
+ace: $(SYSTEM_ACE)
+
+exporttosdk: $(SYSTEM_HW_HANDOFF_DEP)
+
+netlist: $(POSTSYN_NETLIST)
+
+libs: $(LIBRARIES)
+
+program: $(ALL_USER_ELF_FILES)
+ @echo "No user software applications specified"
+
+download: $(DOWNLOAD_BIT) dummy
+ @echo "*********************************************"
+ @echo "Downloading Bitstream onto the target board"
+ @echo "*********************************************"
+ impact -batch etc/download.cmd
+
+init_bram: $(DOWNLOAD_BIT)
+
+sim: $(DEFAULT_SIM_SCRIPT)
+ cd simulation/behavioral; \
+ $(SIM_CMD) &
+
+simmodel: $(DEFAULT_SIM_SCRIPT)
+
+behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)
+
+structural_model: $(STRUCTURAL_SIM_SCRIPT)
+
+clean: hwclean swclean simclean
+ rm -f _impact.cmd
+
+hwclean: netlistclean bitsclean
+ rm -rf implementation synthesis xst hdl
+ rm -rf xst.srp $(SYSTEM).srp
+ rm -f __xps/ise/_xmsgs/bitinit.xmsgs
+
+netlistclean:
+ rm -f $(POSTSYN_NETLIST)
+ rm -f platgen.log
+ rm -f __xps/ise/_xmsgs/platgen.xmsgs
+ rm -f $(BMM_FILE)
+
+bitsclean:
+ rm -f $(SYSTEM_BIT)
+ rm -f implementation/$(SYSTEM).ncd
+ rm -f implementation/$(SYSTEM)_bd.bmm
+ rm -f implementation/$(SYSTEM)_map.ncd
+ rm -f __xps/$(SYSTEM)_routed
+
+simclean:
+ rm -rf simulation/behavioral
+ rm -f simgen.log
+ rm -f __xps/ise/_xmsgs/simgen.xmsgs
+
+swclean: libsclean programclean
+
+libsclean: $(LIBSCLEAN_TARGETS)
+ rm -f libgen.log
+ rm -f __xps/ise/_xmsgs/libgen.xmsgs
+
+programclean: $(PROGRAMCLEAN_TARGETS)
+
+#################################################################
+# SOFTWARE PLATFORM FLOW
+#################################################################
+
+
+$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt
+ @echo "*********************************************"
+ @echo "Creating software libraries..."
+ @echo "*********************************************"
+ libgen $(LIBGEN_OPTIONS) $(MSSFILE)
+
+
+#################################################################
+# BOOTLOOP ELF FILES
+#################################################################
+
+
+
+#################################################################
+# HARDWARE IMPLEMENTATION FLOW
+#################################################################
+
+
+$(BMM_FILE) \
+$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
+ $(CORE_STATE_DEVELOPMENT_FILES)
+ @echo "****************************************************"
+ @echo "Creating system netlist for hardware specification.."
+ @echo "****************************************************"
+ platgen $(PLATGEN_OPTIONS) $(MHSFILE)
+
+$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)
+ @echo "Running synthesis..."
+ bash -c "cd synthesis; ./synthesis.sh"
+
+__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY)
+ @echo "*********************************************"
+ @echo "Running Xilinx Implementation tools.."
+ @echo "*********************************************"
+ @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf
+ @cp -f etc/fast_runtime.opt implementation/xflow.opt
+ xflow -wd implementation -p $(DEVICE) -implement xflow.opt -ise ../__xps/ise/$(SYSTEM).ise $(SYSTEM).ngc
+ touch __xps/$(SYSTEM)_routed
+
+$(SYSTEM_BIT): __xps/$(SYSTEM)_routed $(BITGEN_UT_FILE)
+ xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par
+ @echo "*********************************************"
+ @echo "Running Bitgen.."
+ @echo "*********************************************"
+ @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut
+ cd implementation; bitgen -w -f bitgen.ut $(SYSTEM); cd ..
+
+$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt
+ # @cp -f implementation/$(SYSTEM)_bd.bmm .
+ @echo "*********************************************"
+ @echo "Initializing BRAM contents of the bitstream"
+ @echo "*********************************************"
+ bitinit -p $(DEVICE) $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \
+ -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)
+ @rm -f $(SYSTEM)_bd.bmm
+
+$(SYSTEM_ACE):
+ @echo "In order to generate ace file, you must have:-"
+ @echo "- exactly one processor."
+ @echo "- opb_mdm, if using microblaze."
+
+#################################################################
+# EXPORT_TO_SDK FLOW
+#################################################################
+
+
+$(SYSTEM_HW_HANDOFF): $(MHSFILE) __xps/platgen.opt
+ mkdir -p $(SDK_EXPORT_DIR)
+ psf2Edward -inp $(SYSTEM).xmp -xml $(SDK_EXPORT_DIR)/$(SYSTEM).xml $(GLOBAL_SEARCHPATHOPT)
+ xdsgen -inp $(SYSTEM).xmp -report $(SDK_EXPORT_DIR)/$(SYSTEM).html $(GLOBAL_SEARCHPATHOPT) -make_docs_local
+
+$(SYSTEM_HW_HANDOFF_BIT): $(SYSTEM_BIT)
+ @rm -rf $(SYSTEM_HW_HANDOFF_BIT)
+ @cp -f $(SYSTEM_BIT) $(SDK_EXPORT_DIR)/
+
+
+#################################################################
+# SIMULATION FLOW
+#################################################################
+
+
+################## BEHAVIORAL SIMULATION ##################
+
+$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
+ $(BRAMINIT_ELF_FILES)
+ @echo "*********************************************"
+ @echo "Creating behavioral simulation models..."
+ @echo "*********************************************"
+ simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)
+
+################## STRUCTURAL SIMULATION ##################
+
+$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \
+ $(BRAMINIT_ELF_FILES)
+ @echo "*********************************************"
+ @echo "Creating structural simulation models..."
+ @echo "*********************************************"
+ simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)
+
+
+################## TIMING SIMULATION ##################
+
+implementation/$(SYSTEM).ncd: __xps/$(SYSTEM)_routed
+
+$(TIMING_SIM_SCRIPT): implementation/$(SYSTEM).ncd __xps/simgen.opt \
+ $(BRAMINIT_ELF_FILES)
+ @echo "*********************************************"
+ @echo "Creating timing simulation models..."
+ @echo "*********************************************"
+ simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)
+
+dummy:
+ @echo ""
+
Index: trunk/systems/test_system_sim/wb_retries/simulation/testbench/system_tb.vhd
===================================================================
--- trunk/systems/test_system_sim/wb_retries/simulation/testbench/system_tb.vhd (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/simulation/testbench/system_tb.vhd (revision 2)
@@ -0,0 +1,146 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+entity system_tb is
+end system_tb;
+
+architecture STRUCTURE of system_tb is
+
+ constant sys_clk_period : time := 10.000000 ns;
+ constant wb_clk_period : time := 13.333333 ns;
+ constant sys_rst_length : time := 160 ns;
+
+ constant SYNCH_PART : integer := 1;
+ constant SYNCH_SUBPART : integer := 2;
+ constant SYNCH_SUBSUBPART : integer := 3;
+
+ constant SUBSUBPART_LENGTH : integer := 15; -- 10 clock cycles
+ constant SUBPART_LENGTH : integer := 5; -- 7 times SUBSUBPART_LENGTH
+ constant PART_LENGTH : integer := 5; -- 6 times SUBPART_LENGTH
+
+ component system is
+ port (
+ sys_clk_pin : in std_logic;
+ sys_rst_pin : in std_logic;
+ to_synch_in_pin : in std_logic_vector( 0 to 31 );
+ from_synch_out_pin : out std_logic_vector( 0 to 31 );
+ wb_clk_pin : in std_logic;
+ wb_rst_pin : in std_logic
+ );
+ end component;
+
+
+ signal sys_clk : std_logic;
+ signal sys_rst : std_logic := '1';
+ signal wb_clk : std_logic;
+ signal wb_rst : std_logic;
+
+
+ signal to_synch_in : std_logic_vector( 0 to 31 );
+ signal from_synch_out : std_logic_vector( 0 to 31 );
+ signal tb_synch_out : std_logic_vector( 0 to 31 ) := ( others => '0' );
+
+ procedure SendSynch( signal synch_out : OUT std_logic_vector;
+ COMMAND : integer ) is
+ begin
+ synch_out( COMMAND ) <= '1';
+ wait for sys_clk_period*1;
+ synch_out( COMMAND ) <= '0';
+ end procedure SendSynch;
+
+
+begin
+
+ to_synch_in <= from_synch_out or tb_synch_out;
+
+
+
+ dut : system
+ port map (
+ sys_clk_pin => sys_clk,
+ sys_rst_pin => sys_rst,
+ to_synch_in_pin => to_synch_in,
+ from_synch_out_pin => from_synch_out,
+ wb_clk_pin => wb_clk,
+ wb_rst_pin => wb_rst
+ );
+
+
+ --
+ -- generate plb-clk
+ --
+ process
+ begin
+ sys_clk <= '0';
+ loop
+ wait for (sys_clk_period/2);
+ sys_clk <= not sys_clk;
+ end loop;
+ end process;
+
+
+ --
+ --
+ --
+ process
+ begin
+ wb_clk <= '0';
+ loop
+ wait for (wb_clk_period/2);
+ wb_clk <= not wb_clk;
+ end loop;
+ end process;
+
+
+
+
+ process
+ begin
+ sys_rst <= '1';
+ wb_rst <= '1';
+ wait for ( sys_rst_length );
+ wb_rst <= not wb_rst;
+ sys_rst <= not sys_rst;
+ wait;
+ end process;
+
+
+ process
+ begin
+
+ wait until sys_rst = '0';
+ -- wait until masters a ready
+ wait for sys_clk_period * 10;
+
+
+ while true loop
+ for i in 0 to PART_LENGTH-1 loop
+ SendSynch( tb_synch_out, SYNCH_PART );
+
+ for j in 0 to SUBPART_LENGTH-1 loop
+ SendSynch( tb_synch_out, SYNCH_SUBPART );
+
+ for k in 0 to SUBSUBPART_LENGTH loop
+ SendSynch( tb_synch_out, SYNCH_SUBSUBPART );
+ wait for (SUBSUBPART_LENGTH * sys_clk_period );
+ end loop;
+
+
+ end loop;
+
+
+ end loop;
+
+ end loop;
+
+ end process;
+
+
+
+
+end architecture STRUCTURE;
+
Index: trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/wave.do
===================================================================
--- trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/wave.do (revision 2)
@@ -0,0 +1,56 @@
+
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+
+eval add wave -noupdate $binopt -label Clock -color SteelBlue /system_tb/sys_clk
+eval add wave -noupdate $binopt -label Reset -color SteelBlue /system_tb/sys_rst
+eval add wave -noupdate $hexopt -label synch_in -color Yellow /system_tb/dut/synch_in
+
+
+
+eval add wave -noupdate $binopt -label Mn_request -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_request
+
+eval add wave -noupdate $binopt -label Mn_RNW -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_rnw
+eval add wave -noupdate $binopt -label Mn_BE -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_be
+eval add wave -noupdate $binopt -label Mn_size -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_size
+eval add wave -noupdate $binopt -label Mn_type -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_type
+eval add wave -noupdate $hexopt -label Mn_ABus -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_abus
+eval add wave -noupdate $binopt -label PLB_PAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_pavalid
+eval add wave -noupdate $binopt -label PLB_SAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_savalid
+eval add wave -noupdate $binopt -label PLB_rdPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_rdprim
+eval add wave -noupdate $binopt -label PLB_wrPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_wrprim
+
+eval add wave -noupdate $hexopt -label Sl_rdDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddbus
+eval add wave -noupdate $binopt -label Sl_rdDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddack
+eval add wave -noupdate $binopt -label Sl_rdComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rdcomp
+
+
+eval add wave -noupdate $hexopt -label Sl_wrDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/plb_wrdbus
+eval add wave -noupdate $binopt -label Sl_wrDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrdack
+eval add wave -noupdate $binopt -label Sl_wrComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrcomp
+
+
+
+eval add wave -noupdate $binopt -label WB_CLK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_clk_i
+eval add wave -noupdate $binopt -label WB_RST_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rst_i
+eval add wave -noupdate $hexopt -label WB_ADR_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_adr_o
+eval add wave -noupdate $hexopt -label WB_DAT_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_o
+eval add wave -noupdate $hexopt -label WB_DAT_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_i
+eval add wave -noupdate $binopt -label WB_ACK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_ack_i
+eval add wave -noupdate $binopt -label WB_RTY_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rty_i
+eval add wave -noupdate $binopt -label WB_ERR_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_err_i
+eval add wave -noupdate $binopt -label WB_SEL_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_sel_o
+eval add wave -noupdate $binopt -label WB_STB_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_stb_o
+eval add wave -noupdate $binopt -label WB_LOCK_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_lock_o
+eval add wave -noupdate $binopt -label WB_WE_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_we_o
+
+
+
+eval add wave -noupdate $binopt -label bram0_ack_o -color Orange /system_tb/dut/onchip_ram_0/wb_ack_o
+eval add wave -noupdate $binopt -label bram1_ack_o -color Orange /system_tb/dut/onchip_ram_1/wb_ack_o
+eval add wave -noupdate $binopt -label bram2_ack_o -color Orange /system_tb/dut/onchip_ram_2/wb_ack_o
+
+
+configure wave -gridperiod 1
+configure wave -namecolwidth 200
Index: trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/transfers.bfl (revision 2)
@@ -0,0 +1,52 @@
+
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+
+
+ mem_update(addr=f0000000,data=11000001_11000002_11000003_11000004)
+ mem_update(addr=f0000010,data=11111111_11111112_11111113_11111114)
+ mem_update(addr=f0000020,data=11222221_11222222_11222223_11222224)
+ mem_update(addr=f0000030,data=11333331_11333332_11333333_11333334)
+
+ mem_update(addr=f1000000,data=22000001_22000002_22000003_22000004)
+ mem_update(addr=f1000010,data=22111111_22111112_22111113_22111114)
+ mem_update(addr=f1000020,data=22222221_22222222_22222223_22222224)
+ mem_update(addr=f1000030,data=22333331_22333332_22333333_22333334)
+
+ mem_update(addr=f2000000,data=33000001_33000002_33000003_33000004)
+ mem_update(addr=f2000010,data=33111111_33111112_33111113_33111114)
+ mem_update(addr=f2000020,data=33222221_33222222_33222223_33222224)
+ mem_update(addr=f2000030,data=33333331_33333332_33333333_33333334)
+
+
+
+ wait( level=SUBPART )
+
+ write ( addr=f0000000, size=0001, be=1111 )
+ write ( addr=f1000000, size=0001, be=1111 )
+ write ( addr=f2000000, size=0001, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f0000000, size=0001, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f1000000, size=0001, be=1111 )
+
+ wait ( level=SUBSUBPART )
+ read ( addr=f2000000, size=0001, be=1111 )
+
+
+
+
+
+
Index: trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/sim.do
===================================================================
--- trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 10000 ns
+
+
Index: trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/Makefile
===================================================================
--- trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/simulation/test_cases/simple_retries/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/wb_retries/simulation/Makefile
===================================================================
--- trunk/systems/test_system_sim/wb_retries/simulation/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/simulation/Makefile (revision 2)
@@ -0,0 +1,110 @@
+SIM_DIR=$(shell pwd)
+
+XPS_PROJ_DIR=$(SIM_DIR)/..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+COMMON_DIR=$(SIM_DIR)/../../common
+LOG_DIR=$(SIM_DIR)/log
+PLB_BFM_SETUP_DIR=$(SIM_DIR)/../../plb_bfm_setup
+
+
+include $(COMMON_DIR)/Makefile
+
+
+
+all: sim
+
+
+TEST_CASES += test_cases/simple_retries
+
+WORK_TARGET=$(SIM_BIN_DIR)/work/system/_primary.dat
+
+
+
+###
+#
+# note: WORK_TARGET is defined some lines above, the rest in ../../common/Makefile
+#
+COMPILE_COMPONENTS=$(TESTRAM_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET) $(PLB_BFM_TARGET) $(WORK_TARGET)
+
+
+
+#
+# Generate Simulation HDL Files
+# (This is the same than XPS-Gui->Simulation->Generate Simulation HDL Files)
+#
+$(SIM_DIR)/behavioral: $(XPS_PROJ_DIR)/system.mhs
+ @mkdir -p $(LOG_DIR)
+ simgen $(XPS_PROJ_DIR)/system.mhs -lang vhdl \
+ -p virtex5 \
+ -m beh \
+ -od $(XPS_PROJ_DIR)/ \
+ -s mti \
+ -lp $(LIB_DIR) \
+ -log $(LOG_DIR)/simgen
+ @mv simgen.opt log # there is no simgen-flag for this!
+
+
+
+
+
+# PLB_BFM_TARGET=$(SIM_BIN_DIR)/plbv46_bfm/system/_primary.dat
+# #BFM_SOURCE=$() TODO
+# $(PLB_BFM_TARGET):
+# cd $(SIM_BIN_DIR); \
+# vlib plbv46_bfm; \
+# vmap plbv46_bfm plbv46_bfm; \
+# vlib plbv46_master_bfm_v1_00_a; \
+# vmap plbv46_master_bfm_v1_00_a plbv46_master_bfm_v1_00_a; \
+# vlib plbv46_monitor_bfm_v1_00_a; \
+# vmap plbv46_monitor_bfm_v1_00_a plbv46_monitor_bfm_v1_00_a; \
+# vlib plbv46_slave_bfm_v1_00_a; \
+# vmap plbv46_slave_bfm_v1_00_a plbv46_slave_bfm_v1_00_a; \
+# vcom $(VHDL_CFLAGS) -work plbv46_bfm \
+# "$(PLB_BFM_SETUP_DIR)/plb_dcl_128.vhd"; \
+# vcom $(VHDL_CFLAGS) -work plbv46_master_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_master_bfm_v1_00_a/hdl/vhdl/plbv46_master_bfm.vhd" ; \
+# vcom $(VHDL_CFLAGS) -work plbv46_monitor_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_monitor_bfm_v1_00_a/hdl/vhdl/plbv46_monitor_bfm.vhd";\
+# vcom $(VHDL_CFLAGS) -work plbv46_slave_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_slave_bfm_v1_00_a/hdl/vhdl/plbv46_slave_bfm.vhd";
+
+
+
+
+
+$(WORK_TARGET): $(SIM_DIR)/behavioral $(SIM_BIN_DIR)/../testbench/system_tb.vhd
+ cd $(SIM_BIN_DIR); \
+ vlib work; \
+ vmap work work; \
+ vlog -novopt -93 -work work "../behavioral/wb_conbus_0_wrapper.v"; \
+ vcom $(VHDL_CFLAGS) -work work \
+ "../behavioral/onchip_ram_0_wrapper.vhd" \
+ "../behavioral/onchip_ram_1_wrapper.vhd" \
+ "../behavioral/onchip_ram_2_wrapper.vhd" \
+ "../behavioral/mb_plb_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_32_wrapper.vhd" \
+ "../behavioral/plb_bfm_monitor_wrapper.vhd" \
+ "../behavioral/plb_bfm_synch_wrapper.vhd" \
+ "../behavioral/plb2wb_bridge_0_wrapper.vhd" \
+ "../behavioral/system.vhd" \
+ "../testbench/system_tb.vhd"
+
+
+
+
+
+
+compile: $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS)
+
+
+
+
+
+
+clean:
+ @echo "cleaning sim bin dir in retries\n"
+ rm -rf \
+ $(SIM_DIR)/behavioral \
+ $(SIM_BIN_DIR) \
+ $(LOG_DIR)
+
Index: trunk/systems/test_system_sim/wb_retries/system_incl.make
===================================================================
--- trunk/systems/test_system_sim/wb_retries/system_incl.make (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/system_incl.make (revision 2)
@@ -0,0 +1,101 @@
+#################################################################
+# Makefile generated by Xilinx Platform Studio
+# Project:/home/christian/share/semesterproject/trunk/systems/test_system_sim/wb_retries/system.xmp
+#
+# WARNING : This file will be re-generated every time a command
+# to run a make target is invoked. So, any changes made to this
+# file manually, will be lost when make is invoked next.
+#################################################################
+
+XILINX_EDK_DIR = /opt/Xilinx/11.1/EDK
+NON_CYG_XILINX_EDK_DIR = /opt/Xilinx/11.1/EDK
+
+SYSTEM = system
+
+MHSFILE = system.mhs
+
+MSSFILE = system.mss
+
+FPGA_ARCH = virtex5
+
+DEVICE = xc5vlx50ff676-1
+
+LANGUAGE = vhdl
+
+SEARCHPATHOPT = -lp /home/christian/share/semesterproject/trunk/systems/EDK_Libs/
+GLOBAL_SEARCHPATHOPT =
+
+SUBMODULE_OPT =
+
+PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst
+
+LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst
+
+OBSERVE_PAR_OPTIONS = -error yes
+
+MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf
+PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf
+PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf
+BOOTLOOP_DIR = bootloops
+
+BRAMINIT_ELF_FILES =
+BRAMINIT_ELF_FILE_ARGS =
+
+ALL_USER_ELF_FILES =
+
+SIM_CMD = vsim
+
+BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.do
+
+STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.do
+
+TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do
+
+DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
+
+MIX_LANG_SIM_OPT = -mixed yes
+
+SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s mti
+
+
+LIBRARIES =
+
+LIBSCLEAN_TARGETS =
+
+PROGRAMCLEAN_TARGETS =
+
+CORE_STATE_DEVELOPMENT_FILES =
+
+WRAPPER_NGC_FILES = implementation/mb_plb_wrapper.ngc \
+implementation/plb2wb_bridge_0_wrapper.ngc \
+implementation/wb_conbus_0_wrapper.ngc \
+implementation/onchip_ram_0_wrapper.ngc \
+implementation/onchip_ram_1_wrapper.ngc \
+implementation/onchip_ram_2_wrapper.ngc
+
+POSTSYN_NETLIST = implementation/$(SYSTEM).ngc
+
+SYSTEM_BIT = implementation/$(SYSTEM).bit
+
+DOWNLOAD_BIT = implementation/download.bit
+
+SYSTEM_ACE = implementation/$(SYSTEM).ace
+
+UCF_FILE = data/system.ucf
+
+BMM_FILE = implementation/$(SYSTEM).bmm
+
+BITGEN_UT_FILE = etc/bitgen.ut
+
+XFLOW_OPT_FILE = etc/fast_runtime.opt
+XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)
+
+XPLORER_DEPENDENCY = __xps/xplorer.opt
+XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7
+
+FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY)
+
+SDK_EXPORT_DIR = SDK/SDK_Export/hw
+SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml
+SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit
+SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT)
Index: trunk/systems/test_system_sim/wb_retries/system.xmp
===================================================================
--- trunk/systems/test_system_sim/wb_retries/system.xmp (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/system.xmp (revision 2)
@@ -0,0 +1,25 @@
+#Please do not modify this file by hand
+XmpVersion: 11.4
+VerMgmt: 11.4
+IntStyle: default
+ModuleSearchPath: ../../EDK_Libs/
+MHS File: system.mhs
+MSS File: system.mss
+Architecture: virtex5
+Device: xc5vlx50
+Package: ff676
+SpeedGrade: -1
+UserCmd1:
+UserCmd1Type: 0
+UserCmd2:
+UserCmd2Type: 0
+GenSimTB: 0
+SdkExportBmmBit: 1
+SdkExportDir: SDK/SDK_Export
+InsertNoPads: 0
+WarnForEAArch: 1
+HdlLang: VHDL
+SimModel: BEHAVIORAL
+UcfFile: data/system.ucf
+EnableParTimingError: 1
+ShowLicenseDialog: 1
Index: trunk/systems/test_system_sim/wb_retries/data/system.ucf
===================================================================
--- trunk/systems/test_system_sim/wb_retries/data/system.ucf (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/data/system.ucf (revision 2)
@@ -0,0 +1,6 @@
+# Virtex 5 ML501 Evaluation Platform
+Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
+TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
+Net fpga_0_clk_1_sys_clk_pin LOC = AD8 | IOSTANDARD=LVCMOS33;
+Net fpga_0_rst_1_sys_rst_pin TIG;
+Net fpga_0_rst_1_sys_rst_pin LOC = T23 | IOSTANDARD=LVCMOS33 | PULLUP;
Index: trunk/systems/test_system_sim/wb_retries/system.mhs
===================================================================
--- trunk/systems/test_system_sim/wb_retries/system.mhs (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/system.mhs (revision 2)
@@ -0,0 +1,135 @@
+
+# ##############################################################################
+# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
+# Fri Mar 5 18:02:26 2010
+# Target Board: Xilinx Virtex 5 ML501 Evaluation Platform Rev 1
+# Family: virtex5
+# Device: xc5vlx50
+# Package: ff676
+# Speed Grade: -1
+# Processor number: 1
+# Processor 1: microblaze_0
+# System clock frequency: 125.0
+# Debug Interface: On-Chip HW Debug Module
+# ##############################################################################
+ PARAMETER VERSION = 2.1.0
+
+
+ PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
+ PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
+ PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]
+ PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]
+ PORT wb_clk_pin = wb_clk, DIR = I, SIGIS = CLK
+ PORT wb_rst_pin = wb_rst, DIR = I, SIGIS = RST
+
+
+BEGIN plb_v46
+ PARAMETER INSTANCE = mb_plb
+ PARAMETER HW_VER = 1.04.a
+ PARAMETER C_EXT_RESET_HIGH = 1
+ PARAMETER C_DCR_INTFCE = 1
+ PARAMETER C_BASEADDR = 0b0000000000
+ PARAMETER C_HIGHADDR = 0b1111111111
+ PORT PLB_Clk = clk_100MHz
+ PORT SYS_Rst = sys_rst_s
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_32
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_SIZE = 0b10
+ PARAMETER PLB_MASTER_NUM = 0b0000
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_0
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_monitor_bfm
+ PARAMETER INSTANCE = plb_bfm_monitor
+ PARAMETER HW_VER = 1.00.a
+ BUS_INTERFACE MON_PLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_3
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN bfm_synch
+ PARAMETER INSTANCE = plb_bfm_synch
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_NUM_SYNCH = 2
+ PORT TO_SYNCH_IN = synch_out
+ PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_3
+END
+
+BEGIN plb2wb_bridge
+ PARAMETER INSTANCE = plb2wb_bridge_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_BASEADDR = 0xf0000000
+ PARAMETER C_HIGHADDR = 0xf7ffffff
+ PARAMETER WB_ADR_OFFSET = 0xf0000000
+ PARAMETER WB_ADR_OFFSET_NEG = 1
+ PARAMETER SYNCHRONY = false
+ PARAMETER WB_PIC_INTS = 1
+ BUS_INTERFACE SPLB = mb_plb
+ BUS_INTERFACE MWB = wb_conbus_0
+ PORT SPLB_Clk = clk_100MHz
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+ PORT wb_pic_int_i = net_gnd
+END
+
+BEGIN wb_conbus
+ PARAMETER INSTANCE = wb_conbus_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER wb_s0_addr = 0x00
+ PARAMETER wb_s27_addr_w = 8
+ PARAMETER wb_s1_addr = 0x01
+ PARAMETER wb_s2_addr = 0x02
+ PARAMETER wb_s3_addr = 0x03
+ PARAMETER wb_s4_addr = 0x04
+ PARAMETER wb_s5_addr = 0x05
+ PARAMETER wb_s6_addr = 0x06
+ PARAMETER wb_s7_addr = 0x07
+ PARAMETER wb_s0_addr_w = 8
+ PARAMETER wb_s1_addr_w = 8
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 0
+ PARAMETER WR_DELAY = 0
+ PARAMETER WITH_ERR_OR_RTY = 0b10
+ PARAMETER ERR_RTY_INTERVAL = 5
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_1
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 1
+ PARAMETER WR_DELAY = 1
+ PARAMETER WITH_ERR_OR_RTY = 0b10
+ PARAMETER ERR_RTY_INTERVAL = 2
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_2
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 5
+ PARAMETER WR_DELAY = 5
+ PARAMETER WITH_ERR_OR_RTY = 0b10
+ PARAMETER ERR_RTY_INTERVAL = 3
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
Index: trunk/systems/test_system_sim/wb_retries/etc/bitgen.ut
===================================================================
--- trunk/systems/test_system_sim/wb_retries/etc/bitgen.ut (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/etc/bitgen.ut (revision 2)
@@ -0,0 +1,14 @@
+-g TdoPin:PULLNONE
+-g DriveDone:No
+-g StartUpClk:JTAGCLK
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g TckPin:PULLUP
+-g TdiPin:PULLUP
+-g TmsPin:PULLUP
+-g DonePipe:No
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:NONE
+-g Persist:No
+
Index: trunk/systems/test_system_sim/wb_retries/etc/fast_runtime.opt
===================================================================
--- trunk/systems/test_system_sim/wb_retries/etc/fast_runtime.opt (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/etc/fast_runtime.opt (revision 2)
@@ -0,0 +1,84 @@
+FLOWTYPE = FPGA;
+###############################################################
+## Filename: fast_runtime.opt
+##
+## Option File For Xilinx FPGA Implementation Flow for Fast
+## Runtime.
+##
+## Version: 4.1.1
+###############################################################
+#
+# Options for Translator
+#
+# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
+#
+Program ngdbuild
+-p ; # Partname to use - picked from xflow commandline
+-nt timestamp; # NGO File generation. Regenerate only when
+ # source netlist is newer than existing
+ # NGO file (default)
+-bm .bmm # Block RAM memory map file
+; # User design - pick from xflow command line
+-uc .ucf; # ucf constraints
+.ngd; # Name of NGD file. Filebase same as design filebase
+End Program ngdbuild
+
+#
+# Options for Mapper
+#
+# Type "map -h " for a detailed list of map command line options
+#
+Program map
+-o _map.ncd; # Output Mapped ncd file
+-w; # Overwrite output files.
+-pr b; # Pack internal FF/latches into IOBs
+#-fp .mfp; # Floorplan file
+-ol high;
+-timing;
+-detail;
+.ngd; # Input NGD file
+.pcf; # Physical constraints file
+END Program map
+
+#
+# Options for Post Map Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_map_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o _map.twr; # Output trace report file
+-xml _map.twx; # Output XML version of the timing report
+#-tsi _map.tsi; # Produce Timing Specification Interaction report
+_map.ncd; # Input mapped ncd
+.pcf; # Physical constraints file
+END Program post_map_trce
+
+#
+# Options for Place and Route
+#
+# Type "par -h" for a detailed list of par command line options
+#
+Program par
+-w; # Overwrite existing placed and routed ncd
+-ol high; # Overall effort level
+_map.ncd; # Input mapped NCD file
+.ncd; # Output placed and routed NCD
+.pcf; # Input physical constraints file
+END Program par
+
+#
+# Options for Post Par Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_par_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o .twr; # Output trace report file
+-xml .twx; # Output XML version of the timing report
+#-tsi .tsi; # Produce Timing Specification Interaction report
+.ncd; # Input placed and routed ncd
+.pcf; # Physical constraints file
+END Program post_par_trce
+
+
Index: trunk/systems/test_system_sim/wb_retries/etc/download.cmd
===================================================================
--- trunk/systems/test_system_sim/wb_retries/etc/download.cmd (nonexistent)
+++ trunk/systems/test_system_sim/wb_retries/etc/download.cmd (revision 2)
@@ -0,0 +1,6 @@
+setMode -bscan
+setCable -p auto
+identify
+assignfile -p 4 -file implementation/download.bit
+program -p 4
+quit
Index: trunk/systems/test_system_sim/wb_irqs/system.make
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/system.make (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/system.make (revision 2)
@@ -0,0 +1,248 @@
+#################################################################
+# Makefile generated by Xilinx Platform Studio
+# Project:/home/christian/share/semesterproject/trunk/systems/test_system_sim/wb_irqs/system.xmp
+#
+# WARNING : This file will be re-generated every time a command
+# to run a make target is invoked. So, any changes made to this
+# file manually, will be lost when make is invoked next.
+#################################################################
+
+# Name of the Microprocessor system
+# The hardware specification of the system is in file :
+# /home/christian/share/semesterproject/trunk/systems/test_system_sim/wb_irqs/system.mhs
+# The software specification of the system is in file :
+# /home/christian/share/semesterproject/trunk/systems/test_system_sim/wb_irqs/system.mss
+
+include system_incl.make
+
+#################################################################
+# PHONY TARGETS
+#################################################################
+.PHONY: dummy
+.PHONY: netlistclean
+.PHONY: bitsclean
+.PHONY: simclean
+.PHONY: exporttosdk
+
+#################################################################
+# EXTERNAL TARGETS
+#################################################################
+all:
+ @echo "Makefile to build a Microprocessor system :"
+ @echo "Run make with any of the following targets"
+ @echo " "
+ @echo " netlist : Generates the netlist for the given MHS "
+ @echo " bits : Runs Implementation tools to generate the bitstream"
+ @echo " exporttosdk: Export files to SDK"
+ @echo " "
+ @echo " libs : Configures the sw libraries for this system"
+ @echo " program : Compiles the program sources for all the processor instances"
+ @echo " "
+ @echo " init_bram: Initializes bitstream with BRAM data"
+ @echo " ace : Generate ace file from bitstream and elf"
+ @echo " download : Downloads the bitstream onto the board"
+ @echo " "
+ @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"
+ @echo " simmodel : Generates HDL simulation models for chosen simulation mode"
+ @echo " behavioral_model : Generates behavioral HDL models with BRAM initialization"
+ @echo " structural_model : Generates structural simulation HDL models with BRAM initialization"
+ @echo " timing : Generates timing simulation HDL models with BRAM initialization"
+ @echo " "
+ @echo " netlistclean: Deletes netlist"
+ @echo " bitsclean: Deletes bit, ncd, bmm files"
+ @echo " hwclean : Deletes implementation dir"
+ @echo " libsclean: Deletes sw libraries"
+ @echo " programclean: Deletes compiled ELF files"
+ @echo " swclean : Deletes sw libraries and ELF files"
+ @echo " simclean : Deletes simulation dir"
+ @echo " clean : Deletes all generated files/directories"
+ @echo " "
+ @echo " make : (Default)"
+ @echo " Creates a Microprocessor system using default initializations"
+ @echo " specified for each processor in MSS file"
+
+
+bits: $(SYSTEM_BIT)
+
+ace: $(SYSTEM_ACE)
+
+exporttosdk: $(SYSTEM_HW_HANDOFF_DEP)
+
+netlist: $(POSTSYN_NETLIST)
+
+libs: $(LIBRARIES)
+
+program: $(ALL_USER_ELF_FILES)
+ @echo "No user software applications specified"
+
+download: $(DOWNLOAD_BIT) dummy
+ @echo "*********************************************"
+ @echo "Downloading Bitstream onto the target board"
+ @echo "*********************************************"
+ impact -batch etc/download.cmd
+
+init_bram: $(DOWNLOAD_BIT)
+
+sim: $(DEFAULT_SIM_SCRIPT)
+ cd simulation/behavioral; \
+ $(SIM_CMD) &
+
+simmodel: $(DEFAULT_SIM_SCRIPT)
+
+behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)
+
+structural_model: $(STRUCTURAL_SIM_SCRIPT)
+
+clean: hwclean swclean simclean
+ rm -f _impact.cmd
+
+hwclean: netlistclean bitsclean
+ rm -rf implementation synthesis xst hdl
+ rm -rf xst.srp $(SYSTEM).srp
+ rm -f __xps/ise/_xmsgs/bitinit.xmsgs
+
+netlistclean:
+ rm -f $(POSTSYN_NETLIST)
+ rm -f platgen.log
+ rm -f __xps/ise/_xmsgs/platgen.xmsgs
+ rm -f $(BMM_FILE)
+
+bitsclean:
+ rm -f $(SYSTEM_BIT)
+ rm -f implementation/$(SYSTEM).ncd
+ rm -f implementation/$(SYSTEM)_bd.bmm
+ rm -f implementation/$(SYSTEM)_map.ncd
+ rm -f __xps/$(SYSTEM)_routed
+
+simclean:
+ rm -rf simulation/behavioral
+ rm -f simgen.log
+ rm -f __xps/ise/_xmsgs/simgen.xmsgs
+
+swclean: libsclean programclean
+
+libsclean: $(LIBSCLEAN_TARGETS)
+ rm -f libgen.log
+ rm -f __xps/ise/_xmsgs/libgen.xmsgs
+
+programclean: $(PROGRAMCLEAN_TARGETS)
+
+#################################################################
+# SOFTWARE PLATFORM FLOW
+#################################################################
+
+
+$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt
+ @echo "*********************************************"
+ @echo "Creating software libraries..."
+ @echo "*********************************************"
+ libgen $(LIBGEN_OPTIONS) $(MSSFILE)
+
+
+#################################################################
+# BOOTLOOP ELF FILES
+#################################################################
+
+
+
+#################################################################
+# HARDWARE IMPLEMENTATION FLOW
+#################################################################
+
+
+$(BMM_FILE) \
+$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
+ $(CORE_STATE_DEVELOPMENT_FILES)
+ @echo "****************************************************"
+ @echo "Creating system netlist for hardware specification.."
+ @echo "****************************************************"
+ platgen $(PLATGEN_OPTIONS) $(MHSFILE)
+
+$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)
+ @echo "Running synthesis..."
+ bash -c "cd synthesis; ./synthesis.sh"
+
+__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY)
+ @echo "*********************************************"
+ @echo "Running Xilinx Implementation tools.."
+ @echo "*********************************************"
+ @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf
+ @cp -f etc/fast_runtime.opt implementation/xflow.opt
+ xflow -wd implementation -p $(DEVICE) -implement xflow.opt -ise ../__xps/ise/$(SYSTEM).ise $(SYSTEM).ngc
+ touch __xps/$(SYSTEM)_routed
+
+$(SYSTEM_BIT): __xps/$(SYSTEM)_routed $(BITGEN_UT_FILE)
+ xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par
+ @echo "*********************************************"
+ @echo "Running Bitgen.."
+ @echo "*********************************************"
+ @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut
+ cd implementation; bitgen -w -f bitgen.ut $(SYSTEM); cd ..
+
+$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt
+ # @cp -f implementation/$(SYSTEM)_bd.bmm .
+ @echo "*********************************************"
+ @echo "Initializing BRAM contents of the bitstream"
+ @echo "*********************************************"
+ bitinit -p $(DEVICE) $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \
+ -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)
+ @rm -f $(SYSTEM)_bd.bmm
+
+$(SYSTEM_ACE):
+ @echo "In order to generate ace file, you must have:-"
+ @echo "- exactly one processor."
+ @echo "- opb_mdm, if using microblaze."
+
+#################################################################
+# EXPORT_TO_SDK FLOW
+#################################################################
+
+
+$(SYSTEM_HW_HANDOFF): $(MHSFILE) __xps/platgen.opt
+ mkdir -p $(SDK_EXPORT_DIR)
+ psf2Edward -inp $(SYSTEM).xmp -xml $(SDK_EXPORT_DIR)/$(SYSTEM).xml $(GLOBAL_SEARCHPATHOPT)
+ xdsgen -inp $(SYSTEM).xmp -report $(SDK_EXPORT_DIR)/$(SYSTEM).html $(GLOBAL_SEARCHPATHOPT) -make_docs_local
+
+$(SYSTEM_HW_HANDOFF_BIT): $(SYSTEM_BIT)
+ @rm -rf $(SYSTEM_HW_HANDOFF_BIT)
+ @cp -f $(SYSTEM_BIT) $(SDK_EXPORT_DIR)/
+
+
+#################################################################
+# SIMULATION FLOW
+#################################################################
+
+
+################## BEHAVIORAL SIMULATION ##################
+
+$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
+ $(BRAMINIT_ELF_FILES)
+ @echo "*********************************************"
+ @echo "Creating behavioral simulation models..."
+ @echo "*********************************************"
+ simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)
+
+################## STRUCTURAL SIMULATION ##################
+
+$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \
+ $(BRAMINIT_ELF_FILES)
+ @echo "*********************************************"
+ @echo "Creating structural simulation models..."
+ @echo "*********************************************"
+ simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)
+
+
+################## TIMING SIMULATION ##################
+
+implementation/$(SYSTEM).ncd: __xps/$(SYSTEM)_routed
+
+$(TIMING_SIM_SCRIPT): implementation/$(SYSTEM).ncd __xps/simgen.opt \
+ $(BRAMINIT_ELF_FILES)
+ @echo "*********************************************"
+ @echo "Creating timing simulation models..."
+ @echo "*********************************************"
+ simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)
+
+dummy:
+ @echo ""
+
Index: trunk/systems/test_system_sim/wb_irqs/simulation/testbench/system_tb.vhd
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/simulation/testbench/system_tb.vhd (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/simulation/testbench/system_tb.vhd (revision 2)
@@ -0,0 +1,164 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+entity system_tb is
+end system_tb;
+
+architecture STRUCTURE of system_tb is
+
+ constant sys_clk_period : time := 10.000000 ns;
+ constant wb_clk_period : time := 13.333333 ns;
+ constant sys_rst_length : time := 160 ns;
+
+ constant SYNCH_PART : integer := 1;
+ constant SYNCH_SUBPART : integer := 2;
+ constant SYNCH_SUBSUBPART : integer := 3;
+
+ constant SUBSUBPART_LENGTH : integer := 15; -- 10 clock cycles
+ constant SUBPART_LENGTH : integer := 5; -- 7 times SUBSUBPART_LENGTH
+ constant PART_LENGTH : integer := 5; -- 6 times SUBPART_LENGTH
+
+ component system is
+ port (
+ sys_clk_pin : in std_logic;
+ sys_rst_pin : in std_logic;
+ to_synch_in_pin : in std_logic_vector( 0 to 31 );
+ from_synch_out_pin : out std_logic_vector( 0 to 31 );
+ wb_clk_pin : in std_logic;
+ wb_rst_pin : in std_logic;
+ PLB2WB_IRQ_pin : out std_logic;
+ wb_pic_int_i_pin : in std_logic_vector( 0 to 3 )
+ );
+ end component;
+
+
+ signal sys_clk : std_logic;
+ signal sys_rst : std_logic := '1';
+ signal wb_clk : std_logic;
+ signal wb_rst : std_logic;
+ signal plb_irq : std_logic;
+ signal wb_irq : std_logic_vector( 0 to 3 );
+
+ signal to_synch_in : std_logic_vector( 0 to 31 );
+ signal from_synch_out : std_logic_vector( 0 to 31 );
+ signal tb_synch_out : std_logic_vector( 0 to 31 ) := ( others => '0' );
+
+
+ procedure SendSynch( signal synch_out : OUT std_logic_vector;
+ COMMAND : integer ) is
+ begin
+ synch_out( COMMAND ) <= '1';
+ wait for sys_clk_period*1;
+ synch_out( COMMAND ) <= '0';
+ end procedure SendSynch;
+
+
+begin
+
+ to_synch_in <= from_synch_out or tb_synch_out;
+
+
+
+ dut : system
+ port map (
+ sys_clk_pin => sys_clk,
+ sys_rst_pin => sys_rst,
+ to_synch_in_pin => to_synch_in,
+ from_synch_out_pin => from_synch_out,
+ wb_clk_pin => wb_clk,
+ wb_rst_pin => wb_rst,
+ PLB2WB_IRQ_pin => plb_irq,
+ wb_pic_int_i_pin => wb_irq
+ );
+
+
+ --
+ -- generate plb-clk
+ --
+ process
+ begin
+ sys_clk <= '0';
+ loop
+ wait for (sys_clk_period/2);
+ sys_clk <= not sys_clk;
+ end loop;
+ end process;
+
+
+ --
+ --
+ --
+ process
+ begin
+ wb_clk <= '0';
+ loop
+ wait for (wb_clk_period/2);
+ wb_clk <= not wb_clk;
+ end loop;
+ end process;
+
+
+
+
+ process
+ begin
+ sys_rst <= '1';
+ wb_rst <= '1';
+ wait for ( sys_rst_length );
+ wb_rst <= not wb_rst;
+ sys_rst <= not sys_rst;
+ wait;
+ end process;
+
+
+
+ process
+ begin
+ wb_irq <= ( others => '0' );
+ wait until sys_rst = '0';
+
+ wait for wb_clk_period * 18;
+ wb_irq(0) <= '1';
+ wait for wb_clk_period * 3;
+ wb_irq(0) <= '0';
+ wait for wb_clk_period * 1;
+ wb_irq(2) <= '1';
+ wait for wb_clk_period * 1;
+ wb_irq(2) <= '0';
+ wait for wb_clk_period * 10;
+
+ SendSynch( tb_synch_out, SYNCH_PART );
+
+ wait for wb_clk_period * 20;
+ wb_irq(1) <= '1';
+ wait for wb_clk_period * 3;
+ wb_irq(1) <= '0';
+ wait for wb_clk_period * 10;
+
+ SendSynch( tb_synch_out, SYNCH_PART );
+
+ wait for wb_clk_period * 20;
+ wb_irq(2) <= '1';
+ wait for wb_clk_period * 3;
+ wb_irq(2) <= '0';
+ wait for wb_clk_period * 10;
+
+ SendSynch( tb_synch_out, SYNCH_PART );
+
+ wait for wb_clk_period * 20;
+ wb_irq(3) <= '1';
+ wait for wb_clk_period * 3;
+ wb_irq(3) <= '0';
+ wait for wb_clk_period * 10;
+
+ SendSynch( tb_synch_out, SYNCH_PART );
+
+ end process;
+
+
+end architecture STRUCTURE;
+
Index: trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/wave.do
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/wave.do (revision 2)
@@ -0,0 +1,262 @@
+
+#
+# Display top-level ports
+#
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+set tbpath {/system_tb/dut}
+
+eval add wave -color DarkGreen -noupdate -divider {"top-level ports"}
+eval add wave -color DarkGreen -noupdate $binopt $tbpath/sys_clk_pin
+eval add wave -color DarkGreen -noupdate $binopt $tbpath/sys_rst_pin
+#eval add wave -color DarkGreen -noupdate $binopt $tbpath/dut/plb_bfm_slave/to_synch_in
+eval add wave -color DarkGreen -noupdate $binopt /system_tb/to_synch_in
+eval add wave -noupdate $hexopt -label wb_irq -color Yellow /system_tb/wb_irq
+eval add wave -noupdate $hexopt -label plb_irq -color Yellow /system_tb/plb_irq
+
+ # Master signals
+ proc add_master { num color } {
+ global binopt hexopt tbpath
+ eval add wave -color ${color} -noupdate -group Master_${num}
+ eval add wave -color ${color} -label ${num}_m_request -group Master_${num} -noupdate $binopt $tbpath/plb_bfm_master_${num}/m_request
+ eval add wave -color ${color} -label ${num}_m_abus -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_abus
+ eval add wave -color ${color} -label ${num}_m_be -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_be
+ eval add wave -color ${color} -label ${num}_m_rnw -group Master_${num} -noupdate $binopt $tbpath/plb_bfm_master_${num}/m_rnw
+ eval add wave -color ${color} -label ${num}_m_size -group Master_${num} -noupdate $binopt $tbpath/plb_bfm_master_${num}/m_size
+ eval add wave -color ${color} -label ${num}_m_priority -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_priority
+ eval add wave -color ${color} -label ${num}_plb_mrddbus -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/plb_mrddbus
+ eval add wave -color ${color} -label ${num}_m_wrdbus -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_wrdbus
+ }
+ add_master 32 White
+
+
+
+
+
+# do ../behavioral/mb_plb_wave.do
+# do ../behavioral/plb_bfm_monitor_wave.do
+# do ../behavioral/plb_bfm_slave_wave.do
+
+
+ proc add_ocram { num color } {
+ global binopt hexopt tbpath
+ eval add wave -color ${color} -noupdate -group ocram${num}
+ eval add wave -color ${color} -label wb_stb_i -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_stb_i
+ eval add wave -color ${color} -label wb_ack_o -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_ack_o
+ eval add wave -color ${color} -label wb_err_o -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_err_o
+ eval add wave -color ${color} -label wb_rty_o -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_rty_o
+ eval add wave -color ${color} -label w_ack -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/w_ack
+ eval add wave -color ${color} -label err_rty_count_r -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/err_rty_count_r
+ eval add wave -color ${color} -label err_rty_count_w -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/err_rty_count_w
+ eval add wave -color ${color} -label r_delay_count -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/r_delay_count
+ eval add wave -color ${color} -label w_delay_count -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/w_delay_count
+
+ eval add wave -color ${color} -label ram(0) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(0)
+ eval add wave -color ${color} -label ram(1) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(1)
+ eval add wave -color ${color} -label ram(2) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(2)
+ eval add wave -color ${color} -label ram(3) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(3)
+ eval add wave -color ${color} -label ram(4) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(4)
+ eval add wave -color ${color} -label ram(5) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(5)
+ eval add wave -color ${color} -label ram(6) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(6)
+ eval add wave -color ${color} -label ram(7) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(7)
+ }
+
+
+
+
+ #
+ # General bridge signals
+ #
+ eval add wave -color purple -group bridge_general -noupdate
+ eval add wave -color purple -label sl_addrack -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_addrack
+ eval add wave -color purple -label plb_abus -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb_abus
+ eval add wave -color purple -label plb_be -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb_be
+ eval add wave -color purple -label plb_pavalid -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_pavalid
+ eval add wave -color purple -label plb_savalid -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_savalid
+ eval add wave -color purple -label plb_rnw -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_rnw
+ eval add wave -color purple -label plb_msize -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_msize
+ eval add wave -color purple -label plb_type -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_type
+ eval add wave -color purple -label plb_wrdbus -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb_wrdbus
+ eval add wave -color purple -label sl_rddbus -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/sl_rddbus
+
+ eval add wave -color purple -label sl_wrdack -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_wrdack
+ eval add wave -color maroon -label sl_wrcomp -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_wrcomp
+ eval add wave -color purple -label sl_rddack -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_rddack
+ eval add wave -color maroon -label sl_rdcomp -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_rdcomp
+
+ eval add wave -color maroon -label sl_rdprim -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_rdprim
+ eval add wave -color maroon -label sl_wrprim -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_wrprim
+
+
+ eval add wave -color maroon -label wb_adr_o -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_adr_o
+ eval add wave -color maroon -label wb_cyc_o -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_cyc_o
+ eval add wave -color maroon -label wb_dat_i -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_dat_i
+ eval add wave -color maroon -label wb_dat_o -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_dat_o
+ eval add wave -color maroon -label wb_err_i -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_err_i
+ eval add wave -color maroon -label wb_rst_i -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_rst_i
+ eval add wave -color maroon -label wb_sel_o -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_sel_o
+ eval add wave -color maroon -label wb_stb_o -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_stb_o
+ eval add wave -color maroon -label wb_we_o -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_we_o
+ eval add wave -color maroon -label sl_mbusy -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mbusy
+ eval add wave -color maroon -label sl_mwrerr -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mwrerr
+ eval add wave -color maroon -label sl_mrderr -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mrderr
+
+
+ #
+ # Bridge - Transfer Control Unit
+ #
+ eval add wave -color aquamarine -group bridge_TCU -noupdate
+ eval add wave -color aquamarine -label c_plb_wstate -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/c_plb_wstate
+ eval add wave -color aquamarine -label c_plb_rstate -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/c_plb_rstate
+ eval add wave -color aquamarine -label c_wb_state -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/c_wb_state
+ eval add wave -color aquamarine -label wb_ack -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_ack
+ eval add wave -color aquamarine -label wb_err -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_err
+ eval add wave -color aquamarine -label wb_rty -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_rty
+ eval add wave -color aquamarine -label wb_rst_i -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_rst_i
+ eval add wave -color aquamarine -label wb_rst_short -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_rst_short
+
+ eval add wave -color aquamarine -label tcu_addrack -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_addrack
+ eval add wave -color aquamarine -label sl_rdwdaddr -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/sl_rdwdaddr
+
+ eval add wave -color aquamarine -label tcu_adr_offset -group bridge_TCU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_adr_offset
+ eval add wave -color aquamarine -label tcu_adrbufren -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_adrbufren
+ eval add wave -color aquamarine -label tcu_adrbufwen -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_adrbufwen
+ eval add wave -color aquamarine -label tcu_rpiperden -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_rpiperden
+ eval add wave -color aquamarine -label tcu_wpiperden -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_wpiperden
+
+ eval add wave -color aquamarine -label tcu_enrddbus -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_enrddbus
+ eval add wave -color aquamarine -label tcu_rbufren -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_rbufren
+ eval add wave -color aquamarine -label tcu_rbufwen -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_rbufwen
+ eval add wave -color aquamarine -label tcu_wbufren -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_wbufren
+ eval add wave -color aquamarine -label tcu_wbufwen -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_wbufwen
+
+ eval add wave -color aquamarine -label tcu_enStuRDDbus -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_ensturddbus
+ eval add wave -color aquamarine -label tcu_stuWritePA -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_stuwritepa
+ eval add wave -color aquamarine -label tcu_stuWriteSA -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_stuwritesa
+ eval add wave -color aquamarine -label tcu_stat2plb_en -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_stat2plb_en
+ eval add wave -color aquamarine -label tcu_wb_status_info -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/tcu_wb_status_info
+
+ eval add wave -color aquamarine -label tcu_mrbusy -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_mrbusy
+ eval add wave -color aquamarine -label mbusy_read_out -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/mbusy_read_out
+ eval add wave -color aquamarine -label mbusy_write_out -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/mbusy_write_out
+ eval add wave -color aquamarine -label SL_MWrErr -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/SL_MWrErr
+ eval add wave -color aquamarine -label SL_MRdErr -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/SL_MRdErr
+ eval add wave -color aquamarine -label sl_wrbterm -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/sl_wrbterm
+ eval add wave -color aquamarine -label sl_rdbterm -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/sl_rdbterm
+
+ eval add wave -color aquamarine -label wb_pic_int_i -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_pic_int_i
+ eval add wave -color aquamarine -label pic_int_ahigh_short -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/pic_int_ahigh_short
+ eval add wave -color aquamarine -label pic_int_ahigh -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/pic_int_ahigh
+ #
+ # Bridge - Status Unit
+ #
+ eval add wave -color DarkSalmon -group bridge_STU -noupdate
+ eval add wave -color DarkSalmon -label STU_full -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_full
+ eval add wave -color DarkSalmon -label STU_softReset -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_softReset
+ eval add wave -color DarkSalmon -label STU_continue -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_continue
+ eval add wave -color DarkSalmon -label STU_abort -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_abort
+ eval add wave -color DarkSalmon -label amu_masterid -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/amu_masterid
+ eval add wave -color DarkSalmon -label plb_masterid -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/plb_masterid
+
+ eval add wave -color DarkSalmon -label stat2plb_empty -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2plb_empty
+ eval add wave -color DarkSalmon -label stat2plb_rd_en -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2plb_rd_en
+ eval add wave -color DarkSalmon -label stat2wb_rd_en -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_rd_en
+ eval add wave -color DarkSalmon -label stat2wb_wr_en -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_wr_en
+ eval add wave -color DarkSalmon -label stat2wb_full -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_full
+ eval add wave -color DarkSalmon -label stat2wb_empty -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_empty
+ eval add wave -color DarkSalmon -label stat2wb_dout -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_dout
+ eval add wave -color DarkSalmon -label stat2wb_din -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_din
+
+ eval add wave -color DarkSalmon -label tcu_stuLatchPA -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/tcu_stulatchpa
+ eval add wave -color DarkSalmon -label tcu_stuLatchSA -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/tcu_stulatchsa
+
+
+ eval add wave -color DarkSalmon -label soft_reset_count -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/soft_reset_count
+ eval add wave -color DarkSalmon -label address_reg -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/address_reg
+ eval add wave -color DarkSalmon -label status_reg0 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(0)
+ eval add wave -color DarkSalmon -label status_reg1 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(1)
+ eval add wave -color DarkSalmon -label status_reg2 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(2)
+ eval add wave -color DarkSalmon -label status_reg3 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(3)
+ eval add wave -color DarkSalmon -label status_reg_out -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_reg_out
+
+
+
+
+ #
+ # Bridge - Adress Management Unit
+ #
+ eval add wave -color RosyBrown -group bridge_AMU -noupdate
+ eval add wave -color RosyBrown -label amu_addrack -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_addrack
+ eval add wave -color RosyBrown -label plb_savalid -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/plb_savalid
+ eval add wave -color RosyBrown -label amu_buf_rnw -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_rnw
+ eval add wave -color RosyBrown -label amu_bufempty -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_bufempty
+ eval add wave -color RosyBrown -label amu_buffull -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buffull
+ eval add wave -color RosyBrown -label amu_deviceselect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_deviceselect
+ eval add wave -color RosyBrown -label amu_statusselect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_statusselect
+ eval add wave -color RosyBrown -label amu_pipe_rmID -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_rmID
+ eval add wave -color RosyBrown -label amu_pipe_wmID -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_wmID
+ eval add wave -color rosyBrown -label amu_buf_size -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_size
+ eval add wave -color rosyBrown -label amu_buf_BE -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_BE
+ eval add wave -color rosyBrown -label amu_pipe_size -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_size
+ eval add wave -color rosyBrown -label amu_pipe_size -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_BE
+ eval add wave -color RosyBrown -label amu_buf_adr -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_adr
+ eval add wave -color RosyBrown -label wb_sel_o -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/wb_sel_o
+ eval add wave -color RosyBrown -label rpipe_out -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/rpipe_out
+ eval add wave -color RosyBrown -label wpipe_out -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/wpipe_out
+ eval add wave -color RosyBrown -label pipeline_in -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/pipeline_in
+ eval add wave -color RosyBrown -label AMU_pipe_adr -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_adr
+ eval add wave -color RosyBrown -label AMU_pipe_rStatusSelect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_rStatusSelect
+ eval add wave -color RosyBrown -label AMU_pipe_wStatusSelect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_wStatusSelect
+
+
+ #
+ # Read buffer
+ #
+ eval add wave -color SpringGreen -group bridge_RBF -noupdate
+ eval add wave -color SpringGreen -label rbuf_din -group bridge_RBF -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbuf_din
+ eval add wave -color SpringGreen -label rbuf_dout -group bridge_RBF -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbuf_dout
+ eval add wave -color SpringGreen -label tcu_rbufren -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/tcu_rbufren
+ eval add wave -color SpringGreen -label tcu_rbufwen -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/tcu_rbufwen
+ eval add wave -color SpringGreen -label rbf_empty -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbf_empty
+ eval add wave -color SpringGreen -label rbf_full -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbf_full
+
+
+ #
+ # Write buffer
+ #
+ eval add wave -color LimeGreen -group bridge_WBF -noupdate
+ eval add wave -color LimeGreen -label plb_size -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/plb_size
+ eval add wave -color LimeGreen -label wbf_empty -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/wbf_empty
+ eval add wave -color LimeGreen -label wbf_full -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/wbf_full
+ eval add wave -color LimeGreen -label wbf_wbus -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/wbf_wbus
+ eval add wave -color LimeGreen -label tcu_wbufren -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/tcu_wbufren
+ eval add wave -color LimeGreen -label tcu_wbufwen -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/tcu_wbufwen
+
+
+
+ #
+ # Whishbone signals
+ #
+ eval add wave -color Orange -noupdate -group Wishbone
+
+ eval add wave -color Orange -label wb_m_dat_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_dat_o
+ eval add wave -color Orange -label wb_m_ack_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_ack_o
+ eval add wave -color Orange -label wb_m_err_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_err_o
+ eval add wave -color Orange -label wb_m_rty_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_rty_o
+ eval add wave -color Orange -label wb_s_dat_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_dat_o
+ eval add wave -color Orange -label wb_s_adr_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_adr_o
+ eval add wave -color Orange -label wb_s_sel_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_sel_o
+ eval add wave -color Orange -label wb_s_we_o -group Wishbone -noupdate $binopt $tbpath/wb_conbus_0/wb_s_we_o
+ eval add wave -color Orange -label wb_s_cyc_o -group Wishbone -noupdate $binopt $tbpath/wb_conbus_0/wb_s_cyc_o
+ eval add wave -color Orange -label wb_s_stb_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_stb_o
+# eval add wave -color Orange -label wb_s_lock_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_lock_o
+ eval add wave -color Orange -label wb_clk_i -group Wishbone -noupdate $binopt $tbpath/wb_conbus_0/wb_clk_i
+
+
+ add_ocram 0 OrangeRed
+
+ configure wave -namecolwidth 347
+ configure wave -valuecolwidth 252
+ configure wave -timeline 0
+ configure wave -timelineunits ns
Index: trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/wave2.do
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/wave2.do (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/wave2.do (revision 2)
@@ -0,0 +1,55 @@
+
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+
+eval add wave -noupdate $binopt -label Clock -color SteelBlue /system_tb/sys_clk
+eval add wave -noupdate $binopt -label Reset -color SteelBlue /system_tb/sys_rst
+eval add wave -noupdate $hexopt -label synch_in -color Yellow /system_tb/dut/synch_in
+
+eval add wave -noupdate $hexopt -label wb_irq -color Yellow /system_tb/wb_irq
+eval add wave -noupdate $hexopt -label plb_irq -color Yellow /system_tb/plb_irq
+
+
+eval add wave -noupdate $binopt -label Mn_request -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_request
+
+eval add wave -noupdate $binopt -label Mn_RNW -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_rnw
+eval add wave -noupdate $binopt -label Mn_BE -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_be
+eval add wave -noupdate $binopt -label Mn_size -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_size
+eval add wave -noupdate $binopt -label Mn_type -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_type
+eval add wave -noupdate $hexopt -label Mn_ABus -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_abus
+eval add wave -noupdate $binopt -label PLB_PAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_pavalid
+eval add wave -noupdate $binopt -label PLB_SAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_savalid
+eval add wave -noupdate $binopt -label PLB_rdPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_rdprim
+eval add wave -noupdate $binopt -label PLB_wrPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_wrprim
+
+eval add wave -noupdate $hexopt -label Sl_rdDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddbus
+eval add wave -noupdate $binopt -label Sl_rdDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddack
+eval add wave -noupdate $binopt -label Sl_rdComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rdcomp
+
+
+eval add wave -noupdate $hexopt -label Sl_wrDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/plb_wrdbus
+eval add wave -noupdate $binopt -label Sl_wrDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrdack
+eval add wave -noupdate $binopt -label Sl_wrComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrcomp
+
+
+
+eval add wave -noupdate $binopt -label WB_CLK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_clk_i
+eval add wave -noupdate $binopt -label WB_RST_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rst_i
+eval add wave -noupdate $hexopt -label WB_ADR_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_adr_o
+eval add wave -noupdate $hexopt -label WB_DAT_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_o
+eval add wave -noupdate $hexopt -label WB_DAT_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_i
+eval add wave -noupdate $binopt -label WB_ACK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_ack_i
+eval add wave -noupdate $binopt -label WB_RTY_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rty_i
+eval add wave -noupdate $binopt -label WB_ERR_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_err_i
+eval add wave -noupdate $binopt -label WB_SEL_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_sel_o
+eval add wave -noupdate $binopt -label WB_STB_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_stb_o
+eval add wave -noupdate $binopt -label WB_WE_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_we_o
+
+
+
+eval add wave -noupdate $binopt -label bram0_ack_o -color Orange /system_tb/dut/onchip_ram_0/wb_ack_o
+
+
+configure wave -gridperiod 1
+configure wave -namecolwidth 200
Index: trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/transfers.bfl (revision 2)
@@ -0,0 +1,59 @@
+
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+
+
+ mem_update(addr=00010000,data=80000000)
+ mem_update(addr=0001000c,data=80000000)
+ wait( level=PART )
+
+ -- the first irq was rised
+ read ( addr=0001000c, size=0000, be=1111 )
+
+ -- clear the bridge-irq
+ write ( addr=00010000, size=0000, be=1111 )
+
+ -- there should be a second irq (rised directly after the first)
+ mem_update(addr=0001000c,data=20000000)
+ read ( addr=0001000c, size=0000, be=1111 )
+
+ -- clear the bridge-irq
+ write ( addr=00010000, size=0000, be=1111 )
+
+
+ mem_update(addr=00010000,data=80000000)
+ mem_update(addr=0001000c,data=40000000)
+ wait( level=PART )
+ read ( addr=00010000, size=0000, be=1111 )
+ read ( addr=0001000c, size=0000, be=1111 )
+ mem_update(addr=00010000,data=00000000)
+ write ( addr=00010000, size=0000, be=1111 )
+
+
+ mem_update(addr=00010000,data=80000000)
+ mem_update(addr=0001000c,data=20000000)
+ wait( level=PART )
+ read ( addr=00010000, size=0000, be=1111 )
+ read ( addr=0001000c, size=0000, be=1111 )
+ mem_update(addr=00010000,data=00000000)
+ write ( addr=00010000, size=0000, be=1111 )
+
+
+ mem_update(addr=00010000,data=80000000)
+ mem_update(addr=0001000c,data=10000000)
+ wait( level=PART )
+ read ( addr=0001000c, size=0000, be=1111 )
+ mem_update(addr=00010000,data=00000000)
+ write ( addr=00010000, size=0000, be=1111 )
+
+
Index: trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/sim.do
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 3000 ns
+
+
Index: trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/Makefile
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/simulation/test_cases/irq_tests/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/wb_irqs/simulation/Makefile
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/simulation/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/simulation/Makefile (revision 2)
@@ -0,0 +1,107 @@
+SIM_DIR=$(shell pwd)
+
+XPS_PROJ_DIR=$(SIM_DIR)/..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+COMMON_DIR=$(SIM_DIR)/../../common
+LOG_DIR=$(SIM_DIR)/log
+PLB_BFM_SETUP_DIR=$(SIM_DIR)/../../plb_bfm_setup
+
+
+include $(COMMON_DIR)/Makefile
+
+
+
+all: sim
+
+
+
+WORK_TARGET=$(SIM_BIN_DIR)/work/system/_primary.dat
+
+
+
+###
+#
+# note: WORK_TARGET is defined some lines above, the rest in ../../common/Makefile
+#
+COMPILE_COMPONENTS=$(TESTRAM_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET) $(PLB_BFM_TARGET) $(WORK_TARGET)
+
+
+
+#
+# Generate Simulation HDL Files
+# (This is the same than XPS-Gui->Simulation->Generate Simulation HDL Files)
+#
+$(SIM_DIR)/behavioral: $(XPS_PROJ_DIR)/system.mhs
+ @mkdir -p $(LOG_DIR)
+ simgen $(XPS_PROJ_DIR)/system.mhs -lang vhdl \
+ -p virtex5 \
+ -m beh \
+ -od $(XPS_PROJ_DIR)/ \
+ -s mti \
+ -lp $(LIB_DIR) \
+ -log $(LOG_DIR)/simgen
+ @mv simgen.opt log # there is no simgen-flag for this!
+
+
+
+
+
+# PLB_BFM_TARGET=$(SIM_BIN_DIR)/plbv46_bfm/system/_primary.dat
+# #BFM_SOURCE=$() TODO
+# $(PLB_BFM_TARGET):
+# cd $(SIM_BIN_DIR); \
+# vlib plbv46_bfm; \
+# vmap plbv46_bfm plbv46_bfm; \
+# vlib plbv46_master_bfm_v1_00_a; \
+# vmap plbv46_master_bfm_v1_00_a plbv46_master_bfm_v1_00_a; \
+# vlib plbv46_monitor_bfm_v1_00_a; \
+# vmap plbv46_monitor_bfm_v1_00_a plbv46_monitor_bfm_v1_00_a; \
+# vlib plbv46_slave_bfm_v1_00_a; \
+# vmap plbv46_slave_bfm_v1_00_a plbv46_slave_bfm_v1_00_a; \
+# vcom $(VHDL_CFLAGS) -work plbv46_bfm \
+# "$(PLB_BFM_SETUP_DIR)/plb_dcl_128.vhd"; \
+# vcom $(VHDL_CFLAGS) -work plbv46_master_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_master_bfm_v1_00_a/hdl/vhdl/plbv46_master_bfm.vhd" ; \
+# vcom $(VHDL_CFLAGS) -work plbv46_monitor_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_monitor_bfm_v1_00_a/hdl/vhdl/plbv46_monitor_bfm.vhd";\
+# vcom $(VHDL_CFLAGS) -work plbv46_slave_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_slave_bfm_v1_00_a/hdl/vhdl/plbv46_slave_bfm.vhd";
+
+
+
+
+
+$(WORK_TARGET): $(SIM_DIR)/behavioral $(SIM_BIN_DIR)/../testbench/system_tb.vhd
+ cd $(SIM_BIN_DIR); \
+ vlib work; \
+ vmap work work; \
+ vlog -novopt -93 -work work "../behavioral/wb_conbus_0_wrapper.v"; \
+ vcom $(VHDL_CFLAGS) -work work \
+ "../behavioral/onchip_ram_0_wrapper.vhd" \
+ "../behavioral/mb_plb_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_32_wrapper.vhd" \
+ "../behavioral/plb_bfm_monitor_wrapper.vhd" \
+ "../behavioral/plb_bfm_synch_wrapper.vhd" \
+ "../behavioral/plb2wb_bridge_0_wrapper.vhd" \
+ "../behavioral/system.vhd" \
+ "../testbench/system_tb.vhd"
+
+
+
+
+
+
+compile: $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS)
+
+
+
+
+
+
+clean:
+ @echo "cleaning sim bin dir in retries\n"
+ rm -rf \
+ $(SIM_DIR)/behavioral \
+ $(SIM_BIN_DIR) \
+ $(LOG_DIR)
+
Index: trunk/systems/test_system_sim/wb_irqs/system_incl.make
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/system_incl.make (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/system_incl.make (revision 2)
@@ -0,0 +1,99 @@
+#################################################################
+# Makefile generated by Xilinx Platform Studio
+# Project:/home/christian/share/semesterproject/trunk/systems/test_system_sim/wb_irqs/system.xmp
+#
+# WARNING : This file will be re-generated every time a command
+# to run a make target is invoked. So, any changes made to this
+# file manually, will be lost when make is invoked next.
+#################################################################
+
+XILINX_EDK_DIR = /opt/Xilinx/11.1/EDK
+NON_CYG_XILINX_EDK_DIR = /opt/Xilinx/11.1/EDK
+
+SYSTEM = system
+
+MHSFILE = system.mhs
+
+MSSFILE = system.mss
+
+FPGA_ARCH = virtex5
+
+DEVICE = xc5vlx50ff676-1
+
+LANGUAGE = vhdl
+
+SEARCHPATHOPT = -lp /home/christian/share/semesterproject/trunk/systems/EDK_Libs/
+GLOBAL_SEARCHPATHOPT =
+
+SUBMODULE_OPT =
+
+PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst
+
+LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst
+
+OBSERVE_PAR_OPTIONS = -error yes
+
+MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf
+PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf
+PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf
+BOOTLOOP_DIR = bootloops
+
+BRAMINIT_ELF_FILES =
+BRAMINIT_ELF_FILE_ARGS =
+
+ALL_USER_ELF_FILES =
+
+SIM_CMD = vsim
+
+BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.do
+
+STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.do
+
+TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do
+
+DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
+
+MIX_LANG_SIM_OPT = -mixed yes
+
+SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s mti
+
+
+LIBRARIES =
+
+LIBSCLEAN_TARGETS =
+
+PROGRAMCLEAN_TARGETS =
+
+CORE_STATE_DEVELOPMENT_FILES =
+
+WRAPPER_NGC_FILES = implementation/mb_plb_wrapper.ngc \
+implementation/plb2wb_bridge_0_wrapper.ngc \
+implementation/wb_conbus_0_wrapper.ngc \
+implementation/onchip_ram_0_wrapper.ngc
+
+POSTSYN_NETLIST = implementation/$(SYSTEM).ngc
+
+SYSTEM_BIT = implementation/$(SYSTEM).bit
+
+DOWNLOAD_BIT = implementation/download.bit
+
+SYSTEM_ACE = implementation/$(SYSTEM).ace
+
+UCF_FILE = data/system.ucf
+
+BMM_FILE = implementation/$(SYSTEM).bmm
+
+BITGEN_UT_FILE = etc/bitgen.ut
+
+XFLOW_OPT_FILE = etc/fast_runtime.opt
+XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)
+
+XPLORER_DEPENDENCY = __xps/xplorer.opt
+XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7
+
+FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY)
+
+SDK_EXPORT_DIR = SDK/SDK_Export/hw
+SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml
+SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit
+SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT)
Index: trunk/systems/test_system_sim/wb_irqs/system.mss
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/system.mss (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/system.mss (revision 2)
@@ -0,0 +1,24 @@
+
+
+
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = mb_plb
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = plb2wb_bridge_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_0
+END
+
+
Index: trunk/systems/test_system_sim/wb_irqs/system.xmp
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/system.xmp (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/system.xmp (revision 2)
@@ -0,0 +1,25 @@
+#Please do not modify this file by hand
+XmpVersion: 11.4
+VerMgmt: 11.4
+IntStyle: default
+ModuleSearchPath: ../../EDK_Libs/
+MHS File: system.mhs
+MSS File: system.mss
+Architecture: virtex5
+Device: xc5vlx50
+Package: ff676
+SpeedGrade: -1
+UserCmd1:
+UserCmd1Type: 0
+UserCmd2:
+UserCmd2Type: 0
+GenSimTB: 0
+SdkExportBmmBit: 1
+SdkExportDir: SDK/SDK_Export
+InsertNoPads: 0
+WarnForEAArch: 1
+HdlLang: VHDL
+SimModel: BEHAVIORAL
+UcfFile: data/system.ucf
+EnableParTimingError: 1
+ShowLicenseDialog: 1
Index: trunk/systems/test_system_sim/wb_irqs/data/system.ucf
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/data/system.ucf (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/data/system.ucf (revision 2)
@@ -0,0 +1,6 @@
+# Virtex 5 ML501 Evaluation Platform
+Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
+TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
+Net fpga_0_clk_1_sys_clk_pin LOC = AD8 | IOSTANDARD=LVCMOS33;
+Net fpga_0_rst_1_sys_rst_pin TIG;
+Net fpga_0_rst_1_sys_rst_pin LOC = T23 | IOSTANDARD=LVCMOS33 | PULLUP;
Index: trunk/systems/test_system_sim/wb_irqs/system.mhs
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/system.mhs (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/system.mhs (revision 2)
@@ -0,0 +1,116 @@
+
+# ##############################################################################
+# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
+# Fri Mar 5 18:02:26 2010
+# Target Board: Xilinx Virtex 5 ML501 Evaluation Platform Rev 1
+# Family: virtex5
+# Device: xc5vlx50
+# Package: ff676
+# Speed Grade: -1
+# Processor number: 1
+# Processor 1: microblaze_0
+# System clock frequency: 125.0
+# Debug Interface: On-Chip HW Debug Module
+# ##############################################################################
+ PARAMETER VERSION = 2.1.0
+
+
+ PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
+ PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
+ PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]
+ PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]
+ PORT wb_clk_pin = wb_clk, DIR = I, SIGIS = CLK
+ PORT wb_rst_pin = wb_rst, DIR = I, SIGIS = RST
+ PORT PLB2WB_IRQ_pin = PLB2WB_IRQ, DIR = O
+ PORT wb_pic_int_i_pin = wb_pic_int_i, DIR = I, VEC = [3:0]
+
+
+BEGIN plb_v46
+ PARAMETER INSTANCE = mb_plb
+ PARAMETER HW_VER = 1.04.a
+ PARAMETER C_EXT_RESET_HIGH = 1
+ PARAMETER C_DCR_INTFCE = 1
+ PARAMETER C_BASEADDR = 0b0000000000
+ PARAMETER C_HIGHADDR = 0b1111111111
+ PORT PLB_Clk = clk_100MHz
+ PORT SYS_Rst = sys_rst_s
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_32
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_SIZE = 0b10
+ PARAMETER PLB_MASTER_NUM = 0b0000
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_0
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_monitor_bfm
+ PARAMETER INSTANCE = plb_bfm_monitor
+ PARAMETER HW_VER = 1.00.a
+ BUS_INTERFACE MON_PLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_1
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN bfm_synch
+ PARAMETER INSTANCE = plb_bfm_synch
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_NUM_SYNCH = 2
+ PORT TO_SYNCH_IN = synch_out
+ PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_1
+END
+
+BEGIN plb2wb_bridge
+ PARAMETER INSTANCE = plb2wb_bridge_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_BASEADDR = 0xf0000000
+ PARAMETER C_HIGHADDR = 0xf7ffffff
+ PARAMETER WB_ADR_OFFSET = 0xf0000000
+ PARAMETER WB_ADR_OFFSET_NEG = 1
+ PARAMETER SYNCHRONY = false
+ PARAMETER C_STATUS_BASEADDR = 0x00010000
+ PARAMETER C_STATUS_HIGHADDR = 0x0001FFFF
+ PARAMETER WB_PIC_INTS = 4
+ BUS_INTERFACE SPLB = mb_plb
+ BUS_INTERFACE MWB = wb_conbus_0
+ PORT SPLB_Clk = clk_100MHz
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+ PORT PLB2WB_IRQ = PLB2WB_IRQ
+ PORT wb_pic_int_i = wb_pic_int_i
+END
+
+BEGIN wb_conbus
+ PARAMETER INSTANCE = wb_conbus_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER wb_s0_addr = 0x00
+ PARAMETER wb_s27_addr_w = 8
+ PARAMETER wb_s1_addr = 0x01
+ PARAMETER wb_s2_addr = 0x02
+ PARAMETER wb_s3_addr = 0x03
+ PARAMETER wb_s4_addr = 0x04
+ PARAMETER wb_s5_addr = 0x05
+ PARAMETER wb_s6_addr = 0x06
+ PARAMETER wb_s7_addr = 0x07
+ PARAMETER wb_s0_addr_w = 8
+ PARAMETER wb_s1_addr_w = 8
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 0
+ PARAMETER WR_DELAY = 0
+ PARAMETER WITH_ERR_OR_RTY = 0b10
+ PARAMETER ERR_RTY_INTERVAL = 5
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
Index: trunk/systems/test_system_sim/wb_irqs/etc/bitgen.ut
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/etc/bitgen.ut (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/etc/bitgen.ut (revision 2)
@@ -0,0 +1,14 @@
+-g TdoPin:PULLNONE
+-g DriveDone:No
+-g StartUpClk:JTAGCLK
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g TckPin:PULLUP
+-g TdiPin:PULLUP
+-g TmsPin:PULLUP
+-g DonePipe:No
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:NONE
+-g Persist:No
+
Index: trunk/systems/test_system_sim/wb_irqs/etc/fast_runtime.opt
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/etc/fast_runtime.opt (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/etc/fast_runtime.opt (revision 2)
@@ -0,0 +1,84 @@
+FLOWTYPE = FPGA;
+###############################################################
+## Filename: fast_runtime.opt
+##
+## Option File For Xilinx FPGA Implementation Flow for Fast
+## Runtime.
+##
+## Version: 4.1.1
+###############################################################
+#
+# Options for Translator
+#
+# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
+#
+Program ngdbuild
+-p ; # Partname to use - picked from xflow commandline
+-nt timestamp; # NGO File generation. Regenerate only when
+ # source netlist is newer than existing
+ # NGO file (default)
+-bm .bmm # Block RAM memory map file
+; # User design - pick from xflow command line
+-uc .ucf; # ucf constraints
+.ngd; # Name of NGD file. Filebase same as design filebase
+End Program ngdbuild
+
+#
+# Options for Mapper
+#
+# Type "map -h " for a detailed list of map command line options
+#
+Program map
+-o _map.ncd; # Output Mapped ncd file
+-w; # Overwrite output files.
+-pr b; # Pack internal FF/latches into IOBs
+#-fp .mfp; # Floorplan file
+-ol high;
+-timing;
+-detail;
+.ngd; # Input NGD file
+.pcf; # Physical constraints file
+END Program map
+
+#
+# Options for Post Map Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_map_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o _map.twr; # Output trace report file
+-xml _map.twx; # Output XML version of the timing report
+#-tsi _map.tsi; # Produce Timing Specification Interaction report
+_map.ncd; # Input mapped ncd
+.pcf; # Physical constraints file
+END Program post_map_trce
+
+#
+# Options for Place and Route
+#
+# Type "par -h" for a detailed list of par command line options
+#
+Program par
+-w; # Overwrite existing placed and routed ncd
+-ol high; # Overall effort level
+_map.ncd; # Input mapped NCD file
+.ncd; # Output placed and routed NCD
+.pcf; # Input physical constraints file
+END Program par
+
+#
+# Options for Post Par Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_par_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o .twr; # Output trace report file
+-xml .twx; # Output XML version of the timing report
+#-tsi .tsi; # Produce Timing Specification Interaction report
+.ncd; # Input placed and routed ncd
+.pcf; # Physical constraints file
+END Program post_par_trce
+
+
Index: trunk/systems/test_system_sim/wb_irqs/etc/download.cmd
===================================================================
--- trunk/systems/test_system_sim/wb_irqs/etc/download.cmd (nonexistent)
+++ trunk/systems/test_system_sim/wb_irqs/etc/download.cmd (revision 2)
@@ -0,0 +1,6 @@
+setMode -bscan
+setCable -p auto
+identify
+assignfile -p 4 -file implementation/download.bit
+program -p 4
+quit
Index: trunk/systems/test_system_sim/common/Makefile
===================================================================
--- trunk/systems/test_system_sim/common/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/common/Makefile (revision 2)
@@ -0,0 +1,143 @@
+WB_SRC=$(WISHBONE_LIB_DIR)/pcores/wb_conbus_v1_00_a/hdl/verilog/*.v
+TESTRAM_SRC=$(WISHBONE_LIB_DIR)/pcores/testram_v1_00_a/hdl/vhdl/testram.vhd
+PLB2WB_BRIDGE_SRC=$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/*.vhd
+
+
+PLB2WB_BRIDGE_TARGET=$(SIM_BIN_DIR)/plb2wb_bridge_*/plb2wb_bridge/_primary.dat
+TESTRAM_TARGET=$(SIM_BIN_DIR)/testram_*/testram/_primary.dat
+WB_TARGET=$(SIM_BIN_DIR)/wb_conbus_*/wb_conbus_*/_primary.dat
+
+
+
+
+VMAP_WIN= \
+ vmap -c; \
+ vmap unisim 'c:/Programme/CAEE/ISE_Lib/unisim/'; \
+ vmap bfm_synch_v1_00_a 'c:/Programme/CAEE/EDK_Lib/bfm_synch_v1_00_a/'; \
+ vmap plb_v46_v1_04_a 'c:/Programme/CAEE/EDK_Lib/plb_v46_v1_00_a/'; \
+ vmap plbv46_bfm 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_bfm/'; \
+ vmap plbv46_master_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_master_bfm_v1_00_a/'; \
+ vmap plbv46_monitor_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_monitor_bfm_v1_00_a/'; \
+ vmap plbv46_slave_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_slave_bfm_v1_00_a/'; \
+ vmap proc_common_v3_00_a 'c:/Programme/CAEE/EDK_Lib/edk/proc_common_v3_00_a/'; \
+ vlib work; \
+ vmap work work; \
+ vlib plb2wb_bridge_v1_00_a; \
+ vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;
+
+VMAP= \
+ vmap -c; \
+ vmap unisims_ver '/opt/Xilinx/11.1/compxlib/unisims_ver/'; \
+ vmap unisim '/opt/Xilinx/11.1/compxlib/unisim/'; \
+ vmap bfm_synch_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/bfm_synch_v1_00_a/'; \
+ vmap plb_v46_v1_04_a '/opt/Xilinx/11.1/compxlib/edk/plb_v46_v1_04_a/'; \
+ vmap plbv46_bfm '/opt/Xilinx/11.1/compxlib/edk/plbv46_bfm/'; \
+ vmap plbv46_master_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_master_bfm_v1_00_a/'; \
+ vmap plbv46_monitor_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_monitor_bfm_v1_00_a/'; \
+ vmap plbv46_slave_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_slave_bfm_v1_00_a/'; \
+ vmap proc_common_v3_00_a '/opt/Xilinx/11.1/compxlib/edk/proc_common_v3_00_a/'; \
+ vlib work; \
+ vmap work work; \
+ vlib plb2wb_bridge_v1_00_a; \
+ vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;
+
+
+
+
+
+###
+#
+# Generate the modelsim.ini file and working directory
+# after this, modelsim.ini contains the library mappings
+#
+$(SIM_BIN_DIR)/modelsim.ini:
+ @mkdir -p $(SIM_BIN_DIR)
+ @echo " "
+ @if [ "$(ENVIRONMENT)" = "cygwin" ]; then \
+ cd $(SIM_BIN_DIR); $(VMAP_WIN) \
+ else \
+ cd $(SIM_BIN_DIR); $(VMAP) \
+ fi
+ @echo " "
+ @echo " "
+
+
+
+
+
+
+###
+#
+# Compile testram
+#
+$(TESTRAM_TARGET): $(TESTRAM_SRC)
+ cd $(SIM_BIN_DIR); \
+ vlib testram_v1_00_a; \
+ vmap testram_v1_00_a testram_v1_00_a; \
+ vcom $(VHDL_CFLAGS) -work testram_v1_00_a $(WISHBONE_LIB_DIR)/pcores/testram_v1_00_a/hdl/vhdl/testram.vhd
+
+
+###
+#
+# Compile Wishbone-BUS
+#
+$(WB_TARGET): $(WB_SRC)
+ cd $(SIM_BIN_DIR); \
+ vlib wb_conbus_v1_00_a; \
+ vmap wb_conbus_v1_00_a wb_conbus_v1_00_a; \
+ vlog -novopt -93 -work wb_conbus_v1_00_a "$(WISHBONE_LIB_DIR)/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_arb.v" \
+ "$(WISHBONE_LIB_DIR)/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_top.v" \
+ "$(WISHBONE_LIB_DIR)/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_wrapper.v"
+
+
+
+###
+#
+# Compile PLB2WB-Bridge
+#
+$(PLB2WB_BRIDGE_TARGET): $(PLB2WB_BRIDGE_SRC)
+ echo "VHDL-Flags: $(VHDL_CFLAGS)"
+ cd $(SIM_BIN_DIR); \
+ vlib plb2wb_bridge_v1_00_a; \
+ vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;\
+ vcom $(VHDL_CFLAGS) -work plb2wb_bridge_v1_00_a \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_pkg.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_short_impulse.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_cc_4.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_ic_4.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_cc_3.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_ic_3.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_cc_2.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_ic_2.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_cc_1.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_ic_1.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_rdat_cc_32.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_rdat_ic_32.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_rdat.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_wdat_cc_32.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_wdat_ic_32.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_wdat.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_ic_4.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_cc_4.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_ic_3.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_cc_3.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_ic_2.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_cc_2.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_ic_1.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_cc_1.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2wb.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2wb_ic.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2wb_cc.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_fifo.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_stu.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_tcu.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_amu.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_rbuf.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_wbuf.vhd" \
+ "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_bridge.vhd"
+
+
+
+
Index: trunk/systems/test_system_sim/simple/simulation/testbench/system_tb.vhd
===================================================================
--- trunk/systems/test_system_sim/simple/simulation/testbench/system_tb.vhd (nonexistent)
+++ trunk/systems/test_system_sim/simple/simulation/testbench/system_tb.vhd (revision 2)
@@ -0,0 +1,146 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+entity system_tb is
+end system_tb;
+
+architecture STRUCTURE of system_tb is
+
+ constant sys_clk_period : time := 10.000000 ns;
+ constant wb_clk_period : time := 13.333333 ns;
+ constant sys_rst_length : time := 160 ns;
+
+ constant SYNCH_PART : integer := 1;
+ constant SYNCH_SUBPART : integer := 2;
+ constant SYNCH_SUBSUBPART : integer := 3;
+
+ constant SUBSUBPART_LENGTH : integer := 15; -- 10 clock cycles
+ constant SUBPART_LENGTH : integer := 5; -- 7 times SUBSUBPART_LENGTH
+ constant PART_LENGTH : integer := 5; -- 6 times SUBPART_LENGTH
+
+ component system is
+ port (
+ sys_clk_pin : in std_logic;
+ sys_rst_pin : in std_logic;
+ to_synch_in_pin : in std_logic_vector( 0 to 31 );
+ from_synch_out_pin : out std_logic_vector( 0 to 31 );
+ wb_clk_pin : in std_logic;
+ wb_rst_pin : in std_logic
+ );
+ end component;
+
+
+ signal sys_clk : std_logic;
+ signal sys_rst : std_logic := '1';
+ signal wb_clk : std_logic;
+ signal wb_rst : std_logic;
+
+
+ signal to_synch_in : std_logic_vector( 0 to 31 );
+ signal from_synch_out : std_logic_vector( 0 to 31 );
+ signal tb_synch_out : std_logic_vector( 0 to 31 ) := ( others => '0' );
+
+ procedure SendSynch( signal synch_out : OUT std_logic_vector;
+ COMMAND : integer ) is
+ begin
+ synch_out( COMMAND ) <= '1';
+ wait for sys_clk_period*1;
+ synch_out( COMMAND ) <= '0';
+ end procedure SendSynch;
+
+
+begin
+
+ to_synch_in <= from_synch_out or tb_synch_out;
+
+
+
+ dut : system
+ port map (
+ sys_clk_pin => sys_clk,
+ sys_rst_pin => sys_rst,
+ to_synch_in_pin => to_synch_in,
+ from_synch_out_pin => from_synch_out,
+ wb_clk_pin => wb_clk,
+ wb_rst_pin => wb_rst
+ );
+
+
+ --
+ -- generate plb-clk
+ --
+ process
+ begin
+ sys_clk <= '0';
+ loop
+ wait for (sys_clk_period/2);
+ sys_clk <= not sys_clk;
+ end loop;
+ end process;
+
+
+ --
+ --
+ --
+ process
+ begin
+ wb_clk <= '0';
+ loop
+ wait for (wb_clk_period/2);
+ wb_clk <= not wb_clk;
+ end loop;
+ end process;
+
+
+
+
+ process
+ begin
+ sys_rst <= '1';
+ wb_rst <= '1';
+ wait for ( sys_rst_length );
+ wb_rst <= not wb_rst;
+ sys_rst <= not sys_rst;
+ wait;
+ end process;
+
+
+ process
+ begin
+
+ wait until sys_rst = '0';
+ -- wait until masters a ready
+ wait for sys_clk_period * 10;
+
+
+ while true loop
+ for i in 0 to PART_LENGTH-1 loop
+ SendSynch( tb_synch_out, SYNCH_PART );
+
+ for j in 0 to SUBPART_LENGTH-1 loop
+ SendSynch( tb_synch_out, SYNCH_SUBPART );
+
+ for k in 0 to SUBSUBPART_LENGTH loop
+ SendSynch( tb_synch_out, SYNCH_SUBSUBPART );
+ wait for (SUBSUBPART_LENGTH * sys_clk_period );
+ end loop;
+
+
+ end loop;
+
+
+ end loop;
+
+ end loop;
+
+ end process;
+
+
+
+
+end architecture STRUCTURE;
+
Index: trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/wave.do
===================================================================
--- trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/wave.do (revision 2)
@@ -0,0 +1,54 @@
+
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+
+eval add wave -noupdate $binopt -label Clock -color SteelBlue /system_tb/sys_clk
+eval add wave -noupdate $binopt -label Reset -color SteelBlue /system_tb/sys_rst
+eval add wave -noupdate $hexopt -label synch_in -color Yellow /system_tb/dut/synch_in
+
+
+
+eval add wave -noupdate $binopt -label Mn_request -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_request
+
+eval add wave -noupdate $binopt -label Mn_RNW -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_rnw
+eval add wave -noupdate $binopt -label Mn_BE -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_be
+eval add wave -noupdate $binopt -label Mn_size -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_size
+eval add wave -noupdate $binopt -label Mn_type -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_type
+eval add wave -noupdate $hexopt -label Mn_ABus -color DarkGreen /system_tb/dut/mb_plb/mb_plb/m_abus
+eval add wave -noupdate $binopt -label PLB_PAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_pavalid
+eval add wave -noupdate $binopt -label PLB_SAValid -color DarkGreen /system_tb/dut/mb_plb/mb_plb/plb_savalid
+eval add wave -noupdate $binopt -label PLB_rdPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_rdprim
+eval add wave -noupdate $binopt -label PLB_wrPrim -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb_wrprim
+
+eval add wave -noupdate $hexopt -label Sl_rdDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddbus
+eval add wave -noupdate $binopt -label Sl_rdDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rddack
+eval add wave -noupdate $binopt -label Sl_rdComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_rdcomp
+
+
+eval add wave -noupdate $hexopt -label Sl_wrDBus -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/plb_wrdbus
+eval add wave -noupdate $binopt -label Sl_wrDAck -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrdack
+eval add wave -noupdate $binopt -label Sl_wrComp -color DarkGreen /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/sl_wrcomp
+
+
+eval add wave -noupdate $binopt -label WB_CLK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_clk_i
+eval add wave -noupdate $binopt -label WB_RST_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_rst_i
+eval add wave -noupdate $hexopt -label WB_ADR_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_adr_o
+eval add wave -noupdate $hexopt -label WB_DAT_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_o
+eval add wave -noupdate $hexopt -label WB_DAT_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_dat_i
+eval add wave -noupdate $binopt -label WB_ACK_I -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_ack_i
+eval add wave -noupdate $binopt -label WB_SEL_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_sel_o
+eval add wave -noupdate $binopt -label WB_STB_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_stb_o
+eval add wave -noupdate $binopt -label WB_LOCK_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_lock_o
+eval add wave -noupdate $binopt -label WB_WE_O -color Green /system_tb/dut/plb2wb_bridge_0/plb2wb_bridge_0/wb_we_o
+
+
+
+eval add wave -noupdate $binopt -label bram0_ack_o -color Orange /system_tb/dut/onchip_ram_0/wb_ack_o
+eval add wave -noupdate $binopt -label bram1_ack_o -color Orange /system_tb/dut/onchip_ram_1/wb_ack_o
+eval add wave -noupdate $binopt -label bram2_ack_o -color Orange /system_tb/dut/onchip_ram_2/wb_ack_o
+eval add wave -noupdate $binopt -label bram3_ack_o -color Orange /system_tb/dut/onchip_ram_3/wb_ack_o
+
+
+configure wave -gridperiod 1
+configure wave -namecolwidth 200
Index: trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/transcript
===================================================================
--- trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/transcript (nonexistent)
+++ trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/transcript (revision 2)
@@ -0,0 +1,19 @@
+# // ModelSim SE 6.6 Jan 5 2010 Linux 2.6.34-gentoo-r2
+# //
+# // Copyright 1991-2010 Mentor Graphics Corporation
+# // All Rights Reserved.
+# //
+# // THIS WORK CONTAINS TRADE SECRET AND
+# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
+# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
+# // AND IS SUBJECT TO LICENSE TERMS.
+# //
+# vsim -view result/wave.wlf
+# vsim -view result/wave.wlf
+# Updating msgviewer database...
+# result/wave.wlf opened as dataset "wave"
+# view wave
+# .main_pane.wave.interior.cs.body.pw.wf
+# do wave.do
+# -logic
+# -literal -hex
Index: trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/sim.do
===================================================================
--- trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 80000 ns
+
+
Index: trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/transfers.bfl (revision 2)
@@ -0,0 +1,247 @@
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+
+ mem_update(addr=f0000000,data=11223344_22223344_33223344_44223344)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f0000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f0000030,data=01333311_02333311_03333311_04333311)
+ mem_update(addr=f1000000,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000010,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000020,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000030,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f2000000,data=11abcdef_22abcdef_33abcdef_44abcdef)
+ mem_update(addr=f3000000,data=11222222_22222222_33222222_44222222)
+ mem_update(addr=f3000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f3000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f3000030,data=01333311_02333311_03333311_04333311)
+
+ wait( level=SUBPART )
+
+
+
+ write ( addr=f0000000, size=0000, be=1111 )
+ write ( addr=f1000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f3000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f3000000, size=0000, be=1111 )
+ write ( addr=f1000000, size=0000, be=1111 )
+ write ( addr=f0000000, size=0000, be=1111 )
+ write ( addr=f1000000, size=0000, be=1111 )
+
+
+
+ -- this causes several address-pipelining situations
+ read ( addr=f1000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f1000000, size=0000, be=1111 )
+ read ( addr=f1000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f1000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+
+
+ wait( level = SUBSUBPART )
+ wait( level = SUBSUBPART )
+ wait( level = SUBSUBPART )
+
+ write ( addr=f0000000, size=0000, be=1111 )
+ read ( addr=f0000000, size=0000, be=1111 )
+ write ( addr=f1000000, size=0000, be=1111 )
+ read ( addr=f1000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f3000000, size=0000, be=1111 )
+ read ( addr=f3000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f3000000, size=0000, be=1111 )
+ read ( addr=f3000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ write ( addr=f2000000, size=0000, be=1111 )
+
+
+
+
+
+ ---------------------------------
+ -- 64-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_64/plb_bfm_master_64/master,device_type=plb_master)
+ configure(msize=01)
+
+
+ mem_update(addr=f0000000,data=11223344_22223344_33223344_44223344)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f0000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f0000030,data=01333311_02333311_03333311_04333311)
+ mem_update(addr=f1000000,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000010,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000020,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000030,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f2000000,data=11abcdef_22abcdef_33abcdef_44abcdef)
+ mem_update(addr=f3000000,data=11222222_22222222_33222222_44222222)
+ mem_update(addr=f3000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f3000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f3000030,data=01333311_02333311_03333311_04333311)
+
+ wait( level=PART )
+ wait( level=PART )
+
+
+
+
+
+ write ( addr=f0000000, size=0000, be=11111111 )
+ write ( addr=f1000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f3000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f3000000, size=0000, be=11111111 )
+ write ( addr=f1000000, size=0000, be=11111111 )
+ write ( addr=f0000000, size=0000, be=11111111 )
+ write ( addr=f1000000, size=0000, be=11111111 )
+
+
+
+ -- this causes several address-pipelining situations
+ read ( addr=f1000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f1000000, size=0000, be=11111111 )
+ read ( addr=f1000000, size=0000, be=11111111 )
+ read ( addr=f3000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f1000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+
+
+ wait( level = SUBSUBPART )
+ wait( level = SUBSUBPART )
+ wait( level = SUBSUBPART )
+
+ write ( addr=f0000000, size=0000, be=11111111 )
+ read ( addr=f0000000, size=0000, be=11111111 )
+ write ( addr=f1000000, size=0000, be=11111111 )
+ read ( addr=f1000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f3000000, size=0000, be=11111111 )
+ read ( addr=f3000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f3000000, size=0000, be=11111111 )
+ read ( addr=f3000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ read ( addr=f2000000, size=0000, be=11111111 )
+ write ( addr=f2000000, size=0000, be=11111111 )
+
+
+
+
+
+
+ ---------------------------------
+ -- 128-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_128/plb_bfm_master_128/master,device_type=plb_master)
+ configure(msize=10)
+
+
+
+
+ mem_update(addr=f0000000,data=11223344_22223344_33223344_44223344)
+ mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f0000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f0000030,data=01333311_02333311_03333311_04333311)
+ mem_update(addr=f1000000,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000010,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000020,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f1000030,data=11eeffee_22eeffee_33eeffee_44eeffee)
+ mem_update(addr=f2000000,data=11abcdef_22abcdef_33abcdef_44abcdef)
+ mem_update(addr=f3000000,data=11222222_22222222_33222222_44222222)
+ mem_update(addr=f3000010,data=01111111_02111111_03111111_04111111)
+ mem_update(addr=f3000020,data=01222211_02222211_03222211_04222211)
+ mem_update(addr=f3000030,data=01333311_02333311_03333311_04333311)
+
+ wait( level=PART )
+ wait( level=PART )
+ wait( level=PART )
+ wait( level=PART )
+
+
+
+ write ( addr=f0000000, size=0000, be=1111111111111111 )
+ write ( addr=f1000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f3000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f3000000, size=0000, be=1111111111111111 )
+ write ( addr=f1000000, size=0000, be=1111111111111111 )
+ write ( addr=f0000000, size=0000, be=1111111111111111 )
+
+
+
+ -- this causes several address-pipelining situations
+ read ( addr=f1000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f1000000, size=0000, be=1111111111111111 )
+ read ( addr=f1000000, size=0000, be=1111111111111111 )
+ read ( addr=f3000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f1000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+
+
+ wait( level = SUBSUBPART )
+
+ write ( addr=f0000000, size=0000, be=1111111111111111 )
+ read ( addr=f0000000, size=0000, be=1111111111111111 )
+ write ( addr=f1000000, size=0000, be=1111111111111111 )
+ read ( addr=f1000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f3000000, size=0000, be=1111111111111111 )
+ read ( addr=f3000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f3000000, size=0000, be=1111111111111111 )
+ read ( addr=f3000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ read ( addr=f2000000, size=0000, be=1111111111111111 )
+ write ( addr=f2000000, size=0000, be=1111111111111111 )
+
+
+
+
Index: trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/Makefile
===================================================================
--- trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/simple/simulation/test_cases/stressful_read_write/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/simple/simulation/Makefile
===================================================================
--- trunk/systems/test_system_sim/simple/simulation/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/simple/simulation/Makefile (revision 2)
@@ -0,0 +1,113 @@
+SIM_DIR=$(shell pwd)
+
+XPS_PROJ_DIR=$(SIM_DIR)/..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+COMMON_DIR=$(SIM_DIR)/../../common
+LOG_DIR=$(SIM_DIR)/log
+PLB_BFM_SETUP_DIR=$(SIM_DIR)/../../plb_bfm_setup
+
+
+include $(COMMON_DIR)/Makefile
+
+
+
+all: sim
+
+
+TEST_CASES += test_cases/simple_read_write
+
+WORK_TARGET=$(SIM_BIN_DIR)/work/system/_primary.dat
+
+
+
+###
+#
+# note: WORK_TARGET is defined some lines above, the rest in ../../common/Makefile
+#
+COMPILE_COMPONENTS=$(TESTRAM_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET) $(PLB_BFM_TARGET) $(WORK_TARGET)
+
+
+
+#
+# Generate Simulation HDL Files
+# (This is the same than XPS-Gui->Simulation->Generate Simulation HDL Files)
+#
+$(SIM_DIR)/behavioral: $(XPS_PROJ_DIR)/system.mhs
+ @mkdir -p $(LOG_DIR)
+ simgen $(XPS_PROJ_DIR)/system.mhs -lang vhdl \
+ -p virtex5 \
+ -m beh \
+ -od $(XPS_PROJ_DIR)/ \
+ -s mti \
+ -lp $(LIB_DIR) \
+ -log $(LOG_DIR)/simgen
+ @mv simgen.opt log # there is no simgen-flag for this!
+
+
+
+
+
+# PLB_BFM_TARGET=$(SIM_BIN_DIR)/plbv46_bfm/system/_primary.dat
+# #BFM_SOURCE=$() TODO
+# $(PLB_BFM_TARGET):
+# cd $(SIM_BIN_DIR); \
+# vlib plbv46_bfm; \
+# vmap plbv46_bfm plbv46_bfm; \
+# vlib plbv46_master_bfm_v1_00_a; \
+# vmap plbv46_master_bfm_v1_00_a plbv46_master_bfm_v1_00_a; \
+# vlib plbv46_monitor_bfm_v1_00_a; \
+# vmap plbv46_monitor_bfm_v1_00_a plbv46_monitor_bfm_v1_00_a; \
+# vlib plbv46_slave_bfm_v1_00_a; \
+# vmap plbv46_slave_bfm_v1_00_a plbv46_slave_bfm_v1_00_a; \
+# vcom $(VHDL_CFLAGS) -work plbv46_bfm \
+# "$(PLB_BFM_SETUP_DIR)/plb_dcl_128.vhd"; \
+# vcom $(VHDL_CFLAGS) -work plbv46_master_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_master_bfm_v1_00_a/hdl/vhdl/plbv46_master_bfm.vhd" ; \
+# vcom $(VHDL_CFLAGS) -work plbv46_monitor_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_monitor_bfm_v1_00_a/hdl/vhdl/plbv46_monitor_bfm.vhd";\
+# vcom $(VHDL_CFLAGS) -work plbv46_slave_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_slave_bfm_v1_00_a/hdl/vhdl/plbv46_slave_bfm.vhd";
+
+
+
+
+
+$(WORK_TARGET): $(SIM_DIR)/behavioral $(SIM_BIN_DIR)/../testbench/system_tb.vhd
+ cd $(SIM_BIN_DIR); \
+ vlib work; \
+ vmap work work; \
+ vlog -novopt -93 -work work "../behavioral/wb_conbus_0_wrapper.v"; \
+ vcom $(VHDL_CFLAGS) -work work \
+ "../behavioral/onchip_ram_0_wrapper.vhd" \
+ "../behavioral/onchip_ram_1_wrapper.vhd" \
+ "../behavioral/onchip_ram_2_wrapper.vhd" \
+ "../behavioral/onchip_ram_3_wrapper.vhd" \
+ "../behavioral/mb_plb_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_32_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_64_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_128_wrapper.vhd" \
+ "../behavioral/plb_bfm_monitor_wrapper.vhd" \
+ "../behavioral/plb_bfm_slave_wrapper.vhd" \
+ "../behavioral/plb_bfm_synch_wrapper.vhd" \
+ "../behavioral/plb2wb_bridge_0_wrapper.vhd" \
+ "../behavioral/system.vhd" \
+ "../testbench/system_tb.vhd"
+
+
+
+
+
+
+compile: $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS)
+
+
+
+
+
+
+clean:
+ rm -rf \
+ $(SIM_DIR)/behavioral \
+ $(SIM_BIN_DIR) \
+ $(LOG_DIR)
+
Index: trunk/systems/test_system_sim/simple/system.mss
===================================================================
--- trunk/systems/test_system_sim/simple/system.mss (nonexistent)
+++ trunk/systems/test_system_sim/simple/system.mss (revision 2)
@@ -0,0 +1,43 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = plb_bfm_slave
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = plb2wb_bridge_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_3
+END
+
+
Index: trunk/systems/test_system_sim/simple/system.xmp
===================================================================
--- trunk/systems/test_system_sim/simple/system.xmp (nonexistent)
+++ trunk/systems/test_system_sim/simple/system.xmp (revision 2)
@@ -0,0 +1,25 @@
+#Please do not modify this file by hand
+XmpVersion: 11.4
+VerMgmt: 11.4
+IntStyle: default
+ModuleSearchPath: ../../EDK_Libs/
+MHS File: system.mhs
+MSS File: system.mss
+Architecture: virtex5
+Device: xc5vlx50
+Package: ff676
+SpeedGrade: -1
+UserCmd1:
+UserCmd1Type: 0
+UserCmd2:
+UserCmd2Type: 0
+GenSimTB: 0
+SdkExportBmmBit: 1
+SdkExportDir: SDK/SDK_Export
+InsertNoPads: 0
+WarnForEAArch: 1
+HdlLang: VHDL
+SimModel: BEHAVIORAL
+UcfFile: data/system.ucf
+EnableParTimingError: 1
+ShowLicenseDialog: 1
Index: trunk/systems/test_system_sim/simple/data/system.ucf
===================================================================
--- trunk/systems/test_system_sim/simple/data/system.ucf (nonexistent)
+++ trunk/systems/test_system_sim/simple/data/system.ucf (revision 2)
@@ -0,0 +1,6 @@
+# Virtex 5 ML501 Evaluation Platform
+Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
+TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
+Net fpga_0_clk_1_sys_clk_pin LOC = AD8 | IOSTANDARD=LVCMOS33;
+Net fpga_0_rst_1_sys_rst_pin TIG;
+Net fpga_0_rst_1_sys_rst_pin LOC = T23 | IOSTANDARD=LVCMOS33 | PULLUP;
Index: trunk/systems/test_system_sim/simple/system.mhs
===================================================================
--- trunk/systems/test_system_sim/simple/system.mhs (nonexistent)
+++ trunk/systems/test_system_sim/simple/system.mhs (revision 2)
@@ -0,0 +1,177 @@
+
+# ##############################################################################
+# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
+# Fri Mar 5 18:02:26 2010
+# Target Board: Xilinx Virtex 5 ML501 Evaluation Platform Rev 1
+# Family: virtex5
+# Device: xc5vlx50
+# Package: ff676
+# Speed Grade: -1
+# Processor number: 1
+# Processor 1: microblaze_0
+# System clock frequency: 125.0
+# Debug Interface: On-Chip HW Debug Module
+# ##############################################################################
+ PARAMETER VERSION = 2.1.0
+
+
+ PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
+ PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
+ PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]
+ PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]
+ PORT wb_clk_pin = wb_clk, DIR = I, SIGIS = CLK
+ PORT wb_rst_pin = wb_rst, DIR = I, SIGIS = RST
+
+
+BEGIN plb_v46
+ PARAMETER INSTANCE = mb_plb
+ PARAMETER HW_VER = 1.04.a
+ PARAMETER C_EXT_RESET_HIGH = 1
+ PARAMETER C_DCR_INTFCE = 1
+ PARAMETER C_BASEADDR = 0b0000000000
+ PARAMETER C_HIGHADDR = 0b1111111111
+ PORT PLB_Clk = clk_100MHz
+ PORT SYS_Rst = sys_rst_s
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_32
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_SIZE = 0b10
+ PARAMETER PLB_MASTER_NUM = 0b0000
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_0
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_64
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ PARAMETER PLB_MASTER_SIZE = 0b10
+ PARAMETER PLB_MASTER_NUM = 0b0001
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_1
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_128
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ PARAMETER PLB_MASTER_NUM = 0b0010
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_2
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_monitor_bfm
+ PARAMETER INSTANCE = plb_bfm_monitor
+ PARAMETER HW_VER = 1.00.a
+ BUS_INTERFACE MON_PLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_3
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_slave_bfm
+ PARAMETER INSTANCE = plb_bfm_slave
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_SLAVE_ADDR_LO_0 = 0xF8000000
+ PARAMETER PLB_SLAVE_ADDR_HI_0 = 0xFFFFfFFF
+ PARAMETER C_SPLB_NATIVE_DWIDTH = 32
+ PARAMETER PLB_SLAVE_SIZE = 0b00
+ BUS_INTERFACE SPLB = mb_plb
+ PORT SYNCH_IN = synch_in
+ PORT SYNCH_OUT = bfm_synch_out_4
+END
+
+BEGIN bfm_synch
+ PARAMETER INSTANCE = plb_bfm_synch
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_NUM_SYNCH = 5
+ PORT TO_SYNCH_IN = synch_out
+ PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_1 & bfm_synch_out_2 & bfm_synch_out_3 & bfm_synch_out_4
+END
+
+BEGIN plb2wb_bridge
+ PARAMETER INSTANCE = plb2wb_bridge_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_BASEADDR = 0xf0000000
+ PARAMETER C_HIGHADDR = 0xf7ffffff
+ PARAMETER WB_ADR_OFFSET = 0xf0000000
+ PARAMETER WB_ADR_OFFSET_NEG = 1
+ PARAMETER SYNCHRONY = false
+ PARAMETER WB_PIC_INTS = 1
+ PARAMETER WB_SUPPORT_BLOCK = 0
+ PARAMETER C_SPLB_SUPPORT_BUR_LINE = 0
+ PARAMETER C_SPLB_SUPPORT_ADR_PIPE = 0
+ BUS_INTERFACE SPLB = mb_plb
+ BUS_INTERFACE MWB = wb_conbus_0
+ PORT SPLB_Clk = clk_100MHz
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+ PORT wb_pic_int_i = net_gnd
+END
+
+BEGIN wb_conbus
+ PARAMETER INSTANCE = wb_conbus_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER wb_s0_addr = 0x00
+ PARAMETER wb_s27_addr_w = 8
+ PARAMETER wb_s1_addr = 0x01
+ PARAMETER wb_s2_addr = 0x02
+ PARAMETER wb_s3_addr = 0x03
+ PARAMETER wb_s4_addr = 0x04
+ PARAMETER wb_s5_addr = 0x05
+ PARAMETER wb_s6_addr = 0x06
+ PARAMETER wb_s7_addr = 0x07
+ PARAMETER wb_s0_addr_w = 8
+ PARAMETER wb_s1_addr_w = 8
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 0
+ PARAMETER WR_DELAY = 0
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_1
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 1
+ PARAMETER WR_DELAY = 1
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_2
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 3
+ PARAMETER WR_DELAY = 3
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_3
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 5
+ PARAMETER WR_DELAY = 5
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
Index: trunk/systems/test_system_sim/simple/etc/bitgen.ut
===================================================================
--- trunk/systems/test_system_sim/simple/etc/bitgen.ut (nonexistent)
+++ trunk/systems/test_system_sim/simple/etc/bitgen.ut (revision 2)
@@ -0,0 +1,14 @@
+-g TdoPin:PULLNONE
+-g DriveDone:No
+-g StartUpClk:JTAGCLK
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g TckPin:PULLUP
+-g TdiPin:PULLUP
+-g TmsPin:PULLUP
+-g DonePipe:No
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:NONE
+-g Persist:No
+
Index: trunk/systems/test_system_sim/simple/etc/fast_runtime.opt
===================================================================
--- trunk/systems/test_system_sim/simple/etc/fast_runtime.opt (nonexistent)
+++ trunk/systems/test_system_sim/simple/etc/fast_runtime.opt (revision 2)
@@ -0,0 +1,84 @@
+FLOWTYPE = FPGA;
+###############################################################
+## Filename: fast_runtime.opt
+##
+## Option File For Xilinx FPGA Implementation Flow for Fast
+## Runtime.
+##
+## Version: 4.1.1
+###############################################################
+#
+# Options for Translator
+#
+# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
+#
+Program ngdbuild
+-p ; # Partname to use - picked from xflow commandline
+-nt timestamp; # NGO File generation. Regenerate only when
+ # source netlist is newer than existing
+ # NGO file (default)
+-bm .bmm # Block RAM memory map file
+; # User design - pick from xflow command line
+-uc .ucf; # ucf constraints
+.ngd; # Name of NGD file. Filebase same as design filebase
+End Program ngdbuild
+
+#
+# Options for Mapper
+#
+# Type "map -h " for a detailed list of map command line options
+#
+Program map
+-o _map.ncd; # Output Mapped ncd file
+-w; # Overwrite output files.
+-pr b; # Pack internal FF/latches into IOBs
+#-fp .mfp; # Floorplan file
+-ol high;
+-timing;
+-detail;
+.ngd; # Input NGD file
+.pcf; # Physical constraints file
+END Program map
+
+#
+# Options for Post Map Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_map_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o _map.twr; # Output trace report file
+-xml _map.twx; # Output XML version of the timing report
+#-tsi _map.tsi; # Produce Timing Specification Interaction report
+_map.ncd; # Input mapped ncd
+.pcf; # Physical constraints file
+END Program post_map_trce
+
+#
+# Options for Place and Route
+#
+# Type "par -h" for a detailed list of par command line options
+#
+Program par
+-w; # Overwrite existing placed and routed ncd
+-ol high; # Overall effort level
+_map.ncd; # Input mapped NCD file
+.ncd; # Output placed and routed NCD
+.pcf; # Input physical constraints file
+END Program par
+
+#
+# Options for Post Par Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_par_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o .twr; # Output trace report file
+-xml .twx; # Output XML version of the timing report
+#-tsi .tsi; # Produce Timing Specification Interaction report
+.ncd; # Input placed and routed ncd
+.pcf; # Physical constraints file
+END Program post_par_trce
+
+
Index: trunk/systems/test_system_sim/simple/etc/download.cmd
===================================================================
--- trunk/systems/test_system_sim/simple/etc/download.cmd (nonexistent)
+++ trunk/systems/test_system_sim/simple/etc/download.cmd (revision 2)
@@ -0,0 +1,6 @@
+setMode -bscan
+setCable -p auto
+identify
+assignfile -p 4 -file implementation/download.bit
+program -p 4
+quit
Index: trunk/systems/test_system_sim/wb_err_and_rst/simulation/testbench/system_tb.vhd
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/simulation/testbench/system_tb.vhd (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/simulation/testbench/system_tb.vhd (revision 2)
@@ -0,0 +1,159 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+entity system_tb is
+end system_tb;
+
+architecture STRUCTURE of system_tb is
+
+ constant sys_clk_period : time := 10.000000 ns;
+ constant wb_clk_period : time := 13.333333 ns;
+ constant sys_rst_length : time := 160 ns;
+
+ constant SYNCH_PART : integer := 1;
+ constant SYNCH_SUBPART : integer := 2;
+ constant SYNCH_SUBSUBPART : integer := 3;
+
+ constant SUBSUBPART_LENGTH : integer := 15; -- 10 clock cycles
+ constant SUBPART_LENGTH : integer := 5; -- 7 times SUBSUBPART_LENGTH
+ constant PART_LENGTH : integer := 5; -- 6 times SUBPART_LENGTH
+
+ component system is
+ port (
+ sys_clk_pin : in std_logic;
+ sys_rst_pin : in std_logic;
+ to_synch_in_pin : in std_logic_vector( 0 to 31 );
+ from_synch_out_pin : out std_logic_vector( 0 to 31 );
+ wb_clk_pin : in std_logic;
+ wb_rst_pin : in std_logic
+ );
+ end component;
+
+
+ signal sys_clk : std_logic;
+ signal sys_rst : std_logic := '1';
+ signal wb_clk : std_logic;
+ signal wb_rst : std_logic;
+
+
+ signal to_synch_in : std_logic_vector( 0 to 31 );
+ signal from_synch_out : std_logic_vector( 0 to 31 );
+ signal tb_synch_out : std_logic_vector( 0 to 31 ) := ( others => '0' );
+
+ procedure SendSynch( signal synch_out : OUT std_logic_vector;
+ COMMAND : integer ) is
+ begin
+ synch_out( COMMAND ) <= '1';
+ wait for sys_clk_period*1;
+ synch_out( COMMAND ) <= '0';
+ end procedure SendSynch;
+
+
+begin
+
+ to_synch_in <= from_synch_out or tb_synch_out;
+
+
+
+ dut : system
+ port map (
+ sys_clk_pin => sys_clk,
+ sys_rst_pin => sys_rst,
+ to_synch_in_pin => to_synch_in,
+ from_synch_out_pin => from_synch_out,
+ wb_clk_pin => wb_clk,
+ wb_rst_pin => wb_rst
+ );
+
+
+ --
+ -- generate plb-clk
+ --
+ process
+ begin
+ sys_clk <= '0';
+ loop
+ wait for (sys_clk_period/2);
+ sys_clk <= not sys_clk;
+ end loop;
+ end process;
+
+
+ --
+ --
+ --
+ process
+ begin
+ wb_clk <= '0';
+ loop
+ wait for (wb_clk_period/2);
+ wb_clk <= not wb_clk;
+ end loop;
+ end process;
+
+
+
+
+ process
+ begin
+ sys_rst <= '1';
+ wait for ( sys_rst_length );
+ sys_rst <= not sys_rst;
+ wait;
+ end process;
+
+
+ process
+ begin
+ wb_rst <= '1';
+ wait for ( sys_rst_length );
+ wb_rst <= '0';
+
+ wait for 7500 ns;
+ wb_rst <= '1';
+ wait for wb_clk_period;
+ wb_rst <= '0';
+ wait;
+ end process;
+
+
+
+ process
+ begin
+
+ wait until sys_rst = '0';
+ -- wait until masters a ready
+ wait for sys_clk_period * 10;
+
+
+ while true loop
+ for i in 0 to PART_LENGTH-1 loop
+ SendSynch( tb_synch_out, SYNCH_PART );
+
+ for j in 0 to SUBPART_LENGTH-1 loop
+ SendSynch( tb_synch_out, SYNCH_SUBPART );
+
+ for k in 0 to SUBSUBPART_LENGTH loop
+ SendSynch( tb_synch_out, SYNCH_SUBSUBPART );
+ wait for (SUBSUBPART_LENGTH * sys_clk_period );
+ end loop;
+
+
+ end loop;
+
+
+ end loop;
+
+ end loop;
+
+ end process;
+
+
+
+
+end architecture STRUCTURE;
+
Index: trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/wave.do
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/wave.do (revision 2)
@@ -0,0 +1,265 @@
+
+#
+# Display top-level ports
+#
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+set tbpath {/system_tb/dut}
+
+eval add wave -color DarkGreen -noupdate -divider {"top-level ports"}
+eval add wave -color DarkGreen -noupdate $binopt /system_tb/sys_clk
+eval add wave -color DarkGreen -noupdate $binopt /system_tb/sys_rst
+eval add wave -color DarkGreen -noupdate $binopt /system_tb/wb_rst
+eval add wave -color DarkGreen -noupdate $binopt /system_tb/dut/plb_bfm_slave/synch_in
+
+
+# eval do ../../behavioral/mb_plb_wave.do
+# eval do ../../behavioral/plb_bfm_monitor_wave.do
+
+
+ # Master signals
+ proc add_master { num color } {
+ global binopt hexopt tbpath
+ eval add wave -color ${color} -noupdate -group Master_${num}
+ eval add wave -color ${color} -label ${num}_m_request -group Master_${num} -noupdate $binopt $tbpath/plb_bfm_master_${num}/m_request
+ eval add wave -color ${color} -label ${num}_m_abus -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_abus
+ eval add wave -color ${color} -label ${num}_m_be -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_be
+ eval add wave -color ${color} -label ${num}_m_rnw -group Master_${num} -noupdate $binopt $tbpath/plb_bfm_master_${num}/m_rnw
+ eval add wave -color ${color} -label ${num}_m_size -group Master_${num} -noupdate $binopt $tbpath/plb_bfm_master_${num}/m_size
+ eval add wave -color ${color} -label ${num}_m_priority -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_priority
+ eval add wave -color ${color} -label ${num}_plb_mrddbus -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/plb_mrddbus
+ eval add wave -color ${color} -label ${num}_m_wrdbus -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_wrdbus
+ }
+ add_master 32 White
+ add_master 64 AliceBlue
+ add_master 128 Seashell
+
+
+
+-- do ../behavioral/mb_plb_wave.do
+
+ proc add_ocram { num color } {
+ global binopt hexopt tbpath
+ eval add wave -color ${color} -noupdate -group ocram${num}
+ eval add wave -color ${color} -label wb_stb_i -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_stb_i
+ eval add wave -color ${color} -label wb_stb_i -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_stb_i
+ eval add wave -color ${color} -label wb_ack_o -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_ack_o
+ eval add wave -color ${color} -label wb_err_o -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_err_o
+ eval add wave -color ${color} -label wb_rty_o -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_rty_o
+ eval add wave -color ${color} -label w_ack -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/w_ack
+ eval add wave -color ${color} -label err_rty_count_r -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/err_rty_count_r
+ eval add wave -color ${color} -label err_rty_count_w -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/err_rty_count_w
+ eval add wave -color ${color} -label r_delay_count -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/r_delay_count
+ eval add wave -color ${color} -label w_delay_count -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/w_delay_count
+
+ eval add wave -color ${color} -label ram(0) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(0)
+ eval add wave -color ${color} -label ram(1) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(1)
+ eval add wave -color ${color} -label ram(2) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(2)
+ eval add wave -color ${color} -label ram(3) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(3)
+ eval add wave -color ${color} -label ram(4) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(4)
+ eval add wave -color ${color} -label ram(5) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(5)
+ eval add wave -color ${color} -label ram(6) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(6)
+ eval add wave -color ${color} -label ram(7) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(7)
+ }
+
+
+
+
+ #
+ # General bridge signals
+ #
+ eval add wave -color purple -group bridge_general -noupdate
+ eval add wave -color purple -label sl_addrack -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_addrack
+ eval add wave -color purple -label plb_abus -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb_abus
+ eval add wave -color purple -label plb_be -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb_be
+ eval add wave -color purple -label plb_pavalid -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_pavalid
+ eval add wave -color purple -label plb_savalid -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_savalid
+ eval add wave -color purple -label plb_rnw -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_rnw
+ eval add wave -color purple -label plb_msize -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_msize
+ eval add wave -color purple -label plb_type -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_type
+ eval add wave -color purple -label plb_wrdbus -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb_wrdbus
+ eval add wave -color purple -label sl_rddbus -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/sl_rddbus
+
+ eval add wave -color purple -label sl_wrdack -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_wrdack
+ eval add wave -color maroon -label sl_wrcomp -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_wrcomp
+ eval add wave -color purple -label sl_rddack -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_rddack
+ eval add wave -color maroon -label sl_rdcomp -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_rdcomp
+
+ eval add wave -color maroon -label sl_rdprim -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_rdprim
+ eval add wave -color maroon -label sl_wrprim -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_wrprim
+
+
+ eval add wave -color maroon -label wb_adr_o -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_adr_o
+ eval add wave -color maroon -label wb_cyc_o -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_cyc_o
+ eval add wave -color maroon -label wb_dat_i -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_dat_i
+ eval add wave -color maroon -label wb_dat_o -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_dat_o
+ eval add wave -color maroon -label wb_err_i -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_err_i
+ eval add wave -color maroon -label wb_rst_i -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_rst_i
+ eval add wave -color maroon -label wb_sel_o -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_sel_o
+ eval add wave -color maroon -label wb_stb_o -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_stb_o
+ eval add wave -color maroon -label wb_we_o -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_we_o
+ eval add wave -color maroon -label sl_mbusy -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mbusy
+ eval add wave -color maroon -label sl_mwrerr -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mwrerr
+ eval add wave -color maroon -label sl_mrderr -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mrderr
+
+ eval add wave -color maroon -label sl_mirq -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mirq
+ #
+ # Bridge - Transfer Control Unit
+ #
+ eval add wave -color aquamarine -group bridge_TCU -noupdate
+ eval add wave -color aquamarine -label c_plb_wstate -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/c_plb_wstate
+ eval add wave -color aquamarine -label c_plb_rstate -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/c_plb_rstate
+ eval add wave -color aquamarine -label c_wb_state -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/c_wb_state
+ eval add wave -color aquamarine -label wb_ack -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_ack
+ eval add wave -color aquamarine -label wb_err -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_err
+ eval add wave -color aquamarine -label wb_rty -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_rty
+
+ eval add wave -color aquamarine -label tcu_addrack -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_addrack
+ eval add wave -color aquamarine -label sl_rdwdaddr -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/sl_rdwdaddr
+
+ eval add wave -color aquamarine -label tcu_adr_offset -group bridge_TCU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_adr_offset
+ eval add wave -color aquamarine -label tcu_adrbufren -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_adrbufren
+ eval add wave -color aquamarine -label tcu_adrbufwen -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_adrbufwen
+ eval add wave -color aquamarine -label tcu_rpiperden -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_rpiperden
+ eval add wave -color aquamarine -label tcu_wpiperden -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_wpiperden
+
+ eval add wave -color aquamarine -label tcu_enrddbus -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_enrddbus
+ eval add wave -color aquamarine -label tcu_rbufren -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_rbufren
+ eval add wave -color aquamarine -label tcu_rbufwen -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_rbufwen
+ eval add wave -color aquamarine -label tcu_wbufren -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_wbufren
+ eval add wave -color aquamarine -label tcu_wbufwen -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_wbufwen
+
+ eval add wave -color aquamarine -label tcu_enStuRDDbus -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_ensturddbus
+ eval add wave -color aquamarine -label tcu_stuWritePA -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_stuwritepa
+ eval add wave -color aquamarine -label tcu_stuWriteSA -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_stuwritesa
+ eval add wave -color aquamarine -label tcu_stat2plb_en -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_stat2plb_en
+ eval add wave -color aquamarine -label tcu_wb_status_info -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/tcu_wb_status_info
+
+ eval add wave -color aquamarine -label tcu_mrbusy -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_mrbusy
+ eval add wave -color aquamarine -label mbusy_read_out -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/mbusy_read_out
+ eval add wave -color aquamarine -label mbusy_write_out -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/mbusy_write_out
+ eval add wave -color aquamarine -label SL_MWrErr -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/SL_MWrErr
+ eval add wave -color aquamarine -label SL_MRdErr -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/SL_MRdErr
+ eval add wave -color aquamarine -label sl_wrbterm -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/sl_wrbterm
+ eval add wave -color aquamarine -label sl_rdbterm -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/sl_rdbterm
+
+
+
+ #
+ # Bridge - Status Unit
+ #
+ eval add wave -color DarkSalmon -group bridge_STU -noupdate
+ eval add wave -color DarkSalmon -label STU_full -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_full
+ eval add wave -color DarkSalmon -label STU_softReset -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_softReset
+ eval add wave -color DarkSalmon -label STU_continue -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_continue
+ eval add wave -color DarkSalmon -label STU_abort -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_abort
+ eval add wave -color DarkSalmon -label amu_masterid -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/amu_masterid
+ eval add wave -color DarkSalmon -label plb_masterid -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/plb_masterid
+
+ eval add wave -color DarkSalmon -label stat2plb_empty -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2plb_empty
+ eval add wave -color DarkSalmon -label stat2plb_rd_en -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2plb_rd_en
+ eval add wave -color DarkSalmon -label stat2wb_rd_en -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_rd_en
+ eval add wave -color DarkSalmon -label stat2wb_wr_en -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_wr_en
+ eval add wave -color DarkSalmon -label stat2wb_full -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_full
+ eval add wave -color DarkSalmon -label stat2wb_empty -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_empty
+ eval add wave -color DarkSalmon -label stat2wb_dout -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_dout
+ eval add wave -color DarkSalmon -label stat2wb_din -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_din
+
+ eval add wave -color DarkSalmon -label tcu_stuLatchPA -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/tcu_stulatchpa
+ eval add wave -color DarkSalmon -label tcu_stuLatchSA -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/tcu_stulatchsa
+
+
+ eval add wave -color DarkSalmon -label soft_reset_count -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/soft_reset_count
+ eval add wave -color DarkSalmon -label address_reg -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/address_reg
+ eval add wave -color DarkSalmon -label status_reg0 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(0)
+ eval add wave -color DarkSalmon -label status_reg1 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(1)
+ eval add wave -color DarkSalmon -label status_reg2 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(2)
+ eval add wave -color DarkSalmon -label status_reg3 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(3)
+ eval add wave -color DarkSalmon -label status_reg_out -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_reg_out
+
+ eval add wave -color DarkSalmon -label sl_mirq -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/sl_mirq
+
+
+ #
+ # Bridge - Adress Management Unit
+ #
+ eval add wave -color RosyBrown -group bridge_AMU -noupdate
+ eval add wave -color RosyBrown -label amu_addrack -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_addrack
+ eval add wave -color RosyBrown -label plb_savalid -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/plb_savalid
+ eval add wave -color RosyBrown -label amu_buf_rnw -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_rnw
+ eval add wave -color RosyBrown -label amu_bufempty -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_bufempty
+ eval add wave -color RosyBrown -label amu_buffull -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buffull
+ eval add wave -color RosyBrown -label amu_deviceselect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_deviceselect
+ eval add wave -color RosyBrown -label amu_statusselect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_statusselect
+ eval add wave -color RosyBrown -label amu_pipe_rmID -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_rmID
+ eval add wave -color RosyBrown -label amu_pipe_wmID -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_wmID
+ eval add wave -color rosyBrown -label amu_buf_size -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_size
+ eval add wave -color rosyBrown -label amu_buf_BE -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_BE
+ eval add wave -color rosyBrown -label amu_pipe_size -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_size
+ eval add wave -color rosyBrown -label amu_pipe_size -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_BE
+ eval add wave -color RosyBrown -label amu_buf_adr -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_adr
+ eval add wave -color RosyBrown -label wb_sel_o -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/wb_sel_o
+ eval add wave -color RosyBrown -label rpipe_out -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/rpipe_out
+ eval add wave -color RosyBrown -label wpipe_out -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/wpipe_out
+ eval add wave -color RosyBrown -label pipeline_in -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/pipeline_in
+ eval add wave -color RosyBrown -label AMU_pipe_adr -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_adr
+ eval add wave -color RosyBrown -label AMU_pipe_rStatusSelect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_rStatusSelect
+ eval add wave -color RosyBrown -label AMU_pipe_wStatusSelect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_wStatusSelect
+
+
+ #
+ # Read buffer
+ #
+ eval add wave -color SpringGreen -group bridge_RBF -noupdate
+ eval add wave -color SpringGreen -label rbuf_din -group bridge_RBF -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbuf_din
+ eval add wave -color SpringGreen -label rbuf_dout -group bridge_RBF -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbuf_dout
+ eval add wave -color SpringGreen -label tcu_rbufren -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/tcu_rbufren
+ eval add wave -color SpringGreen -label tcu_rbufwen -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/tcu_rbufwen
+ eval add wave -color SpringGreen -label rbf_empty -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbf_empty
+ eval add wave -color SpringGreen -label rbf_full -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbf_full
+
+
+ #
+ # Write buffer
+ #
+ eval add wave -color LimeGreen -group bridge_WBF -noupdate
+ eval add wave -color LimeGreen -label plb_size -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/plb_size
+ eval add wave -color LimeGreen -label wbf_empty -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/wbf_empty
+ eval add wave -color LimeGreen -label wbf_full -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/wbf_full
+ eval add wave -color LimeGreen -label wbf_wbus -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/wbf_wbus
+ eval add wave -color LimeGreen -label tcu_wbufren -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/tcu_wbufren
+ eval add wave -color LimeGreen -label tcu_wbufwen -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/tcu_wbufwen
+
+
+
+ #
+ # Whishbone signals
+ #
+ eval add wave -color Orange -noupdate -group Wishbone
+
+ eval add wave -color Orange -label wb_m_dat_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_dat_o
+ eval add wave -color Orange -label wb_m_ack_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_ack_o
+ eval add wave -color Orange -label wb_m_err_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_err_o
+ eval add wave -color Orange -label wb_m_rty_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_rty_o
+ eval add wave -color Orange -label wb_s_dat_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_dat_o
+ eval add wave -color Orange -label wb_s_adr_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_adr_o
+ eval add wave -color Orange -label wb_s_sel_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_sel_o
+ eval add wave -color Orange -label wb_s_we_o -group Wishbone -noupdate $binopt $tbpath/wb_conbus_0/wb_s_we_o
+ eval add wave -color Orange -label wb_s_cyc_o -group Wishbone -noupdate $binopt $tbpath/wb_conbus_0/wb_s_cyc_o
+ eval add wave -color Orange -label wb_s_stb_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_stb_o
+ # eval add wave -color Orange -label wb_s_lock_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_lock_o
+ eval add wave -color Orange -label wb_clk_i -group Wishbone -noupdate $binopt $tbpath/wb_conbus_0/wb_clk_i
+
+
+ add_ocram 0 OrangeRed
+ add_ocram 1 OrangeRed
+ add_ocram 2 OrangeRed
+ add_ocram 3 OrangeRed
+ add_ocram 4 OrangeRed
+ add_ocram 5 OrangeRed
+
+ configure wave -namecolwidth 347
+ configure wave -valuecolwidth 252
+ configure wave -timeline 0
+ configure wave -timelineunits ns
Index: trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/sim.do
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 10000 ns
+
+
Index: trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/transfers.bfl (revision 2)
@@ -0,0 +1,139 @@
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+ mem_update(addr=00010000,data=00000000_00000000_00000000_00000000)
+ mem_update(addr=00010010,data=00000000_00000000_00000000_00000000)
+
+
+ mem_update(addr=f0000000,data=11000001_11000002_11000003_11000004)
+ mem_update(addr=f0000010,data=11111111_11111112_11111113_11111114)
+ mem_update(addr=f0000020,data=11222221_11222222_11222223_11222224)
+ mem_update(addr=f0000030,data=11333331_11333332_11333333_11333334)
+
+ mem_update(addr=f1000000,data=22000001_22000002_22000003_22000004)
+ mem_update(addr=f1000010,data=22111111_22111112_22111113_22111114)
+ mem_update(addr=f1000020,data=22222221_22222222_22222223_22222224)
+ mem_update(addr=f1000030,data=22333331_22333332_22333333_22333334)
+
+ mem_update(addr=f2000000,data=33000001_33000002_33000003_33000004)
+ mem_update(addr=f2000010,data=33111111_33111112_33111113_33111114)
+ mem_update(addr=f2000020,data=33222221_33222222_33222223_33222224)
+ mem_update(addr=f2000030,data=33333331_33333332_33333333_33333334)
+
+
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+
+
+ write ( addr=f0000000, size=0000, be=1111 )
+ write ( addr=f0000004, size=0000, be=1111 )
+ -- we will get an error on wb-side after two successful writes
+ write ( addr=f0000008, size=0000, be=1111 )
+
+
+
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+ -- we're now checking the status registers:
+ mem_update( addr=00010000, data=20000000 )
+ mem_update( addr=00010004, data=11000003 )
+ mem_update( addr=00010008, data=f0000008 )
+ read ( addr=00010000, size=0001, be=1111 )
+ read ( addr=00010004, size=0000, be=1111 )
+ read ( addr=00010008, size=0000, be=1111 )
+
+ -- we have to clear the exception
+ mem_update( addr=00010000, data=00000000 )
+ write ( addr=00010000, size=0000, be=1111 )
+
+ -- we abort the transfer
+ write ( addr=00010008, size=0000, be=1111 )
+
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+
+
+ ------------------
+
+ write ( addr=f0000000, size=0001, be=1111 )
+ -- we wait (this simulates the interrupt-latency)
+ -- and continue the transfer
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+ write ( addr=00010004, size=0000, be=1111 )
+ -- we have to clear the exception
+ write ( addr=00010000, size=0000, be=1111 )
+
+
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+
+
+ --------------------
+
+
+ write ( addr=f1000000, size=0001, be=1111 )
+ -- we wait (this simulates the interrupt-latency)
+ -- and continue the transfer
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+ write ( addr=00010004, size=0000, be=1111 )
+ -- we have to clear the exception
+ write ( addr=00010000, size=0000, be=1111 )
+
+
+
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+
+
+ --------------------
+
+
+ write ( addr=f2000000, size=0010, be=1111 )
+ -- we wait (this simulates the interrupt-latency)
+ -- and continue the transfer
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+ write ( addr=00010004, size=0000, be=1111 )
+ -- we have to clear the exception
+ write ( addr=00010000, size=0000, be=1111 )
+
+
+
+
+ -- this causes several address-pipelining situations
+ read ( addr=f1000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=0001, be=1111 )
+ read ( addr=f1000000, size=0000, be=1111 )
+ read ( addr=f1000000, size=1010, be=0011 )
+ read ( addr=f2000000, size=1010, be=0011 )
+ read ( addr=f2000000, size=0001, be=1111 )
+ read ( addr=f1000000, size=1010, be=0010 )
+ read ( addr=f2000000, size=0000, be=1111 )
+ read ( addr=f2000000, size=1010, be=0001 )
+
+
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+ -- we're now checking the status registers:
+ mem_update( addr=00010000, data=40000000 )
+ read ( addr=00010000, size=0000, be=1111 )
+ mem_update( addr=00010000, data=00000000 )
+
+ -- clear the interrupt
+ write ( addr=00010000, size=0000, be=1111 )
+
Index: trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/Makefile
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/errors_and_rst/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/wave.do
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/wave.do (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/wave.do (revision 2)
@@ -0,0 +1,273 @@
+
+#
+# Display top-level ports
+#
+set binopt {-logic}
+set hexopt {-literal -hex}
+
+set tbpath {/system_tb/dut}
+
+eval add wave -color DarkGreen -noupdate -divider {"top-level ports"}
+eval add wave -color DarkGreen -noupdate $binopt /system_tb/sys_clk
+eval add wave -color DarkGreen -noupdate $binopt /system_tb/sys_rst
+eval add wave -color DarkGreen -noupdate $binopt /system_tb/wb_rst
+eval add wave -color DarkGreen -noupdate $binopt /system_tb/dut/plb_bfm_slave/synch_in
+
+
+# eval do ../../behavioral/mb_plb_wave.do
+# eval do ../../behavioral/plb_bfm_monitor_wave.do
+
+
+ # Master signals
+ proc add_master { num color } {
+ global binopt hexopt tbpath
+ eval add wave -color ${color} -noupdate -group Master_${num}
+ eval add wave -color ${color} -label ${num}_m_request -group Master_${num} -noupdate $binopt $tbpath/plb_bfm_master_${num}/m_request
+ eval add wave -color ${color} -label ${num}_m_abus -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_abus
+ eval add wave -color ${color} -label ${num}_m_be -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_be
+ eval add wave -color ${color} -label ${num}_m_rnw -group Master_${num} -noupdate $binopt $tbpath/plb_bfm_master_${num}/m_rnw
+ eval add wave -color ${color} -label ${num}_m_size -group Master_${num} -noupdate $binopt $tbpath/plb_bfm_master_${num}/m_size
+ eval add wave -color ${color} -label ${num}_m_priority -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_priority
+ eval add wave -color ${color} -label ${num}_plb_mrddbus -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/plb_mrddbus
+ eval add wave -color ${color} -label ${num}_m_wrdbus -group Master_${num} -noupdate $hexopt $tbpath/plb_bfm_master_${num}/m_wrdbus
+ }
+ add_master 32 White
+ add_master 64 AliceBlue
+ add_master 128 Seashell
+
+
+
+-- do ../behavioral/mb_plb_wave.do
+
+ proc add_ocram { num color } {
+ global binopt hexopt tbpath
+ eval add wave -color ${color} -noupdate -group ocram${num}
+ eval add wave -color ${color} -label wb_stb_i -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_stb_i
+ eval add wave -color ${color} -label wb_stb_i -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_stb_i
+ eval add wave -color ${color} -label wb_ack_o -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_ack_o
+ eval add wave -color ${color} -label wb_err_o -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_err_o
+ eval add wave -color ${color} -label wb_rty_o -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/wb_rty_o
+ eval add wave -color ${color} -label w_ack -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/w_ack
+ eval add wave -color ${color} -label err_rty_count_r -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/err_rty_count_r
+ eval add wave -color ${color} -label err_rty_count_w -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/err_rty_count_w
+ eval add wave -color ${color} -label r_delay_count -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/r_delay_count
+ eval add wave -color ${color} -label w_delay_count -group ocram${num} -noupdate $tbpath/onchip_ram_${num}/onchip_ram_${num}/w_delay_count
+
+ eval add wave -color ${color} -label ram(0) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(0)
+ eval add wave -color ${color} -label ram(1) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(1)
+ eval add wave -color ${color} -label ram(2) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(2)
+ eval add wave -color ${color} -label ram(3) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(3)
+ eval add wave -color ${color} -label ram(4) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(4)
+ eval add wave -color ${color} -label ram(5) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(5)
+ eval add wave -color ${color} -label ram(6) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(6)
+ eval add wave -color ${color} -label ram(7) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(7)
+ eval add wave -color ${color} -label ram(8) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(8)
+ eval add wave -color ${color} -label ram(9) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(9)
+ eval add wave -color ${color} -label ram(10) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(10)
+ eval add wave -color ${color} -label ram(11) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(11)
+ eval add wave -color ${color} -label ram(12) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(12)
+ eval add wave -color ${color} -label ram(13) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(13)
+ eval add wave -color ${color} -label ram(14) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(14)
+ eval add wave -color ${color} -label ram(15) -group ocram${num} -noupdate $hexopt $tbpath/onchip_ram_${num}/onchip_ram_${num}/ram(15)
+ }
+
+
+
+
+ #
+ # General bridge signals
+ #
+ eval add wave -color purple -group bridge_general -noupdate
+ eval add wave -color purple -label sl_addrack -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_addrack
+ eval add wave -color purple -label plb_abus -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb_abus
+ eval add wave -color purple -label plb_be -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb_be
+ eval add wave -color purple -label plb_pavalid -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_pavalid
+ eval add wave -color purple -label plb_savalid -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_savalid
+ eval add wave -color purple -label plb_rnw -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_rnw
+ eval add wave -color purple -label plb_msize -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_msize
+ eval add wave -color purple -label plb_type -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_type
+ eval add wave -color purple -label plb_wrdbus -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb_wrdbus
+ eval add wave -color purple -label sl_rddbus -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/sl_rddbus
+
+ eval add wave -color purple -label sl_wrdack -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_wrdack
+ eval add wave -color maroon -label sl_wrcomp -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_wrcomp
+ eval add wave -color purple -label sl_rddack -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_rddack
+ eval add wave -color maroon -label sl_rdcomp -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_rdcomp
+
+ eval add wave -color maroon -label sl_rdprim -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_rdprim
+ eval add wave -color maroon -label sl_wrprim -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/plb_wrprim
+
+
+ eval add wave -color maroon -label wb_adr_o -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_adr_o
+ eval add wave -color maroon -label wb_cyc_o -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_cyc_o
+ eval add wave -color maroon -label wb_dat_i -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_dat_i
+ eval add wave -color maroon -label wb_dat_o -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_dat_o
+ eval add wave -color maroon -label wb_err_i -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_err_i
+ eval add wave -color maroon -label wb_rst_i -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_rst_i
+ eval add wave -color maroon -label wb_sel_o -group bridge_general -noupdate $hexopt $tbpath/plb2wb_bridge_0/wb_sel_o
+ eval add wave -color maroon -label wb_stb_o -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_stb_o
+ eval add wave -color maroon -label wb_we_o -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/wb_we_o
+ eval add wave -color maroon -label sl_mbusy -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mbusy
+ eval add wave -color maroon -label sl_mwrerr -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mwrerr
+ eval add wave -color maroon -label sl_mrderr -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mrderr
+
+ eval add wave -color maroon -label sl_mirq -group bridge_general -noupdate $tbpath/plb2wb_bridge_0/sl_mirq
+ #
+ # Bridge - Transfer Control Unit
+ #
+ eval add wave -color aquamarine -group bridge_TCU -noupdate
+ eval add wave -color aquamarine -label c_plb_wstate -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/c_plb_wstate
+ eval add wave -color aquamarine -label c_plb_rstate -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/c_plb_rstate
+ eval add wave -color aquamarine -label c_wb_state -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/c_wb_state
+ eval add wave -color aquamarine -label wb_ack -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_ack
+ eval add wave -color aquamarine -label wb_err -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_err
+ eval add wave -color aquamarine -label wb_rty -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_rty
+
+ eval add wave -color aquamarine -label tcu_addrack -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_addrack
+ eval add wave -color aquamarine -label sl_rdwdaddr -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/sl_rdwdaddr
+
+ eval add wave -color aquamarine -label tcu_adr_offset -group bridge_TCU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_adr_offset
+ eval add wave -color aquamarine -label tcu_adrbufren -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_adrbufren
+ eval add wave -color aquamarine -label tcu_adrbufwen -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_adrbufwen
+ eval add wave -color aquamarine -label tcu_rpiperden -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_rpiperden
+ eval add wave -color aquamarine -label tcu_wpiperden -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_wpiperden
+
+ eval add wave -color aquamarine -label tcu_enrddbus -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_enrddbus
+ eval add wave -color aquamarine -label tcu_rbufren -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_rbufren
+ eval add wave -color aquamarine -label tcu_rbufwen -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_rbufwen
+ eval add wave -color aquamarine -label tcu_wbufren -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_wbufren
+ eval add wave -color aquamarine -label tcu_wbufwen -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_wbufwen
+
+ eval add wave -color aquamarine -label tcu_enStuRDDbus -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_ensturddbus
+ eval add wave -color aquamarine -label tcu_stuWritePA -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_stuwritepa
+ eval add wave -color aquamarine -label tcu_stuWriteSA -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_stuwritesa
+ eval add wave -color aquamarine -label tcu_stat2plb_en -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_stat2plb_en
+ eval add wave -color aquamarine -label tcu_wb_status_info -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/tcu_wb_status_info
+
+ eval add wave -color aquamarine -label tcu_mrbusy -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/tcu_mrbusy
+ eval add wave -color aquamarine -label mbusy_read_out -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/mbusy_read_out
+ eval add wave -color aquamarine -label mbusy_write_out -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/mbusy_write_out
+ eval add wave -color aquamarine -label SL_MWrErr -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/SL_MWrErr
+ eval add wave -color aquamarine -label SL_MRdErr -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/SL_MRdErr
+ eval add wave -color aquamarine -label sl_wrbterm -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/sl_wrbterm
+ eval add wave -color aquamarine -label sl_rdbterm -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/sl_rdbterm
+
+ eval add wave -color aquamarine -label wb_tout_reset -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_tout_reset
+ eval add wave -color aquamarine -label wb_tout_count -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_tout_count
+ eval add wave -color aquamarine -label wb_tout_counter -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_tout_counter
+ eval add wave -color aquamarine -label wb_tout_alarm -group bridge_TCU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/tcu/wb_tout_alarm
+
+
+ #
+ # Bridge - Status Unit
+ #
+ eval add wave -color DarkSalmon -group bridge_STU -noupdate
+ eval add wave -color DarkSalmon -label STU_full -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_full
+ eval add wave -color DarkSalmon -label STU_softReset -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_softReset
+ eval add wave -color DarkSalmon -label STU_continue -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_continue
+ eval add wave -color DarkSalmon -label STU_abort -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/STU_abort
+ eval add wave -color DarkSalmon -label amu_masterid -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/amu_masterid
+ eval add wave -color DarkSalmon -label plb_masterid -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/plb_masterid
+
+ eval add wave -color DarkSalmon -label stat2plb_empty -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2plb_empty
+ eval add wave -color DarkSalmon -label stat2plb_rd_en -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2plb_rd_en
+ eval add wave -color DarkSalmon -label stat2wb_rd_en -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_rd_en
+ eval add wave -color DarkSalmon -label stat2wb_wr_en -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_wr_en
+ eval add wave -color DarkSalmon -label stat2wb_full -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_full
+ eval add wave -color DarkSalmon -label stat2wb_empty -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_empty
+ eval add wave -color DarkSalmon -label stat2wb_dout -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_dout
+ eval add wave -color DarkSalmon -label stat2wb_din -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/stat2wb_din
+
+ eval add wave -color DarkSalmon -label tcu_stuLatchPA -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/tcu_stulatchpa
+ eval add wave -color DarkSalmon -label tcu_stuLatchSA -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/tcu_stulatchsa
+
+
+ eval add wave -color DarkSalmon -label soft_reset_count -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/soft_reset_count
+ eval add wave -color DarkSalmon -label address_reg -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/address_reg
+ eval add wave -color DarkSalmon -label status_reg0 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(0)
+ eval add wave -color DarkSalmon -label status_reg1 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(1)
+ eval add wave -color DarkSalmon -label status_reg2 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(2)
+ eval add wave -color DarkSalmon -label status_reg3 -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_regs(3)
+ eval add wave -color DarkSalmon -label status_reg_out -group bridge_STU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/status_reg_out
+
+ eval add wave -color DarkSalmon -label sl_mirq -group bridge_STU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/stu/sl_mirq
+
+
+ #
+ # Bridge - Adress Management Unit
+ #
+ eval add wave -color RosyBrown -group bridge_AMU -noupdate
+ eval add wave -color RosyBrown -label amu_addrack -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_addrack
+ eval add wave -color RosyBrown -label plb_savalid -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/plb_savalid
+ eval add wave -color RosyBrown -label amu_buf_rnw -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_rnw
+ eval add wave -color RosyBrown -label amu_bufempty -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_bufempty
+ eval add wave -color RosyBrown -label amu_buffull -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buffull
+ eval add wave -color RosyBrown -label amu_deviceselect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_deviceselect
+ eval add wave -color RosyBrown -label amu_statusselect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_statusselect
+ eval add wave -color RosyBrown -label amu_pipe_rmID -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_rmID
+ eval add wave -color RosyBrown -label amu_pipe_wmID -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_wmID
+ eval add wave -color rosyBrown -label amu_buf_size -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_size
+ eval add wave -color rosyBrown -label amu_buf_BE -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_BE
+ eval add wave -color rosyBrown -label amu_pipe_size -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_size
+ eval add wave -color rosyBrown -label amu_pipe_size -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_BE
+ eval add wave -color RosyBrown -label amu_buf_adr -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_buf_adr
+ eval add wave -color RosyBrown -label wb_sel_o -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/wb_sel_o
+ eval add wave -color RosyBrown -label rpipe_out -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/rpipe_out
+ eval add wave -color RosyBrown -label wpipe_out -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/wpipe_out
+ eval add wave -color RosyBrown -label pipeline_in -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/pipeline_in
+ eval add wave -color RosyBrown -label AMU_pipe_adr -group bridge_AMU -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_adr
+ eval add wave -color RosyBrown -label AMU_pipe_rStatusSelect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_rStatusSelect
+ eval add wave -color RosyBrown -label AMU_pipe_wStatusSelect -group bridge_AMU -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/amu/amu_pipe_wStatusSelect
+
+
+ #
+ # Read buffer
+ #
+ eval add wave -color SpringGreen -group bridge_RBF -noupdate
+ eval add wave -color SpringGreen -label rbuf_din -group bridge_RBF -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbuf_din
+ eval add wave -color SpringGreen -label rbuf_dout -group bridge_RBF -noupdate $hexopt $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbuf_dout
+ eval add wave -color SpringGreen -label tcu_rbufren -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/tcu_rbufren
+ eval add wave -color SpringGreen -label tcu_rbufwen -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/tcu_rbufwen
+ eval add wave -color SpringGreen -label rbf_empty -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbf_empty
+ eval add wave -color SpringGreen -label rbf_full -group bridge_RBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/rbuf/rbf_full
+
+
+ #
+ # Write buffer
+ #
+ eval add wave -color LimeGreen -group bridge_WBF -noupdate
+ eval add wave -color LimeGreen -label plb_size -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/plb_size
+ eval add wave -color LimeGreen -label wbf_empty -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/wbf_empty
+ eval add wave -color LimeGreen -label wbf_full -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/wbf_full
+ eval add wave -color LimeGreen -label wbf_wbus -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/wbf_wbus
+ eval add wave -color LimeGreen -label tcu_wbufren -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/tcu_wbufren
+ eval add wave -color LimeGreen -label tcu_wbufwen -group bridge_WBF -noupdate $tbpath/plb2wb_bridge_0/plb2wb_bridge_0/wbuf/tcu_wbufwen
+
+
+
+ #
+ # Whishbone signals
+ #
+ eval add wave -color Orange -noupdate -group Wishbone
+
+ eval add wave -color Orange -label wb_m_dat_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_dat_o
+ eval add wave -color Orange -label wb_m_ack_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_ack_o
+ eval add wave -color Orange -label wb_m_err_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_err_o
+ eval add wave -color Orange -label wb_m_rty_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_m_rty_o
+ eval add wave -color Orange -label wb_s_dat_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_dat_o
+ eval add wave -color Orange -label wb_s_adr_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_adr_o
+ eval add wave -color Orange -label wb_s_sel_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_sel_o
+ eval add wave -color Orange -label wb_s_we_o -group Wishbone -noupdate $binopt $tbpath/wb_conbus_0/wb_s_we_o
+ eval add wave -color Orange -label wb_s_cyc_o -group Wishbone -noupdate $binopt $tbpath/wb_conbus_0/wb_s_cyc_o
+ eval add wave -color Orange -label wb_s_stb_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_stb_o
+ # eval add wave -color Orange -label wb_s_lock_o -group Wishbone -noupdate $hexopt $tbpath/wb_conbus_0/wb_s_lock_o
+ eval add wave -color Orange -label wb_clk_i -group Wishbone -noupdate $binopt $tbpath/wb_conbus_0/wb_clk_i
+
+
+ add_ocram 4 OrangeRed
+ add_ocram 5 OrangeRed
+
+ configure wave -namecolwidth 347
+ configure wave -valuecolwidth 252
+ configure wave -timeline 0
+ configure wave -timelineunits ns
Index: trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/onchip_ram.bin
===================================================================
Index: trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/transfers.bfl
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/transfers.bfl (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/transfers.bfl (revision 2)
@@ -0,0 +1,52 @@
+
+ set_alias(PART = 1)
+ set_alias(SUBPART = 2)
+ set_alias(SUBSUBPART = 3)
+
+
+ ---------------------------------
+ -- 32-Bit Master --
+
+ set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
+ configure(msize=00)
+ mem_update(addr=00010000,data=00000000_00000000_00000000_00000000)
+ mem_update(addr=00010010,data=00000000_00000000_00000000_00000000)
+
+
+ mem_update(addr=f4000000,data=11000001_11000002_11000003_11000004)
+ mem_update(addr=f4000010,data=11111111_11111112_11111113_11111114)
+ mem_update(addr=f4000020,data=11222221_11222222_11222223_11222224)
+ mem_update(addr=f4000030,data=11333331_11333332_11333333_11333334)
+
+ mem_update(addr=f5000000,data=22000001_22000002_22000003_22000004)
+ mem_update(addr=f5000010,data=22111111_22111112_22111113_22111114)
+ mem_update(addr=f5000020,data=22222221_22222222_22222223_22222224)
+ mem_update(addr=f5000030,data=22333331_22333332_22333333_22333334)
+
+
+
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+
+
+ write ( addr=f4000000, size=1010, be=1111 )
+
+ read ( addr=f4000000, size=0000, be=1111 )
+ read ( addr=f4000010, size=1010, be=0010 )
+ read ( addr=f4000000, size=0001, be=1111 )
+
+
+ wait( level=SUBPART )
+ wait( level=SUBPART )
+
+ -- this leads to a write stall
+ write ( addr=f5000000, size=1010, be=1111 )
+
+ wait( level=SUBSUBPART )
+ wait( level=SUBSUBPART )
+
+ write ( addr=00010000, size=0000, be=1111 )
+ write ( addr=00010004, size=0000, be=1111 )
+
+
+
Index: trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/sim.do
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/sim.do (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/sim.do (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+vsim -wlf result/wave.wlf -novopt -t ps system_tb
+
+do wave.do
+
+
+do transfers.do
+
+
+
+run 10000 ns
+
+
Index: trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/Makefile
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/simulation/test_cases/timeouts/Makefile (revision 2)
@@ -0,0 +1,55 @@
+CUR_DIR=$(shell pwd)
+SIM_DIR=$(CUR_DIR)/../..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+RESULT_DIR=$(CUR_DIR)/result
+VSIM=vsim -quiet -c -assertfile $(RESULT_DIR)/assert.log -errorfile $(RESULT_DIR)/error.log -l $(RESULT_DIR)/simulation.log -do
+
+TEST_CASE_TARGETS=./result/wave.wlf
+
+
+
+
+
+sim: $(TEST_CASE_TARGETS)
+
+
+$(TEST_CASE_TARGETS): $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS) transfers.do
+ @$(MAKE) link
+ @mkdir -p result
+ @echo "Run vsim ....."
+ @$(VSIM) "do sim.do; exit" > /dev/null
+ @echo ".... done! Result in $(RESULT_DIR)"
+
+
+
+#
+# we first do `unlink`. If there are no links, this does nothing.
+# If there are links, we unlink it and link it again
+link: unlink
+ @ln -s `find ../../sim_bin -maxdepth 1` ./
+
+
+unlink:
+ @for file in $(shell find . -maxdepth 1 -type l); do \
+ unlink $$file; \
+ done;
+
+transfers.do: transfers.bfl
+ xilbfc transfers.bfl
+
+
+
+view:
+ vsim -do "vsim -view result/wave.wlf; view wave; do wave.do"
+
+
+clean: unlink
+ rm -rf \
+ xilbfc.log \
+ transfers.do \
+ log \
+ result
+
+
+cleansim:
+ rm -rf result
Index: trunk/systems/test_system_sim/wb_err_and_rst/simulation/Makefile
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/simulation/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/simulation/Makefile (revision 2)
@@ -0,0 +1,114 @@
+SIM_DIR=$(shell pwd)
+
+XPS_PROJ_DIR=$(SIM_DIR)/..
+SIM_BIN_DIR=$(SIM_DIR)/sim_bin
+COMMON_DIR=$(SIM_DIR)/../../common
+LOG_DIR=$(SIM_DIR)/log
+PLB_BFM_SETUP_DIR=$(SIM_DIR)/../../plb_bfm_setup
+
+
+include $(COMMON_DIR)/Makefile
+
+
+
+all: sim
+
+
+
+WORK_TARGET=$(SIM_BIN_DIR)/work/system/_primary.dat
+
+
+
+###
+#
+# note: WORK_TARGET is defined some lines above, the rest in ../../common/Makefile
+#
+COMPILE_COMPONENTS=$(TESTRAM_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET) $(PLB_BFM_TARGET) $(WORK_TARGET)
+
+
+
+#
+# Generate Simulation HDL Files
+# (This is the same than XPS-Gui->Simulation->Generate Simulation HDL Files)
+#
+$(SIM_DIR)/behavioral: $(XPS_PROJ_DIR)/system.mhs
+ @mkdir -p $(LOG_DIR)
+ simgen $(XPS_PROJ_DIR)/system.mhs -lang vhdl \
+ -p virtex5 \
+ -m beh \
+ -od $(XPS_PROJ_DIR)/ \
+ -s mti \
+ -lp $(LIB_DIR) \
+ -log $(LOG_DIR)/simgen
+ @mv simgen.opt log # there is no simgen-flag for this!
+
+
+
+
+
+# PLB_BFM_TARGET=$(SIM_BIN_DIR)/plbv46_bfm/system/_primary.dat
+# #BFM_SOURCE=$() TODO
+# $(PLB_BFM_TARGET):
+# cd $(SIM_BIN_DIR); \
+# vlib plbv46_bfm; \
+# vmap plbv46_bfm plbv46_bfm; \
+# vlib plbv46_master_bfm_v1_00_a; \
+# vmap plbv46_master_bfm_v1_00_a plbv46_master_bfm_v1_00_a; \
+# vlib plbv46_monitor_bfm_v1_00_a; \
+# vmap plbv46_monitor_bfm_v1_00_a plbv46_monitor_bfm_v1_00_a; \
+# vlib plbv46_slave_bfm_v1_00_a; \
+# vmap plbv46_slave_bfm_v1_00_a plbv46_slave_bfm_v1_00_a; \
+# vcom $(VHDL_CFLAGS) -work plbv46_bfm \
+# "$(PLB_BFM_SETUP_DIR)/plb_dcl_128.vhd"; \
+# vcom $(VHDL_CFLAGS) -work plbv46_master_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_master_bfm_v1_00_a/hdl/vhdl/plbv46_master_bfm.vhd" ; \
+# vcom $(VHDL_CFLAGS) -work plbv46_monitor_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_monitor_bfm_v1_00_a/hdl/vhdl/plbv46_monitor_bfm.vhd";\
+# vcom $(VHDL_CFLAGS) -work plbv46_slave_bfm_v1_00_a \
+# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_slave_bfm_v1_00_a/hdl/vhdl/plbv46_slave_bfm.vhd";
+
+
+
+
+
+$(WORK_TARGET): $(SIM_DIR)/behavioral $(SIM_BIN_DIR)/../testbench/system_tb.vhd
+ cd $(SIM_BIN_DIR); \
+ vlib work; \
+ vmap work work; \
+ vlog -novopt -93 -work work "../behavioral/wb_conbus_0_wrapper.v"; \
+ vcom $(VHDL_CFLAGS) -work work \
+ "../behavioral/onchip_ram_0_wrapper.vhd" \
+ "../behavioral/onchip_ram_1_wrapper.vhd" \
+ "../behavioral/onchip_ram_2_wrapper.vhd" \
+ "../behavioral/onchip_ram_3_wrapper.vhd" \
+ "../behavioral/onchip_ram_4_wrapper.vhd" \
+ "../behavioral/onchip_ram_5_wrapper.vhd" \
+ "../behavioral/mb_plb_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_32_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_64_wrapper.vhd" \
+ "../behavioral/plb_bfm_master_128_wrapper.vhd" \
+ "../behavioral/plb_bfm_monitor_wrapper.vhd" \
+ "../behavioral/plb_bfm_slave_wrapper.vhd" \
+ "../behavioral/plb_bfm_synch_wrapper.vhd" \
+ "../behavioral/plb2wb_bridge_0_wrapper.vhd" \
+ "../behavioral/system.vhd" \
+ "../testbench/system_tb.vhd"
+
+
+
+
+
+
+compile: $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS)
+
+
+
+
+
+
+clean:
+ rm -rf \
+ $(SIM_DIR)/behavioral \
+ $(SIM_BIN_DIR) \
+ $(LOG_DIR)
+
Index: trunk/systems/test_system_sim/wb_err_and_rst/system_incl.make
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/system_incl.make (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/system_incl.make (revision 2)
@@ -0,0 +1,104 @@
+#################################################################
+# Makefile generated by Xilinx Platform Studio
+# Project:/home/christian/share/semesterproject/trunk/systems/test_system_sim/wb_err_and_rst/system.xmp
+#
+# WARNING : This file will be re-generated every time a command
+# to run a make target is invoked. So, any changes made to this
+# file manually, will be lost when make is invoked next.
+#################################################################
+
+XILINX_EDK_DIR = /opt/Xilinx/11.1/EDK
+NON_CYG_XILINX_EDK_DIR = /opt/Xilinx/11.1/EDK
+
+SYSTEM = system
+
+MHSFILE = system.mhs
+
+MSSFILE = system.mss
+
+FPGA_ARCH = virtex5
+
+DEVICE = xc5vlx50ff676-1
+
+LANGUAGE = vhdl
+
+SEARCHPATHOPT = -lp /home/christian/share/semesterproject/trunk/systems/EDK_Libs/
+GLOBAL_SEARCHPATHOPT =
+
+SUBMODULE_OPT =
+
+PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst
+
+LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst
+
+OBSERVE_PAR_OPTIONS = -error yes
+
+MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf
+PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf
+PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf
+BOOTLOOP_DIR = bootloops
+
+BRAMINIT_ELF_FILES =
+BRAMINIT_ELF_FILE_ARGS =
+
+ALL_USER_ELF_FILES =
+
+SIM_CMD = vsim
+
+BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.do
+
+STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.do
+
+TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do
+
+DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
+
+MIX_LANG_SIM_OPT = -mixed yes
+
+SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s mti
+
+
+LIBRARIES =
+
+LIBSCLEAN_TARGETS =
+
+PROGRAMCLEAN_TARGETS =
+
+CORE_STATE_DEVELOPMENT_FILES =
+
+WRAPPER_NGC_FILES = implementation/mb_plb_wrapper.ngc \
+implementation/plb2wb_bridge_0_wrapper.ngc \
+implementation/wb_conbus_0_wrapper.ngc \
+implementation/onchip_ram_0_wrapper.ngc \
+implementation/onchip_ram_1_wrapper.ngc \
+implementation/onchip_ram_2_wrapper.ngc \
+implementation/onchip_ram_3_wrapper.ngc \
+implementation/onchip_ram_4_wrapper.ngc \
+implementation/onchip_ram_5_wrapper.ngc
+
+POSTSYN_NETLIST = implementation/$(SYSTEM).ngc
+
+SYSTEM_BIT = implementation/$(SYSTEM).bit
+
+DOWNLOAD_BIT = implementation/download.bit
+
+SYSTEM_ACE = implementation/$(SYSTEM).ace
+
+UCF_FILE = data/system.ucf
+
+BMM_FILE = implementation/$(SYSTEM).bmm
+
+BITGEN_UT_FILE = etc/bitgen.ut
+
+XFLOW_OPT_FILE = etc/fast_runtime.opt
+XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)
+
+XPLORER_DEPENDENCY = __xps/xplorer.opt
+XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7
+
+FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY)
+
+SDK_EXPORT_DIR = SDK/SDK_Export/hw
+SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml
+SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit
+SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT)
Index: trunk/systems/test_system_sim/wb_err_and_rst/system.mss
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/system.mss (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/system.mss (revision 2)
@@ -0,0 +1,55 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = plb_bfm_slave
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = plb2wb_bridge_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_4
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = onchip_ram_5
+END
+
+
Index: trunk/systems/test_system_sim/wb_err_and_rst/system.xmp
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/system.xmp (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/system.xmp (revision 2)
@@ -0,0 +1,25 @@
+#Please do not modify this file by hand
+XmpVersion: 11.4
+VerMgmt: 11.4
+IntStyle: default
+ModuleSearchPath: ../../EDK_Libs/
+MHS File: system.mhs
+MSS File: system.mss
+Architecture: virtex5
+Device: xc5vlx50
+Package: ff676
+SpeedGrade: -1
+UserCmd1:
+UserCmd1Type: 0
+UserCmd2:
+UserCmd2Type: 0
+GenSimTB: 0
+SdkExportBmmBit: 1
+SdkExportDir: SDK/SDK_Export
+InsertNoPads: 0
+WarnForEAArch: 1
+HdlLang: VHDL
+SimModel: BEHAVIORAL
+UcfFile: data/system.ucf
+EnableParTimingError: 1
+ShowLicenseDialog: 1
Index: trunk/systems/test_system_sim/wb_err_and_rst/data/system.ucf
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/data/system.ucf (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/data/system.ucf (revision 2)
@@ -0,0 +1,6 @@
+# Virtex 5 ML501 Evaluation Platform
+Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
+TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
+Net fpga_0_clk_1_sys_clk_pin LOC = AD8 | IOSTANDARD=LVCMOS33;
+Net fpga_0_rst_1_sys_rst_pin TIG;
+Net fpga_0_rst_1_sys_rst_pin LOC = T23 | IOSTANDARD=LVCMOS33 | PULLUP;
Index: trunk/systems/test_system_sim/wb_err_and_rst/system.mhs
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/system.mhs (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/system.mhs (revision 2)
@@ -0,0 +1,208 @@
+
+# ##############################################################################
+# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
+# Fri Mar 5 18:02:26 2010
+# Target Board: Xilinx Virtex 5 ML501 Evaluation Platform Rev 1
+# Family: virtex5
+# Device: xc5vlx50
+# Package: ff676
+# Speed Grade: -1
+# Processor number: 1
+# Processor 1: microblaze_0
+# System clock frequency: 125.0
+# Debug Interface: On-Chip HW Debug Module
+# ##############################################################################
+ PARAMETER VERSION = 2.1.0
+
+
+ PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
+ PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
+ PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]
+ PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]
+ PORT wb_clk_pin = wb_clk, DIR = I, SIGIS = CLK
+ PORT wb_rst_pin = wb_rst, DIR = I, SIGIS = RST
+
+
+BEGIN plb_v46
+ PARAMETER INSTANCE = mb_plb
+ PARAMETER HW_VER = 1.04.a
+ PARAMETER C_EXT_RESET_HIGH = 1
+ PARAMETER C_DCR_INTFCE = 1
+ PARAMETER C_BASEADDR = 0b0000000000
+ PARAMETER C_HIGHADDR = 0b1111111111
+ PORT PLB_Clk = clk_100MHz
+ PORT SYS_Rst = sys_rst_s
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_32
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_SIZE = 0b10
+ PARAMETER PLB_MASTER_NUM = 0b0000
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_0
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_64
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ PARAMETER PLB_MASTER_SIZE = 0b10
+ PARAMETER PLB_MASTER_NUM = 0b0001
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_1
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_master_bfm
+ PARAMETER INSTANCE = plb_bfm_master_128
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
+ PARAMETER C_MPLB_NATIVE_DWIDTH = 128
+ PARAMETER PLB_MASTER_NUM = 0b0010
+ BUS_INTERFACE MPLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_2
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_monitor_bfm
+ PARAMETER INSTANCE = plb_bfm_monitor
+ PARAMETER HW_VER = 1.00.a
+ BUS_INTERFACE MON_PLB = mb_plb
+ PORT SYNCH_OUT = bfm_synch_out_3
+ PORT SYNCH_IN = synch_in
+END
+
+BEGIN plbv46_slave_bfm
+ PARAMETER INSTANCE = plb_bfm_slave
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER PLB_SLAVE_ADDR_LO_0 = 0x00020000
+ PARAMETER PLB_SLAVE_ADDR_HI_0 = 0x0002ffff
+ PARAMETER C_SPLB_NATIVE_DWIDTH = 32
+ PARAMETER PLB_SLAVE_SIZE = 0b00
+ BUS_INTERFACE SPLB = mb_plb
+ PORT SYNCH_IN = synch_in
+ PORT SYNCH_OUT = bfm_synch_out_4
+END
+
+BEGIN bfm_synch
+ PARAMETER INSTANCE = plb_bfm_synch
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_NUM_SYNCH = 5
+ PORT TO_SYNCH_IN = synch_out
+ PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_1 & bfm_synch_out_2 & bfm_synch_out_3 & bfm_synch_out_4
+END
+
+BEGIN plb2wb_bridge
+ PARAMETER INSTANCE = plb2wb_bridge_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_BASEADDR = 0xf0000000
+ PARAMETER C_HIGHADDR = 0xf7ffffff
+ PARAMETER WB_ADR_OFFSET = 0xf0000000
+ PARAMETER WB_ADR_OFFSET_NEG = 1
+ PARAMETER SYNCHRONY = false
+ PARAMETER C_STATUS_BASEADDR = 0x00010000
+ PARAMETER C_STATUS_HIGHADDR = 0x0001FFFF
+ PARAMETER WB_PIC_INTS = 1
+ BUS_INTERFACE SPLB = mb_plb
+ BUS_INTERFACE MWB = wb_conbus_0
+ PORT SPLB_Clk = clk_100MHz
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+ PORT wb_pic_int_i = net_gnd
+END
+
+BEGIN wb_conbus
+ PARAMETER INSTANCE = wb_conbus_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER wb_s0_addr = 0x00
+ PARAMETER wb_s27_addr_w = 8
+ PARAMETER wb_s1_addr = 0x01
+ PARAMETER wb_s2_addr = 0x02
+ PARAMETER wb_s3_addr = 0x03
+ PARAMETER wb_s4_addr = 0x04
+ PARAMETER wb_s5_addr = 0x05
+ PARAMETER wb_s6_addr = 0x06
+ PARAMETER wb_s7_addr = 0x07
+ PARAMETER wb_s0_addr_w = 8
+ PARAMETER wb_s1_addr_w = 8
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 0
+ PARAMETER WR_DELAY = 0
+ PARAMETER WITH_ERR_OR_RTY = 0b01
+# PARAMETER WITH_ERR_OR_RTY = 0b00
+ PARAMETER ERR_RTY_INTERVAL = 2
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_1
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 1
+ PARAMETER WR_DELAY = 1
+ PARAMETER WITH_ERR_OR_RTY = 0b01
+# PARAMETER WITH_ERR_OR_RTY = 0b00
+ PARAMETER ERR_RTY_INTERVAL = 3
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_2
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 3
+ PARAMETER WR_DELAY = 3
+ PARAMETER WITH_ERR_OR_RTY = 0b01
+# PARAMETER WITH_ERR_OR_RTY = 0b00
+ PARAMETER ERR_RTY_INTERVAL = 4
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_3
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 5
+ PARAMETER WR_DELAY = 5
+ PARAMETER WITH_ERR_OR_RTY = 0b01
+# PARAMETER WITH_ERR_OR_RTY = 0b00
+ PARAMETER ERR_RTY_INTERVAL = 2
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_clk_i = wb_clk
+ PORT wb_rst_i = wb_rst
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_4
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 11
+ PARAMETER WR_DELAY = 8
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
+BEGIN testram
+ PARAMETER INSTANCE = onchip_ram_5
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER RD_DELAY = 11
+ PARAMETER WR_DELAY = 11
+ BUS_INTERFACE SWB = wb_conbus_0
+ PORT wb_rst_i = wb_rst
+ PORT wb_clk_i = wb_clk
+END
+
Index: trunk/systems/test_system_sim/wb_err_and_rst/etc/bitgen.ut
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/etc/bitgen.ut (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/etc/bitgen.ut (revision 2)
@@ -0,0 +1,14 @@
+-g TdoPin:PULLNONE
+-g DriveDone:No
+-g StartUpClk:JTAGCLK
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g TckPin:PULLUP
+-g TdiPin:PULLUP
+-g TmsPin:PULLUP
+-g DonePipe:No
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:NONE
+-g Persist:No
+
Index: trunk/systems/test_system_sim/wb_err_and_rst/etc/fast_runtime.opt
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/etc/fast_runtime.opt (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/etc/fast_runtime.opt (revision 2)
@@ -0,0 +1,84 @@
+FLOWTYPE = FPGA;
+###############################################################
+## Filename: fast_runtime.opt
+##
+## Option File For Xilinx FPGA Implementation Flow for Fast
+## Runtime.
+##
+## Version: 4.1.1
+###############################################################
+#
+# Options for Translator
+#
+# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
+#
+Program ngdbuild
+-p ; # Partname to use - picked from xflow commandline
+-nt timestamp; # NGO File generation. Regenerate only when
+ # source netlist is newer than existing
+ # NGO file (default)
+-bm .bmm # Block RAM memory map file
+; # User design - pick from xflow command line
+-uc .ucf; # ucf constraints
+.ngd; # Name of NGD file. Filebase same as design filebase
+End Program ngdbuild
+
+#
+# Options for Mapper
+#
+# Type "map -h " for a detailed list of map command line options
+#
+Program map
+-o _map.ncd; # Output Mapped ncd file
+-w; # Overwrite output files.
+-pr b; # Pack internal FF/latches into IOBs
+#-fp .mfp; # Floorplan file
+-ol high;
+-timing;
+-detail;
+.ngd; # Input NGD file
+.pcf; # Physical constraints file
+END Program map
+
+#
+# Options for Post Map Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_map_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o _map.twr; # Output trace report file
+-xml _map.twx; # Output XML version of the timing report
+#-tsi _map.tsi; # Produce Timing Specification Interaction report
+_map.ncd; # Input mapped ncd
+.pcf; # Physical constraints file
+END Program post_map_trce
+
+#
+# Options for Place and Route
+#
+# Type "par -h" for a detailed list of par command line options
+#
+Program par
+-w; # Overwrite existing placed and routed ncd
+-ol high; # Overall effort level
+_map.ncd; # Input mapped NCD file
+.ncd; # Output placed and routed NCD
+.pcf; # Input physical constraints file
+END Program par
+
+#
+# Options for Post Par Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_par_trce
+-e 3; # Produce error report limited to 3 items per constraint
+#-o .twr; # Output trace report file
+-xml .twx; # Output XML version of the timing report
+#-tsi .tsi; # Produce Timing Specification Interaction report
+.ncd; # Input placed and routed ncd
+.pcf; # Physical constraints file
+END Program post_par_trce
+
+
Index: trunk/systems/test_system_sim/wb_err_and_rst/etc/download.cmd
===================================================================
--- trunk/systems/test_system_sim/wb_err_and_rst/etc/download.cmd (nonexistent)
+++ trunk/systems/test_system_sim/wb_err_and_rst/etc/download.cmd (revision 2)
@@ -0,0 +1,6 @@
+setMode -bscan
+setCable -p auto
+identify
+assignfile -p 4 -file implementation/download.bit
+program -p 4
+quit
Index: trunk/systems/test_system_sim/Makefile
===================================================================
--- trunk/systems/test_system_sim/Makefile (nonexistent)
+++ trunk/systems/test_system_sim/Makefile (revision 2)
@@ -0,0 +1,144 @@
+CUR_DIR=$(shell pwd)
+
+
+# IP-Library
+LIB_DIR=$(CUR_DIR)/../EDK_Libs
+# Wishbone Library
+WISHBONE_LIB_DIR=$(LIB_DIR)/WishboneIPLib
+# VHDL compile flags
+VHDL_CFLAGS="-novopt -93 -error -check_synthesis -defercheck -deferSubpgmCheck -rangecheck "
+
+# not used at the moment
+#PLB_BFM_LIB_DIR=/opt/Xilinx/11.1/EDK/hw/XilinxBFMinterface
+
+## Uncomment this, if you are using cygwin in a windows environment
+# (Check the paths in common/Makefile ->> vmap entries)
+#ENVIRONMENT="cygwin"
+
+
+
+
+all: sim assert.log simulation.log error.log
+
+.PHONY: sim assert.log simulation.log error.log
+
+newsim: cleansim sim
+
+sim: t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
+
+
+TEST_CASES+="32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write"
+TEST_CASES+="32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw"
+TEST_CASES+="32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw"
+TEST_CASES+="32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write"
+TEST_CASES+="32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write"
+TEST_CASES+="32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw"
+TEST_CASES+="32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw"
+TEST_CASES+="32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write"
+TEST_CASES+="wb_retries/simulation/test_cases/simple_retries"
+TEST_CASES+="wb_err_and_rst/simulation/test_cases/errors_and_rst"
+TEST_CASES+="wb_err_and_rst/simulation/test_cases/timeouts"
+TEST_CASES+="wb_irqs/simulation/test_cases/irq_tests"
+TEST_CASES+="simple/simulation/test_cases/stressful_read_write"
+
+
+t1:
+ $(MAKE) -C "32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+t2:
+ $(MAKE) -C "32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+t3:
+ $(MAKE) -C "32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+t4:
+ $(MAKE) -C "32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+
+t5:
+ $(MAKE) -C "32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+t6:
+ $(MAKE) -C "32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+t7:
+ $(MAKE) -C "32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+t8:
+ $(MAKE) -C "32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+t9:
+ $(MAKE) -C "wb_retries/simulation/test_cases/simple_retries" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+t10:
+ $(MAKE) -C "wb_err_and_rst/simulation/test_cases/errors_and_rst" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+t11:
+ $(MAKE) -C "wb_err_and_rst/simulation/test_cases/timeouts" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+t12:
+ $(MAKE) -C "wb_irqs/simulation/test_cases/irq_tests" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+t13:
+ $(MAKE) -C "simple/simulation/test_cases/stressful_read_write" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+
+
+
+compile:
+ $(MAKE) -C $(CUR_DIR)/32bit_on_128bitPLB_syn/simulation compile LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) VHDL_CFLAGS=$(VHDL_CFLAGS);
+ $(MAKE) -C $(CUR_DIR)/32bit_on_128bitPLB_asyn/simulation compile LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) VHDL_CFLAGS=$(VHDL_CFLAGS);
+ $(MAKE) -C $(CUR_DIR)/wb_retries/simulation compile LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) VHDL_CFLAGS=$(VHDL_CFLAGS);
+ $(MAKE) -C $(CUR_DIR)/wb_err_and_rst/simulation compile LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) VHDL_CFLAGS=$(VHDL_CFLAGS);
+ $(MAKE) -C $(CUR_DIR)/wb_irqs/simulation compile LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) VHDL_CFLAGS=$(VHDL_CFLAGS);
+ $(MAKE) -C $(CUR_DIR)/simple/simulation compile LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) VHDL_CFLAGS=$(VHDL_CFLAGS);
+
+
+clean:
+ $(MAKE) -C $(CUR_DIR)/32bit_on_128bitPLB_syn/simulation clean
+ $(MAKE) -C $(CUR_DIR)/32bit_on_128bitPLB_asyn/simulation clean
+ $(MAKE) -C $(CUR_DIR)/wb_retries/simulation clean
+ $(MAKE) -C $(CUR_DIR)/wb_err_and_rst/simulation clean
+ $(MAKE) -C $(CUR_DIR)/wb_irqs/simulation clean
+ $(MAKE) -C $(CUR_DIR)/simple/simulation clean
+ @for i in $(TEST_CASES); do \
+ $(MAKE) -C $$i clean; \
+ done;
+
+cleansim:
+ @for i in $(TEST_CASES); do \
+ $(MAKE) -C $$i clean; \
+ done;
+ rm -rf error.log assert.log simulation.log
+
+
+
+simulation.log: sim
+ @rm -rf simulation.log
+ @for i in $(TEST_CASES); do \
+ echo "------------------------------------------------------" >> simulation.log; \
+ echo "---- $$i ----" >> simulation.log; \
+ echo "------------------------------------------------------" >> simulation.log; \
+ cat $$i/result/simulation.log >> simulation.log; \
+ done;
+
+error.log: sim
+ @rm -rf error.log
+ @for i in $(TEST_CASES); do \
+ echo "------------------------------------------------------" >> error.log; \
+ echo "---- $$i ----" >> error.log; \
+ echo "------------------------------------------------------" >> error.log; \
+ cat $$i/result/error.log >> error.log; \
+ done;
+
+
+assert.log: sim
+ @rm -rf assert.log
+ @for i in $(TEST_CASES); do \
+ echo "------------------------------------------------------" >> assert.log; \
+ echo "---- $$i ----" >> assert.log; \
+ echo "------------------------------------------------------" >> assert.log; \
+ cat $$i/result/assert.log >> assert.log; \
+ done;
+
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/testram_v1_00_a/hdl/vhdl/testram.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/testram_v1_00_a/hdl/vhdl/testram.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/testram_v1_00_a/hdl/vhdl/testram.vhd (revision 2)
@@ -0,0 +1,583 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+
+
+entity testram is
+
+ generic(
+ MEM_FILE_NAME : string := "onchip_ram.bin";
+ WB_ADR_W : integer := 32;
+ WB_DAT_W : integer := 32;
+ RAM_ADR_W : integer := 15;
+
+ RD_DELAY : natural := 1;
+ WR_DELAY : natural := 1;
+ WITH_ERR_OR_RTY : std_logic_vector( 1 downto 0 ) := "00"; -- "00" = none, "01" = err, "10" = rty", "11" = none
+ ERR_RTY_INTERVAL : integer := 0
+ );
+ port(
+
+ wb_clk_i : in std_logic;
+ wb_rst_i : in std_logic;
+ wb_adr_i : in std_logic_vector( WB_ADR_W-1 downto 0 );
+ wb_stb_i : in std_logic;
+ wb_cyc_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_sel_i : in std_logic_vector( (WB_ADR_W/8)-1 downto 0 );
+ wb_dat_i : in std_logic_vector( WB_DAT_W-1 downto 0 );
+ wb_dat_o : out std_logic_vector( WB_DAT_W-1 downto 0 );
+ wb_ack_o : out std_logic;
+ wb_err_o : out std_logic;
+ wb_rty_o : out std_logic
+ );
+
+end entity testram;
+
+
+
+architecture IMP of testram is
+
+ type ram_type is array( integer range <> ) of std_logic_vector( WB_DAT_W-1 downto 0 );
+
+ procedure load_ram(signal data_word : inout ram_type ) is
+-- file ram_file : text open read_mode is MEM_FILE_NAME;
+
+ type CHRF is file of character;
+ file char_file : CHRF;
+
+
+ variable cbuf : character;
+ variable lbuf : line;
+ variable byte_index : integer := 0;
+ variable line_index : integer := 0;
+ variable data : std_logic_vector( WB_DAT_W-1 downto 0 );
+ begin
+ file_open( char_file, MEM_FILE_NAME, read_mode );
+
+
+
+
+ while not endfile( char_file ) and line_index < ( 2**RAM_ADR_W ) loop
+
+ for i in 0 to ( WB_DAT_W/8)-1 loop
+ read( char_file, cbuf );
+ data_word( line_index )( (i+1)*8-1 downto i*8 ) <= std_logic_vector( to_unsigned( character'pos(cbuf), 8 ) );
+ if endfile( char_file ) then
+ exit;
+ end if;
+ end loop;
+ line_index := line_index+1;
+
+ end loop;
+
+ while line_index < (2**RAM_ADR_W) loop
+ data_word( line_index ) <= (others => '0' );
+ line_index := line_index + 1;
+ end loop;
+
+
+ end procedure;
+
+
+
+ function log_2( x : positive ) return natural is
+
+ begin
+ if x <= 1 then
+ return 0;
+ else
+ return 1 + log_2( x/2 );
+ end if;
+
+ end function;
+
+
+ --
+ -- Returns the maximum of x and y. If x and y are less than 2, 2 is returned.
+ --
+ function get_delay_count_vsize( x,y : natural ) return positive is
+ variable temp : natural;
+ begin
+ if x > y then
+ temp := x;
+ else
+ temp := y;
+ end if;
+
+ if temp < 2 then
+ temp := 2;
+ end if;
+ return temp;
+ end function;
+
+
+
+ function vec_size ( x : natural ) return natural is
+ variable temp, i : natural;
+ begin
+
+ temp := 0;
+ i := 0;
+ while temp <= x loop
+ i := i + 1;
+ temp := 2**i;
+ end loop;
+ return i;
+
+ end function vec_size;
+
+
+ constant test_a : natural := vec_size( RD_DELAY );
+ constant test_b : natural := vec_size( WR_DELAY );
+
+ constant DELAY_COUNT_SIZE : natural := get_delay_count_vsize( vec_size( RD_DELAY ), vec_size( WR_DELAY ) );
+ constant DELAY_COUNT_ZERO : std_logic_vector( DELAY_COUNT_SIZE-1 downto 0 ) := ( others => '0' );
+
+
+ constant ERR_RTY_COUNT_SIZE : natural := vec_size( ERR_RTY_INTERVAL );
+ constant ERR_RTY_COUNT_ZERO : std_logic_vector( ERR_RTY_COUNT_SIZE-1 downto 0 ) := ( others => '0' );
+
+ --
+ -- RAM_ADR_LB (low bit) and RAM_ADR_HB (high bit):
+ -- => used select the address lines, which we use to address the ram
+ --
+ -- eg. WB_ADR_W = 64 and RAM_ADR_W = 5:
+ --
+ -- We don't want to use the lower 3 bit, because one ram-line contains 8 byte
+ -- RAM_ADR_LB = 3
+ -- RAM_ADR_HB = 7
+ --
+ -- ==>> 7 downto 3 = 5 address line, which address 2**5 * 8 byte = 32 * 8 byte
+ --
+ constant RAM_ADR_LB : integer := log_2( WB_ADR_W/8);
+ constant RAM_ADR_HB : integer := RAM_ADR_LB + RAM_ADR_W - 1;
+
+
+ signal ram : ram_type(2**RAM_ADR_W -1 downto 0);
+ signal w_ack, r_ack : std_logic := '0';
+ signal w_err, r_err : std_logic := '0';
+ signal w_rty, r_rty : std_logic := '0';
+ signal r_delay_count : std_logic_vector( DELAY_COUNT_SIZE -1 downto 0 ) := ( others => '0' );
+ signal w_delay_count : std_logic_vector( DELAY_COUNT_SIZE -1 downto 0 ) := ( others => '0' );
+ signal ram_adr : std_logic_vector( RAM_ADR_W-1 downto 0 ) := ( others => '0' );
+ signal ram_line : std_logic_vector( WB_DAT_W-1 downto 0 ) := ( others => '0' );
+
+ signal err_rty_count_r : std_logic_vector( ERR_RTY_COUNT_SIZE-1 downto 0 );
+ signal err_rty_count_w : std_logic_vector( ERR_RTY_COUNT_SIZE-1 downto 0 );
+ constant err_rty_zero : std_logic_vector( ERR_RTY_COUNT_SIZE-1 downto 0 ) := ( others => '0' );
+
+
+
+begin
+
+
+ with wb_rst_i select
+ ram_adr <= wb_adr_i( RAM_ADR_HB downto RAM_ADR_LB ) when '0',
+ ( others => '0' ) when others;
+
+ gen_read_ack1 : if RD_DELAY > 1 generate
+
+ -- generate read ack after a delay
+ read_ack_p1 : process( wb_clk_i, wb_rst_i ) begin
+ if wb_rst_i = '1' then
+
+ r_rty <= '0';
+ r_ack <= '0';
+ r_err <= '0';
+ r_delay_count <= std_logic_vector( to_unsigned( RD_DELAY, DELAY_COUNT_SIZE ) );
+ err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
+
+ elsif wb_clk_i'event and wb_clk_i = '1' then
+
+ r_delay_count <= std_logic_vector( to_unsigned( RD_DELAY, DELAY_COUNT_SIZE ) );
+
+ if wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0'
+ and not ( r_ack = '1' or r_rty = '1' or r_err = '1' ) then
+
+ r_delay_count <= r_delay_count -1;
+
+ if r_delay_count = DELAY_COUNT_ZERO then
+
+ r_delay_count <= std_logic_vector( to_unsigned( RD_DELAY, DELAY_COUNT_SIZE ) );
+ if err_rty_count_r = ERR_RTY_COUNT_ZERO then
+ err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
+ else
+ err_rty_count_r <= err_rty_count_r - 1;
+ end if;
+ end if;
+ end if;
+
+
+
+ if r_delay_count = DELAY_COUNT_ZERO and wb_cyc_i = '1' and wb_stb_i = '1' then
+ err_rty_count_r <= err_rty_count_r - 1;
+
+ if ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then
+ r_rty <= '1';
+ r_ack <= '0';
+ r_err <= '0';
+ elsif ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then
+ r_rty <= '0';
+ r_ack <= '0';
+ r_err <= '1';
+ else
+ r_rty <= '0';
+ r_ack <= '1';
+ r_err <= '0';
+ end if;
+
+ else
+ r_rty <= '0';
+ r_ack <= '0';
+ r_err <= '0';
+ end if;
+
+ end if;
+ end process;
+
+ end generate;
+
+ gen_read_ack2 : if RD_DELAY = 1 generate
+
+ -- generate read ack after a delay
+ read_ack_p2 : process( wb_clk_i, wb_rst_i ) begin
+
+ if wb_rst_i = '1' then
+
+ r_ack <= '0';
+ r_err <= '0';
+ r_rty <= '0';
+ err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
+
+ elsif wb_clk_i'event and wb_clk_i = '1' then
+
+ if ( wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0'
+ and not (r_ack = '1' or r_rty = '1' or r_err = '1' ) ) then
+
+ if err_rty_count_r = ERR_RTY_COUNT_ZERO then
+ err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
+ else
+ err_rty_count_r <= err_rty_count_r - 1;
+ end if;
+
+ if ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then
+ r_rty <= '1';
+ r_ack <= '0';
+ r_err <= '0';
+ elsif ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then
+ r_rty <= '0';
+ r_ack <= '0';
+ r_err <= '1';
+ else
+ r_rty <= '0';
+ r_ack <= '1';
+ r_err <= '0';
+ end if;
+
+ else
+ r_ack <= '0';
+ r_err <= '0';
+ r_rty <= '0';
+ end if;
+
+ end if;
+
+ end process;
+
+ end generate;
+
+
+
+ gen_read_ack3 : if RD_DELAY = 0 generate
+
+ read_ack_p3 : process( wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, err_rty_count_r ) begin
+ if wb_rst_i = '1' then
+ err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
+ elsif wb_clk_i'event and wb_clk_i = '1' then
+ if ( wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0' ) then
+ if err_rty_count_r = ERR_RTY_COUNT_ZERO then
+ err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
+ else
+ err_rty_count_r <= err_rty_count_r - 1;
+ end if;
+ end if;
+ end if;
+
+ r_err <= '0';
+ r_rty <= '0';
+ r_ack <= '0';
+
+ if ( wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0' ) then
+
+ if ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then
+ r_rty <= '1';
+ elsif ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then
+ r_err <= '1';
+ else
+ r_ack <= '1';
+ end if;
+
+ end if;
+
+
+
+ end process;
+
+
+ end generate;
+
+
+
+ gen_write_ack1 : if WR_DELAY > 1 generate
+
+ -- generate write ack after a delay
+ -- and write byte-wise data to ram, depending on select
+ write_ack_p1 : process( wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, w_ack ) begin
+
+ if wb_rst_i = '1' then
+ load_ram( ram );
+ w_err <= '0';
+ w_rty <= '0';
+ w_ack <= '0';
+ w_delay_count <= std_logic_vector( to_unsigned( WR_DELAY, DELAY_COUNT_SIZE ) );
+ err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
+
+ elsif wb_clk_i'event and wb_clk_i = '1' then
+
+ w_delay_count <= std_logic_vector( to_unsigned( WR_DELAY, DELAY_COUNT_SIZE ) );
+
+ if wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1'
+ and not ( w_ack = '1' or w_err = '1' or w_rty = '1' ) then
+ w_delay_count <= w_delay_count -1;
+
+ if w_delay_count = DELAY_COUNT_ZERO then
+ w_delay_count <= std_logic_vector( to_unsigned( WR_DELAY, DELAY_COUNT_SIZE ) );
+ if err_rty_count_w = ERR_RTY_COUNT_ZERO then
+ err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
+ else
+ err_rty_count_w <= err_rty_count_w - 1;
+ end if;
+ end if;
+ end if;
+
+ if w_delay_count = DELAY_COUNT_ZERO and wb_cyc_i = '1' and wb_stb_i = '1' then
+
+ err_rty_count_w <= err_rty_count_w - 1;
+
+ if ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then
+ w_err <= '0';
+ w_rty <= '1';
+ w_ack <= '0';
+ elsif ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then
+ w_err <= '1';
+ w_rty <= '0';
+ w_ack <= '0';
+ else
+ w_err <= '0';
+ w_rty <= '0';
+ w_ack <= '1';
+ for i in 0 to ( WB_DAT_W/8)-1 loop
+ if ( wb_sel_i(i) = '1' ) then
+ ram( conv_integer( ram_adr ) )( (i+1)*8-1 downto i*8 ) <= wb_dat_i( (i+1)*8-1 downto i*8 );
+ end if;
+ end loop;
+ end if;
+
+ else
+ w_err <= '0';
+ w_rty <= '0';
+ w_ack <= '0';
+ end if;
+
+ end if;
+ end process;
+
+ end generate;
+
+
+ gen_write_ack2 : if WR_DELAY = 1 generate
+
+ -- generate write ack after a delay
+ -- and write byte-wise data to ram, depending on select
+ write_ack_p2 : process( wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, w_ack, w_err, w_rty ) begin
+
+ if wb_rst_i = '1' then
+
+ load_ram( ram );
+ err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
+ w_err <= '0';
+ w_rty <= '0';
+ w_ack <= '0';
+
+ elsif wb_clk_i'event and wb_clk_i = '1' then
+
+ if wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1'
+ and not ( w_ack = '1' or w_err = '1' or w_rty = '1' ) then
+
+ if err_rty_count_w = ERR_RTY_COUNT_ZERO then
+ err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
+ else
+ err_rty_count_w <= err_rty_count_w - 1;
+ end if;
+
+
+
+ if ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then
+ w_err <= '0';
+ w_rty <= '1';
+ w_ack <= '0';
+ elsif ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then
+ w_err <= '1';
+ w_rty <= '0';
+ w_ack <= '0';
+ else
+ w_err <= '0';
+ w_rty <= '0';
+ w_ack <= '1';
+ for i in 0 to ( WB_DAT_W/8)-1 loop
+ if ( wb_sel_i(i) = '1' ) then
+ ram( conv_integer( ram_adr ) )( (i+1)*8-1 downto i*8 ) <= wb_dat_i( (i+1)*8-1 downto i*8 );
+ end if;
+ end loop;
+ end if;
+ else
+ w_err <= '0';
+ w_rty <= '0';
+ w_ack <= '0';
+ end if;
+
+ end if;
+
+
+
+
+ end process;
+
+ end generate;
+
+
+
+ gen_write_ack3 : if WR_DELAY = 0 generate
+
+
+ write_ack_p3 : process( wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, err_rty_count_w ) begin
+
+ if wb_rst_i = '1' then
+ load_ram( ram );
+ err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
+ elsif wb_clk_i = '1' and wb_clk_i'event then
+
+ if w_ack = '1' or w_rty = '1' or w_err = '1' then
+ if err_rty_count_w = ERR_RTY_COUNT_ZERO then
+ err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
+ else
+ err_rty_count_w <= err_rty_count_w - 1;
+ end if;
+ end if;
+
+ if w_ack = '1' then
+
+ for i in 0 to ( WB_DAT_W/8)-1 loop
+ if ( wb_sel_i(i) = '1' ) then
+ ram( conv_integer( ram_adr ) )( (i+1)*8-1 downto i*8 ) <= wb_dat_i( (i+1)*8-1 downto i*8 );
+ end if;
+ end loop;
+ end if;
+ end if;
+
+
+ w_err <= '0';
+ w_rty <= '0';
+ w_ack <= '0';
+
+
+ if ( wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1' ) then
+
+ if ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then
+ w_rty <= '1';
+ elsif ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then
+ w_err <= '1';
+ else
+ w_ack <= '1';
+ end if;
+
+ end if;
+
+
+
+
+ end process;
+
+ end generate;
+
+
+
+ -- assign byte-wise ram output, depending on select line
+ ram_line <= ram( conv_integer( ram_adr ) );
+ output_loop : for i in 0 to WB_DAT_W/8-1 generate
+ with wb_sel_i( i ) select
+ wb_dat_o( (i+1)*8-1 downto i*8 ) <= ram_line( (i+1)*8-1 downto i*8 ) when '1',
+ "00000000" when others;
+ end generate;
+
+
+
+ wb_ack_o <= w_ack or r_ack;
+ wb_err_o <= w_err or r_err;
+ wb_rty_o <= w_rty or r_rty;
+
+
+
+end architecture IMP;
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/testram_v1_00_a/data/testram_v2_1_0.pao
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/testram_v1_00_a/data/testram_v2_1_0.pao (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/testram_v1_00_a/data/testram_v2_1_0.pao (revision 2)
@@ -0,0 +1,3 @@
+
+lib testram_v1_00_a testram vhdl
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/testram_v1_00_a/data/testram_v2_1_0.mpd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/testram_v1_00_a/data/testram_v2_1_0.mpd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/testram_v1_00_a/data/testram_v2_1_0.mpd (revision 2)
@@ -0,0 +1,38 @@
+
+
+BEGIN testram
+
+OPTION IPTYPE = PERIPHERAL
+OPTION IMP_NETLIST = TRUE
+OPTION HDL = VHDL
+OPTION IP_GROUP = Memory and Memory Controller:MICROBLAZE
+OPTION DESC = Test-RAM
+
+BUS_INTERFACE BUS = SWB, BUS_STD = WB, BUS_TYPE = SLAVE
+
+
+
+PARAMETER MEM_FILE_NAME = "onchip_ram.bin", DT = STRING
+PARAMETER WB_ADR_W = 32, DT = INTEGER, BUS=SWB, ASSIGNMENT=CONSTANT
+PARAMETER WB_DAT_W = 32, DT = INTEGER, BIS=SWB, ASSIGNMENT=CONSTANT
+PARAMETER RAM_ADR_W = 15, DT = INTEGER
+PARAMETER RD_DELAY = 1, DT = INTEGER
+PARAMETER WR_DELAY = 1, DT = INTEGER
+
+PARAMETER WITH_ERR_OR_RTY = 0b00, VALUES=( 0b00=none, 0b01=err, 0b10=rty, 0b11=none), DT = STD_LOGIC_VECTOR
+PARAMETER ERR_RTY_INTERVAL = 0, DT = INTEGER
+
+PORT wb_clk_i = "", DIR = I, SIGIS = CLK
+PORT wb_rst_i = "", DIR = I, SIGIS = RST
+PORT wb_adr_i = wb_s_adr_o, DIR = I, VEC = [ WB_ADR_W-1 : 0 ], BUS = SWB
+PORT wb_stb_i = wb_s_stb_o, DIR = I, BUS = SWB
+PORT wb_cyc_i = wb_s_cyc_o, DIR = I, BUS = SWB
+PORT wb_we_i = wb_s_we_o, DIR = I, BUS = SWB
+PORT wb_sel_i = wb_s_sel_o, DIR = I, VEC = [ WB_DAT_W/8-1 : 0 ], BUS = SWB
+PORT wb_dat_i = wb_s_dat_o, DIR = I, VEC = [ WB_DAT_W-1 : 0 ], BUS = SWB
+PORT wb_dat_o = wb_s_dat_i, DIR = O, VEC = [ WB_DAT_W-1 : 0 ], BUS = SWB
+PORT wb_ack_o = wb_s_ack_i, DIR = O, BUS = SWB
+PORT wb_err_o = wb_s_err_i, DIR = O, BUS = SWB
+PORT wb_rty_o = wb_s_rty_i, DIR = O, BUS = SWB
+
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_defines.v
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_defines.v (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_defines.v (revision 2)
@@ -0,0 +1,42 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// WISHBONE Connection ShareBus Definitions ////
+//// ////
+//// ////
+//// Author: Johny Chi ////
+//// chisuhua@yahoo.com.cn ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+/// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+
+`timescale 1ns / 10ps
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_wrapper.v
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_wrapper.v (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_wrapper.v (revision 2)
@@ -0,0 +1,331 @@
+
+
+
+
+module wb_conbus_wrapper(
+
+ wb_clk_i,
+ wb_rst_i,
+
+ wb_m_dat_i,
+ wb_m_dat_o,
+ wb_m_adr_i,
+ wb_m_sel_i,
+ wb_m_we_i,
+ wb_m_cyc_i,
+ wb_m_stb_i,
+ wb_m_ack_o,
+ wb_m_err_o,
+ wb_m_rty_o,
+ wb_m_cab_i,
+
+ wb_s_dat_i,
+ wb_s_dat_o,
+ wb_s_adr_o,
+ wb_s_sel_o,
+ wb_s_we_o,
+ wb_s_cyc_o,
+ wb_s_stb_o,
+ wb_s_ack_i,
+ wb_s_err_i,
+ wb_s_rty_i,
+ wb_s_cab_o
+
+
+);
+
+
+
+////// MUST BE CONSTANT: DON'T CHANGE THIS!! ///
+parameter WB_DAT_W = 32; // Data bus Width
+parameter WB_ADR_W = 32; // Address bus Width
+parameter wb_num_masters = 8; // number of masters
+parameter wb_num_slaves = 8; // number of slavers
+/////////
+parameter wb_s0_addr_w = 4 ; // slave 0 address decode width
+parameter wb_s0_addr = 4'h0; // slave 0 address
+parameter wb_s1_addr_w = 4 ; // slave 1 address decode width
+parameter wb_s1_addr = 4'h1; // slave 1 address
+parameter wb_s27_addr_w = 8 ; // slave 2 to slave 7 address decode width
+parameter wb_s2_addr = 8'h92; // slave 2 address
+parameter wb_s3_addr = 8'h93; // slave 3 address
+parameter wb_s4_addr = 8'h94; // slave 4 address
+parameter wb_s5_addr = 8'h95; // slave 5 address
+parameter wb_s6_addr = 8'h96; // slave 6 address
+parameter wb_s7_addr = 8'h97; // slave 7 address
+
+
+
+input wb_clk_i;
+input wb_rst_i;
+input [(WB_DAT_W*wb_num_masters)-1 : 0 ] wb_m_dat_i;
+output [WB_DAT_W-1 : 0 ] wb_m_dat_o;
+input [(WB_ADR_W*wb_num_masters)-1 : 0 ] wb_m_adr_i;
+input [(WB_DAT_W/8*wb_num_masters)-1 : 0 ] wb_m_sel_i;
+input [wb_num_masters-1 : 0 ] wb_m_we_i;
+input [wb_num_masters-1 : 0 ] wb_m_cyc_i;
+input [wb_num_masters-1 : 0 ] wb_m_stb_i;
+output [wb_num_masters-1 : 0 ] wb_m_ack_o;
+output [wb_num_masters-1 : 0 ] wb_m_err_o;
+output [wb_num_masters-1 : 0 ] wb_m_rty_o;
+input [wb_num_masters-1 : 0 ] wb_m_cab_i;
+
+input [WB_DAT_W*wb_num_slaves-1 : 0 ] wb_s_dat_i;
+output [WB_DAT_W-1 : 0 ] wb_s_dat_o;
+output [WB_ADR_W-1 : 0 ] wb_s_adr_o;
+output [WB_DAT_W/8-1 : 0 ] wb_s_sel_o;
+output wb_s_we_o;
+output wb_s_cyc_o;
+output [wb_num_slaves-1 : 0 ] wb_s_stb_o;
+input [wb_num_slaves-1 : 0 ] wb_s_ack_i;
+input [wb_num_slaves-1 : 0 ] wb_s_err_i;
+input [wb_num_slaves-1 : 0 ] wb_s_rty_i;
+output wb_s_cab_o;
+
+
+
+
+
+
+
+wb_conbus_top #(
+ .s0_addr_w ( wb_s0_addr_w ),
+ .s0_addr ( wb_s0_addr ),
+ .s1_addr_w ( wb_s1_addr_w ),
+ .s1_addr ( wb_s1_addr ),
+ .s27_addr_w ( wb_s27_addr_w ),
+ .s2_addr ( wb_s2_addr ),
+ .s3_addr ( wb_s3_addr ),
+ .s4_addr ( wb_s4_addr ),
+ .s5_addr ( wb_s5_addr ),
+ .s6_addr ( wb_s6_addr ),
+ .s7_addr ( wb_s7_addr )
+ )
+wb_conbus_top(
+
+ .clk_i( wb_clk_i ),
+ .rst_i( wb_rst_i ),
+
+ // Master 0 Interface
+ .m0_dat_i( wb_m_dat_i[ (0+1)*WB_DAT_W-1 : 0*WB_DAT_W ] ),
+ .m0_dat_o( wb_m_dat_o ),
+ .m0_adr_i( wb_m_adr_i[ (0+1)*WB_ADR_W-1 : 0*WB_ADR_W ] ),
+ .m0_sel_i( wb_m_sel_i[ (0+1)*WB_DAT_W/8-1 : 0*WB_DAT_W/8] ),
+ .m0_we_i ( wb_m_we_i[0] ),
+ .m0_cyc_i( wb_m_cyc_i[0] ),
+ .m0_stb_i( wb_m_stb_i[0] ),
+ .m0_ack_o( wb_m_ack_o[0] ),
+ .m0_err_o( wb_m_err_o[0] ),
+ .m0_rty_o( wb_m_rty_o[0] ),
+ .m0_cab_i( wb_m_cab_i[0] ),
+
+
+ // Master 1 Interface
+ .m1_dat_i( wb_m_dat_i[ (1+1)*WB_DAT_W-1 : 1*WB_DAT_W ] ),
+ .m1_dat_o( ),
+ .m1_adr_i( wb_m_adr_i[ (1+1)*WB_ADR_W-1 : 1*WB_ADR_W ] ),
+ .m1_sel_i( wb_m_sel_i[ (1+1)*WB_DAT_W/8-1 : 1*WB_DAT_W/8] ),
+ .m1_we_i ( wb_m_we_i[1] ),
+ .m1_cyc_i( wb_m_cyc_i[1] ),
+ .m1_stb_i( wb_m_stb_i[1] ),
+ .m1_ack_o( wb_m_ack_o[1] ),
+ .m1_err_o( wb_m_err_o[1] ),
+ .m1_rty_o( wb_m_rty_o[1] ),
+ .m1_cab_i( wb_m_cab_i[1] ),
+
+
+ // Master 2 Interface
+ .m2_dat_i( wb_m_dat_i[ (2+1)*WB_DAT_W-1 : 2*WB_DAT_W ] ),
+ .m2_dat_o( ),
+ .m2_adr_i( wb_m_adr_i[ (2+1)*WB_ADR_W-1 : 2*WB_ADR_W ] ),
+ .m2_sel_i( wb_m_sel_i[ (2+1)*WB_DAT_W/8-1 : 2*WB_DAT_W/8] ),
+ .m2_we_i ( wb_m_we_i[2] ),
+ .m2_cyc_i( wb_m_cyc_i[2] ),
+ .m2_stb_i( wb_m_stb_i[2] ),
+ .m2_ack_o( wb_m_ack_o[2] ),
+ .m2_err_o( wb_m_err_o[2] ),
+ .m2_rty_o( wb_m_rty_o[2] ),
+ .m2_cab_i( wb_m_cab_i[2] ),
+
+
+ // Master 3 Interface
+ .m3_dat_i( wb_m_dat_i[ (3+1)*WB_DAT_W-1 : 3*WB_DAT_W ] ),
+ .m3_dat_o( ),
+ .m3_adr_i( wb_m_adr_i[ (3+1)*WB_ADR_W-1 : 3*WB_ADR_W ] ),
+ .m3_sel_i( wb_m_sel_i[ (3+1)*WB_DAT_W/8-1 : 3*WB_DAT_W/8] ),
+ .m3_we_i ( wb_m_we_i[3] ),
+ .m3_cyc_i( wb_m_cyc_i[3] ),
+ .m3_stb_i( wb_m_stb_i[3] ),
+ .m3_ack_o( wb_m_ack_o[3] ),
+ .m3_err_o( wb_m_err_o[3] ),
+ .m3_rty_o( wb_m_rty_o[3] ),
+ .m3_cab_i( wb_m_cab_i[3] ),
+
+
+ // Master 4 Interface
+ .m4_dat_i( wb_m_dat_i[ (4+1)*WB_DAT_W-1 : 4*WB_DAT_W ] ),
+ .m4_dat_o( ),
+ .m4_adr_i( wb_m_adr_i[ (4+1)*WB_ADR_W-1 : 4*WB_ADR_W ] ),
+ .m4_sel_i( wb_m_sel_i[ (4+1)*WB_DAT_W/8-1 : 4*WB_DAT_W/8] ),
+ .m4_we_i ( wb_m_we_i[4] ),
+ .m4_cyc_i( wb_m_cyc_i[4] ),
+ .m4_stb_i( wb_m_stb_i[4] ),
+ .m4_ack_o( wb_m_ack_o[4] ),
+ .m4_err_o( wb_m_err_o[4] ),
+ .m4_rty_o( wb_m_rty_o[4] ),
+ .m4_cab_i( wb_m_cab_i[4] ),
+
+
+ // Master 5 Interface
+ .m5_dat_i( wb_m_dat_i[ (5+1)*WB_DAT_W-1 : 5*WB_DAT_W ] ),
+ .m5_dat_o( ),
+ .m5_adr_i( wb_m_adr_i[ (5+1)*WB_ADR_W-1 : 5*WB_ADR_W ] ),
+ .m5_sel_i( wb_m_sel_i[ (5+1)*WB_DAT_W/8-1 : 5*WB_DAT_W/8] ),
+ .m5_we_i ( wb_m_we_i[5] ),
+ .m5_cyc_i( wb_m_cyc_i[5] ),
+ .m5_stb_i( wb_m_stb_i[5] ),
+ .m5_ack_o( wb_m_ack_o[5] ),
+ .m5_err_o( wb_m_err_o[5] ),
+ .m5_rty_o( wb_m_rty_o[5] ),
+ .m5_cab_i( wb_m_cab_i[5] ),
+
+
+ // Master 6 Interface
+ .m6_dat_i( wb_m_dat_i[ (6+1)*WB_DAT_W-1 : 6*WB_DAT_W ] ),
+ .m6_dat_o( ),
+ .m6_adr_i( wb_m_adr_i[ (6+1)*WB_ADR_W-1 : 6*WB_ADR_W ] ),
+ .m6_sel_i( wb_m_sel_i[ (6+1)*WB_DAT_W/8-1 : 6*WB_DAT_W/8] ),
+ .m6_we_i ( wb_m_we_i[6] ),
+ .m6_cyc_i( wb_m_cyc_i[6] ),
+ .m6_stb_i( wb_m_stb_i[6] ),
+ .m6_ack_o( wb_m_ack_o[6] ),
+ .m6_err_o( wb_m_err_o[6] ),
+ .m6_rty_o( wb_m_rty_o[6] ),
+ .m6_cab_i( wb_m_cab_i[6] ),
+
+
+ // Master 7 Interface
+ .m7_dat_i( wb_m_dat_i[ (7+1)*WB_DAT_W-1 : 7*WB_DAT_W ] ),
+ .m7_dat_o( ),
+ .m7_adr_i( wb_m_adr_i[ (7+1)*WB_ADR_W-1 : 7*WB_ADR_W ] ),
+ .m7_sel_i( wb_m_sel_i[ (7+1)*WB_DAT_W/8-1 : 7*WB_DAT_W/8] ),
+ .m7_we_i ( wb_m_we_i[7] ),
+ .m7_cyc_i( wb_m_cyc_i[7] ),
+ .m7_stb_i( wb_m_stb_i[7] ),
+ .m7_ack_o( wb_m_ack_o[7] ),
+ .m7_err_o( wb_m_err_o[7] ),
+ .m7_rty_o( wb_m_rty_o[7] ),
+ .m7_cab_i( wb_m_cab_i[7] ),
+
+
+
+ // Slave 0 Interface
+ .s0_dat_i( wb_s_dat_i[ (0+1)*WB_DAT_W-1 : 0*WB_DAT_W ] ),
+ .s0_dat_o( wb_s_dat_o ),
+ .s0_adr_o( wb_s_adr_o ),
+ .s0_sel_o( wb_s_sel_o ),
+ .s0_we_o ( wb_s_we_o ),
+ .s0_cyc_o( wb_s_cyc_o ),
+ .s0_stb_o( wb_s_stb_o[0] ),
+ .s0_ack_i( wb_s_ack_i[0] ),
+ .s0_err_i( wb_s_err_i[0] ),
+ .s0_rty_i( wb_s_rty_i[0] ),
+ .s0_cab_o( wb_s_cab_o ),
+
+ // Slave 1 Interface
+ .s1_dat_i( wb_s_dat_i[ (1+1)*WB_DAT_W-1 : 1*WB_DAT_W ] ),
+ .s1_dat_o( ),
+ .s1_adr_o( ),
+ .s1_sel_o( ),
+ .s1_we_o ( ),
+ .s1_cyc_o( ),
+ .s1_stb_o( wb_s_stb_o[1] ),
+ .s1_ack_i( wb_s_ack_i[1] ),
+ .s1_err_i( wb_s_err_i[1] ),
+ .s1_rty_i( wb_s_rty_i[1] ),
+ .s1_cab_o( ),
+
+ // Slave 2 Interface
+ .s2_dat_i( wb_s_dat_i[ (2+1)*WB_DAT_W-1 : 2*WB_DAT_W ] ),
+ .s2_dat_o( ),
+ .s2_adr_o( ),
+ .s2_sel_o( ),
+ .s2_we_o ( ),
+ .s2_cyc_o( ),
+ .s2_stb_o( wb_s_stb_o[2] ),
+ .s2_ack_i( wb_s_ack_i[2] ),
+ .s2_err_i( wb_s_err_i[2] ),
+ .s2_rty_i( wb_s_rty_i[2] ),
+ .s2_cab_o( ),
+
+ // Slave 3 Interface
+ .s3_dat_i( wb_s_dat_i[ (3+1)*WB_DAT_W-1 : 3*WB_DAT_W ] ),
+ .s3_dat_o( ),
+ .s3_adr_o( ),
+ .s3_sel_o( ),
+ .s3_we_o ( ),
+ .s3_cyc_o( ),
+ .s3_stb_o( wb_s_stb_o[3] ),
+ .s3_ack_i( wb_s_ack_i[3] ),
+ .s3_err_i( wb_s_err_i[3] ),
+ .s3_rty_i( wb_s_rty_i[3] ),
+ .s3_cab_o( ),
+
+ // Slave 4 Interface
+ .s4_dat_i( wb_s_dat_i[ (4+1)*WB_DAT_W-1 : 4*WB_DAT_W ] ),
+ .s4_dat_o( ),
+ .s4_adr_o( ),
+ .s4_sel_o( ),
+ .s4_we_o ( ),
+ .s4_cyc_o( ),
+ .s4_stb_o( wb_s_stb_o[4] ),
+ .s4_ack_i( wb_s_ack_i[4] ),
+ .s4_err_i( wb_s_err_i[4] ),
+ .s4_rty_i( wb_s_rty_i[4] ),
+ .s4_cab_o( ),
+
+ // Slave 5 Interface
+ .s5_dat_i( wb_s_dat_i[ (5+1)*WB_DAT_W-1 : 5*WB_DAT_W ] ),
+ .s5_dat_o( ),
+ .s5_adr_o( ),
+ .s5_sel_o( ),
+ .s5_we_o ( ),
+ .s5_cyc_o( ),
+ .s5_stb_o( wb_s_stb_o[5] ),
+ .s5_ack_i( wb_s_ack_i[5] ),
+ .s5_err_i( wb_s_err_i[5] ),
+ .s5_rty_i( wb_s_rty_i[5] ),
+ .s5_cab_o( ),
+
+ // Slave 6 Interface
+ .s6_dat_i( wb_s_dat_i[ (6+1)*WB_DAT_W-1 : 6*WB_DAT_W ] ),
+ .s6_dat_o( ),
+ .s6_adr_o( ),
+ .s6_sel_o( ),
+ .s6_we_o ( ),
+ .s6_cyc_o( ),
+ .s6_stb_o( wb_s_stb_o[6] ),
+ .s6_ack_i( wb_s_ack_i[6] ),
+ .s6_err_i( wb_s_err_i[6] ),
+ .s6_rty_i( wb_s_rty_i[6] ),
+ .s6_cab_o( ),
+
+ // Slave 7 Interface
+ .s7_dat_i( wb_s_dat_i[ (7+1)*WB_DAT_W-1 : 7*WB_DAT_W ] ),
+ .s7_dat_o( ),
+ .s7_adr_o( ),
+ .s7_sel_o( ),
+ .s7_we_o ( ),
+ .s7_cyc_o( ),
+ .s7_stb_o( wb_s_stb_o[7] ),
+ .s7_ack_i( wb_s_ack_i[7] ),
+ .s7_err_i( wb_s_err_i[7] ),
+ .s7_rty_i( wb_s_rty_i[7] ),
+ .s7_cab_o( )
+
+);
+
+
+
+
+endmodule
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_top.v
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_top.v (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_top.v (revision 2)
@@ -0,0 +1,656 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// WISHBONE Connection Bus Top Level ////
+//// ////
+//// ////
+//// Author: Johny Chi ////
+//// chisuhua@yahoo.com.cn ////
+//// ////
+//// ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// Description
+// 1. Up to 8 masters and 8 slaves share bus Wishbone connection
+// 2. no priorty arbitor , 8 masters are processed in a round
+// robin way,
+// 3. if WB_USE_TRISTATE was defined, the share bus is a tristate
+// bus, and use less logic resource.
+// 4. wb_conbus was synthesis to XC2S100-5-PQ208 using synplify,
+// Max speed >60M , and 374 SLICE if using Multiplexor bus
+// or 150 SLICE if using tri-state bus.
+//
+//`include "wb_conbus_defines.v"
+`define dw 32 // Data bus Width
+`define aw 32 // Address bus Width
+`define sw `dw / 8 // Number of Select Lines
+`define mbusw `aw + `sw + `dw +4 //address width + byte select width + dat width + cyc + we + stb +cab , input from master interface
+`define sbusw 3 // ack + err + rty, input from slave interface
+`define mselectw 8 // number of masters
+`define sselectw 8 // number of slavers
+
+//`define WB_USE_TRISTATE
+
+
+module wb_conbus_top(
+ clk_i, rst_i,
+
+ // Master 0 Interface
+ m0_dat_i, m0_dat_o, m0_adr_i, m0_sel_i, m0_we_i, m0_cyc_i,
+ m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o, m0_cab_i,
+
+ // Master 1 Interface
+ m1_dat_i, m1_dat_o, m1_adr_i, m1_sel_i, m1_we_i, m1_cyc_i,
+ m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o, m1_cab_i,
+
+ // Master 2 Interface
+ m2_dat_i, m2_dat_o, m2_adr_i, m2_sel_i, m2_we_i, m2_cyc_i,
+ m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o, m2_cab_i,
+
+ // Master 3 Interface
+ m3_dat_i, m3_dat_o, m3_adr_i, m3_sel_i, m3_we_i, m3_cyc_i,
+ m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o, m3_cab_i,
+
+ // Master 4 Interface
+ m4_dat_i, m4_dat_o, m4_adr_i, m4_sel_i, m4_we_i, m4_cyc_i,
+ m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o, m4_cab_i,
+
+ // Master 5 Interface
+ m5_dat_i, m5_dat_o, m5_adr_i, m5_sel_i, m5_we_i, m5_cyc_i,
+ m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o, m5_cab_i,
+
+ // Master 6 Interface
+ m6_dat_i, m6_dat_o, m6_adr_i, m6_sel_i, m6_we_i, m6_cyc_i,
+ m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o, m6_cab_i,
+
+ // Master 7 Interface
+ m7_dat_i, m7_dat_o, m7_adr_i, m7_sel_i, m7_we_i, m7_cyc_i,
+ m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o, m7_cab_i,
+
+ // Slave 0 Interface
+ s0_dat_i, s0_dat_o, s0_adr_o, s0_sel_o, s0_we_o, s0_cyc_o,
+ s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i, s0_cab_o,
+
+ // Slave 1 Interface
+ s1_dat_i, s1_dat_o, s1_adr_o, s1_sel_o, s1_we_o, s1_cyc_o,
+ s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i, s1_cab_o,
+
+ // Slave 2 Interface
+ s2_dat_i, s2_dat_o, s2_adr_o, s2_sel_o, s2_we_o, s2_cyc_o,
+ s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i, s2_cab_o,
+
+ // Slave 3 Interface
+ s3_dat_i, s3_dat_o, s3_adr_o, s3_sel_o, s3_we_o, s3_cyc_o,
+ s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i, s3_cab_o,
+
+ // Slave 4 Interface
+ s4_dat_i, s4_dat_o, s4_adr_o, s4_sel_o, s4_we_o, s4_cyc_o,
+ s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i, s4_cab_o,
+
+ // Slave 5 Interface
+ s5_dat_i, s5_dat_o, s5_adr_o, s5_sel_o, s5_we_o, s5_cyc_o,
+ s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i, s5_cab_o,
+
+ // Slave 6 Interface
+ s6_dat_i, s6_dat_o, s6_adr_o, s6_sel_o, s6_we_o, s6_cyc_o,
+ s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i, s6_cab_o,
+
+ // Slave 7 Interface
+ s7_dat_i, s7_dat_o, s7_adr_o, s7_sel_o, s7_we_o, s7_cyc_o,
+ s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i, s7_cab_o
+
+ );
+
+////////////////////////////////////////////////////////////////////
+//
+// Module Parameters
+//
+
+
+parameter s0_addr_w = 4 ; // slave 0 address decode width
+parameter s0_addr = 4'h0; // slave 0 address
+parameter s1_addr_w = 4 ; // slave 1 address decode width
+parameter s1_addr = 4'h1; // slave 1 address
+parameter s27_addr_w = 8 ; // slave 2 to slave 7 address decode width
+parameter s2_addr = 8'h92; // slave 2 address
+parameter s3_addr = 8'h93; // slave 3 address
+parameter s4_addr = 8'h94; // slave 4 address
+parameter s5_addr = 8'h95; // slave 5 address
+parameter s6_addr = 8'h96; // slave 6 address
+parameter s7_addr = 8'h97; // slave 7 address
+
+
+////////////////////////////////////////////////////////////////////
+//
+// Module IOs
+//
+
+input clk_i, rst_i;
+
+// Master 0 Interface
+input [`dw-1:0] m0_dat_i;
+output [`dw-1:0] m0_dat_o;
+input [`aw-1:0] m0_adr_i;
+input [`sw-1:0] m0_sel_i;
+input m0_we_i;
+input m0_cyc_i;
+input m0_stb_i;
+input m0_cab_i;
+output m0_ack_o;
+output m0_err_o;
+output m0_rty_o;
+
+// Master 1 Interface
+input [`dw-1:0] m1_dat_i;
+output [`dw-1:0] m1_dat_o;
+input [`aw-1:0] m1_adr_i;
+input [`sw-1:0] m1_sel_i;
+input m1_we_i;
+input m1_cyc_i;
+input m1_stb_i;
+input m1_cab_i;
+output m1_ack_o;
+output m1_err_o;
+output m1_rty_o;
+
+// Master 2 Interface
+input [`dw-1:0] m2_dat_i;
+output [`dw-1:0] m2_dat_o;
+input [`aw-1:0] m2_adr_i;
+input [`sw-1:0] m2_sel_i;
+input m2_we_i;
+input m2_cyc_i;
+input m2_stb_i;
+input m2_cab_i;
+output m2_ack_o;
+output m2_err_o;
+output m2_rty_o;
+
+// Master 3 Interface
+input [`dw-1:0] m3_dat_i;
+output [`dw-1:0] m3_dat_o;
+input [`aw-1:0] m3_adr_i;
+input [`sw-1:0] m3_sel_i;
+input m3_we_i;
+input m3_cyc_i;
+input m3_stb_i;
+input m3_cab_i;
+output m3_ack_o;
+output m3_err_o;
+output m3_rty_o;
+
+// Master 4 Interface
+input [`dw-1:0] m4_dat_i;
+output [`dw-1:0] m4_dat_o;
+input [`aw-1:0] m4_adr_i;
+input [`sw-1:0] m4_sel_i;
+input m4_we_i;
+input m4_cyc_i;
+input m4_stb_i;
+input m4_cab_i;
+output m4_ack_o;
+output m4_err_o;
+output m4_rty_o;
+
+// Master 5 Interface
+input [`dw-1:0] m5_dat_i;
+output [`dw-1:0] m5_dat_o;
+input [`aw-1:0] m5_adr_i;
+input [`sw-1:0] m5_sel_i;
+input m5_we_i;
+input m5_cyc_i;
+input m5_stb_i;
+input m5_cab_i;
+output m5_ack_o;
+output m5_err_o;
+output m5_rty_o;
+
+// Master 6 Interface
+input [`dw-1:0] m6_dat_i;
+output [`dw-1:0] m6_dat_o;
+input [`aw-1:0] m6_adr_i;
+input [`sw-1:0] m6_sel_i;
+input m6_we_i;
+input m6_cyc_i;
+input m6_stb_i;
+input m6_cab_i;
+output m6_ack_o;
+output m6_err_o;
+output m6_rty_o;
+
+// Master 7 Interface
+input [`dw-1:0] m7_dat_i;
+output [`dw-1:0] m7_dat_o;
+input [`aw-1:0] m7_adr_i;
+input [`sw-1:0] m7_sel_i;
+input m7_we_i;
+input m7_cyc_i;
+input m7_stb_i;
+input m7_cab_i;
+output m7_ack_o;
+output m7_err_o;
+output m7_rty_o;
+
+// Slave 0 Interface
+input [`dw-1:0] s0_dat_i;
+output [`dw-1:0] s0_dat_o;
+output [`aw-1:0] s0_adr_o;
+output [`sw-1:0] s0_sel_o;
+output s0_we_o;
+output s0_cyc_o;
+output s0_stb_o;
+output s0_cab_o;
+input s0_ack_i;
+input s0_err_i;
+input s0_rty_i;
+
+// Slave 1 Interface
+input [`dw-1:0] s1_dat_i;
+output [`dw-1:0] s1_dat_o;
+output [`aw-1:0] s1_adr_o;
+output [`sw-1:0] s1_sel_o;
+output s1_we_o;
+output s1_cyc_o;
+output s1_stb_o;
+output s1_cab_o;
+input s1_ack_i;
+input s1_err_i;
+input s1_rty_i;
+
+// Slave 2 Interface
+input [`dw-1:0] s2_dat_i;
+output [`dw-1:0] s2_dat_o;
+output [`aw-1:0] s2_adr_o;
+output [`sw-1:0] s2_sel_o;
+output s2_we_o;
+output s2_cyc_o;
+output s2_stb_o;
+output s2_cab_o;
+input s2_ack_i;
+input s2_err_i;
+input s2_rty_i;
+
+// Slave 3 Interface
+input [`dw-1:0] s3_dat_i;
+output [`dw-1:0] s3_dat_o;
+output [`aw-1:0] s3_adr_o;
+output [`sw-1:0] s3_sel_o;
+output s3_we_o;
+output s3_cyc_o;
+output s3_stb_o;
+output s3_cab_o;
+input s3_ack_i;
+input s3_err_i;
+input s3_rty_i;
+
+// Slave 4 Interface
+input [`dw-1:0] s4_dat_i;
+output [`dw-1:0] s4_dat_o;
+output [`aw-1:0] s4_adr_o;
+output [`sw-1:0] s4_sel_o;
+output s4_we_o;
+output s4_cyc_o;
+output s4_stb_o;
+output s4_cab_o;
+input s4_ack_i;
+input s4_err_i;
+input s4_rty_i;
+
+// Slave 5 Interface
+input [`dw-1:0] s5_dat_i;
+output [`dw-1:0] s5_dat_o;
+output [`aw-1:0] s5_adr_o;
+output [`sw-1:0] s5_sel_o;
+output s5_we_o;
+output s5_cyc_o;
+output s5_stb_o;
+output s5_cab_o;
+input s5_ack_i;
+input s5_err_i;
+input s5_rty_i;
+
+// Slave 6 Interface
+input [`dw-1:0] s6_dat_i;
+output [`dw-1:0] s6_dat_o;
+output [`aw-1:0] s6_adr_o;
+output [`sw-1:0] s6_sel_o;
+output s6_we_o;
+output s6_cyc_o;
+output s6_stb_o;
+output s6_cab_o;
+input s6_ack_i;
+input s6_err_i;
+input s6_rty_i;
+
+// Slave 7 Interface
+input [`dw-1:0] s7_dat_i;
+output [`dw-1:0] s7_dat_o;
+output [`aw-1:0] s7_adr_o;
+output [`sw-1:0] s7_sel_o;
+output s7_we_o;
+output s7_cyc_o;
+output s7_stb_o;
+output s7_cab_o;
+input s7_ack_i;
+input s7_err_i;
+input s7_rty_i;
+
+
+////////////////////////////////////////////////////////////////////
+//
+// Local wires
+//
+
+wire [`mselectw -1:0] i_gnt_arb;
+wire [2:0] gnt;
+reg [`sselectw -1:0] i_ssel_dec;
+`ifdef WB_USE_TRISTATE
+wire [`mbusw -1:0] i_bus_m;
+`else
+reg [`mbusw -1:0] i_bus_m; // internal share bus, master data and control to slave
+`endif
+wire [`dw -1:0] i_dat_s; // internal share bus , slave data to master
+wire [`sbusw -1:0] i_bus_s; // internal share bus , slave control to master
+
+
+
+
+////////////////////////////////////////////////////////////////////
+//
+// Master output Interfaces
+//
+
+// master0
+assign m0_dat_o = i_dat_s;
+assign {m0_ack_o, m0_err_o, m0_rty_o} = i_bus_s & {3{i_gnt_arb[0]}};
+
+// master1
+assign m1_dat_o = i_dat_s;
+assign {m1_ack_o, m1_err_o, m1_rty_o} = i_bus_s & {3{i_gnt_arb[1]}};
+
+// master2
+
+assign m2_dat_o = i_dat_s;
+assign {m2_ack_o, m2_err_o, m2_rty_o} = i_bus_s & {3{i_gnt_arb[2]}};
+
+// master3
+
+assign m3_dat_o = i_dat_s;
+assign {m3_ack_o, m3_err_o, m3_rty_o} = i_bus_s & {3{i_gnt_arb[3]}};
+
+// master4
+
+assign m4_dat_o = i_dat_s;
+assign {m4_ack_o, m4_err_o, m4_rty_o} = i_bus_s & {3{i_gnt_arb[4]}};
+
+// master5
+
+assign m5_dat_o = i_dat_s;
+assign {m5_ack_o, m5_err_o, m5_rty_o} = i_bus_s & {3{i_gnt_arb[5]}};
+
+// master6
+
+assign m6_dat_o = i_dat_s;
+assign {m6_ack_o, m6_err_o, m6_rty_o} = i_bus_s & {3{i_gnt_arb[6]}};
+
+// master7
+
+assign m7_dat_o = i_dat_s;
+assign {m7_ack_o, m7_err_o, m7_rty_o} = i_bus_s & {3{i_gnt_arb[7]}};
+
+
+assign i_bus_s = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i ,
+ s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i ,
+ s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i };
+
+////////////////////////////////
+// Slave output interface
+//
+// slave0
+assign {s0_adr_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cab_o,s0_cyc_o} = i_bus_m[`mbusw -1:1];
+assign s0_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[0]; // stb_o = cyc_i & stb_i & i_ssel_dec
+
+// slave1
+
+assign {s1_adr_o, s1_sel_o, s1_dat_o, s1_we_o, s1_cab_o, s1_cyc_o} = i_bus_m[`mbusw -1:1];
+assign s1_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[1];
+
+// slave2
+
+assign {s2_adr_o, s2_sel_o, s2_dat_o, s2_we_o, s2_cab_o, s2_cyc_o} = i_bus_m[`mbusw -1:1];
+assign s2_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[2];
+
+// slave3
+
+assign {s3_adr_o, s3_sel_o, s3_dat_o, s3_we_o, s3_cab_o, s3_cyc_o} = i_bus_m[`mbusw -1:1];
+assign s3_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[3];
+
+// slave4
+
+assign {s4_adr_o, s4_sel_o, s4_dat_o, s4_we_o, s4_cab_o, s4_cyc_o} = i_bus_m[`mbusw -1:1];
+assign s4_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[4];
+
+// slave5
+
+assign {s5_adr_o, s5_sel_o, s5_dat_o, s5_we_o, s5_cab_o, s5_cyc_o} = i_bus_m[`mbusw -1:1];
+assign s5_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[5];
+
+// slave6
+
+assign {s6_adr_o, s6_sel_o, s6_dat_o, s6_we_o, s6_cab_o, s6_cyc_o} = i_bus_m[`mbusw -1:1];
+assign s6_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[6];
+
+// slave7
+
+assign {s7_adr_o, s7_sel_o, s7_dat_o, s7_we_o, s7_cab_o, s7_cyc_o} = i_bus_m[`mbusw -1:1];
+assign s7_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[7];
+
+///////////////////////////////////////
+// Master and Slave input interface
+//
+
+`ifdef WB_USE_TRISTATE
+// input from master interface
+assign i_bus_m = i_gnt_arb[0] ? {m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i, m0_stb_i} : 72'bz ;
+assign i_bus_m = i_gnt_arb[1] ? {m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i,m1_cyc_i, m1_stb_i} : 72'bz ;
+assign i_bus_m = i_gnt_arb[2] ? {m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i, m2_stb_i} : 72'bz ;
+assign i_bus_m = i_gnt_arb[3] ? {m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i, m3_stb_i} : 72'bz ;
+assign i_bus_m = i_gnt_arb[4] ? {m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i, m4_stb_i} : 72'bz ;
+assign i_bus_m = i_gnt_arb[5] ? {m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i, m5_stb_i} : 72'bz ;
+assign i_bus_m = i_gnt_arb[6] ? {m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i, m6_stb_i} : 72'bz ;
+assign i_bus_m = i_gnt_arb[7] ? {m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i} : 72'bz ;
+// input from slave interface
+assign i_dat_s = i_ssel_dec[0] ? s0_dat_i: 32'bz;
+assign i_dat_s = i_ssel_dec[1] ? s1_dat_i: 32'bz;
+assign i_dat_s = i_ssel_dec[2] ? s2_dat_i: 32'bz;
+assign i_dat_s = i_ssel_dec[3] ? s3_dat_i: 32'bz;
+assign i_dat_s = i_ssel_dec[4] ? s4_dat_i: 32'bz;
+assign i_dat_s = i_ssel_dec[5] ? s5_dat_i: 32'bz;
+assign i_dat_s = i_ssel_dec[6] ? s6_dat_i: 32'bz;
+assign i_dat_s = i_ssel_dec[7] ? s7_dat_i: 32'bz;
+
+`else
+
+always @(gnt , m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i,
+ m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i, m1_cyc_i,m1_stb_i,
+ m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i,m2_stb_i,
+ m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i,m3_stb_i,
+ m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i,m4_stb_i,
+ m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i,m5_stb_i,
+ m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i,m6_stb_i,
+ m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i)
+ case(gnt)
+ 3'h0: i_bus_m = {m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i};
+ 3'h1: i_bus_m = {m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i, m1_cyc_i,m1_stb_i};
+ 3'h2: i_bus_m = {m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i,m2_stb_i};
+ 3'h3: i_bus_m = {m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i,m3_stb_i};
+ 3'h4: i_bus_m = {m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i,m4_stb_i};
+ 3'h5: i_bus_m = {m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i,m5_stb_i};
+ 3'h6: i_bus_m = {m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i,m6_stb_i};
+ 3'h7: i_bus_m = {m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i};
+ default:i_bus_m = 72'b0;//{m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i};
+endcase
+
+assign i_dat_s = i_ssel_dec[0] ? s0_dat_i :
+ i_ssel_dec[1] ? s1_dat_i :
+ i_ssel_dec[2] ? s2_dat_i :
+ i_ssel_dec[3] ? s3_dat_i :
+ i_ssel_dec[4] ? s4_dat_i :
+ i_ssel_dec[5] ? s5_dat_i :
+ i_ssel_dec[6] ? s6_dat_i :
+ i_ssel_dec[7] ? s7_dat_i : {`dw{1'b0}};
+`endif
+//
+// arbitor
+//
+assign i_gnt_arb[0] = (gnt == 3'd0);
+assign i_gnt_arb[1] = (gnt == 3'd1);
+assign i_gnt_arb[2] = (gnt == 3'd2);
+assign i_gnt_arb[3] = (gnt == 3'd3);
+assign i_gnt_arb[4] = (gnt == 3'd4);
+assign i_gnt_arb[5] = (gnt == 3'd5);
+assign i_gnt_arb[6] = (gnt == 3'd6);
+assign i_gnt_arb[7] = (gnt == 3'd7);
+
+wb_conbus_arb wb_conbus_arb(
+ .clk(clk_i),
+ .rst(rst_i),
+ .req({ m7_cyc_i,
+ m6_cyc_i,
+ m5_cyc_i,
+ m4_cyc_i,
+ m3_cyc_i,
+ m2_cyc_i,
+ m1_cyc_i,
+ m0_cyc_i}),
+ .gnt(gnt)
+);
+
+//////////////////////////////////
+// address decode logic
+//
+wire [7:0] m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec;
+always @(gnt, m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec)
+ case(gnt)
+ 3'h0: i_ssel_dec = m0_ssel_dec;
+ 3'h1: i_ssel_dec = m1_ssel_dec;
+ 3'h2: i_ssel_dec = m2_ssel_dec;
+ 3'h3: i_ssel_dec = m3_ssel_dec;
+ 3'h4: i_ssel_dec = m4_ssel_dec;
+ 3'h5: i_ssel_dec = m5_ssel_dec;
+ 3'h6: i_ssel_dec = m6_ssel_dec;
+ 3'h7: i_ssel_dec = m7_ssel_dec;
+ default: i_ssel_dec = 7'b0;
+endcase
+//
+// decode all master address before arbitor for running faster
+//
+assign m0_ssel_dec[0] = (m0_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
+assign m0_ssel_dec[1] = (m0_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
+assign m0_ssel_dec[2] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
+assign m0_ssel_dec[3] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
+assign m0_ssel_dec[4] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
+assign m0_ssel_dec[5] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
+assign m0_ssel_dec[6] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
+assign m0_ssel_dec[7] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+
+assign m1_ssel_dec[0] = (m1_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
+assign m1_ssel_dec[1] = (m1_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
+assign m1_ssel_dec[2] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
+assign m1_ssel_dec[3] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
+assign m1_ssel_dec[4] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
+assign m1_ssel_dec[5] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
+assign m1_ssel_dec[6] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
+assign m1_ssel_dec[7] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+
+assign m2_ssel_dec[0] = (m2_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
+assign m2_ssel_dec[1] = (m2_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
+assign m2_ssel_dec[2] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
+assign m2_ssel_dec[3] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
+assign m2_ssel_dec[4] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
+assign m2_ssel_dec[5] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
+assign m2_ssel_dec[6] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
+assign m2_ssel_dec[7] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+
+assign m3_ssel_dec[0] = (m3_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
+assign m3_ssel_dec[1] = (m3_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
+assign m3_ssel_dec[2] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
+assign m3_ssel_dec[3] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
+assign m3_ssel_dec[4] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
+assign m3_ssel_dec[5] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
+assign m3_ssel_dec[6] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
+assign m3_ssel_dec[7] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+
+assign m4_ssel_dec[0] = (m4_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
+assign m4_ssel_dec[1] = (m4_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
+assign m4_ssel_dec[2] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
+assign m4_ssel_dec[3] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
+assign m4_ssel_dec[4] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
+assign m4_ssel_dec[5] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
+assign m4_ssel_dec[6] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
+assign m4_ssel_dec[7] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+
+assign m5_ssel_dec[0] = (m5_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
+assign m5_ssel_dec[1] = (m5_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
+assign m5_ssel_dec[2] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
+assign m5_ssel_dec[3] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
+assign m5_ssel_dec[4] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
+assign m5_ssel_dec[5] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
+assign m5_ssel_dec[6] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
+assign m5_ssel_dec[7] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+
+assign m6_ssel_dec[0] = (m6_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
+assign m6_ssel_dec[1] = (m6_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
+assign m6_ssel_dec[2] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
+assign m6_ssel_dec[3] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
+assign m6_ssel_dec[4] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
+assign m6_ssel_dec[5] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
+assign m6_ssel_dec[6] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
+assign m6_ssel_dec[7] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+
+assign m7_ssel_dec[0] = (m7_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);
+assign m7_ssel_dec[1] = (m7_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);
+assign m7_ssel_dec[2] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);
+assign m7_ssel_dec[3] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);
+assign m7_ssel_dec[4] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);
+assign m7_ssel_dec[5] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);
+assign m7_ssel_dec[6] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);
+assign m7_ssel_dec[7] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);
+
+//assign i_ssel_dec[0] = (i_bus_m[`mbusw -1 : `mbusw - s0_addr_w ] == s0_addr);
+//assign i_ssel_dec[1] = (i_bus_m[`mbusw -1 : `mbusw - s1_addr_w ] == s1_addr);
+//assign i_ssel_dec[2] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s2_addr);
+//assign i_ssel_dec[3] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s3_addr);
+//assign i_ssel_dec[4] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s4_addr);
+//assign i_ssel_dec[5] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s5_addr);
+//assign i_ssel_dec[6] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s6_addr);
+//assign i_ssel_dec[7] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s7_addr);
+
+
+endmodule
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_arb.v
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_arb.v (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_arb.v (revision 2)
@@ -0,0 +1,252 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// General Round Robin Arbiter ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+
+//
+// copy from wb_conmax
+//
+//
+//
+//
+//
+
+//`include "wb_conbus_defines.v"
+
+module wb_conbus_arb(clk, rst, req, gnt);
+
+input clk;
+input rst;
+input [7:0] req; // Req input
+output [2:0] gnt; // Grant output
+//input next; // Next Target
+
+///////////////////////////////////////////////////////////////////////
+//
+// Parameters
+//
+
+
+parameter [2:0]
+ grant0 = 3'h0,
+ grant1 = 3'h1,
+ grant2 = 3'h2,
+ grant3 = 3'h3,
+ grant4 = 3'h4,
+ grant5 = 3'h5,
+ grant6 = 3'h6,
+ grant7 = 3'h7;
+
+///////////////////////////////////////////////////////////////////////
+//
+// Local Registers and Wires
+//
+
+reg [2:0] state, next_state;
+
+///////////////////////////////////////////////////////////////////////
+//
+// Misc Logic
+//
+
+assign gnt = state;
+
+always@(posedge clk or posedge rst)
+ if(rst) state <= #1 grant0;
+ else state <= #1 next_state;
+
+///////////////////////////////////////////////////////////////////////
+//
+// Next State Logic
+// - implements round robin arbitration algorithm
+// - switches grant if current req is dropped or next is asserted
+// - parks at last grant
+//
+
+always@(state or req )
+ begin
+ next_state = state; // Default Keep State
+ case(state) // synopsys parallel_case full_case
+ grant0:
+ // if this req is dropped or next is asserted, check for other req's
+ if(!req[0] )
+ begin
+ if(req[1]) next_state = grant1;
+ else
+ if(req[2]) next_state = grant2;
+ else
+ if(req[3]) next_state = grant3;
+ else
+ if(req[4]) next_state = grant4;
+ else
+ if(req[5]) next_state = grant5;
+ else
+ if(req[6]) next_state = grant6;
+ else
+ if(req[7]) next_state = grant7;
+ end
+ grant1:
+ // if this req is dropped or next is asserted, check for other req's
+ if(!req[1] )
+ begin
+ if(req[2]) next_state = grant2;
+ else
+ if(req[3]) next_state = grant3;
+ else
+ if(req[4]) next_state = grant4;
+ else
+ if(req[5]) next_state = grant5;
+ else
+ if(req[6]) next_state = grant6;
+ else
+ if(req[7]) next_state = grant7;
+ else
+ if(req[0]) next_state = grant0;
+ end
+ grant2:
+ // if this req is dropped or next is asserted, check for other req's
+ if(!req[2] )
+ begin
+ if(req[3]) next_state = grant3;
+ else
+ if(req[4]) next_state = grant4;
+ else
+ if(req[5]) next_state = grant5;
+ else
+ if(req[6]) next_state = grant6;
+ else
+ if(req[7]) next_state = grant7;
+ else
+ if(req[0]) next_state = grant0;
+ else
+ if(req[1]) next_state = grant1;
+ end
+ grant3:
+ // if this req is dropped or next is asserted, check for other req's
+ if(!req[3] )
+ begin
+ if(req[4]) next_state = grant4;
+ else
+ if(req[5]) next_state = grant5;
+ else
+ if(req[6]) next_state = grant6;
+ else
+ if(req[7]) next_state = grant7;
+ else
+ if(req[0]) next_state = grant0;
+ else
+ if(req[1]) next_state = grant1;
+ else
+ if(req[2]) next_state = grant2;
+ end
+ grant4:
+ // if this req is dropped or next is asserted, check for other req's
+ if(!req[4] )
+ begin
+ if(req[5]) next_state = grant5;
+ else
+ if(req[6]) next_state = grant6;
+ else
+ if(req[7]) next_state = grant7;
+ else
+ if(req[0]) next_state = grant0;
+ else
+ if(req[1]) next_state = grant1;
+ else
+ if(req[2]) next_state = grant2;
+ else
+ if(req[3]) next_state = grant3;
+ end
+ grant5:
+ // if this req is dropped or next is asserted, check for other req's
+ if(!req[5] )
+ begin
+ if(req[6]) next_state = grant6;
+ else
+ if(req[7]) next_state = grant7;
+ else
+ if(req[0]) next_state = grant0;
+ else
+ if(req[1]) next_state = grant1;
+ else
+ if(req[2]) next_state = grant2;
+ else
+ if(req[3]) next_state = grant3;
+ else
+ if(req[4]) next_state = grant4;
+ end
+ grant6:
+ // if this req is dropped or next is asserted, check for other req's
+ if(!req[6] )
+ begin
+ if(req[7]) next_state = grant7;
+ else
+ if(req[0]) next_state = grant0;
+ else
+ if(req[1]) next_state = grant1;
+ else
+ if(req[2]) next_state = grant2;
+ else
+ if(req[3]) next_state = grant3;
+ else
+ if(req[4]) next_state = grant4;
+ else
+ if(req[5]) next_state = grant5;
+ end
+ grant7:
+ // if this req is dropped or next is asserted, check for other req's
+ if(!req[7] )
+ begin
+ if(req[0]) next_state = grant0;
+ else
+ if(req[1]) next_state = grant1;
+ else
+ if(req[2]) next_state = grant2;
+ else
+ if(req[3]) next_state = grant3;
+ else
+ if(req[4]) next_state = grant4;
+ else
+ if(req[5]) next_state = grant5;
+ else
+ if(req[6]) next_state = grant6;
+ end
+ endcase
+ end
+
+endmodule
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/data/wb_conbus_v2_1_0.pao
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/data/wb_conbus_v2_1_0.pao (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/data/wb_conbus_v2_1_0.pao (revision 2)
@@ -0,0 +1,9 @@
+
+
+
+lib wb_conbus_v1_00_a wb_conbus_arb verilog
+lib wb_conbus_v1_00_a wb_conbus_top verilog
+lib wb_conbus_v1_00_a wb_conbus_wrapper verilog
+
+
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/data/wb_conbus_v2_1_0.mpd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/data/wb_conbus_v2_1_0.mpd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/data/wb_conbus_v2_1_0.mpd (revision 2)
@@ -0,0 +1,65 @@
+BEGIN wb_conbus
+
+
+
+OPTION IPTYPE = BUS
+OPTION IMP_NETLIST = TRUE
+OPTION HDL = VERILOG
+OPTION BUS_STD = WB
+OPTION RUN_NGCBUILD = TRUE
+OPTION MAX_MASTERS = 8
+OPTION MAX_SLAVES = 8
+OPTION DESC = Wishbone (WB) bus and arbiter
+OPTION LONG_DESC = Wishbone (WB) bus and arbiter: Downloaded from: http://opencores.org/project,wb_conbus. Copyright (C) 2000 Authors and OPENCORES.ORG. You should have received a copy of the GNU Lesser General Public License along with this source; if not, download it from http://www.opencores.org/lgpl.shtml
+OPTION IP_GROUP = Bus and Bridge:MICROBLAZE
+OPTION STYLE = HDL
+OPTION TOP = wb_conbus_wrapper
+
+
+
+PARAMETER WB_DAT_W = 32, DT = integer, ASSIGNMENT = CONSTANT
+PARAMETER WB_ADR_W = 32, DT = integer, ASSIGNMENT = CONSTANT
+PARAMETER wb_num_masters = 8, DT = integer, ASSIGNMENT = CONSTANT
+PARAMETER wb_num_slaves = 8, DT = integer, ASSIGNMENT = CONSTANT
+
+PARAMETER wb_s0_addr_w = 4, DT = integer, RANGE = ( 1 : 32 )
+PARAMETER wb_s0_addr = 0x0, DT = std_logic_vector
+PARAMETER wb_s1_addr_w = 4, DT = integer, RANGE = ( 1 : 32 )
+PARAMETER wb_s1_addr = 0x1, DT = std_logic_vector
+PARAMETER wb_s27_addr_w = 8, DT = integer, RANGE = ( 1 : 32 )
+PARAMETER wb_s2_addr = 0x92, DT = std_logic_vector
+PARAMETER wb_s3_addr = 0x93, DT = std_logic_vector
+PARAMETER wb_s4_addr = 0x94, DT = std_logic_vector
+PARAMETER wb_s5_addr = 0x95, DT = std_logic_vector
+PARAMETER wb_s6_addr = 0x96, DT = std_logic_vector
+PARAMETER wb_s7_addr = 0x97, DT = std_logic_vector
+
+
+PORT wb_clk_i = "", DIR = I, SIGIS = CLK
+PORT wb_rst_i = "", DIR = I, SIGIS = RST
+PORT wb_m_dat_i = wb_m_dat_i, DIR = I, VEC = [ (WB_DAT_W*wb_num_masters)-1 : 0 ]
+PORT wb_m_dat_o = wb_m_dat_o, DIR = O, VEC = [ WB_DAT_W-1 : 0 ]
+PORT wb_m_adr_i = wb_m_adr_i, DIR = I, VEC = [ (WB_ADR_W*wb_num_masters)-1 : 0 ]
+PORT wb_m_sel_i = wb_m_sel_i, DIR = I, VEC = [ (WB_DAT_W/8*wb_num_masters)-1 : 0 ]
+PORT wb_m_we_i = wb_m_we_i, DIR = I, VEC = [ wb_num_masters-1 : 0 ]
+PORT wb_m_cyc_i = wb_m_cyc_i, DIR = I, VEC = [ wb_num_masters-1 : 0 ]
+PORT wb_m_stb_i = wb_m_stb_i, DIR = I, VEC = [ wb_num_masters-1 : 0 ]
+PORT wb_m_ack_o = wb_m_ack_o, DIR = O, VEC = [ wb_num_masters-1 : 0 ]
+PORT wb_m_err_o = wb_m_err_o, DIR = O, VEC = [ wb_num_masters-1 : 0 ]
+PORT wb_m_rty_o = wb_m_rty_o, DIR = O, VEC = [ wb_num_masters-1 : 0 ]
+PORT wb_m_cab_i = wb_m_cab_i, DIR = I, VEC = [ wb_num_masters-1 : 0 ]
+
+PORT wb_s_dat_i = wb_s_dat_i, DIR = I, VEC = [WB_DAT_W*wb_num_slaves-1 : 0 ]
+PORT wb_s_dat_o = wb_s_dat_o, DIR = O, VEC = [WB_DAT_W-1 : 0 ]
+PORT wb_s_adr_o = wb_s_adr_o, DIR = O, VEC = [WB_ADR_W-1 : 0 ]
+PORT wb_s_sel_o = wb_s_sel_o, DIR = O, VEC = [WB_DAT_W/8-1 : 0 ]
+PORT wb_s_we_o = wb_s_we_o, DIR = O,
+PORT wb_s_cyc_o = wb_s_cyc_o, DIR = O,
+PORT wb_s_stb_o = wb_s_stb_o, DIR = O, VEC = [wb_num_slaves-1 : 0 ]
+PORT wb_s_ack_i = wb_s_ack_i, DIR = I, VEC = [wb_num_slaves-1 : 0 ]
+PORT wb_s_err_i = wb_s_err_i, DIR = I, VEC = [wb_num_slaves-1 : 0 ]
+PORT wb_s_rty_i = wb_s_rty_i, DIR = I, VEC = [wb_num_slaves-1 : 0 ]
+PORT wb_s_cab_o = wb_s_cab_o, DIR = O
+
+
+END
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/ise/top.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/ise/top.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/ise/top.vhd (revision 2)
@@ -0,0 +1,265 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+
+library plb2wb_bridge_v1_00_a;
+use plb2wb_bridge_v1_00_a.all;
+
+
+entity top is
+
+ generic
+ (
+ SYNCHRONY : boolean := false; -- true = synchron, false = asynchron!
+
+ -- PLB Parameters -----------------------------------
+ C_BASEADDR : std_logic_vector := X"FFFFFFFF";
+ C_HIGHADDR : std_logic_vector := X"00000000";
+ C_STATUS_BASEADDR : std_logic_vector := X"FFFFFFFF";
+ C_STATUS_HIGHADDR : std_logic_vector := X"00000000";
+ C_SPLB_AWIDTH : integer := 32;
+ C_SPLB_DWIDTH : integer := 128;
+ C_SPLB_NUM_MASTERS : integer := 8;
+ C_SPLB_MID_WIDTH : integer := 3;
+ C_SPLB_NATIVE_DWIDTH : integer := 32;
+ C_SPLB_SUPPORT_BUR_LINE : integer := 1;
+ C_SPLB_SUPPORT_ADR_PIPE : integer := 1;
+
+ -- WB Parameters -----------------------------------
+ WB_DAT_W : integer := 32;
+ WB_ADR_W : integer := 32;
+ WB_TIMEOUT_CYCLES : integer := 32;
+ WB_ADR_OFFSET : std_logic_vector := X"f0000000";
+ WB_ADR_OFFSET_NEG : std_logic := '0';
+ WB_PIC_INTS : integer := 32;
+ WB_PIC_INT_LEVEL : std_logic := '1';
+ WB_SUPPORT_BLOCK : integer := 1
+ );
+
+
+port(
+ PLB2WB_IRQ : out std_logic;
+
+ -- WB Signals ---------------------------------------
+ wb_clk_i : in std_logic;
+ wb_rst_i : in std_logic;
+ wb_dat_i : in std_logic_vector( WB_DAT_W-1 downto 0 );
+ wb_dat_o : out std_logic_vector( WB_DAT_W-1 downto 0 );
+ wb_adr_o : out std_logic_vector( WB_ADR_W-1 downto 0 );
+ wb_sel_o : out std_logic_vector( WB_DAT_W/8-1 downto 0 );
+ wb_we_o : out std_logic;
+ wb_cyc_o : out std_logic;
+ wb_stb_o : out std_logic;
+ wb_ack_i : in std_logic;
+ wb_err_i : in std_logic;
+ wb_rty_i : in std_logic;
+ wb_lock_o : out std_logic;
+
+ wb_pic_int_i : in std_logic_vector( WB_PIC_INTS-1 downto 0 );
+
+ -- PLB Signals --------------------------------------
+ SPLB_Clk : in std_logic;
+ SPLB_Rst : in std_logic;
+ PLB_ABus : in std_logic_vector( 0 to 31 );
+ PLB_UABus : in std_logic_vector( 0 to 31 );
+ PLB_PAValid : in std_logic;
+ PLB_SAValid : in std_logic;
+ PLB_rdPrim : in std_logic;
+ PLB_wrPrim : in std_logic;
+ PLB_masterID : in std_logic_vector( 0 to C_SPLB_MID_WIDTH-1 );
+ PLB_abort : in std_logic;
+ PLB_busLock : in std_logic;
+ PLB_RNW : in std_logic;
+ PLB_BE : in std_logic_vector( 0 to C_SPLB_DWIDTH/8-1 );
+ PLB_MSize : in std_logic_vector( 0 to 1 );
+ PLB_size : in std_logic_vector( 0 to 3 );
+ PLB_type : in std_logic_vector( 0 to 2 );
+ PLB_lockErr : in std_logic;
+ PLB_wrDBus : in std_logic_vector( 0 to C_SPLB_DWIDTH-1 );
+ PLB_wrBurst : in std_logic;
+ PLB_rdBurst : in std_logic;
+ PLB_wrPendReq : in std_logic;
+ PLB_rdPendReq : in std_logic;
+ PLB_wrPendPri : in std_logic_vector( 0 to 1 );
+ PLB_rdPendPri : in std_logic_vector( 0 to 1 );
+ PLB_reqPri : in std_logic_vector( 0 to 1 );
+ PLB_TAttribute : in std_logic_vector( 0 to 15 );
+ Sl_addrAck : out std_logic;
+ Sl_SSize : out std_logic_vector( 0 to 1 );
+ Sl_wait : out std_logic;
+ Sl_rearbitrate : out std_logic;
+ Sl_wrDAck : out std_logic;
+ Sl_wrComp : out std_logic;
+ Sl_wrBTerm : out std_logic;
+ Sl_rdDBus : out std_logic_vector( 0 to C_SPLB_DWIDTH-1 );
+ Sl_rdWdAddr : out std_logic_vector( 0 to 3 );
+ Sl_rdDAck : out std_logic;
+ Sl_rdComp : out std_logic;
+ Sl_rdBTerm : out std_logic;
+ Sl_MBusy : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ Sl_MWrErr : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ Sl_MRdErr : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ Sl_MIRQ : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 )
+
+);
+
+
+end entity top;
+
+
+architecture imp of top is
+
+
+
+begin
+
+ bridge : entity plb2wb_bridge_v1_00_a.plb2wb_bridge(IMP)
+ generic map
+ (
+ SYNCHRONY => SYNCHRONY ,
+
+ C_BASEADDR => C_BASEADDR ,
+ C_HIGHADDR => C_HIGHADDR ,
+ C_STATUS_BASEADDR => C_STATUS_BASEADDR ,
+ C_STATUS_HIGHADDR => C_STATUS_HIGHADDR ,
+ C_SPLB_AWIDTH => C_SPLB_AWIDTH ,
+ C_SPLB_DWIDTH => C_SPLB_DWIDTH ,
+ C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS ,
+ C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH ,
+ C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH ,
+ C_SPLB_SUPPORT_BUR_LINE => C_SPLB_SUPPORT_BUR_LINE ,
+ C_SPLB_SUPPORT_ADR_PIPE => C_SPLB_SUPPORT_ADR_PIPE,
+
+ WB_DAT_W => WB_DAT_W ,
+ WB_ADR_W => WB_ADR_W ,
+ WB_TIMEOUT_CYCLES => WB_TIMEOUT_CYCLES ,
+ WB_ADR_OFFSET => WB_ADR_OFFSET ,
+ WB_ADR_OFFSET_NEG => WB_ADR_OFFSET_NEG ,
+ WB_PIC_INTS => WB_PIC_INTS ,
+ WB_PIC_INT_LEVEL => WB_PIC_INT_LEVEL ,
+ WB_SUPPORT_BLOCK => WB_SUPPORT_BLOCK
+ )
+ port map
+ (
+
+ PLB2WB_IRQ => PLB2WB_IRQ ,
+
+ wb_clk_i => wb_clk_i ,
+ wb_rst_i => wb_rst_i ,
+ wb_dat_i => wb_dat_i ,
+ wb_dat_o => wb_dat_o ,
+ wb_adr_o => wb_adr_o ,
+ wb_sel_o => wb_sel_o ,
+ wb_we_o => wb_we_o ,
+ wb_cyc_o => wb_cyc_o ,
+ wb_stb_o => wb_stb_o ,
+ wb_ack_i => wb_ack_i ,
+ wb_err_i => wb_err_i ,
+ wb_rty_i => wb_rty_i ,
+ wb_lock_o => wb_lock_o ,
+
+ wb_pic_int_i => wb_pic_int_i ,
+
+ SPLB_Clk => SPLB_Clk ,
+ SPLB_Rst => SPLB_Rst ,
+ PLB_ABus => PLB_ABus ,
+ PLB_UABus => PLB_UABus ,
+ PLB_PAValid => PLB_PAValid ,
+ PLB_SAValid => PLB_SAValid ,
+ PLB_rdPrim => PLB_rdPrim ,
+ PLB_wrPrim => PLB_wrPrim ,
+ PLB_masterID => PLB_masterID ,
+ PLB_abort => PLB_abort ,
+ PLB_busLock => PLB_busLock ,
+ PLB_RNW => PLB_RNW ,
+ PLB_BE => PLB_BE ,
+ PLB_MSize => PLB_MSize ,
+ PLB_size => PLB_size ,
+ PLB_type => PLB_type ,
+ PLB_lockErr => PLB_lockErr ,
+ PLB_wrDBus => PLB_wrDBus ,
+ PLB_wrBurst => PLB_wrBurst ,
+ PLB_rdBurst => PLB_rdBurst ,
+ PLB_wrPendReq => PLB_wrPendReq ,
+ PLB_rdPendReq => PLB_rdPendReq ,
+ PLB_wrPendPri => PLB_wrPendPri ,
+ PLB_rdPendPri => PLB_rdPendPri ,
+ PLB_reqPri => PLB_reqPri ,
+ PLB_TAttribute => PLB_TAttribute ,
+ Sl_addrAck => Sl_addrAck ,
+ Sl_SSize => Sl_SSize ,
+ Sl_wait => Sl_wait ,
+ Sl_rearbitrate => Sl_rearbitrate ,
+ Sl_wrDAck => Sl_wrDAck ,
+ Sl_wrComp => Sl_wrComp ,
+ Sl_wrBTerm => Sl_wrBTerm ,
+ Sl_rdDBus => Sl_rdDBus ,
+ Sl_rdWdAddr => Sl_rdWdAddr ,
+ Sl_rdDAck => Sl_rdDAck ,
+ Sl_rdComp => Sl_rdComp ,
+ Sl_rdBTerm => Sl_rdBTerm ,
+ Sl_MBusy => Sl_MBusy ,
+ Sl_MWrErr => Sl_MWrErr ,
+ Sl_MRdErr => Sl_MRdErr ,
+ Sl_MIRQ => Sl_MIRQ
+ );
+
+
+
+
+
+
+
+
+
+end architecture imp;
+
+
+
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/ise/project.xise
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/ise/project.xise (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/ise/project.xise (revision 2)
@@ -0,0 +1,470 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_wdat.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_wdat.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_wdat.vhd (revision 2)
@@ -0,0 +1,150 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+
+library plb2wb_bridge_v1_00_a;
+use plb2wb_bridge_v1_00_a.plb2wb_pkg.all;
+
+
+entity fifo_wdat is
+ generic
+ (
+ SYNCHRONY : boolean := true; -- true = synchron
+ -- false = asynchron
+ C_SPLB_NATIVE_DWIDTH : integer
+ range PLB_DWIDTH_MIN to PLB_DWIDTH_MAX := WBUF_DWIDTH32
+ );
+ port(
+ rd_en : in std_logic := 'X';
+ wr_en : in std_logic := 'X';
+ wr_clk : in std_logic := 'X';
+ rst : in std_logic := 'X';
+ rd_clk : in std_logic := 'X';
+ din : in std_logic_vector ( WBUF_DWIDTH32-1 downto 0 );
+ full : out std_logic;
+ empty : out std_logic;
+ dout : out std_logic_vector ( WBUF_DWIDTH32-1 downto 0 )
+ );
+end entity fifo_wdat;
+
+
+
+
+architecture IMP of fifo_wdat is
+
+
+ component fifo_wdat_cc_32 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( WBUF_DWIDTH32-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( WBUF_DWIDTH32-1 downto 0 )
+ );
+ end component fifo_wdat_cc_32;
+
+
+ component fifo_wdat_ic_32 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ wr_clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ rd_clk : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( WBUF_DWIDTH32-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( WBUF_DWIDTH32-1 downto 0 )
+ );
+ end component fifo_wdat_ic_32;
+
+begin
+
+
+
+fifo1: if ( SYNCHRONY = true and C_SPLB_NATIVE_DWIDTH = WBUF_DWIDTH32 )
+generate
+U_fifo_cc : fifo_wdat_cc_32
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ clk => rd_clk, -- rd_clk is the same than wr_clk
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo1;
+
+fifo2: if ( SYNCHRONY = false and C_SPLB_NATIVE_DWIDTH = WBUF_DWIDTH32 )
+generate
+U_fifo_ic : fifo_wdat_ic_32
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ rd_clk => rd_clk,
+ wr_clk => wr_clk,
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo2;
+
+
+
+
+end architecture IMP;
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_stu.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_stu.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_stu.vhd (revision 2)
@@ -0,0 +1,435 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library plb2wb_bridge_v1_00_a;
+use plb2wb_bridge_v1_00_a.plb2wb_pkg.all;
+
+entity plb2wb_stu is
+ generic(
+ SYNCHRONY : boolean := true;
+ WB_DWIDTH : integer := 32;
+ WB_AWIDTH : integer := 32;
+ C_SPLB_AWIDTH : integer := 32;
+ C_SPLB_DWIDTH : integer := 128;
+ C_SPLB_MID_WIDTH : integer := 3;
+ C_SPLB_NUM_MASTERS : integer := 1;
+ C_SPLB_SIZE_WIDTH : integer := 4;
+ C_SPLB_BE_WIDTH : integer := 4;
+ C_SPLB_NATIVE_BE_WIDTH : integer := 4;
+ C_SPLB_NATIVE_DWIDTH : integer := 32
+
+
+ );
+ port(
+
+ wb_clk_i : in std_logic;
+ SPLB_Clk : in std_logic;
+ SPLB_Rst : in std_logic;
+
+ PLB_size : in std_logic_vector( 0 to C_SPLB_SIZE_WIDTH -1 );
+ PLB_wrDBus : in std_logic_vector( 0 to C_SPLB_DWIDTH -1 );
+ PLB_masterID : in std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+ PLB_BE : in std_logic_vector( 0 to C_SPLB_BE_WIDTH -1 );
+
+ PLB_ABus : in std_logic_vector( 0 to C_SPLB_AWIDTH -1 );
+
+ --TODO remove this four signals, they are not used!
+ AMU_masterID : in std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+ AMU_buf_masterID : in std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+ AMU_pipe_adr : in std_logic_vector( 0 to C_SPLB_AWIDTH -1 );
+ AMU_buf_adr_wo : in std_logic_vector( WB_AWIDTH-1 downto 0 ); -- without offset
+
+ ----
+ -- When TCU_stat2plb_en is '1', TCU_wb_status_info is written to
+ -- the status pipe, which transfers this info to the plb-side
+ TCU_wb_status_info : in std_logic_vector( STATUS2PLB_INFO_SIZE-1 downto 0 ) ;
+ TCU_stat2plb_en : in std_logic;
+
+
+ ----
+ -- This two signals says if we either do a write transfer, which is
+ -- addressed directly with PLB_ABus or if we do a write transfer
+ -- which is addressed with a secondary address AMU_pipe_adr
+ -- (which comes from address-pipe -> see amu)
+ --
+ TCU_stuWritePA : in std_logic; -- write, addressed with primary address
+ TCU_stuWriteSA : in std_logic; -- write, addressed with second. address
+
+ ----
+ -- This two signals says, if we must latch the primary address
+ -- from PLB_ABus or the secondary address from AMU_pipe_adr
+ -- With latching the address, the read-bus STU_rdDBus has
+ -- assigned the desired data
+ --
+ TCU_stuLatchPA : in std_logic;
+ TCU_stuLatchSA : in std_logic;
+
+
+ -- This signal enalbes the read-bus STU_rdDBus.
+ -- If this signal is '0', STU_rdDBus is complete '0'
+ --
+ TCU_enStuRdDBus : in std_logic;
+ TCU_wb_irq_info : in std_logic_vector( IRQ_INFO_SIZE-1 downto 0 );
+ Sl_rdWdAddr : in std_logic_vector( 0 to 3 );
+ Sl_MIRQ : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+
+ WBF_wBus : in std_logic_vector( 0 to C_SPLB_NATIVE_DWIDTH -1 );
+
+ PLB2WB_IRQ : out std_logic;
+
+
+ ----
+ -- This two signals are used on the wb-side to decide if a transfer must be
+ -- continued or aborted
+ --
+ STU_abort : out std_logic;
+ STU_continue : out std_logic;
+
+
+ STU_full : out std_logic;
+ STU_rdDBus : out std_logic_vector( 0 to C_SPLB_DWIDTH-1 );
+
+ -- The reset-signal, which does a software reset
+ STU_softReset : out std_logic
+ );
+
+end entity plb2wb_stu;
+
+architecture IMP of plb2wb_stu is
+
+ type reg_type is array( integer range<> ) of std_logic_vector( 0 to C_SPLB_NATIVE_DWIDTH-1 );
+
+ signal status_regs : reg_type( 0 to 3);
+ signal status_reg_out : std_logic_vector( 0 to C_SPLB_NATIVE_DWIDTH-1 );
+
+
+
+
+ -------
+ --
+ -- This two bit are used for read transfers from our status registers.
+ -- We DON'T need this for write transfers, because we write in
+ -- one clock cycle ( we don't need to latch the address ).
+ --
+ -- This address-register is loaded with TCU_stuLatchPA or TCU_stuLatchSA
+ --
+ signal address_reg : std_logic_vector( 0 to 1 );
+
+ signal stat2plb_rd_en : std_logic;
+ signal stat2plb_empty : std_logic;
+ signal stat2plb_dout : std_logic_vector( IRQ_INFO_SIZE + C_SPLB_NATIVE_DWIDTH + C_SPLB_AWIDTH + C_SPLB_MID_WIDTH + STATUS2PLB_INFO_SIZE -1 downto 0 );
+ signal stat2plb_din : std_logic_vector( IRQ_INFO_SIZE + C_SPLB_NATIVE_DWIDTH + C_SPLB_AWIDTH + C_SPLB_MID_WIDTH + STATUS2PLB_INFO_SIZE -1 downto 0 );
+
+ signal stat2wb_rd_en : std_logic;
+ signal stat2wb_wr_en : std_logic;
+ signal stat2wb_empty : std_logic;
+ signal stat2wb_full : std_logic;
+ signal stat2wb_dout : std_logic_vector( 1-1 downto 0 );
+ signal stat2wb_din : std_logic_vector( 1-1 downto 0 );
+
+ signal addr_with_offset : std_logic_vector( 0 to 31 );
+
+ signal STU_softReset_t : std_logic;
+ signal soft_reset_count : std_logic_vector( 0 to 1 ); -- counter, implemented with gray-code
+
+
+
+ signal plb2wb_rst : std_logic;
+ signal status_loaded : std_logic;
+
+ signal wb_status_info : std_logic_vector( STATUS2PLB_INFO_SIZE-1 downto 0 );
+ signal wb_master_id : std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+
+
+ signal Sl_MIRQ_t : std_logic_vector( C_SPLB_NUM_MASTERS -1 downto 0 );
+
+
+begin
+
+ Sl_MIRQ <= ( others => '0' );
+
+
+ plb2wb_rst <= SPLB_Rst or STU_softReset_t;
+ STU_softReset <= STU_softReset_t;
+
+
+ status_reg_out <= status_regs(0) when std_logic_vector( unsigned ( address_reg ) + unsigned( Sl_rdWdAddr( 2 to 3 ) ) )= "00" else
+ status_regs(1) when std_logic_vector( unsigned ( address_reg ) + unsigned( Sl_rdWdAddr( 2 to 3 ) ) )= "01" else
+ status_regs(2) when std_logic_vector( unsigned ( address_reg ) + unsigned( Sl_rdWdAddr( 2 to 3 ) ) )= "10" else
+ status_regs(3);
+
+
+ gen_128 : if C_SPLB_DWIDTH = 128 generate
+ STU_rdDBus <= status_reg_out & status_reg_out & status_reg_out & status_reg_out when TCU_enStuRdDBus = '1' else
+ ( others => '0' );
+ end generate;
+
+ gen_64 : if C_SPLB_DWIDTH = 64 generate
+ STU_rdDBus <= status_reg_out & status_reg_out when TCU_enStuRdDBus = '1' else
+ ( others => '0' );
+ end generate;
+
+ gen_32 : if C_SPLB_DWIDTH = 32 generate
+ STU_rdDBus <= status_reg_out when TCU_enStuRdDBus = '1' else
+ ( others => '0' );
+ end generate;
+
+
+
+
+ stat2plb : entity plb2wb_bridge_v1_00_a.fifo_stat2plb
+ generic map(
+ SYNCHRONY => SYNCHRONY,
+ WB_DWIDTH => WB_DWIDTH,
+ WB_AWIDTH => WB_AWIDTH,
+ C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH
+ )
+ port map(
+ rd_en => stat2plb_rd_en,
+ wr_en => TCU_stat2plb_en,
+ full => STU_full,
+ empty => stat2plb_empty,
+ wr_clk => wb_clk_i,
+ rst => plb2wb_rst,
+ rd_clk => SPLB_Clk,
+ dout => stat2plb_dout,
+ din => stat2plb_din
+ );
+
+
+
+ stat2wb : entity plb2wb_bridge_v1_00_a.fifo_stat2wb
+ generic map(
+ SYNCHRONY => SYNCHRONY
+ )
+ port map(
+ rd_en => stat2wb_rd_en,
+ wr_en => stat2wb_wr_en,
+ full => stat2wb_full,
+ empty => stat2wb_empty,
+ wr_clk => SPLB_Clk,
+ rst => plb2wb_rst,
+ rd_clk => wb_clk_i,
+ dout => stat2wb_dout,
+ din => stat2wb_din
+ );
+
+ stat2plb_din <= TCU_wb_irq_info & AMU_buf_adr_wo & WBF_wBus & TCU_wb_status_info & AMU_buf_masterID;
+
+ wb_status_info <= stat2plb_dout( STATUS2PLB_INFO_SIZE + C_SPLB_MID_WIDTH -1 downto C_SPLB_MID_WIDTH );
+
+ wb_master_id <= stat2plb_dout( C_SPLB_MID_WIDTH-1 downto 0 );
+
+
+
+
+ status_reg_p : process( SPLB_Clk, SPLB_Rst, stat2plb_rd_en, Sl_MIRQ_t, status_regs, plb2wb_rst )
+ begin
+
+ if plb2wb_rst = '1' then
+ status_regs <= ( others => ( others => '0' ) );
+ address_reg <= ( others => '0' );
+ status_loaded <= '0';
+ elsif SPLB_Clk'event and SPLB_Clk = '1' then
+
+
+ if TCU_stuLatchPA = '1' then
+ address_reg <= PLB_ABus( 28 to 29 );
+ elsif TCU_stuLatchSA = '1' then
+ address_reg <= AMU_pipe_adr( 28 to 29 );
+ end if;
+
+
+ ----
+ -- Write acceess to the first regser address = "00"
+ -- -> clears the irq
+ if ( ( TCU_stuWritePA = '1' and PLB_ABus( 28 to 29 ) = "00" ) or
+ ( TCU_stuWriteSA = '1' and AMU_pipe_adr( 28 to 29 ) = "00" ) )
+ then
+ status_loaded <= '0';
+ status_regs( 0 ) <= ( others => '0' );
+ end if;
+
+
+ -----
+ --
+ -- if there is something in the pipe, we save it
+ -- (we don't save the bit about the finished transfer!)
+ --
+ -- NOTE: This has a higher priority than writing from plb-bus!!
+ --
+ --
+ if ( stat2plb_rd_en = '1' ) then
+ status_regs(0)(0 to STATUS2PLB_INFO_SIZE-1 ) <= status_regs(0)(0 to STATUS2PLB_INFO_SIZE-1 ) or wb_status_info( STATUS2PLB_INFO_SIZE-1 downto 0 );
+ status_loaded <= '1';
+
+
+ status_regs(3) <= stat2plb_dout( IRQ_INFO_SIZE +
+ C_SPLB_AWIDTH +
+ C_SPLB_NATIVE_DWIDTH +
+ STATUS2PLB_INFO_SIZE +
+ C_SPLB_MID_WIDTH -1
+ downto
+ C_SPLB_AWIDTH +
+ C_SPLB_NATIVE_DWIDTH +
+ STATUS2PLB_INFO_SIZE +
+ C_SPLB_MID_WIDTH );
+
+
+ status_regs(2) <= stat2plb_dout( C_SPLB_AWIDTH + C_SPLB_NATIVE_DWIDTH +
+ STATUS2PLB_INFO_SIZE + C_SPLB_MID_WIDTH -1
+ downto
+ C_SPLB_NATIVE_DWIDTH + STATUS2PLB_INFO_SIZE +
+ C_SPLB_MID_WIDTH );
+
+
+
+ status_regs(1) <= stat2plb_dout( C_SPLB_NATIVE_DWIDTH + STATUS2PLB_INFO_SIZE +
+ C_SPLB_MID_WIDTH -1
+ downto
+ STATUS2PLB_INFO_SIZE + C_SPLB_MID_WIDTH );
+
+ status_regs(0)( C_SPLB_NATIVE_DWIDTH - C_SPLB_MID_WIDTH to C_SPLB_NATIVE_DWIDTH -1 ) <= wb_master_id;
+
+
+
+ end if;
+
+ end if;
+
+
+
+
+ end process;
+
+
+ stat2plb_rd_en <= '1' when ( stat2plb_empty = '0' and status_loaded = '0' and TCU_stuWritePA = '0' and TCU_stuWriteSA = '0' ) else
+ '0';
+
+
+ --------
+ --
+ -- Interrupt generation
+ --
+ Sl_MIRQ_t <= ( others => '0' ); -- is not supported by xilinx!
+ PLB2WB_IRQ <= status_regs(0)( 2 ) or status_regs(0)( 1 ) or status_regs(0)( 0 );
+
+
+
+
+
+
+ ----------
+ --
+ -- Handling of write access to the status registers
+ -- (except clearing the irq)
+ -- - soft reset (for 4 clock cycles) address = "11"
+ -- - continue failed write transfer address = "01"
+ -- - abort failed write transfer address = "10"
+ --
+ status_state_p : process( SPLB_Clk, SPLB_Rst, TCU_stuWritePA, PLB_ABus, TCU_stuWriteSA, AMU_pipe_adr )
+ begin
+
+ if SPLB_Rst = '1' then
+ soft_reset_count <= ( others => '0' );
+ elsif SPLB_Clk'event and SPLB_Clk = '1' then
+
+ -- if the status-address range is selected:
+ -- do a soft reset, depending on the address
+ if ( ( soft_reset_count = "00" and TCU_stuWritePA = '1' and PLB_ABus( 28 to 29 ) = "11" ) or
+ ( soft_reset_count = "00" and TCU_stuWriteSA = '1' and AMU_pipe_adr( 28 to 29 ) = "11" ) ) then
+ soft_reset_count <= "10";
+ end if;
+
+ if soft_reset_count = "10" then
+ soft_reset_count <= "11";
+ elsif soft_reset_count = "11" then
+ soft_reset_count <= "01";
+ elsif soft_reset_count = "01" then
+ soft_reset_count <= "00";
+ end if;
+
+
+
+ end if;
+
+
+ -- if the status-address range is selected:
+ -- add a continue or abort information to the fifo, depending on the address
+ --
+ stat2wb_din <= "0";
+ stat2wb_wr_en <= '0';
+ if ( ( TCU_stuWritePA = '1' and PLB_ABus( 28 to 29 ) = "01" ) or
+ ( TCU_stuWriteSA = '1' and AMU_pipe_adr( 28 to 29 ) = "01" ) ) then
+ stat2wb_din <= STATUS_CONTINUE;
+ stat2wb_wr_en <= '1';
+ elsif ( ( TCU_stuWritePA = '1' and PLB_ABus( 28 to 29 ) = "10" ) or
+ ( TCU_stuWriteSA = '1' and AMU_pipe_adr( 28 to 29 ) = "10" ) ) then
+ stat2wb_din <= STATUS_ABORT;
+ stat2wb_wr_en <= '1';
+ end if;
+
+ end process;
+
+
+ stat2wb_rd_en <= not stat2wb_empty;
+ STU_continue <= '1' when stat2wb_empty = '0' and stat2wb_dout = STATUS_CONTINUE else
+ '0';
+ STU_abort <= '1' when stat2wb_empty = '0' and stat2wb_dout = STATUS_ABORT else
+ '0';
+
+
+
+ STU_softReset_t <= '0' when soft_reset_count = "00" else
+ '1';
+
+
+
+end architecture IMP;
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_tcu.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_tcu.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_tcu.vhd (revision 2)
@@ -0,0 +1,1931 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+
+
+library plb2wb_bridge_v1_00_a;
+use plb2wb_bridge_v1_00_a.plb2wb_pkg.all;
+
+entity plb2wb_tcu is
+ generic(
+ C_SPLB_NUM_MASTERS : integer := 1;
+ C_SPLB_MID_WIDTH : integer := 3;
+ C_SPLB_SIZE_WIDTH : integer := 4;
+ C_SPLB_NATIVE_BE_WIDTH : integer := 4;
+ C_SPLB_DWIDTH : integer := 128;
+ C_SPLB_TYPE_WIDTH : integer := 4;
+ C_SPLB_SUPPORT_BUR_LINE : integer := 1;
+ WB_PIC_INTS : integer := 0;
+ WB_PIC_INT_LEVEL : std_logic := '1';
+ WB_TIMEOUT_CYCLES : integer := 10;
+ WB_SUPPORT_BLOCK : integer := 1
+
+ );
+ port(
+
+ wb_clk_i : in std_logic;
+ wb_ack_i : in std_logic;
+ wb_err_i : in std_logic;
+ wb_rty_i : in std_logic;
+ wb_rst_i : in std_logic;
+ wb_pic_int_i : in std_logic_vector( WB_PIC_INTS-1 downto 0 );
+
+ AMU_deviceSelect : in std_logic;
+ AMU_statusSelect : in std_logic;
+ AMU_bufEmpty : in std_logic;
+ AMU_bufFull : in std_logic;
+ AMU_buf_RNW : in std_logic;
+ AMU_buf_size : in std_logic_vector( C_SPLB_SIZE_WIDTH-1 downto 0 );
+ AMU_buf_BE : in std_logic_vector( C_SPLB_NATIVE_BE_WIDTH-1 downto 0 );
+ AMU_pipe_size : in std_logic_vector( 0 to C_SPLB_SIZE_WIDTH-1 );
+ AMU_pipe_rmID : in std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+ AMU_pipe_wmID : in std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+ AMU_pipe_BE : in std_logic_vector( 0 to C_SPLB_NATIVE_BE_WIDTH-1 );
+ AMU_pipe_rStatusSelect : in std_logic;
+ AMU_pipe_wStatusSelect : in std_logic;
+
+ WBF_empty : in std_logic;
+ WBF_full : in std_logic;
+
+ RBF_empty : in std_logic;
+ RBF_almostEmpty : in std_logic;
+ RBF_full : in std_logic;
+
+ SPLB_Clk : in std_logic;
+ plb2wb_rst : in std_logic;
+ PLB_MSize : in std_logic_vector( 0 to 1 );
+ PLB_TAttribute : in std_logic_vector( 0 to 15 );
+ PLB_lockErr : in std_logic;
+ PLB_abort : in std_logic;
+ PLB_rdBurst : in std_logic;
+ PLB_wrBurst : in std_logic;
+ PLB_RNW : in std_logic;
+ PLB_PAValid : in std_logic;
+ PLB_masterID : in std_logic_vector( 0 to C_SPLB_MID_WIDTH-1 );
+ PLB_rdPrim : in std_logic;
+ PLB_wrPrim : in std_logic;
+ PLB_size : in std_logic_vector( 0 to C_SPLB_SIZE_WIDTH-1 );
+ PLB_BE : in std_logic_vector( 0 to C_SPLB_DWIDTH/8-1 );
+ PLB_type : in std_logic_vector( 0 to C_SPLB_TYPE_WIDTH -1 );
+
+ STU_abort : in std_logic;
+ STU_continue : in std_logic;
+
+ RBF_rdErrOut : in std_logic;
+ RBF_rdErrIn : out std_logic;
+
+
+ Sl_MRdErr : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ Sl_MWrErr : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ Sl_wrDAck : out std_logic;
+ Sl_wrComp : out std_logic;
+ Sl_wrBTerm : out std_logic;
+ Sl_rdDAck : out std_logic;
+ Sl_rdComp : out std_logic;
+ Sl_rdBTerm : out std_logic;
+ Sl_rdWdAddr : out std_logic_vector( 0 to 3 );
+ Sl_wait : out std_logic;
+ Sl_rearbitrate : out std_logic;
+
+ TCU_wbufWEn : out std_logic;
+ TCU_wbufREn : out std_logic;
+
+ TCU_rbufWEn : out std_logic;
+ TCU_rbufREn : out std_logic;
+
+ TCU_adrBufWEn : out std_logic;
+ TCU_adrBufREn : out std_logic;
+ TCU_rpipeRdEn : out std_logic;
+ TCU_wpipeRdEn : out std_logic;
+
+ TCU_enRdDBus : out std_logic;
+ TCU_MRBusy : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ TCU_addrAck : out std_logic;
+ TCU_adr_offset : out std_logic_vector( 3 downto 0 );
+
+ TCU_stuLatchPA : out std_logic;
+ TCU_stuLatchSA : out std_logic;
+ TCU_stuWritePA : out std_logic;
+ TCU_stuWriteSA : out std_logic;
+ TCU_stat2plb_en : out std_logic;
+ TCU_enStuRdDBus : out std_logic;
+ TCU_wb_status_info : out std_logic_vector( STATUS2PLB_INFO_SIZE-1 downto 0 );
+ TCU_wb_irq_info : out std_logic_vector( IRQ_INFO_SIZE-1 downto 0 );
+
+ wb_lock_o : out std_logic;
+ wb_stb_o : out std_logic;
+ wb_we_o : out std_logic;
+ wb_cyc_o : out std_logic
+
+
+ );
+end entity plb2wb_tcu;
+
+
+architecture IMP of plb2wb_tcu is
+
+
+ signal TCU_wbufWEn_t : std_logic;
+ signal TCU_wbufREn_t : std_logic;
+ signal TCU_adrBufWEn_w : std_logic;
+ signal TCU_adrBufWEn_r : std_logic;
+ signal TCU_rbufWEn_t : std_logic;
+ signal TCU_rbufREn_t : std_logic;
+ signal TCU_stuWritePA_t : std_logic;
+ signal TCU_stuWriteSA_t : std_logic;
+
+ signal Sl_rdComp_t : std_logic;
+ signal Sl_wrComp_t : std_logic;
+
+ signal Sl_rdDAck_t : std_logic;
+
+ signal TCU_rpipeRdEn_t : std_logic;
+ signal TCU_wpipeRdEn_t : std_logic;
+
+ --
+ -- Wishbone current and next state
+ type wb_trans_state is ( wb_idle, wb_write, wb_read, wb_write_rty, wb_read_rty, wb_write_stall );
+ type wb_trans_state_type is record
+ state : wb_trans_state;
+ transfer_count : std_logic_vector( 3 downto 0 );
+ abort : std_logic;
+ end record;
+ signal c_wb_state, n_wb_state : wb_trans_state_type;
+
+
+
+ --
+ -- PLB current and next state
+ type plb_wtrans_state is( plb_widle, plb_write, plb_burst_write );
+ type plb_rtrans_state is( plb_ridle, plb_read, plb_read_ack, plb_line_read,
+ plb_line_read_ack, plb_burst_read, plb_burst_read_ack,
+ plb_wait_line_read, plb_wait_burst_read );
+
+ type plb_rtrans_state_type is record
+ state : plb_rtrans_state;
+ r_master_id : std_logic_vector( C_SPLB_MID_WIDTH-1 downto 0 );
+ r_secondary : std_logic;
+ transfer_count : std_logic_vector( 0 to 3 );
+ transfer_size : std_logic_vector( 0 to C_SPLB_SIZE_WIDTH-1 );
+ status_transfer : std_logic;
+ end record;
+
+ type plb_wtrans_state_type is record
+ state : plb_wtrans_state;
+ w_master_id : std_logic_vector( C_SPLB_MID_WIDTH-1 downto 0 );
+ w_secondary : std_logic;
+ transfer_count : std_logic_vector( 0 to 3 );
+ transfer_size : std_logic_vector( 0 to C_SPLB_SIZE_WIDTH-1 );
+ status_transfer : std_logic;
+ end record;
+
+ signal c_plb_wstate : plb_wtrans_state_type; -- current write state
+ signal n_plb_wstate : plb_wtrans_state_type; -- next write state
+ signal c_plb_rstate : plb_rtrans_state_type; -- current read state
+ signal n_plb_rstate : plb_rtrans_state_type; -- next read state
+
+
+
+ signal mbusy_read_out : std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ signal mbusy_write_out : std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+
+
+ signal start_plb_w : std_logic; -- start plb write (to wb side)
+ signal start_plb_r : std_logic; -- start plb read (from wb side)
+
+ signal start_plb_stat_w : std_logic; -- start plb status write
+ signal start_plb_stat_r : std_logic; -- start plb status read
+
+ signal start_plb_sec_w : std_logic; -- start plb write (to wb side, pipelined)
+ signal start_plb_sec_r : std_logic; -- start plb read (from wb side, pipelined)
+
+ signal start_plb_sec_stat_r : std_logic; -- start plb write to status (pipelined)
+ signal start_plb_sec_stat_w : std_logic; -- start plb read from status (pipelined)
+
+
+
+ signal start_wb_w : std_logic; -- start wb write
+ signal start_wb_r : std_logic; -- start wb read
+
+ signal wb_ack : std_logic;
+ signal wb_rty : std_logic;
+ signal wb_err : std_logic;
+
+ signal addrAck_w : std_logic;
+ signal addrAck_r : std_logic;
+
+ signal TCU_stuLatchPA_r : std_logic;
+ signal TCU_stuLatchSA_r : std_logic;
+ signal TCU_stuLatchPA_w : std_logic;
+ signal TCU_stuLatchSA_w : std_logic;
+
+
+ signal wb_rst_short : std_logic;
+
+
+ signal pic_int_ahigh : std_logic_vector( WB_PIC_INTS-1 downto 0 );
+ signal pic_int_ahigh_short : std_logic_vector( WB_PIC_INTS-1 downto 0 );
+ signal pic_int2plb_en : std_logic;
+
+
+ -----
+ -- wishbone timeout counter
+ --
+ constant WB_TOUT_COUNTER_SIZE : integer := log2( WB_TIMEOUT_CYCLES );
+ constant WB_TOUT_MAX_VALUE : std_logic_vector( WB_TOUT_COUNTER_SIZE-1 downto 0 )
+ := std_logic_vector( to_unsigned( WB_TIMEOUT_CYCLES-1, WB_TOUT_COUNTER_SIZE ) );
+ constant WB_TOUT_MIN_VALUE : std_logic_vector( WB_TOUT_COUNTER_SIZE-1 downto 0 )
+ := ( others => '0' );
+ signal wb_tout_counter : std_logic_vector( WB_TOUT_COUNTER_SIZE-1 downto 0 );
+ signal wb_tout_count : std_logic;
+ signal wb_tout_reset : std_logic;
+ signal wb_tout_alarm : std_logic;
+
+
+
+begin
+
+
+
+
+ TCU_wbufWEn <= TCU_wbufWEn_t;
+ TCU_wbufREn <= TCU_wbufREn_t;
+ TCU_adrBufWEn <= TCU_adrBufWEn_w or TCU_adrBufWEn_r;
+ TCU_rbufWEn <= TCU_rbufWEn_t;
+ TCU_rbufREn <= TCU_rbufREn_t;
+ Sl_rdComp <= Sl_rdComp_t;
+ Sl_wrComp <= Sl_wrComp_t;
+ Sl_rdDAck <= Sl_rdDAck_t;
+ TCU_rpipeRdEn <= TCU_rpipeRdEn_t;
+ TCU_wpipeRdEn <= TCU_wpipeRdEn_t;
+ TCU_stuWritePA <= TCU_stuWritePA_t;
+ TCU_stuWriteSA <= TCU_stuWriteSA_t;
+ TCU_stuLatchSA <= TCU_stuLatchSA_r or TCU_stuLatchSA_w;
+ TCU_stuLatchPA <= TCU_stuLatchPA_r or TCU_stuLatchPA_w;
+
+ TCU_addrAck <= addrAck_w or addrAck_r;
+
+
+
+
+
+
+ Sl_rearbitrate <= '0'; -- there is no situation, where we want to reabitrate
+
+
+
+
+
+ Sl_wait <= '1' when addrAck_w = '0' and addrAck_r = '0'
+ and AMU_deviceSelect = '1'
+ and PLB_PAValid = '1'
+ and PLB_RNW = '0'
+ and AMU_bufFull = '1';
+
+
+
+ ------
+ --
+ -- interrupt signals: they are converted to active-high signals,
+ -- which are only for one clock cycle '1'
+ --
+ pic_ints : if WB_PIC_INTS > 0 generate
+
+ --
+ -- Generate the active-high interrupt levels
+ -- (we work internaly only with active-high interrupt levels)
+ --
+ gen_active_high1 : if WB_PIC_INT_LEVEL = '0' generate
+ pic_int_ahigh <= not wb_pic_int_i;
+ end generate gen_active_high1;
+ gen_active_high2 : if WB_PIC_INT_LEVEL = '1' generate
+ pic_int_ahigh <= wb_pic_int_i;
+ end generate gen_active_high2;
+
+ --
+ -- Generate short impulses (of one clock cycle)
+ --
+ gen_active_high_short : for i in 0 to WB_PIC_INTS-1 generate
+ ah_short : entity plb2wb_bridge_v1_00_a.plb2wb_short_impulse( IMP )
+ port map( CLK => wb_clk_i,
+ RESET => plb2wb_rst,
+ IMPULSE => pic_int_ahigh(i),
+ SHORT_IMPULSE => pic_int_ahigh_short(i) );
+
+ end generate;
+
+ end generate;
+ --
+ -----
+
+
+
+
+
+
+
+ short_impulse : entity plb2wb_bridge_v1_00_a.plb2wb_short_impulse( IMP )
+ port map ( CLK => wb_clk_i,
+ RESET => plb2wb_rst,
+ IMPULSE => wb_rst_i,
+ SHORT_IMPULSE => wb_rst_short );
+
+
+
+
+
+ ------------------------------
+ --
+ -- This signals are '1' if a transfer is started:
+ -- (burst and line transfers are supported)
+ --
+ -- start_plb_w: start a write transfer to the WB side
+ -- start_plb_r: start a read transfer from the WB side
+ -- start_plb_stat_w: start a write transfer to the status registers
+ -- start_plb_stat_r: start a read transfer from the status registers
+ --
+ --
+ with_plb_bursts : if C_SPLB_SUPPORT_BUR_LINE > 0 generate
+
+
+ start_plb_w <= '1' when ( -- we are in the idle state
+ c_plb_wstate.state = plb_widle
+
+ -- Address in our range, primary-addr is valid and it is a write transfer
+ and AMU_deviceSelect = '1' and PLB_PAValid = '1' and PLB_RNW = '0'
+
+ -- this transfer-type is implemented
+ --(normal, line and burst -> all fixed-length word bursts)
+ and ( PLB_size( 0 to 1 ) = "00" or ( PLB_size = "1010" and PLB_BE( 0 to 3 ) /= "0000" ) )
+
+ -- we are not transfering data from the read pipe
+ and TCU_rpipeRdEn_t /= '1'
+
+ -- the address buffer is not full
+ and AMU_bufFull = '0'
+
+ -- supported transfer-type (only mem-type is supported, see PLB-Spec. page 43)
+ and ( PLB_type = "000" or PLB_type = "110" ) )
+ else '0';
+
+
+ start_plb_r <= '1' when( -- we are in the idle state
+ c_plb_rstate.state = plb_ridle
+
+ -- Address in our range, primary-addr is valid and it is a read transfer
+ and AMU_deviceSelect = '1' and PLB_PAValid = '1' and PLB_RNW = '1'
+
+ -- this transfer-type is implemented (normal and line)
+ and ( PLB_size( 0 to 1 ) = "00" or ( PLB_size = "1010" and PLB_BE( 0 to 3 ) /="0000" ) )
+
+ -- we are not transfering data from the write-pipe
+ and TCU_wpipeRdEn_t /= '1'
+
+ -- the address buffer is not full
+ and AMU_bufFull = '0'
+
+ -- supported transfer-type (only mem-type is supported, see PLB-Spec. page 43)
+ and ( PLB_type = "000" or PLB_type = "110" ) )
+
+ else '0';
+
+
+
+ start_plb_stat_w <= '1' when ( -- we are in the idle state
+ c_plb_wstate.state = plb_widle
+
+ -- Address in our range, primary-addr is valid and it is a write transfer
+ and AMU_statusSelect = '1' and PLB_PAValid = '1' and PLB_RNW = '0'
+
+ -- this transfer-type is implemented
+ --(normal, line and burst -> all fixed-length word bursts)
+ and ( PLB_size( 0 to 1 ) = "00" or ( PLB_size = "1010" and PLB_BE( 0 to 3 ) /= "0000" ) )
+
+ -- supported transfer-type (only mem-type is supported, see PLB-Spec. page 43)
+ and ( PLB_type = "000" or PLB_type = "110" ) )
+ else '0';
+
+
+
+
+ start_plb_stat_r <= '1' when (
+ -- we are in the idle state
+ c_plb_rstate.state = plb_ridle
+
+ -- Address in our range, primary-addr is valid and it is a write transfer
+ and AMU_statusSelect = '1' and PLB_PAValid = '1' and PLB_RNW = '1'
+
+ -- this transfer-type is implemented
+ --(normal, line and burst -> all fixed-length word bursts)
+ and ( PLB_size( 0 to 1 ) = "00" or ( PLB_size = "1010" and PLB_BE( 0 to 3 ) /= "0000" ) )
+
+ -- supported transfer-type (only mem-type is supported, see PLB-Spec. page 43)
+ and ( PLB_type = "000" or PLB_type = "110" ) )
+ else '0';
+
+ end generate with_plb_bursts;
+
+
+
+
+
+
+
+ ------------------------------
+ --
+ -- This signals are '1' if a transfer is started:
+ -- (burst and line transfers are not supported)
+ --
+ -- start_plb_w: start a write transfer to the WB side
+ -- start_plb_r: start a read transfer from the WB side
+ -- start_plb_stat_w: start a write transfer to the status registers
+ -- start_plb_stat_r: start a read transfer from the status registers
+ --
+ --
+ without_plb_bursts : if C_SPLB_SUPPORT_BUR_LINE = 0 generate
+
+
+ start_plb_w <= '1' when ( -- we are in the idle state
+ c_plb_wstate.state = plb_widle
+
+ -- Address in our range, primary-addr is valid and it is a write transfer
+ and AMU_deviceSelect = '1' and PLB_PAValid = '1' and PLB_RNW = '0'
+
+ -- this transfer-type is implemented (only single)
+ and ( PLB_size = "0000" )
+
+ -- we are not transfering data from the read pipe
+ and TCU_rpipeRdEn_t /= '1'
+
+ -- the address buffer is not full
+ and AMU_bufFull = '0'
+
+ -- supported transfer-type (only mem-type is supported, see PLB-Spec. page 43)
+ and ( PLB_type = "000" or PLB_type = "110" ) )
+ else '0';
+
+
+ start_plb_r <= '1' when( -- we are in the idle state
+ c_plb_rstate.state = plb_ridle
+
+ -- Address in our range, primary-addr is valid and it is a read transfer
+ and AMU_deviceSelect = '1' and PLB_PAValid = '1' and PLB_RNW = '1'
+
+ -- this transfer-type is implemented (only single)
+ and ( PLB_size = "0000" )
+
+ -- we are not transfering data from the write-pipe
+ and TCU_wpipeRdEn_t /= '1'
+
+ -- the address buffer is not full
+ and AMU_bufFull = '0'
+
+ -- supported transfer-type (only mem-type is supported, see PLB-Spec. page 43)
+ and ( PLB_type = "000" or PLB_type = "110" ) )
+
+ else '0';
+
+
+
+ start_plb_stat_w <= '1' when ( -- we are in the idle state
+ c_plb_wstate.state = plb_widle
+
+ -- Address in our range, primary-addr is valid and it is a write transfer
+ and AMU_statusSelect = '1' and PLB_PAValid = '1' and PLB_RNW = '0'
+
+ -- this transfer-type is implemented (only single)
+ and ( PLB_size = "0000" )
+
+ -- supported transfer-type (only mem-type is supported, see PLB-Spec. page 43)
+ and ( PLB_type = "000" or PLB_type = "110" ) )
+ else '0';
+
+
+
+
+ start_plb_stat_r <= '1' when (
+ -- we are in the idle state
+ c_plb_rstate.state = plb_ridle
+
+ -- Address in our range, primary-addr is valid and it is a write transfer
+ and AMU_statusSelect = '1' and PLB_PAValid = '1' and PLB_RNW = '1'
+
+ -- this transfer-type is implemented (only single)
+ and ( PLB_size = "0000" )
+
+ -- supported transfer-type (only mem-type is supported, see PLB-Spec. page 43)
+ and ( PLB_type = "000" or PLB_type = "110" ) )
+ else '0';
+
+ end generate without_plb_bursts;
+
+
+
+
+
+
+
+
+
+ start_plb_sec_w <= '1' when(
+ c_plb_wstate.state = plb_widle -- ----
+ and c_plb_wstate.w_secondary = '1' -- This is the case, when there is a write
+ and AMU_bufFull = '0' -- from a secondary request directly after a write
+ and AMU_pipe_wStatusSelect = '0' -- (this transfer does not write to our status regs)
+ -- and TCU_rpipeRdEn_t /= '1' -- note: start_plb_sec_w has a higher priority
+ -- than start_plb_sec_r, (we can't check
+ -- TCU_rpipeRdEn_t, because this generates a
+ -- combinatorial loop!!)
+ ) -- ----
+ else '0';
+
+
+ start_plb_sec_stat_w <= '1' when( c_plb_wstate.state = plb_widle -- ----
+ and c_plb_wstate.w_secondary = '1' -- This is the case, when there is a write
+ and AMU_pipe_wStatusSelect = '1' -- from a secondary request (we write to our status regs)
+ ) -- ----
+ else '0';
+
+
+ start_plb_sec_r <= '1' when( c_plb_rstate.state = plb_ridle -- ----
+ and c_plb_rstate.r_secondary = '1' -- This is the case, when there is a read
+ and AMU_bufFull = '0' -- from a secondary request directly after a read
+ and AMU_pipe_rStatusSelect = '0' -- (this transfer does not read from our status regs)
+ and TCU_wpipeRdEn_t /= '1' ) -- ----
+ else '0';
+
+
+ start_plb_sec_stat_r <= '1' when( c_plb_rstate.state = plb_ridle -- ----
+ and c_plb_rstate.r_secondary = '1' -- This is the case, when there is a read
+ and AMU_pipe_rStatusSelect = '1' -- from a secondary request (we read from our status regs)
+ ) -- ----
+ else '0';
+
+
+
+ c_plb_state_p : process( SPLB_Clk, plb2wb_rst ) begin
+ if plb2wb_rst='1' then
+
+ c_plb_rstate <= ( state => plb_ridle,
+ r_master_id => ( others => '0' ),
+ transfer_count => ( others => '0' ),
+ transfer_size => ( others => '0' ),
+ status_transfer => '0',
+ r_secondary => '0' );
+ c_plb_wstate <= ( state => plb_widle,
+ w_master_id => ( others => '0' ),
+ transfer_count => ( others => '0' ),
+ transfer_size => ( others => '0' ),
+ status_transfer => '0',
+ w_secondary => '0' );
+
+
+ elsif SPLB_Clk'event and SPLB_Clk='1' then
+ c_plb_rstate <= n_plb_rstate;
+ c_plb_wstate <= n_plb_wstate;
+ end if;
+ end process;
+
+
+
+
+
+ n_plb_wstate_p : process( c_plb_wstate,
+ PLB_PAValid, PLB_RNW, PLB_masterID, PLB_wrPrim, PLB_size, PLB_BE,
+ AMU_deviceSelect, AMU_statusSelect, AMU_bufFull, WBF_full, AMU_pipe_size, AMU_pipe_wmID, AMU_pipe_BE,
+ start_plb_sec_w, start_plb_sec_stat_w, start_plb_w, start_plb_stat_w,
+ TCU_rpipeRdEn_t )
+ begin
+
+
+ Sl_MWrErr <= ( others => '0' );
+
+ -- default output logic
+ Sl_wrDAck <= '0';
+ Sl_wrComp_t <= '0';
+ Sl_wrBTerm <= '0';
+
+ TCU_wbufWEn_t <= '0';
+ TCU_adrBufWEn_w <= '0';
+ TCU_wpipeRdEn_t <= '0';
+ addrAck_w <= '0';
+
+
+ TCU_stuLatchSA_w <= '0';
+ TCU_stuLatchPA_w <= '0';
+
+ -- default state
+ n_plb_wstate <= c_plb_wstate;
+ mbusy_write_out <= ( others => '0' );
+
+ TCU_stuWritePA_t <= '0';
+ TCU_stuWriteSA_t <= '0';
+
+ if PLB_wrPrim = '1' then
+ n_plb_wstate.w_secondary <= '1';
+ end if;
+
+
+
+ if start_plb_sec_w = '1' then
+
+ -- read from pipe and add it to the buffer
+ TCU_wpipeRdEn_t <= '1';
+ TCU_adrBufWEn_w <= '1';
+
+ n_plb_wstate.w_secondary <= '0';
+ n_plb_wstate.status_transfer <= '0';
+
+ -- we latch the masterID
+ n_plb_wstate.w_master_id <= AMU_pipe_wmID;
+
+ -- buffer is not full, this is a implemented transfer and this is a normal/single transfer
+ if WBF_full = '0' and AMU_pipe_size = "0000" then
+
+ -- add data to the buffer
+ TCU_wbufWEn_t <= '1';
+ -- ack transfer to PLB
+ Sl_wrDAck <= '1';
+ Sl_wrComp_t <= '1';
+
+ -- we stay in the idle state
+
+ -- buffer is not full, this is a line transfer
+ elsif WBF_full = '0' and AMU_pipe_size( 0 to 1 ) = "00" and AMU_pipe_size( 2 to 3 ) /= "00" then
+
+ -- add data to the buffer
+ TCU_wbufWEn_t <= '1';
+ -- ack transfer to PLB
+ Sl_wrDAck <= '1';
+
+ n_plb_wstate.state <= plb_write;
+ n_plb_wstate.transfer_size <= AMU_pipe_size;
+ -- we did one transfer in this clock cycle
+ n_plb_wstate.transfer_count <= "0001";
+
+ -- buffer is full, we switch to the wait-state and wait until we can write to the buffer
+ elsif WBF_full = '1' and AMU_pipe_size( 0 to 1 ) = "00" then
+
+ n_plb_wstate.state <= plb_write;
+ n_plb_wstate.transfer_size <= AMU_pipe_size;
+ -- we did one transfer in this clock cycle
+ n_plb_wstate.transfer_count <= "0000";
+
+ -- this is a burst transfer
+ -- and the buffer is not full
+ elsif WBF_full = '0' and AMU_pipe_size( 0 to 1 ) /= "00" then
+
+ -- add data to the buffer
+ TCU_wbufWEn_t <= '1';
+ -- ack transfer to PLB
+ Sl_wrDAck <= '1';
+
+ n_plb_wstate.state <= plb_burst_write;
+ n_plb_wstate.transfer_size <= AMU_pipe_BE;
+ -- we did one transfer in this clock cycle
+ n_plb_wstate.transfer_count <= "0001";
+
+ -- this is a burst transfer
+ -- and the buffer is full
+ elsif WBF_full = '1' and AMU_pipe_size( 0 to 1 ) /= "00" then
+
+ n_plb_wstate.state <= plb_burst_write;
+ n_plb_wstate.transfer_size <= AMU_pipe_BE;
+ -- we did one transfer in this clock cycle
+ n_plb_wstate.transfer_count <= "0000";
+
+ end if;
+
+
+
+ --
+ -- NOTE: it is not allowed to write with a burst or line transfer to the status
+ -- registers, so TCU_stuWriteSA_t is only '1' for a single transfer!
+ --
+ elsif start_plb_sec_stat_w = '1' then
+
+ TCU_wpipeRdEn_t <= '1';
+
+ -- we latch the masterID
+ n_plb_wstate.w_master_id <= AMU_pipe_wmID;
+
+ n_plb_wstate.w_secondary <= '0';
+
+ -- ack transfer to PLB
+ Sl_wrDAck <= '1';
+
+
+ if AMU_pipe_size = "1010" and AMU_pipe_BE( 0 to 3 ) /= "0000" then
+ -- burst transfer
+
+
+ Sl_MWrErr( to_integer( unsigned'( unsigned( AMU_pipe_wmID ) ) ) ) <= '1';
+
+ -- we switch to the burst_write state:
+ -- we write until transfer_count = transfer_size
+ n_plb_wstate.state <= plb_burst_write;
+ n_plb_wstate.transfer_size <= AMU_pipe_BE( 0 to 3 );
+ -- we did no transfer in this clock cycle
+ n_plb_wstate.transfer_count <= "0001";
+
+ n_plb_wstate.status_transfer <= '1';
+
+
+
+ elsif AMU_pipe_size( 0 to 1 ) = "00" and AMU_pipe_size( 2 to 3 ) /= "00" then
+ -- line transfer
+
+ Sl_MWrErr( to_integer( unsigned'( unsigned( AMU_pipe_wmID ) ) ) ) <= '1';
+
+ -- we switch to the write state:
+ -- we write until transfer_count = transfer_size
+ n_plb_wstate.state <= plb_write;
+ n_plb_wstate.transfer_size <= AMU_pipe_size;
+ -- we did one transfer in this clock cycle
+ n_plb_wstate.transfer_count <= "0001";
+
+ n_plb_wstate.status_transfer <= '1';
+
+
+ else
+
+ -- single transfer
+ TCU_stuWriteSA_t <= '1';
+ Sl_wrComp_t <= '1';
+ end if;
+
+
+ --
+ -- start write transfer, initiated through PLB_PAValid
+ --
+ elsif start_plb_w = '1' then
+
+ -- we can accept the address
+
+ -- add address and data to the fifos/buffers
+ -- this implicit acks the address (see plb2wb_amu.vhd)
+ TCU_adrBufWEn_w <= '1';
+
+ addrAck_w <= '1';
+
+
+ -- we latch the masterID
+ n_plb_wstate.w_master_id <= PLB_masterID;
+
+ n_plb_wstate.status_transfer <= '0';
+
+ -- buffer is not full and this is a single/normal transfer
+ -- (we stay in the idle state)
+ if WBF_full = '0' and PLB_size = "0000" then
+
+ -- add data to the buffer
+ TCU_wbufWEn_t <= '1';
+ -- ack transfer to PLB
+ Sl_wrDAck <= '1';
+ Sl_wrComp_t <= '1';
+
+
+ -- this is a line transfer
+ elsif WBF_full = '0' and PLB_size( 0 to 1 ) = "00" and PLB_size( 2 to 3 ) /= "00" then
+
+ -- add data to the buffer
+ TCU_wbufWEn_t <= '1';
+ -- ack transfer to PLB
+ Sl_wrDAck <= '1';
+
+ -- we switch to the write state:
+ -- we write until transfer_count = transfer_size
+ n_plb_wstate.state <= plb_write;
+ n_plb_wstate.transfer_size <= PLB_size;
+ -- we did one transfer in this clock cycle
+ n_plb_wstate.transfer_count <= "0001";
+
+
+ -- the buffer is full:
+ -- if this is a single or line transfer, we switch to the plb_write state
+ elsif WBF_full = '1' and PLB_size( 0 to 1 ) = "00" then
+
+
+ -- we switch to the write state:
+ -- we write until transfer_count = transfer_size
+ n_plb_wstate.state <= plb_write;
+ n_plb_wstate.transfer_size <= PLB_size;
+ -- we did no transfer in this clock cycle
+ n_plb_wstate.transfer_count <= "0000";
+
+
+ -- this is a burst transfer
+ -- and the buffer is not full
+ elsif WBF_full = '0' and PLB_size( 0 to 1 ) /= "00" then
+
+
+ -- add data to the buffer
+ TCU_wbufWEn_t <= '1';
+ -- ack transfer to PLB
+ Sl_wrDAck <= '1';
+
+
+ -- we switch to the burst_write state:
+ -- we write until transfer_count = transfer_size
+ n_plb_wstate.state <= plb_burst_write;
+ n_plb_wstate.transfer_size <= PLB_BE( 0 to 3 );
+ -- we did no transfer in this clock cycle
+ n_plb_wstate.transfer_count <= "0001";
+
+
+ -- this is a burst transfer
+ -- and the buffer is full
+ elsif WBF_full = '1' and PLB_size( 0 to 1 ) /= "00" then
+
+
+ -- we switch to the burst_write state:
+ -- we write until transfer_count = transfer_size
+ n_plb_wstate.state <= plb_burst_write;
+ n_plb_wstate.transfer_size <= PLB_BE( 0 to 3 );
+ -- we did no transfer in this clock cycle
+ n_plb_wstate.transfer_count <= "0000";
+
+ end if;
+
+ --
+ -- start write transfer to state-register, initiated through PLB_PAValid
+ --
+ --
+ -- NOTE: it is not allowed to write with a burst or line transfer to the status
+ -- registers, so TCU_stuWritePA_t is only '1' for a single transfer!
+ --
+ elsif start_plb_stat_w = '1' then
+
+ addrAck_w <= '1';
+
+ -- we latch the masterID
+ n_plb_wstate.w_master_id <= PLB_masterID;
+
+ -- ack transfer to PLB
+ Sl_wrDAck <= '1';
+
+
+ if PLB_size = "1010" and PLB_BE( 0 to 3 ) /= "0000" then
+ -- burst transfer
+
+
+ Sl_MWrErr( to_integer( unsigned'( unsigned( PLB_masterID ) ) ) ) <= '1';
+
+ -- we switch to the burst_write state:
+ -- we write until transfer_count = transfer_size
+ n_plb_wstate.state <= plb_burst_write;
+ n_plb_wstate.transfer_size <= PLB_BE( 0 to 3 );
+ -- we did no transfer in this clock cycle
+ n_plb_wstate.transfer_count <= "0001";
+
+ n_plb_wstate.status_transfer <= '1';
+
+
+
+ elsif PLB_size( 0 to 1 ) = "00" and PLB_size( 2 to 3 ) /= "00" then
+ -- line transfer
+
+ Sl_MWrErr( to_integer( unsigned'( unsigned( PLB_masterID ) ) ) ) <= '1';
+
+ -- we switch to the write state:
+ -- we write until transfer_count = transfer_size
+ n_plb_wstate.state <= plb_write;
+ n_plb_wstate.transfer_size <= PLB_size;
+ -- we did one transfer in this clock cycle
+ n_plb_wstate.transfer_count <= "0001";
+
+ n_plb_wstate.status_transfer <= '1';
+
+
+ else
+
+ -- single transfer
+ TCU_stuWritePA_t <= '1';
+ Sl_wrComp_t <= '1';
+ end if;
+ end if;
+
+
+
+
+
+ --
+ -- write transfer: we are here because
+ -- - the write buffer was full and the adress buffer not, or
+ -- - this is a line transfer
+ --
+ if ( c_plb_wstate.state = plb_write and
+ ( c_plb_wstate.status_transfer = '1' or ( WBF_full = '0' and c_plb_wstate.status_transfer = '0' ) ) ) then -- we can accept data
+
+ -- ack transfer to PLB
+ Sl_wrDAck <= '1';
+
+
+ if ( ( c_plb_wstate.transfer_size( 0 to 3 ) = "0001" and c_plb_wstate.transfer_count = "0011" ) or
+ ( c_plb_wstate.transfer_size( 0 to 3 ) = "0010" and c_plb_wstate.transfer_count = "0111" ) or
+ ( c_plb_wstate.transfer_size( 0 to 3 ) = "0011" and c_plb_wstate.transfer_count = "1111" ) or
+ ( c_plb_wstate.transfer_size( 0 to 3 ) = "0000" ) -- single transfer
+ ) then
+ -- we are at the end of this transfer
+ Sl_wrComp_t <= '1';
+
+ n_plb_wstate.state <= plb_widle;
+
+
+ else
+ n_plb_wstate.transfer_count <= std_logic_vector( unsigned'( unsigned(c_plb_wstate.transfer_count) +1 ) );
+ end if;
+
+
+ if c_plb_wstate.status_transfer = '1' then
+
+ Sl_MWrErr( to_integer( unsigned'( unsigned( c_plb_wstate.w_master_id ) ) ) ) <= '1';
+
+ elsif WBF_full = '0' then
+
+ -- add data to the buffer
+ TCU_wbufWEn_t <= '1';
+
+ end if;
+
+
+
+ end if;
+
+
+ --
+ -- burst write transfer: we are here because
+ -- - this is a burst transfer
+ if( c_plb_wstate.state = plb_burst_write and
+ ( ( WBF_full = '0' and c_plb_wstate.status_transfer = '0' ) or c_plb_wstate.status_transfer = '1' ) )then -- we can accept data
+
+
+ if c_plb_wstate.status_transfer = '1' then
+
+ Sl_MWrErr( to_integer( unsigned'( unsigned( c_plb_wstate.w_master_id ) ) ) ) <= '1';
+
+ elsif WBF_full = '0' then
+
+ -- add data to the buffer
+ TCU_wbufWEn_t <= '1';
+
+ end if;
+
+
+
+ -- ack transfer to PLB
+ Sl_wrDAck <= '1';
+
+
+ -- we show that the burst-transfer ends after the next cycle
+ if c_plb_wstate.transfer_count = std_logic_vector( unsigned'( unsigned( c_plb_wstate.transfer_size ) -1 ) ) then
+ Sl_wrBTerm <= '1';
+ end if;
+
+
+ if c_plb_wstate.transfer_size = c_plb_wstate.transfer_count then
+ -- we are at the end of this transfer
+ Sl_wrComp_t <= '1';
+ n_plb_wstate.state <= plb_widle;
+ else
+ n_plb_wstate.transfer_count <= std_logic_vector( unsigned'( unsigned(c_plb_wstate.transfer_count) +1 ) );
+ end if;
+
+
+
+
+ end if;
+
+
+
+
+ if c_plb_wstate.state = plb_write
+ or c_plb_wstate.state = plb_burst_write then
+ mbusy_write_out( to_integer( unsigned'( unsigned( c_plb_wstate.w_master_id ) ) ) ) <= '1';
+ elsif c_plb_wstate.w_secondary = '1' then
+ mbusy_write_out( to_integer( unsigned'( unsigned( AMU_pipe_wmID ) ) ) ) <= '1';
+ end if;
+
+ end process;
+
+
+
+
+
+
+
+
+
+
+
+
+
+ n_plb_rstate_p : process( c_plb_rstate,
+ PLB_PAValid, PLB_RNW, PLB_masterID, PLB_rdPrim, PLB_size, PLB_BE,
+ AMU_deviceSelect, AMU_bufFull, AMU_pipe_size, AMU_pipe_rmID, AMU_pipe_BE, AMU_statusSelect,
+ RBF_empty, RBF_almostEmpty,
+ start_plb_sec_r, start_plb_sec_stat_r, start_plb_r, start_plb_stat_r,
+ TCU_wpipeRdEn_t )
+ begin
+
+
+ Sl_rdDAck_t <= '0';
+ Sl_rdComp_t <= '0';
+ Sl_rdBTerm <= '0';
+
+ TCU_rbufREn_t <= '0';
+ TCU_adrBufWEn_r <= '0';
+
+ TCU_enRdDBus <= '0';
+ TCU_rpipeRdEn_t <= '0';
+
+-- TCU_rbufPreLoad <= '0'; -- TODO
+-- TCU_rbufPreEn <= '0'; -- TODO
+
+ addrAck_r <= '0';
+
+
+ TCU_stuLatchSA_r <= '0';
+ TCU_stuLatchPA_r <= '0';
+
+ TCU_enStuRdDBus <= '0';
+ Sl_rdWdAddr <= ( others => '0' );
+
+ mbusy_read_out <= ( others => '0' );
+
+ n_plb_rstate <= c_plb_rstate;
+
+ if PLB_rdPrim = '1' then
+ n_plb_rstate.r_secondary <= '1';
+ end if;
+
+
+ if start_plb_sec_r = '1' then
+
+ TCU_adrBufWEn_r <= '1';
+ TCU_rpipeRdEn_t <= '1';
+ n_plb_rstate.r_secondary <= '0';
+
+ -- latch the master-id from AMU
+ n_plb_rstate.r_master_id <= AMU_pipe_rmID;
+
+ n_plb_rstate.status_transfer <= '0';
+
+ -- this is a line transfer
+ if AMU_pipe_size( 0 to 1 ) = "00" and AMU_pipe_size( 2 to 3 ) /= "00" and C_SPLB_SUPPORT_BUR_LINE > 0 then
+
+ n_plb_rstate.state <= plb_line_read;
+ n_plb_rstate.transfer_count <= ( others => '0' );
+ n_plb_rstate.transfer_size <= AMU_pipe_size;
+
+
+ -- this is a burst transfer
+ elsif AMU_pipe_size( 0 to 1 ) /= "00" and C_SPLB_SUPPORT_BUR_LINE > 0 then
+
+ n_plb_rstate.state <= plb_burst_read;
+ n_plb_rstate.transfer_count <= ( others => '0' );
+ n_plb_rstate.transfer_size <= AMU_pipe_BE( 0 to 3 );
+
+ -- this is a single transfer
+ else
+ n_plb_rstate.state <= plb_read;
+ end if;
+
+
+
+ --
+ -- start read transfer from state-register, initiated through secondary request
+ --
+ elsif start_plb_sec_stat_r = '1' then
+
+
+ TCU_rpipeRdEn_t <= '1';
+ n_plb_rstate.r_secondary <= '0';
+
+ -- latch the master-id from AMU
+ n_plb_rstate.r_master_id <= AMU_pipe_rmID;
+
+ -- tell the stu, that it should latch the secondary address
+ TCU_stuLatchSA_r <= '1';
+
+ n_plb_rstate.status_transfer <= '1';
+
+ -- this is a line transfer
+ if AMU_pipe_size( 0 to 1 ) = "00" and AMU_pipe_size( 2 to 3 ) /= "00" and C_SPLB_SUPPORT_BUR_LINE > 0 then
+
+ n_plb_rstate.state <= plb_line_read;
+ n_plb_rstate.transfer_count <= ( others => '0' );
+ n_plb_rstate.transfer_size <= AMU_pipe_size;
+
+
+ -- this is a burst transfer
+ elsif AMU_pipe_size( 0 to 1 ) /= "00" and C_SPLB_SUPPORT_BUR_LINE > 0 then
+
+ n_plb_rstate.state <= plb_burst_read;
+ n_plb_rstate.transfer_count <= ( others => '0' );
+ n_plb_rstate.transfer_size <= AMU_pipe_BE( 0 to 3 );
+
+ -- this is a single transfer
+ else
+ n_plb_rstate.state <= plb_read;
+ end if;
+
+
+
+ --
+ -- start read transfer, initiated through PLB_PAValid
+ --
+ elsif start_plb_r = '1' then
+
+
+ -- add address to the buffer/fifo
+ TCU_adrBufWEn_r <= '1';
+
+ addrAck_r <= '1';
+
+ -- latch the master-id from plb-bus
+ n_plb_rstate.r_master_id <= PLB_masterID;
+
+
+ n_plb_rstate.status_transfer <= '0';
+
+
+ n_plb_rstate.transfer_count <= "0000";
+
+ -- this is a line transfer
+ if PLB_size( 0 to 1 ) = "00" and PLB_size( 2 to 3 ) /= "00" and C_SPLB_SUPPORT_BUR_LINE > 0 then
+ n_plb_rstate.transfer_size <= PLB_size;
+ n_plb_rstate.state <= plb_wait_line_read;
+ n_plb_rstate.transfer_count <= ( others => '0' );
+
+ -- this is a burst transfer
+ elsif PLB_size( 0 to 1 ) /= "00" and C_SPLB_SUPPORT_BUR_LINE > 0 then
+ n_plb_rstate.state <= plb_wait_burst_read;
+ n_plb_rstate.transfer_count <= ( others => '0' );
+ n_plb_rstate.transfer_size <= PLB_BE( 0 to 3 );
+ -- this is a single transfer
+ else
+ n_plb_rstate.transfer_size <= PLB_size;
+ n_plb_rstate.state <= plb_read;
+ end if;
+
+
+ --
+ -- start read transfer from state-register, initiated through PLB_PAValid
+ --
+ elsif start_plb_stat_r = '1' then
+
+
+ -- single transfer
+ addrAck_r <= '1';
+
+ -- tell the stu, that it should latch the primary address
+ TCU_stuLatchPA_r <= '1';
+
+ -- latch the master-id from plb-bus
+ n_plb_rstate.r_master_id <= PLB_masterID;
+
+ n_plb_rstate.transfer_count <= "0000";
+
+
+ n_plb_rstate.status_transfer <= '1';
+
+ -- this is a line transfer
+ if PLB_size( 0 to 1 ) = "00" and PLB_size( 2 to 3 ) /= "00" and C_SPLB_SUPPORT_BUR_LINE > 0 then
+ n_plb_rstate.transfer_size <= PLB_size;
+ n_plb_rstate.state <= plb_wait_line_read;
+ n_plb_rstate.transfer_count <= ( others => '0' );
+
+ -- this is a burst transfer
+ elsif PLB_size( 0 to 1 ) /= "00" and C_SPLB_SUPPORT_BUR_LINE > 0 then
+ n_plb_rstate.state <= plb_wait_burst_read;
+ n_plb_rstate.transfer_count <= ( others => '0' );
+ n_plb_rstate.transfer_size <= PLB_BE( 0 to 3 );
+ -- this is a single transfer
+ else
+ n_plb_rstate.transfer_size <= PLB_size;
+ n_plb_rstate.state <= plb_read;
+
+ end if;
+
+
+
+ end if;
+
+
+
+ -- the wb-side read the data and added it to the fifo
+ -- -> fifo is not empty any more
+ if ( ( c_plb_rstate.state = plb_read and c_plb_rstate.status_transfer = '0' and RBF_empty = '0' )
+ -- this transfer reads from status register
+ or ( c_plb_rstate.state = plb_read and c_plb_rstate.status_transfer = '1' ) )
+ then
+
+ -- complete read transfer
+ Sl_rdComp_t <= '1';
+
+ -- switch to the ack state
+ n_plb_rstate.state <= plb_read_ack;
+
+ end if;
+
+
+
+ if c_plb_rstate.state = plb_read_ack then
+
+ -- switch to idle state
+ n_plb_rstate.state <= plb_ridle;
+
+ -- ack. the read transfer
+ Sl_rdDAck_t <= '1';
+
+
+ if c_plb_rstate.status_transfer = '0' then
+
+ -- read from the buffer
+ TCU_rbufREn_t <= '1';
+
+ end if;
+
+ end if;
+
+
+
+
+ if c_plb_rstate.state = plb_line_read then
+ -- /----- We know, that the fifo contains min. 2 elements
+ if ( c_plb_rstate.status_transfer = '1' or -- \/
+ ( c_plb_rstate.status_transfer = '0' and RBF_almostEmpty = '0' ) ) then
+
+ n_plb_rstate.transfer_count <= std_logic_vector( unsigned'( unsigned(c_plb_rstate.transfer_count) + 1 ) );
+
+ Sl_rdDAck_t <= '1';
+
+ if ( ( c_plb_rstate.transfer_size( 0 to 3 ) = "0001" and c_plb_rstate.transfer_count = "0010" ) or
+ ( c_plb_rstate.transfer_size( 0 to 3 ) = "0010" and c_plb_rstate.transfer_count = "0110" ) or
+ ( c_plb_rstate.transfer_size( 0 to 3 ) = "0011" and c_plb_rstate.transfer_count = "1110" ) ) then
+ -- we are finished after the next clock cycle
+ Sl_rdComp_t <= '1';
+ n_plb_rstate.state <= plb_line_read_ack;
+ end if;
+ end if;
+
+ if ( c_plb_rstate.status_transfer = '0' and RBF_almostEmpty = '0' ) then
+ TCU_rbufREn_t <= '1';
+ end if;
+
+ end if;
+
+
+
+
+
+
+ if c_plb_rstate.state = plb_burst_read then
+
+
+ -- /----- We know, that the fifo contains min. 2 elements
+ if ( c_plb_rstate.status_transfer = '1' or -- \/
+ ( c_plb_rstate.status_transfer = '0' and RBF_almostEmpty = '0' ) ) then
+
+ n_plb_rstate.transfer_count <= std_logic_vector( unsigned'( unsigned(c_plb_rstate.transfer_count) + 1 ) );
+
+ Sl_rdDAck_t <= '1';
+
+ if c_plb_rstate.transfer_count = std_logic_vector( unsigned'( unsigned ( c_plb_rstate.transfer_size ) -1 ) ) then
+
+ -- we are finished after the next clock cycle
+ Sl_rdComp_t <= '1';
+ Sl_rdBTerm <= '1';
+ n_plb_rstate.state <= plb_burst_read_ack;
+ end if;
+
+
+ end if;
+
+ if ( c_plb_rstate.status_transfer = '0' and RBF_almostEmpty = '0' ) then
+ TCU_rbufREn_t <= '1';
+ end if;
+
+ end if;
+
+
+ -- the wait cycles
+ if c_plb_rstate.state = plb_wait_burst_read then
+ n_plb_rstate.state <= plb_burst_read;
+ end if;
+
+ if c_plb_rstate.state = plb_wait_line_read then
+ n_plb_rstate.state <= plb_line_read;
+ end if;
+
+
+
+
+ if c_plb_rstate.state = plb_line_read_ack or
+ c_plb_rstate.state = plb_burst_read_ack then
+
+ Sl_rdDAck_t <= '1';
+ n_plb_rstate.state <= plb_ridle;
+
+ if c_plb_rstate.status_transfer = '0' then
+ TCU_rbufREn_t <= '1';
+ end if;
+
+ end if;
+
+
+ if ( ( c_plb_rstate.state = plb_read
+ or c_plb_rstate.state = plb_read_ack
+ or c_plb_rstate.state = plb_line_read
+ or c_plb_rstate.state = plb_line_read_ack
+ or c_plb_rstate.state = plb_burst_read
+ or c_plb_rstate.state = plb_burst_read_ack)
+ and c_plb_rstate.status_transfer = '0' )
+ then
+ -- we enable the read bus on plb side
+ TCU_enRdDBus <= '1';
+
+ elsif ( ( c_plb_rstate.state = plb_read
+ or c_plb_rstate.state = plb_read_ack
+ or c_plb_rstate.state = plb_line_read
+ or c_plb_rstate.state = plb_line_read_ack
+ or c_plb_rstate.state = plb_burst_read
+ or c_plb_rstate.state = plb_burst_read_ack)
+ and c_plb_rstate.status_transfer = '1' )
+ then
+
+ TCU_enStuRdDBus <= '1';
+ end if;
+
+
+
+ if c_plb_rstate.state = plb_read or
+ c_plb_rstate.state = plb_read_ack or
+ c_plb_rstate.state = plb_line_read or
+ c_plb_rstate.state = plb_line_read_ack or
+ c_plb_rstate.state = plb_burst_read or
+ c_plb_rstate.state = plb_burst_read_ack or
+ c_plb_rstate.state = plb_wait_line_read or
+ c_plb_rstate.state = plb_wait_burst_read
+ then
+ mbusy_read_out( to_integer( unsigned'( unsigned( c_plb_rstate.r_master_id ) ) ) ) <= '1';
+ end if;
+
+
+ if c_plb_rstate.r_secondary = '1' then
+ mbusy_read_out( to_integer( unsigned'( unsigned( AMU_pipe_rmID ) ) ) ) <= '1';
+ end if;
+
+
+ if c_plb_rstate.state = plb_line_read or
+ c_plb_rstate.state = plb_line_read_ack or
+ c_plb_rstate.state = plb_burst_read or
+ c_plb_rstate.state = plb_burst_read_ack
+ then
+ Sl_rdWdAddr <= c_plb_rstate.transfer_count;
+ end if;
+
+
+
+ end process;
+
+ TCU_MRBusy <= mbusy_read_out or mbusy_write_out;
+
+ Sl_MRdErr <= mbusy_read_out when Sl_rdDAck_t = '1' and RBF_rdErrOut = '1' else
+ ( others => '0' );
+
+
+
+
+
+ -- ====================================================================================================|
+ -- |
+ -- ========================= W I S H B O N E -- S I D E =========================================|
+ -- |
+ -- ====================================================================================================|
+
+
+
+
+
+
+ -------
+ -- WB-timeout counter
+ -- -> counts from WB_TOUT_MIN_VALUE to WB_TOUT_MAX_VALUE
+ -- -> is reseted by driving wb_tout_reset high
+ -- -> if counter reaches WB_TOUT_MAX_VALUE, wb_tout_alarm becomes '1'
+ --
+ wb_tout_process : process( wb_clk_i, plb2wb_rst, wb_tout_counter, wb_tout_reset )
+ begin
+ wb_tout_alarm <= '0';
+
+ if plb2wb_rst = '1' or wb_tout_reset = '1' then
+ wb_tout_counter <= WB_TOUT_MIN_VALUE;
+ elsif wb_clk_i'event and wb_clk_i = '1' then
+ if ( wb_tout_count = '1' and wb_tout_counter /= WB_TOUT_MAX_VALUE ) then
+ wb_tout_counter <= wb_tout_counter + 1;
+ end if;
+ end if;
+ if wb_tout_counter = WB_TOUT_MAX_VALUE then
+ wb_tout_alarm <= '1';
+ end if;
+ end process;
+ --
+ -----
+
+
+
+
+
+
+
+
+ c_wb_state_p : process( wb_clk_i, plb2wb_rst ) begin
+ if plb2wb_rst='1' then
+ c_wb_state.state <= wb_idle;
+ c_wb_state.transfer_count <= ( others => '0' );
+ elsif wb_clk_i'event and wb_clk_i='1' then
+ c_wb_state <= n_wb_state;
+
+ end if;
+ end process;
+
+
+
+ --
+ -- Note: we have fall-through fifo's, so the address is assigned when AMU_bufEmpty becomes '0'
+ --
+ start_wb_w <= '1' when ( c_wb_state.state = wb_idle and AMU_buf_RNW = '0' and AMU_bufEmpty = '0' and WBF_empty = '0' ) else
+ '0';
+ start_wb_r <= '1' when ( c_wb_state.state = wb_idle and AMU_buf_RNW = '1' and RBF_full = '0' and AMU_bufEmpty = '0' ) else
+ '0';
+
+
+ wb_ack <= wb_ack_i and not wb_err_i and not wb_rty_i;
+ wb_rty <= wb_rty_i and not wb_err_i;
+ wb_err <= wb_err_i;
+
+
+
+ n_wb_state_p : process( c_wb_state, AMU_buf_size,
+ AMU_buf_BE, WBF_empty,
+ start_wb_w, start_wb_r, wb_ack, wb_rty, wb_err, wb_tout_alarm,
+ STU_continue, STU_abort, wb_rst_short,pic_int_ahigh_short ) begin
+
+ wb_we_o <= '0';
+ wb_stb_o <= '0';
+ wb_cyc_o <= '0';
+ wb_lock_o <= '0';
+
+ TCU_wbufREn_t <= '0';
+ TCU_rbufWEn_t <= '0';
+ TCU_adrBufREn <= '0';
+ TCU_wb_status_info <= ( others => '0' );
+ TCU_stat2plb_en <= '0';
+
+
+ wb_tout_count <= '0';
+ wb_tout_reset <= '0';
+
+ n_wb_state <= c_wb_state;
+
+ if start_wb_w = '1' then
+
+ wb_stb_o <= '1';
+ wb_cyc_o <= '1';
+ wb_we_o <= '1';
+ n_wb_state.abort <= '0';
+ wb_tout_reset <= '1';
+
+ if wb_ack = '1' then
+ TCU_wbufREn_t <= '1';
+
+ if AMU_buf_size /= "0000" then
+ -- this is a line or burst transfer
+ n_wb_state.state <= wb_write;
+ n_wb_state.transfer_count <= "0001";
+ else
+ -- this is a single transfer:
+ -- we read from the address buffer,
+ -- because this transfer is complete
+
+ TCU_adrBufREn <= '1';
+
+ end if;
+
+ elsif wb_err = '1' then
+ -- add error info to the status pipe
+ -- and switch to the stall state
+ n_wb_state.state <= wb_write_stall;
+ TCU_wb_status_info( STATUS2PLB_W_ERR ) <= '1';
+ TCU_stat2plb_en <= '1';
+ elsif wb_rty = '1' then
+ -- retry this transfer
+ n_wb_state.state <= wb_write_rty;
+ else
+ n_wb_state.state <= wb_write;
+ end if;
+
+ end if;
+
+
+
+
+
+ if start_wb_r = '1' then
+
+
+ wb_stb_o <= '1';
+ wb_cyc_o <= '1';
+ wb_we_o <= '0';
+ n_wb_state.abort <= '0';
+ wb_tout_reset <= '1';
+
+
+ if wb_ack = '1' or wb_err = '1' then
+ TCU_rbufWEn_t <= '1';
+
+ if AMU_buf_size /= "0000" then
+ -- this is a line or burst transfer
+
+ n_wb_state.state <= wb_read;
+ n_wb_state.transfer_count <= "0001";
+ else
+ -- this is a single transfer:
+ -- we read from the address buffer,
+ -- because this transfer is complete
+
+
+ TCU_adrBufREn <= '1';
+ end if;
+
+ elsif wb_rty = '1' then
+ n_wb_state.state <= wb_read_rty;
+ else
+ n_wb_state.state <= wb_read;
+ end if;
+
+ end if;
+
+
+
+ --
+ -- write-transfer without writing
+ -- -->> we have to empty the write-pipe
+ if c_wb_state.state = wb_write and WBF_empty ='0' and c_wb_state.abort = '1' then
+
+ TCU_wbufREn_t <= '1';
+
+ if AMU_buf_size = "0000" then
+ -- single write transfer
+
+ n_wb_state.state <= wb_idle;
+ TCU_adrBufREn <= '1';
+
+ elsif AMU_buf_size( 3 downto 2 ) = "00" then
+ -- write line transfer
+
+ if ( ( AMU_buf_size( 1 downto 0 ) = "01" and c_wb_state.transfer_count = "0011" ) or
+ ( AMU_buf_size( 1 downto 0 ) = "10" and c_wb_state.transfer_count = "0111" ) or
+ ( AMU_buf_size( 1 downto 0 ) = "11" and c_wb_state.transfer_count = "1111" ) ) then
+ -- we are at the end of this transfer
+
+ n_wb_state.transfer_count <= ( others => '0' );
+ n_wb_state.state <= wb_idle;
+ TCU_adrBufREn <= '1';
+
+ else
+ n_wb_state.transfer_count <= std_logic_vector( unsigned'( unsigned(c_wb_state.transfer_count) +1 ) );
+ end if;
+
+ else
+ -- write burst transfer
+
+ if c_wb_state.transfer_count = AMU_buf_BE then
+ -- we are at the end of this transfer
+
+ n_wb_state.transfer_count <= ( others => '0' );
+ n_wb_state.state <= wb_idle;
+ TCU_adrBufREn <= '1';
+
+ else
+ n_wb_state.transfer_count <= std_logic_vector( unsigned'( unsigned(c_wb_state.transfer_count) +1 ) );
+ end if;
+
+ end if;
+
+
+
+ elsif c_wb_state.state = wb_write and WBF_empty ='0' and c_wb_state.abort = '0' then
+
+ wb_stb_o <= '1';
+ wb_cyc_o <= '1';
+ wb_we_o <= '1';
+ wb_tout_count <= '1';
+
+
+ if wb_ack = '1' then
+
+ TCU_wbufREn_t <= '1';
+ wb_tout_reset <= '1';
+
+ if AMU_buf_size = "0000" then
+ -- single write transfer
+
+ n_wb_state.state <= wb_idle;
+ TCU_adrBufREn <= '1';
+
+ elsif AMU_buf_size( 3 downto 2 ) = "00" then
+ -- write line transfer
+
+ if ( ( AMU_buf_size( 1 downto 0 ) = "01" and c_wb_state.transfer_count = "0011" ) or
+ ( AMU_buf_size( 1 downto 0 ) = "10" and c_wb_state.transfer_count = "0111" ) or
+ ( AMU_buf_size( 1 downto 0 ) = "11" and c_wb_state.transfer_count = "1111" ) ) then
+ -- we are at the end of this transfer
+
+ n_wb_state.transfer_count <= ( others => '0' );
+ n_wb_state.state <= wb_idle;
+ TCU_adrBufREn <= '1';
+
+ else
+ n_wb_state.transfer_count <= std_logic_vector( unsigned'( unsigned(c_wb_state.transfer_count) +1 ) );
+ end if;
+
+ else
+ -- write burst transfer
+
+ if c_wb_state.transfer_count = AMU_buf_BE then
+ -- we are at the end of this transfer
+
+ n_wb_state.transfer_count <= ( others => '0' );
+ n_wb_state.state <= wb_idle;
+ TCU_adrBufREn <= '1';
+
+ else
+ n_wb_state.transfer_count <= std_logic_vector( unsigned'( unsigned(c_wb_state.transfer_count) +1 ) );
+ end if;
+
+ end if;
+
+ elsif wb_err = '1' then
+ -- add error info to the status pipe
+ -- and switch to the stall state
+ n_wb_state.state <= wb_write_stall;
+ TCU_wb_status_info( STATUS2PLB_W_ERR ) <= '1';
+ TCU_stat2plb_en <= '1';
+ wb_tout_reset <= '1';
+ elsif wb_rty = '1' then
+ n_wb_state.state <= wb_write_rty;
+ wb_tout_reset <= '1';
+ elsif wb_tout_alarm = '1' then
+ n_wb_state.state <= wb_write_stall;
+ TCU_wb_status_info( STATUS2PLB_W_ERR ) <= '1';
+ TCU_stat2plb_en <= '1';
+ end if;
+
+ end if;
+
+ --
+ -- The WB-spec says, that wb_rty_i terminates a cycle, so wb_stb_o and wb_cyc_o is '0'
+ --
+ if c_wb_state.state = wb_write_rty then
+ n_wb_state.state <= wb_write;
+ end if;
+
+
+
+
+ if c_wb_state.state = wb_read then
+
+ wb_stb_o <= '1';
+ wb_cyc_o <= '1';
+ wb_we_o <= '0';
+ wb_tout_count <= '1';
+
+
+ if wb_ack = '1' or wb_err = '1' then
+
+ wb_tout_reset <= '1';
+
+ TCU_rbufWEn_t <= '1';
+
+ if AMU_buf_size = "0000" then
+ -- single read transfer
+
+ n_wb_state.state <= wb_idle;
+ TCU_adrBufREn <= '1';
+
+ elsif AMU_buf_size( 3 downto 2 ) = "00" then
+ -- read line transfer
+
+ if ( ( AMU_buf_size( 1 downto 0 ) = "01" and c_wb_state.transfer_count = "0011" ) or
+ ( AMU_buf_size( 1 downto 0 ) = "10" and c_wb_state.transfer_count = "0111" ) or
+ ( AMU_buf_size( 1 downto 0 ) = "11" and c_wb_state.transfer_count = "1111" ) ) then
+
+ n_wb_state.transfer_count <= ( others => '0' );
+ n_wb_state.state <= wb_idle;
+ TCU_adrBufREn <= '1';
+
+ else
+
+ n_wb_state.transfer_count <= std_logic_vector( unsigned'( unsigned(c_wb_state.transfer_count) +1 ) );
+
+ end if;
+
+
+ else
+ -- burst read transfer
+
+ if c_wb_state.transfer_count = AMU_buf_BE then
+ n_wb_state.transfer_count <= ( others => '0' );
+ n_wb_state.state <= wb_idle;
+ TCU_adrBufREn <= '1';
+ -- add info to the status fifo
+ else
+ n_wb_state.transfer_count <= std_logic_vector( unsigned'( unsigned(c_wb_state.transfer_count) +1 ) );
+ end if;
+
+ end if;
+
+ elsif wb_rty = '1' then
+ n_wb_state.state <= wb_read_rty;
+ wb_tout_reset <= '1';
+
+
+ -----
+ -- NOTE: This must be done after all other if-cases (ack, err, rty)
+ -- doing this together with ack and err, it results into a wrong behavior,
+ -- because the slave gives us a retry in the last timeout cycle
+ --
+ -- we are still waiting for an reaction of the slave ...
+ -- we abort this cycle (we need to drive cyc and stb low)
+ -- and continue with the next datum (if its a burst or line transfer)
+ --
+ elsif wb_tout_alarm = '1' then
+
+ n_wb_state.state <= wb_read_rty;
+ TCU_rbufWEn_t <= '1';
+
+ if AMU_buf_size = "0000" then
+ -- single read transfer
+
+ n_wb_state.state <= wb_idle;
+ TCU_adrBufREn <= '1';
+
+ elsif AMU_buf_size( 3 downto 2 ) = "00" then
+ -- read line transfer
+
+ if ( ( AMU_buf_size( 1 downto 0 ) = "01" and c_wb_state.transfer_count = "0011" ) or
+ ( AMU_buf_size( 1 downto 0 ) = "10" and c_wb_state.transfer_count = "0111" ) or
+ ( AMU_buf_size( 1 downto 0 ) = "11" and c_wb_state.transfer_count = "1111" ) ) then
+
+ n_wb_state.transfer_count <= ( others => '0' );
+ n_wb_state.state <= wb_idle;
+ TCU_adrBufREn <= '1';
+
+ else
+ -- we use the retry state to drive stb and cyc low
+ n_wb_state.state <= wb_read_rty;
+ n_wb_state.transfer_count <= std_logic_vector( unsigned'( unsigned(c_wb_state.transfer_count) +1 ) );
+ end if;
+
+ else
+ -- burst read transfer
+
+ if c_wb_state.transfer_count = AMU_buf_BE then
+ n_wb_state.transfer_count <= ( others => '0' );
+ n_wb_state.state <= wb_idle;
+ TCU_adrBufREn <= '1';
+ -- add info to the status fifo
+ else
+ -- we use the retry state to drive stb and cyc low
+ n_wb_state.state <= wb_read_rty;
+ n_wb_state.transfer_count <= std_logic_vector( unsigned'( unsigned(c_wb_state.transfer_count) +1 ) );
+ end if;
+
+ end if;
+
+ end if;
+
+ end if;
+
+
+
+
+ --
+ -- The generation of the lock-signal. If we are in a transfer (or starting a transfer), which is on
+ -- the plb-size a line or burst transfer and if block transfers are supported, we lock the bus (block transfer)
+ --
+ --
+ if ( ( c_wb_state.state = wb_read or
+ c_wb_state.state = wb_write or
+ c_wb_state.state = wb_read_rty or
+ c_wb_state.state = wb_write_rty or
+ start_wb_w = '1' or
+ start_wb_r = '1' ) and AMU_buf_size /= "0000" and WB_SUPPORT_BLOCK > 0 ) then
+ wb_lock_o <= '1';
+ end if;
+
+
+
+ --
+ -- The WB-spec says, that wb_rty_i terminates a cycle, so wb_stb_o and wb_cyc_o is '0'
+ --
+ if c_wb_state.state = wb_read_rty then
+ n_wb_state.state <= wb_read;
+ wb_tout_reset <= '1';
+ end if;
+
+
+
+ if ( c_wb_state.state = wb_write_stall and ( STU_continue = '1' or STU_abort = '1' ) )then
+ if STU_abort = '1' then
+ n_wb_state.abort <= '1';
+ end if;
+ n_wb_state.state <= wb_write;
+ wb_tout_reset <= '1';
+ end if;
+
+
+
+ if wb_rst_short = '1' then
+ TCU_wb_status_info( STATUS2PLB_RST ) <= '1';
+ TCU_stat2plb_en <= '1';
+ end if;
+
+
+
+ for i in 0 to WB_PIC_INTS-1 loop
+
+ if pic_int_ahigh_short( i ) = '1' then
+ TCU_stat2plb_en <= '1';
+ TCU_wb_status_info( STATUS2PLB_IRQ ) <= '1';
+ end if;
+
+ end loop;
+
+ TCU_wb_irq_info <= ( others => '0' );
+ TCU_wb_irq_info( IRQ_INFO_SIZE-1 downto IRQ_INFO_SIZE-WB_PIC_INTS ) <= pic_int_ahigh_short;
+
+
+ end process;
+
+
+ TCU_adr_offset <= c_wb_state.transfer_count;
+
+ -- We drive this signal high, if
+ -- -> there is a wb-error
+ -- -> there is a timeout and if we are not getting any response in this clock cycle
+ RBF_rdErrIn <= '1' when ( wb_err_i = '1'
+ or ( wb_tout_alarm = '1' and wb_rty_i = '0' and wb_ack_i = '0' ) )
+ else '0';
+
+end architecture IMP;
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_bridge.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_bridge.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_bridge.vhd (revision 2)
@@ -0,0 +1,712 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+
+
+library plb2wb_bridge_v1_00_a;
+use plb2wb_bridge_v1_00_a.all;
+use plb2wb_bridge_v1_00_a.plb2wb_pkg.ALL;
+
+------------------------------------------------------------------------------
+-- Definition of Generics:
+--
+-- SYNCHRONY -- The PLB and WB clocks are synchron
+-- WB_ADR_OFFSET -- Address offset: is added to every address on WB side
+-- WB_ADR_OFFSET_NEG -- Defines if WB_ADR_OFFSET is added or subtracted
+-- WB_PIC_INTS -- Number of Wishbone interrupt lines
+-- WB_PIC_INT_LEVEL -- Interrupts are active high or acrive low
+-- WB_SUPPORT_BLOCK -- Wishbone block transfers are supported
+-- WB_DAT_W -- Wishbone data bus width
+-- WB_ADR_W -- Wishbone address bus width
+-- WB_TIMEOUT_CYCLES -- Watchdog timer cycles
+--
+--
+-- C_BASEADDR -- PLBv46 slave: base address
+-- C_HIGHADDR -- PLBv46 slave: high address
+-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
+-- C_STATUS_BASEADDR -- PLBv46 slave: base address of status registers
+-- C_STATUS_HIGHADDR -- PLBv46 slave: base address of status registers
+-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
+-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
+-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
+-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
+-- C_SPLB_SUPPORT_BUR_LINE -- PLBv46 slave: support burst and line transfers
+-- C_SPLB_SUPPORT_ADR_PIPE -- PLBv46 slave: support address pipelining
+--
+-- Definition of Ports:
+-- SPLB_Clk -- PLB main bus clock
+-- SPLB_Rst -- PLB main bus reset
+-- PLB_ABus -- PLB address bus
+-- PLB_UABus -- PLB upper address bus
+-- PLB_PAValid -- PLB primary address valid indicator
+-- PLB_SAValid -- PLB secondary address valid indicator
+-- PLB_rdPrim -- PLB secondary to primary read request indicator
+-- PLB_wrPrim -- PLB secondary to primary write request indicator
+-- PLB_masterID -- PLB current master identifier
+-- PLB_abort -- PLB abort request indicator
+-- PLB_busLock -- PLB bus lock
+-- PLB_RNW -- PLB read/not write
+-- PLB_BE -- PLB byte enables
+-- PLB_MSize -- PLB master data bus size
+-- PLB_size -- PLB transfer size
+-- PLB_type -- PLB transfer type
+-- PLB_lockErr -- PLB lock error indicator
+-- PLB_wrDBus -- PLB write data bus
+-- PLB_wrBurst -- PLB burst write transfer indicator
+-- PLB_rdBurst -- PLB burst read transfer indicator
+-- PLB_wrPendReq -- PLB write pending bus request indicator
+-- PLB_rdPendReq -- PLB read pending bus request indicator
+-- PLB_wrPendPri -- PLB write pending request priority
+-- PLB_rdPendPri -- PLB read pending request priority
+-- PLB_reqPri -- PLB current request priority
+-- PLB_TAttribute -- PLB transfer attribute
+-- Sl_addrAck -- PLB slave address acknowledge
+-- Sl_SSize -- PLB slave data bus size
+-- Sl_wait -- PLB slave wait indicator
+-- Sl_rearbitrate -- PLB slave re-arbitrate bus indicator
+-- Sl_wrDAck -- PLB slave write data acknowledge
+-- Sl_wrComp -- PLB slave write transfer complete indicator
+-- Sl_wrBTerm -- PLB slave terminate write burst transfer
+-- Sl_rdDBus -- PLB slave read data bus
+-- Sl_rdWdAddr -- PLB slave read word address
+-- Sl_rdDAck -- PLB slave read data acknowledge
+-- Sl_rdComp -- PLB slave read transfer complete indicator
+-- Sl_rdBTerm -- PLB slave terminate read burst transfer
+-- Sl_MBusy -- PLB slave busy indicator
+-- Sl_MWrErr -- PLB slave write error indicator
+-- Sl_MRdErr -- PLB slave read error indicator
+-- Sl_MIRQ -- PLB slave bus interrupt indicator (not used by xilinx)
+-- PLB2WB_IRQ -- PLB slave interrupt out
+
+-- WB Signals ---------------------------------------
+-- wb_clk_i -- WB bus clock
+-- wb_rst_i -- WB bus reset
+-- wb_dat_i -- WB master read data bus
+-- wb_dat_o -- WB master write data bus
+-- wb_adr_o -- WB master address bus
+-- wb_sel_o -- WB master byte enables
+-- wb_we_o -- WB master write enable ('0' when read)
+-- wb_cyc_o -- WB master bus cycle indicator
+-- wb_stb_o -- WB master strobe output
+-- wb_ack_i -- WB master acknowledge input
+-- wb_err_i -- WB master error input
+-- wb_rty_i -- WB master retry input
+-- wb_lock_o -- WB master bus lock
+-- wb_pic_int_i -- WB master interrupt input
+
+------------------------------------------------------------------------------
+
+entity plb2wb_bridge is
+ generic
+ (
+ SYNCHRONY : boolean := true; -- true = synchron, false = asynchron!
+
+ -- PLB Parameters -----------------------------------
+ C_BASEADDR : std_logic_vector := X"FFFFFFFF";
+ C_HIGHADDR : std_logic_vector := X"00000000";
+ C_STATUS_BASEADDR : std_logic_vector := X"FFFFFFFF";
+ C_STATUS_HIGHADDR : std_logic_vector := X"00000000";
+ C_SPLB_AWIDTH : integer := 32;
+ C_SPLB_DWIDTH : integer := 128;
+ C_SPLB_NUM_MASTERS : integer := 8;
+ C_SPLB_MID_WIDTH : integer := 3;
+ C_SPLB_NATIVE_DWIDTH : integer := 32;
+ C_SPLB_SUPPORT_BUR_LINE : integer := 1;
+ C_SPLB_SUPPORT_ADR_PIPE : integer := 1;
+
+ -- WB Parameters -----------------------------------
+ WB_DAT_W : integer := 32;
+ WB_ADR_W : integer := 32;
+ WB_TIMEOUT_CYCLES : integer := 10;
+ WB_ADR_OFFSET : std_logic_vector := X"00000000";
+ WB_ADR_OFFSET_NEG : std_logic := '0';
+ WB_PIC_INTS : integer := 0;
+ WB_PIC_INT_LEVEL : std_logic := '1';
+ WB_SUPPORT_BLOCK : integer := 1
+ );
+ port
+ (
+
+ PLB2WB_IRQ : out std_logic;
+
+ -- WB Signals ---------------------------------------
+ wb_clk_i : in std_logic;
+ wb_rst_i : in std_logic;
+ wb_dat_i : in std_logic_vector( WB_DAT_W-1 downto 0 );
+ wb_dat_o : out std_logic_vector( WB_DAT_W-1 downto 0 );
+ wb_adr_o : out std_logic_vector( WB_ADR_W-1 downto 0 );
+ wb_sel_o : out std_logic_vector( WB_DAT_W/8-1 downto 0 );
+ wb_we_o : out std_logic;
+ wb_cyc_o : out std_logic;
+ wb_stb_o : out std_logic;
+ wb_ack_i : in std_logic;
+ wb_err_i : in std_logic;
+ wb_rty_i : in std_logic;
+ wb_lock_o : out std_logic;
+
+ wb_pic_int_i : in std_logic_vector( WB_PIC_INTS-1 downto 0 );
+
+ -- PLB Signals --------------------------------------
+ SPLB_Clk : in std_logic;
+ SPLB_Rst : in std_logic;
+ PLB_ABus : in std_logic_vector( 0 to 31 );
+ PLB_UABus : in std_logic_vector( 0 to 31 );
+ PLB_PAValid : in std_logic;
+ PLB_SAValid : in std_logic;
+ PLB_rdPrim : in std_logic;
+ PLB_wrPrim : in std_logic;
+ PLB_masterID : in std_logic_vector( 0 to C_SPLB_MID_WIDTH-1 );
+ PLB_abort : in std_logic;
+ PLB_busLock : in std_logic;
+ PLB_RNW : in std_logic;
+ PLB_BE : in std_logic_vector( 0 to C_SPLB_DWIDTH/8-1 );
+ PLB_MSize : in std_logic_vector( 0 to 1 );
+ PLB_size : in std_logic_vector( 0 to 3 );
+ PLB_type : in std_logic_vector( 0 to 2 );
+ PLB_lockErr : in std_logic;
+ PLB_wrDBus : in std_logic_vector( 0 to C_SPLB_DWIDTH-1 );
+ PLB_wrBurst : in std_logic;
+ PLB_rdBurst : in std_logic;
+ PLB_wrPendReq : in std_logic;
+ PLB_rdPendReq : in std_logic;
+ PLB_wrPendPri : in std_logic_vector( 0 to 1 );
+ PLB_rdPendPri : in std_logic_vector( 0 to 1 );
+ PLB_reqPri : in std_logic_vector( 0 to 1 );
+ PLB_TAttribute : in std_logic_vector( 0 to 15 );
+ Sl_addrAck : out std_logic;
+ Sl_SSize : out std_logic_vector( 0 to 1 );
+ Sl_wait : out std_logic;
+ Sl_rearbitrate : out std_logic;
+ Sl_wrDAck : out std_logic;
+ Sl_wrComp : out std_logic;
+ Sl_wrBTerm : out std_logic;
+ Sl_rdDBus : out std_logic_vector( 0 to C_SPLB_DWIDTH-1 );
+ Sl_rdWdAddr : out std_logic_vector( 0 to 3 );
+ Sl_rdDAck : out std_logic;
+ Sl_rdComp : out std_logic;
+ Sl_rdBTerm : out std_logic;
+ Sl_MBusy : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ Sl_MWrErr : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ Sl_MRdErr : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ Sl_MIRQ : out std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 )
+ );
+
+
+ constant WB_DWIDTH : integer := 32;
+ constant WB_AWIDTH : integer := WB_ADR_W;
+ constant C_SPLB_SIZE_WIDTH : integer := 4;
+ constant C_SPLB_TYPE_WIDTH : integer := 3;
+ constant C_SPLB_BE_WIDTH : integer := C_SPLB_DWIDTH/8;
+ constant C_SPLB_NATIVE_BE_WIDTH : integer := C_SPLB_NATIVE_DWIDTH/8;
+
+
+end entity plb2wb_bridge;
+
+
+
+
+
+architecture IMP of plb2wb_bridge is
+
+
+ signal wb_dat_o_t : std_logic_vector( WB_DAT_W-1 downto 0 );
+ signal wb_adr_o_t : std_logic_vector( WB_ADR_W-1 downto 0 );
+ signal wb_sel_o_t : std_logic_vector( WB_DAT_W/8-1 downto 0 );
+ signal wb_we_o_t : std_logic;
+ signal wb_cyc_o_t : std_logic;
+ signal wb_stb_o_t : std_logic;
+
+ signal Sl_addrAck_t : std_logic;
+ signal Sl_SSize_t : std_logic_vector( 0 to 1 );
+ signal Sl_wait_t : std_logic;
+ signal Sl_rearbitrate_t : std_logic;
+ signal Sl_wrDAck_t : std_logic;
+ signal Sl_wrComp_t : std_logic;
+ signal Sl_wrBTerm_t : std_logic;
+ signal Sl_rdDBus_t : std_logic_vector( 0 to C_SPLB_DWIDTH-1 );
+ signal Sl_rdWdAddr_t : std_logic_vector( 0 to 3 );
+ signal Sl_rdDAck_t : std_logic;
+ signal Sl_rdComp_t : std_logic;
+ signal Sl_rdBTerm_t : std_logic;
+ signal Sl_MBusy_t : std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ signal Sl_MWrErr_t : std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ signal Sl_MRdErr_t : std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ signal Sl_MIRQ_t : std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+
+ signal AMU_buf_RNW : std_logic;
+
+ signal AMU_bufEmpty : std_logic;
+ signal AMU_bufFull : std_logic;
+ signal AMU_deviceSelect : std_logic;
+ signal AMU_statusSelect : std_logic;
+ signal AMU_addrAck : std_logic;
+ signal AMU_pipe_wmID : std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+ signal AMU_pipe_rmID : std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+ signal AMU_buf_size : std_logic_vector( C_SPLB_SIZE_WIDTH-1 downto 0 );
+ signal AMU_buf_BE : std_logic_vector( C_SPLB_NATIVE_BE_WIDTH-1 downto 0 );
+ signal AMU_buf_adr : std_logic_vector( WB_ADR_W-1 downto 0 );
+ signal AMU_buf_adr_wo : std_logic_vector( WB_ADR_W-1 downto 0 );
+ signal AMU_pipe_size : std_logic_vector( 0 to C_SPLB_SIZE_WIDTH-1 );
+ signal AMU_pipe_BE : std_logic_vector( 0 to C_SPLB_NATIVE_BE_WIDTH-1 );
+ signal AMU_pipe_adr : std_logic_vector( 0 to C_SPLB_AWIDTH-1 );
+ signal AMU_buf_masterID : std_logic_vector( 0 to C_SPLB_MID_WIDTH-1 );
+ signal AMU_pipe_rStatusSelect : std_logic;
+ signal AMU_pipe_wStatusSelect : std_logic;
+
+
+ signal RBF_rBus : std_logic_vector( WB_DWIDTH-1 downto 0 );
+ signal RBF_empty : std_logic;
+ signal RBF_almostEmpty : std_logic;
+ signal RBF_full : std_logic;
+ signal RBF_rdErrOut : std_logic;
+ signal RBF_rdErrIn : std_logic;
+
+ signal WBF_empty : std_logic;
+ signal WBF_full : std_logic;
+ signal WBF_wBus : std_logic_vector( 0 to C_SPLB_NATIVE_DWIDTH-1 );
+
+
+ signal TCU_wbufWEn : std_logic;
+ signal TCU_wbufREn : std_logic;
+ signal TCU_rbufWEn : std_logic;
+ signal TCU_rbufREn : std_logic;
+ signal TCU_adrBufREn : std_logic;
+ signal TCU_adrBufWEn : std_logic;
+ signal TCU_enRdDBus : std_logic;
+ signal TCU_enStuRdDBus : std_logic;
+ signal TCU_MRBusy : std_logic_vector( 0 to C_SPLB_NUM_MASTERS-1 );
+ signal TCU_addrAck : std_logic;
+ signal TCU_rpipeRdEn : std_logic;
+ signal TCU_wpipeRdEn : std_logic;
+ signal TCU_adr_offset : std_logic_vector( 3 downto 0 );
+ signal TCU_stuLatchPA : std_logic;
+ signal TCU_stuLatchSA : std_logic;
+ signal TCU_stuWritePA : std_logic;
+ signal TCU_stuWriteSA : std_logic;
+
+ signal TCU_wb_status_info : std_logic_vector( STATUS2PLB_INFO_SIZE-1 downto 0 );
+ signal TCU_stat2plb_en : std_logic;
+
+ signal STU_rdDBus : std_logic_vector( 0 to C_SPLB_DWIDTH-1 );
+
+ signal STU_full : std_logic;
+ signal STU_continue : std_logic;
+ signal STU_abort : std_logic;
+ signal STU_softReset : std_logic;
+
+
+ signal plb2wb_rst : std_logic;
+ signal TCU_wb_irq_info : std_logic_vector( IRQ_INFO_SIZE-1 downto 0 );
+
+begin
+
+
+ wb_dat_o <= wb_dat_o_t ;
+ wb_adr_o <= wb_adr_o_t ;
+ wb_sel_o <= wb_sel_o_t ;
+ wb_we_o <= wb_we_o_t ;
+ wb_cyc_o <= wb_cyc_o_t ;
+ wb_stb_o <= wb_stb_o_t ;
+
+ Sl_addrAck <= Sl_addrAck_t ;
+ Sl_SSize <= Sl_SSize_t ;
+ Sl_wait <= Sl_wait_t ;
+ Sl_rearbitrate <= Sl_rearbitrate_t ;
+ Sl_wrDAck <= Sl_wrDAck_t ;
+ Sl_wrComp <= Sl_wrComp_t ;
+ Sl_wrBTerm <= Sl_wrBTerm_t ;
+ Sl_rdDBus <= Sl_rdDBus_t or STU_rdDBus;
+ Sl_rdWdAddr <= Sl_rdWdAddr_t ;
+ Sl_rdDAck <= Sl_rdDAck_t ;
+ Sl_rdComp <= Sl_rdComp_t ;
+ Sl_rdBTerm <= Sl_rdBTerm_t ;
+ Sl_MBusy <= Sl_MBusy_t ;
+ Sl_MWrErr <= Sl_MWrErr_t ;
+ Sl_MRdErr <= Sl_MRdErr_t ;
+ Sl_MIRQ <= Sl_MIRQ_t ;
+
+
+
+ Sl_MBusy_t <= TCU_MRBusy;
+ Sl_addrAck_t <= TCU_addrAck or AMU_addrAck;
+
+ -----
+ --
+ -- Set the slave-size, depending on SPLB_NATIVE_DWIDTH
+ --
+ Sl_SSize_t <= "01" when C_SPLB_NATIVE_DWIDTH = 64 else
+ "10" when C_SPLB_NATIVE_DWIDTH = 128 else
+ "00";
+
+
+
+ plb2wb_rst <= SPLB_Rst or STU_softReset;
+
+
+ stu : entity plb2wb_bridge_v1_00_a.plb2wb_stu( IMP )
+ generic map(
+ SYNCHRONY => SYNCHRONY,
+ WB_DWIDTH => WB_DWIDTH,
+ WB_AWIDTH => WB_AWIDTH,
+ C_SPLB_AWIDTH => C_SPLB_AWIDTH,
+ C_SPLB_DWIDTH => C_SPLB_DWIDTH,
+ C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
+ C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
+ C_SPLB_SIZE_WIDTH => C_SPLB_SIZE_WIDTH,
+ C_SPLB_BE_WIDTH => C_SPLB_BE_WIDTH,
+ C_SPLB_NATIVE_BE_WIDTH => C_SPLB_NATIVE_BE_WIDTH,
+ C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
+ )
+ port map(
+ wb_clk_i => wb_clk_i,
+ SPLB_Clk => SPLB_Clk,
+ SPLB_Rst => SPLB_Rst,
+
+ AMU_masterID => AMU_pipe_wmID,
+ AMU_pipe_adr => AMU_pipe_adr,
+ AMU_buf_adr_wo => AMU_buf_adr_wo,
+ AMU_buf_masterID => AMU_buf_masterID,
+
+ PLB_masterID => PLB_masterID,
+ PLB_size => PLB_size,
+ PLB_wrDBus => PLB_wrDBus,
+ PLB_ABus => PLB_ABus,
+ PLB_BE => PLB_BE ,
+ Sl_rdWdAddr => Sl_rdWdAddr_t,
+ Sl_MIRQ => Sl_MIRQ_t,
+
+ STU_rdDBus => STU_rdDBus,
+ STU_full => STU_full,
+ STU_continue => STU_continue,
+ STU_abort => STU_abort,
+ STU_softReset => STU_softReset,
+ WBF_wBus => WBF_wBus,
+
+ TCU_wb_irq_info => TCU_wb_irq_info,
+ TCU_enStuRdDBus => TCU_enStuRdDBus,
+ TCU_wb_status_info => TCU_wb_status_info,
+ TCU_stuLatchPA => TCU_stuLatchPA,
+ TCU_stuLatchSA => TCU_stuLatchSA,
+ TCU_stuWritePA => TCU_stuWritePA,
+ TCU_stuWriteSA => TCU_stuWriteSA,
+ TCU_stat2plb_en => TCU_stat2plb_en,
+ PLB2WB_IRQ => PLB2WB_IRQ
+ );
+
+
+
+
+
+
+ amu : entity plb2wb_bridge_v1_00_a.plb2wb_amu( IMP )
+ generic map(
+ SYNCHRONY => SYNCHRONY,
+
+ WB_DWIDTH => WB_DWIDTH,
+ WB_AWIDTH => WB_AWIDTH,
+ WB_ADR_OFFSET => WB_ADR_OFFSET,
+ WB_ADR_OFFSET_NEG => WB_ADR_OFFSET_NEG,
+
+ C_BASEADDR => C_BASEADDR,
+ C_HIGHADDR => C_HIGHADDR,
+ C_STATUS_BASEADDR => C_STATUS_BASEADDR,
+ C_STATUS_HIGHADDR => C_STATUS_HIGHADDR,
+ C_SPLB_AWIDTH => C_SPLB_AWIDTH,
+ C_SPLB_SIZE_WIDTH => C_SPLB_SIZE_WIDTH,
+ C_SPLB_TYPE_WIDTH => C_SPLB_TYPE_WIDTH,
+ C_SPLB_BE_WIDTH => C_SPLB_BE_WIDTH,
+ C_SPLB_NATIVE_BE_WIDTH => C_SPLB_NATIVE_BE_WIDTH,
+ C_SPLB_SUPPORT_BUR_LINE => C_SPLB_SUPPORT_BUR_LINE,
+ C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
+ C_SPLB_SUPPORT_ADR_PIPE => C_SPLB_SUPPORT_ADR_PIPE
+ )
+ port map(
+
+ wb_clk_i => wb_clk_i ,
+ wb_sel_o => wb_sel_o_t ,
+
+ SPLB_Clk => SPLB_Clk ,
+ plb2wb_rst => plb2wb_rst ,
+
+ PLB_ABus => PLB_ABus ,
+ PLB_UABus => PLB_UABus ,
+ PLB_SAValid => PLB_SAValid ,
+ PLB_size => PLB_size ,
+ PLB_type => PLB_type ,
+ PLB_BE => PLB_BE ,
+ PLB_RNW => PLB_RNW ,
+ PLB_masterID => PLB_masterID ,
+
+ TCU_adrBufREn => TCU_adrBufREn,
+ TCU_adrBufWEn => TCU_adrBufWEn,
+ TCU_rpipeRdEn => TCU_rpipeRdEn,
+ TCU_wpipeRdEn => TCU_wpipeRdEn ,
+ TCU_stuWriteSA => TCU_stuWriteSA,
+
+ AMU_deviceSelect => AMU_deviceSelect,
+ AMU_statusSelect => AMU_statusSelect,
+ AMU_bufEmpty => AMU_bufEmpty ,
+ AMU_bufFull => AMU_bufFull,
+ AMU_addrAck => AMU_addrAck,
+ AMU_buf_RNW => AMU_buf_RNW,
+ AMU_pipe_wmID => AMU_pipe_wmID,
+ AMU_pipe_rmID => AMU_pipe_rmID,
+ AMU_buf_size => AMU_buf_size,
+ AMU_buf_masterID => AMU_buf_masterID,
+ AMU_buf_adr => AMU_buf_adr,
+ AMU_buf_adr_wo => AMU_buf_adr_wo,
+ AMU_pipe_size => AMU_pipe_size,
+ AMU_pipe_BE => AMU_pipe_BE,
+ AMU_buf_BE => AMU_buf_BE,
+ AMU_pipe_adr => AMU_pipe_adr,
+ AMU_pipe_rStatusSelect =>AMU_pipe_rStatusSelect,
+ AMU_pipe_wStatusSelect =>AMU_pipe_wStatusSelect
+ );
+
+
+ wb_adr_o_t <= std_logic_vector( unsigned( AMU_buf_adr ) + unsigned( TCU_adr_offset & "00" ) );
+
+
+
+
+
+
+
+
+ tcu : entity plb2wb_bridge_v1_00_a.plb2wb_tcu( IMP )
+ generic map(
+ C_SPLB_SIZE_WIDTH => C_SPLB_SIZE_WIDTH,
+ C_SPLB_DWIDTH => C_SPLB_DWIDTH,
+ C_SPLB_NATIVE_BE_WIDTH => C_SPLB_NATIVE_BE_WIDTH,
+ C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
+ C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
+ C_SPLB_TYPE_WIDTH => C_SPLB_TYPE_WIDTH,
+ C_SPLB_SUPPORT_BUR_LINE => C_SPLB_SUPPORT_BUR_LINE,
+ WB_PIC_INTS => WB_PIC_INTS,
+ WB_PIC_INT_LEVEL => WB_PIC_INT_LEVEL,
+ WB_SUPPORT_BLOCK => WB_SUPPORT_BLOCK
+ )
+ port map(
+
+ wb_clk_i => wb_clk_i,
+ wb_stb_o => wb_stb_o_t,
+ wb_we_o => wb_we_o_t,
+ wb_cyc_o => wb_cyc_o_t,
+ wb_ack_i => wb_ack_i,
+ wb_err_i => wb_err_i,
+ wb_rty_i => wb_rty_i,
+ wb_lock_o => wb_lock_o,
+ wb_rst_i => wb_rst_i,
+ wb_pic_int_i => wb_pic_int_i,
+
+ SPLB_Clk => SPLB_Clk,
+ plb2wb_rst => plb2wb_rst,
+ PLB_MSize => PLB_MSize,
+ PLB_TAttribute => PLB_TAttribute,
+ PLB_lockErr => PLB_lockErr,
+ PLB_abort => PLB_abort,
+ PLB_rdBurst => PLB_rdBurst,
+ PLB_wrBurst => PLB_wrBurst,
+ PLB_RNW => PLB_RNW,
+ PLB_PAValid => PLB_PAValid,
+ PLB_masterID => PLB_masterID,
+ PLB_rdPrim => PLB_rdPrim,
+ PLB_wrPrim => PLB_wrPrim,
+ PLB_size => PLB_size,
+ PLB_BE => PLB_BE,
+ PLB_type => PLB_type,
+
+ STU_continue => STU_continue,
+ STU_abort => STU_abort,
+
+ Sl_MWrErr => Sl_MWrErr_t,
+ Sl_wrDAck => Sl_wrDAck_t,
+ Sl_wrComp => Sl_wrComp_t,
+ Sl_wrBTerm => Sl_wrBTerm_t,
+ Sl_rdDAck => Sl_rdDAck_t,
+ Sl_rdComp => Sl_rdComp_t,
+ Sl_rdBTerm => Sl_rdBTerm_t,
+ Sl_rdWdAddr => Sl_rdWdAddr_t,
+ Sl_wait => Sl_wait_t,
+ Sl_rearbitrate => Sl_rearbitrate_t,
+ Sl_MRdErr => Sl_MRdErr_t,
+
+ AMU_deviceSelect => AMU_deviceSelect,
+ AMU_bufEmpty => AMU_bufEmpty,
+ AMU_bufFull => AMU_bufFull,
+ AMU_buf_RNW => AMU_buf_RNW,
+ AMU_buf_BE => AMU_buf_BE,
+ AMU_buf_size => AMU_buf_size,
+ AMU_pipe_rmID => AMU_pipe_rmID,
+ AMU_pipe_wmID => AMU_pipe_wmID,
+ AMU_pipe_size => AMU_pipe_size,
+ AMU_pipe_BE => AMU_pipe_BE,
+ AMU_statusSelect => AMU_statusSelect,
+ AMU_pipe_rStatusSelect =>AMU_pipe_rStatusSelect,
+ AMU_pipe_wStatusSelect =>AMU_pipe_wStatusSelect,
+
+ TCU_wbufWEn => TCU_wbufWEn,
+ TCU_wbufREn => TCU_wbufREn,
+ TCU_rbufWEn => TCU_rbufWEn,
+ TCU_rbufREn => TCU_rbufREn,
+ TCU_adrBufREn => TCU_adrBufREn,
+ TCU_adrBufWEn => TCU_adrBufWEn,
+ TCU_enStuRdDBus => TCU_enStuRdDBus,
+ TCU_enRdDBus => TCU_enRdDBus,
+ TCU_MRBusy => TCU_MRBusy,
+ TCU_addrAck => TCU_addrAck,
+ TCU_rpipeRdEn => TCU_rpipeRdEn,
+ TCU_wpipeRdEn => TCU_wpipeRdEn ,
+ TCU_adr_offset => TCU_adr_offset,
+ TCU_stuLatchPA => TCU_stuLatchPA,
+ TCU_stuLatchSA => TCU_stuLatchSA,
+ TCU_stuWritePA => TCU_stuWritePA,
+ TCU_stuWriteSA => TCU_stuWriteSA,
+ TCU_stat2plb_en => TCU_stat2plb_en,
+ TCU_wb_status_info => TCU_wb_status_info,
+ TCU_wb_irq_info => TCU_wb_irq_info,
+
+ WBF_empty => WBF_empty,
+ WBF_full => WBF_full,
+
+ RBF_rdErrOut => RBF_rdErrOut,
+ RBF_rdErrIn => RBF_rdErrIn,
+ RBF_empty => RBF_empty,
+ RBF_almostEmpty => RBF_almostEmpty,
+ RBF_full => RBF_full
+ );
+
+
+
+
+
+
+
+
+
+
+
+ ---------------------------------
+ --
+ --
+ --
+ -- Read and Write Buffer
+ --
+ --
+ wb_dat_o_t <= WBF_wBus;
+
+ gen_128 : if C_SPLB_DWIDTH = 128 generate
+ Sl_rdDBus_t <= RBF_rBus & RBF_rBus & RBF_rBus & RBF_rBus when TCU_enRdDBus = '1' else
+ ( others => '0' );
+ end generate gen_128;
+
+ gen_64 : if C_SPLB_DWIDTH = 64 generate
+ Sl_rdDBus_t <= RBF_rBus & RBF_rBus when TCU_enRdDBus = '1' else
+ ( others => '0' );
+ end generate gen_64;
+
+ gen_32 : if C_SPLB_DWIDTH = 32 generate
+ Sl_rdDBus_t <= RBF_rBus when TCU_enRdDBus = '1' else
+ ( others => '0' );
+ end generate gen_32;
+
+
+
+
+ wbuf : entity plb2wb_bridge_v1_00_a.plb2wb_wbuf( IMP_32 )
+ generic map(
+ SYNCHRONY => SYNCHRONY,
+ C_SPLB_DWIDTH => C_SPLB_DWIDTH,
+ C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
+ C_SPLB_SIZE_WIDTH => C_SPLB_SIZE_WIDTH
+ )
+ port map(
+
+ wb_clk_i => wb_clk_i,
+ SPLB_Clk => SPLB_Clk,
+ plb2wb_rst => plb2wb_rst,
+ PLB_size => PLB_size,
+ PLB_wrDBus => PLB_wrDBus,
+ TCU_wbufWEn => TCU_wbufWEn,
+ TCU_wbufREn => TCU_wbufREn,
+
+ WBF_empty => WBF_empty,
+ WBF_full => WBF_full,
+ WBF_wBus => WBF_wBus
+ );
+
+ rbuf : entity plb2wb_bridge_v1_00_a.plb2wb_rbuf( IMP_32 )
+ generic map(
+ SYNCHRONY => SYNCHRONY,
+ WB_DWIDTH => WB_DWIDTH
+ )
+ port map(
+ wb_clk_i => wb_clk_i,
+ SPLB_Clk => SPLB_Clk,
+ plb2wb_rst => plb2wb_rst,
+ wb_dat_i => wb_dat_i,
+ RBF_rBus => RBF_rBus,
+ RBF_empty => RBF_empty,
+ RBF_almostEmpty => RBF_almostEmpty,
+ RBF_full => RBF_full,
+ RBF_rdErrOut => RBF_rdErrOut,
+ RBF_rdErrIn => RBF_rdErrIn,
+ TCU_rbufWEn => TCU_rbufWEn,
+ TCU_rbufREn => TCU_rbufREn
+ );
+ --
+ -------------------------------------------
+
+
+
+
+
+
+end IMP;
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_short_impulse.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_short_impulse.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_short_impulse.vhd (revision 2)
@@ -0,0 +1,113 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity plb2wb_short_impulse is
+ Port ( CLK : in STD_LOGIC;
+ RESET : in STD_LOGIC;
+ IMPULSE : in STD_LOGIC;
+ SHORT_IMPULSE : out STD_LOGIC);
+end plb2wb_short_impulse;
+
+architecture IMP of plb2wb_short_impulse is
+
+
+type state is record
+ was_down : std_logic;
+ start_of_high : std_logic;
+end record;
+
+signal current_state, next_state : state;
+
+begin
+
+states_state : process( CLK, RESET )
+
+ begin
+ if CLK'event and CLK='1' then
+
+ if RESET = '1' then
+
+ current_state <= ( was_down => '0',
+ start_of_high => '0' );
+
+ else
+ current_state <= next_state;
+ end if;
+
+ end if;
+ end process;
+
+
+
+detection : process( current_state, IMPULSE )
+ begin
+
+ next_state <= current_state;
+ next_state.start_of_high <= '0';
+ SHORT_IMPULSE <= '0';
+
+ if current_state.was_down = '1' and IMPULSE = '1' then
+ next_state.was_down <= '0';
+ next_State.start_of_high <= '1';
+ SHORT_IMPULSE <= '1';
+ end if;
+
+ if current_state.was_down = '0' and IMPULSE = '0' then
+ next_state.was_down <= '1';
+ end if;
+
+ end process;
+
+
+
+end IMP;
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_rbuf.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_rbuf.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_rbuf.vhd (revision 2)
@@ -0,0 +1,126 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+
+library plb2wb_bridge_v1_00_a;
+
+
+
+
+entity plb2wb_rbuf is
+ generic(
+ SYNCHRONY : boolean := true;
+ WB_DWIDTH : integer := 32
+ );
+ port(
+
+ wb_clk_i : IN std_logic;
+ SPLB_Clk : IN std_logic;
+ plb2wb_rst : IN std_logic;
+
+ wb_dat_i : IN std_logic_vector( WB_DWIDTH-1 downto 0 );
+
+ RBF_rBus : out std_logic_vector( WB_DWIDTH-1 downto 0 );
+ RBF_empty : out std_logic;
+ RBF_almostEmpty : out std_logic;
+ RBF_full : out std_logic;
+
+ RBF_rdErrOut : out std_logic;
+ RBF_rdErrIn : in std_logic;
+
+ TCU_rbufWEn : in std_logic;
+ TCU_rbufREn : in std_logic
+ );
+end entity plb2wb_rbuf;
+
+
+
+architecture IMP_32 of plb2wb_rbuf is
+
+
+ signal rbuf_dout : std_logic_vector( WB_DWIDTH+1-1 downto 0 );
+ signal rbuf_din : std_logic_vector( WB_DWIDTH+1-1 downto 0 );
+ signal pre_load_reg : std_logic_vector( WB_DWIDTH+1-1 downto 0 );
+ signal rd_en : std_logic;
+begin
+
+
+ rbuf_din <= RBF_rdErrIn & wb_dat_i;
+
+ rd_en <= TCU_rbufREn;
+ RBF_rBus <= rbuf_dout( WB_DWIDTH-1 downto 0 );
+
+ RBF_rdErrOut <= rbuf_dout(32);
+
+
+
+ rbuf : entity plb2wb_bridge_v1_00_a.fifo_rdat( IMP )
+ generic map(
+ SYNCHRONY => SYNCHRONY,
+ WB_DWIDTH => WB_DWIDTH
+ )
+ port map(
+ rd_en => rd_en,
+ wr_en => TCU_rbufWEn,
+ full => RBF_full,
+ empty => RBF_empty,
+ almost_empty => RBF_almostEmpty,
+ wr_clk => wb_clk_i,
+ rst => plb2wb_rst,
+ rd_clk => SPLB_Clk,
+ dout => rbuf_dout,
+ din => rbuf_din
+ );
+
+
+
+
+end architecture IMP_32;
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr.vhd (revision 2)
@@ -0,0 +1,326 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library plb2wb_bridge_v1_00_a;
+
+entity fifo_adr is
+ generic
+ (
+ SYNCHRONY : boolean := true; -- true = synchron, false = asynchron
+ C_SPLB_MID_WIDTH : integer := 3
+
+ );
+ port(
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ wr_clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ rd_clk : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( 0 to 41+C_SPLB_MID_WIDTH-1 );
+ din : in STD_LOGIC_VECTOR ( 0 to 41+C_SPLB_MID_WIDTH-1 )
+
+ );
+end entity fifo_adr;
+
+
+
+
+architecture IMP of fifo_adr is
+
+
+
+ component fifo_adr_cc_1 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( 42-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( 42-1 downto 0 )
+ );
+ end component fifo_adr_cc_1;
+
+ component fifo_adr_ic_1 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ wr_clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ rd_clk : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( 42-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( 42-1 downto 0 )
+ );
+ end component fifo_adr_ic_1;
+
+ component fifo_adr_cc_2 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( 43-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( 43-1 downto 0 )
+ );
+ end component fifo_adr_cc_2;
+
+ component fifo_adr_ic_2 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ wr_clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ rd_clk : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( 43-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( 43-1 downto 0 )
+ );
+ end component fifo_adr_ic_2;
+
+ component fifo_adr_cc_3 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( 44-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( 44-1 downto 0 )
+ );
+ end component fifo_adr_cc_3;
+
+ component fifo_adr_ic_3 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ wr_clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ rd_clk : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( 44-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( 44-1 downto 0 )
+ );
+ end component fifo_adr_ic_3;
+
+ component fifo_adr_cc_4 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( 45-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( 45-1 downto 0 )
+ );
+ end component fifo_adr_cc_4;
+
+ component fifo_adr_ic_4 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ wr_clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ rd_clk : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( 45-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( 45-1 downto 0 )
+ );
+ end component fifo_adr_ic_4;
+
+
+begin
+
+
+
+
+fifo_cc_1: if ( SYNCHRONY = true and C_SPLB_MID_WIDTH = 1 ) generate
+U_fifo_cc : fifo_adr_cc_1
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ clk => rd_clk, -- rd_clk must be the same than wr_clk!
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_cc_1;
+
+
+
+fifo_cc_2: if ( SYNCHRONY = true and C_SPLB_MID_WIDTH = 2 ) generate
+U_fifo_cc : fifo_adr_cc_2
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ clk => rd_clk, -- rd_clk must be the same than wr_clk!
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_cc_2;
+
+
+
+fifo_cc_3: if ( SYNCHRONY = true and C_SPLB_MID_WIDTH = 3 ) generate
+U_fifo_cc : fifo_adr_cc_3
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ clk => rd_clk, -- rd_clk must be the same than wr_clk!
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_cc_3;
+
+
+
+fifo_cc_4: if ( SYNCHRONY = true and C_SPLB_MID_WIDTH = 4 ) generate
+U_fifo_cc : fifo_adr_cc_4
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ clk => rd_clk, -- rd_clk must be the same than wr_clk!
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_cc_4;
+
+
+
+fifo_ic_1: if ( SYNCHRONY = false and C_SPLB_MID_WIDTH = 1 ) generate
+U_fifo_ic : fifo_adr_ic_1
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ rd_clk => rd_clk,
+ wr_clk => wr_clk,
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_ic_1;
+
+
+fifo_ic_2: if ( SYNCHRONY = false and C_SPLB_MID_WIDTH = 2 ) generate
+U_fifo_ic : fifo_adr_ic_2
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ rd_clk => rd_clk,
+ wr_clk => wr_clk,
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_ic_2;
+
+
+fifo_ic_3: if ( SYNCHRONY = false and C_SPLB_MID_WIDTH = 3 ) generate
+U_fifo_ic : fifo_adr_ic_3
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ rd_clk => rd_clk,
+ wr_clk => wr_clk,
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_ic_3;
+
+
+fifo_ic_4: if ( SYNCHRONY = false and C_SPLB_MID_WIDTH = 4 ) generate
+U_fifo_ic : fifo_adr_ic_4
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ rd_clk => rd_clk,
+ wr_clk => wr_clk,
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_ic_4;
+
+
+
+
+end architecture IMP;
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_pkg.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_pkg.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_pkg.vhd (revision 2)
@@ -0,0 +1,117 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+
+package plb2wb_pkg is
+
+ --
+ -- The range of the address pipeline depth
+ constant PIPE_D_MIN : integer := 2;
+ constant PIPE_D_MAX : integer := 512;
+
+
+ -- The range of the wishbone-data-bus width
+ constant WB_DWIDTH_MIN : integer := 32;
+ constant WB_DWIDTH_MAX : integer := 64;
+
+ -- The range of the wishbone-address-bus width
+ constant WB_AWIDTH_MIN : integer := 32;
+ constant WB_AWIDTH_MAX : integer := 64;
+
+ constant PLB_DWIDTH_MIN : integer := 32;
+ constant PLB_DWIDTH_MAX : integer := 128;
+
+
+
+
+ --
+ -- error and reset info types and functions
+ --
+ constant STATUS2PLB_INFO_SIZE : integer := 3;
+
+ constant STATUS2PLB_W_ERR : integer := 0 ;
+ constant STATUS2PLB_RST : integer := 1 ;
+ constant STATUS2PLB_IRQ : integer := 2 ;
+
+ -- The size data-size of the read/write buffer
+ constant RBUF_DWIDTH32 : integer := 33;
+ constant WBUF_DWIDTH32 : integer := 32;
+
+
+
+ constant STATUS_CONTINUE : std_logic_vector := "0";
+ constant STATUS_ABORT : std_logic_vector := "1";
+
+
+
+ constant IRQ_INFO_SIZE : integer := 32;
+
+
+ function log2( steps : natural ) return natural;
+
+end package plb2wb_pkg;
+
+
+
+package body plb2wb_pkg is
+
+
+ function log2( steps : natural ) return natural is
+ variable size : natural := 1;
+ begin
+ while( 2**size < steps ) loop
+ size := size + 1;
+ end loop;
+ return size;
+ end log2;
+
+end package body plb2wb_pkg;
+
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2wb.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2wb.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2wb.vhd (revision 2)
@@ -0,0 +1,144 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library plb2wb_bridge_v1_00_a;
+use plb2wb_bridge_v1_00_a.plb2wb_pkg.all;
+
+
+entity fifo_stat2wb is
+ generic
+ (
+ SYNCHRONY : boolean := true -- true = synchron
+ );
+ port(
+ rd_en : in std_logic := 'X';
+ wr_en : in std_logic := 'X';
+ full : out std_logic;
+ empty : out std_logic;
+ wr_clk : in std_logic := 'X';
+ rst : in std_logic := 'X';
+ rd_clk : in std_logic := 'X';
+ dout : out std_logic_vector ( 1 -1 downto 0 );
+ din : in std_logic_vector ( 1 -1 downto 0 )
+ );
+end entity fifo_stat2wb;
+
+
+
+architecture IMP of fifo_stat2wb is
+
+component fifo_stat2wb_cc is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( 0 downto 0 );
+ din : in STD_LOGIC_VECTOR ( 0 downto 0 )
+ );
+end component fifo_stat2wb_cc;
+
+
+component fifo_stat2wb_ic is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ wr_clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ rd_clk : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( 0 downto 0 );
+ din : in STD_LOGIC_VECTOR ( 0 downto 0 )
+ );
+end component fifo_stat2wb_ic;
+
+
+
+begin
+
+fifo1: if ( SYNCHRONY = true ) generate
+U_fifo_cc : fifo_stat2wb_cc
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ clk => rd_clk, -- rd_clk must be the same than wr_clk
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo1;
+
+fifo2: if ( SYNCHRONY = false ) generate
+U_fifo_ic : fifo_stat2wb_ic
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ rd_clk => rd_clk,
+ wr_clk => wr_clk,
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo2;
+
+
+
+
+
+end architecture IMP;
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_amu.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_amu.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_amu.vhd (revision 2)
@@ -0,0 +1,552 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library plb2wb_bridge_v1_00_a;
+
+entity plb2wb_amu is
+ generic(
+ SYNCHRONY : boolean := true;
+ PIPELINE_DEPTH : integer := 2;
+
+ WB_DWIDTH : integer := 4;
+ WB_AWIDTH : integer := 32;
+ WB_ADR_OFFSET : std_logic_vector := X"00000000";
+ WB_ADR_OFFSET_NEG : std_logic := '0';
+
+ C_BASEADDR : std_logic_vector := X"FFFFFFFF";
+ C_HIGHADDR : std_logic_vector := X"00000000";
+ C_STATUS_BASEADDR : std_logic_vector := X"FFFFFFFF";
+ C_STATUS_HIGHADDR : std_logic_vector := X"00000000";
+ C_SPLB_AWIDTH : integer := 32;
+ C_SPLB_SIZE_WIDTH : integer := 4;
+ C_SPLB_TYPE_WIDTH : integer := 4;
+ C_SPLB_BE_WIDTH : integer := 4;
+ C_SPLB_NATIVE_BE_WIDTH : integer := 4;
+ C_SPLB_MID_WIDTH : integer := 0;
+ C_SPLB_SUPPORT_BUR_LINE : integer := 1;
+ C_SPLB_SUPPORT_ADR_PIPE : integer := 1
+
+ );
+ port(
+ wb_clk_i : in std_logic;
+
+
+ -- PLB Signals --
+ SPLB_Clk : in std_logic;
+ plb2wb_rst : in std_logic;
+ PLB_SAValid : in std_logic;
+ PLB_RNW : in std_logic;
+ PLB_ABus : in std_logic_vector( 0 to C_SPLB_AWIDTH -1 );
+ PLB_UABus : in std_logic_vector( 0 to C_SPLB_AWIDTH -1 );
+ PLB_size : in std_logic_vector( 0 to C_SPLB_SIZE_WIDTH -1 );
+ PLB_type : in std_logic_vector( 0 to C_SPLB_TYPE_WIDTH -1 );
+ PLB_BE : in std_logic_vector( 0 to C_SPLB_BE_WIDTH -1 );
+ PLB_masterID : in std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+
+
+ TCU_adrBufWEn : in std_logic;
+ TCU_adrBufREn : in std_logic;
+ TCU_rpipeRdEn : in std_logic;
+ TCU_wpipeRdEn : in std_logic;
+ TCU_stuWriteSA : in std_logic;
+
+ -- Internal signals
+ AMU_deviceSelect : out std_logic;
+ AMU_statusSelect : out std_logic;
+ AMU_addrAck : OUT std_logic;
+
+ AMU_bufEmpty : out std_logic;
+ AMU_bufFull : out std_logic;
+ AMU_buf_RNW : out std_logic;
+ AMU_buf_size : out std_logic_vector( C_SPLB_SIZE_WIDTH -1 downto 0 );
+ AMU_buf_BE : out std_logic_vector( C_SPLB_NATIVE_BE_WIDTH -1 downto 0 );
+ AMU_buf_adr : out std_logic_vector( WB_AWIDTH -1 downto 0 );
+ AMU_buf_adr_wo : out std_logic_vector( WB_AWIDTH -1 downto 0 ); -- address without offset
+ AMU_buf_masterID : out std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+
+
+ AMU_pipe_rmID : out std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+ AMU_pipe_wmID : out std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+ AMU_pipe_size : out std_logic_vector( 0 to C_SPLB_SIZE_WIDTH -1 );
+ AMU_pipe_BE : out std_logic_vector( 0 to C_SPLB_NATIVE_BE_WIDTH -1 );
+ AMU_pipe_adr : out std_logic_vector( 0 to C_SPLB_AWIDTH -1 );
+ AMU_pipe_rStatusSelect : out std_logic;
+ AMU_pipe_wStatusSelect : out std_logic;
+
+ wb_sel_o : out std_logic_vector( WB_DWIDTH/8-1 downto 0 )
+
+ );
+end plb2wb_amu;
+
+
+architecture IMP of plb2wb_amu is
+
+ -- TODO: muss master ID durch pipe und buffer??
+ -- TODO: remove PLB_type und chkecke PLB_type auf "000" und "110"
+ -- TODO: nur ein comperator fuer status_select -->> info durch pipe!
+
+
+ ------------------------------------------------------|
+ -- |
+ --
+ -- Pipelined data types and convertion functions
+ --
+ type pipeline_data_type is record
+ PLB_Abus : std_logic_vector( 0 to C_SPLB_AWIDTH -1 );
+ PLB_size : std_logic_vector( 0 to C_SPLB_SIZE_WIDTH -1 );
+ PLB_BE : std_logic_vector( 0 to C_SPLB_NATIVE_BE_WIDTH-1 );
+ PLB_masterID : std_logic_vector( 0 to C_SPLB_MID_WIDTH -1 );
+ statusSelect : std_logic; -- we transfer the statusSelect through the pipe,
+ end record; -- so we don't need an additional comperator after the pipe
+ constant PIPELINE_DATA_WIDTH : integer := C_SPLB_AWIDTH + C_SPLB_SIZE_WIDTH + C_SPLB_NATIVE_BE_WIDTH + C_SPLB_MID_WIDTH + 1;
+
+ --
+ -- pipeline_data_type to std_logic_vector
+ function pdt_to_vector( data : pipeline_data_type ) return std_logic_vector is
+ begin
+ return data.PLB_Abus & data.PLB_size & data.PLB_BE & data.PLB_masterID & data.statusSelect;
+ end function pdt_to_vector;
+
+
+
+
+ constant PIPE_ABUS_START : integer := 0 ;
+ constant PIPE_SIZE_START : integer := C_SPLB_AWIDTH ;
+ constant PIPE_TYPE_START : integer := C_SPLB_AWIDTH + C_SPLB_SIZE_WIDTH ;
+ constant PIPE_BE_START : integer := C_SPLB_AWIDTH + C_SPLB_SIZE_WIDTH ;
+ constant PIPE_MASTERID_START : integer := C_SPLB_AWIDTH + C_SPLB_SIZE_WIDTH + C_SPLB_NATIVE_BE_WIDTH ;
+
+ constant PIPE_ABUS_END : integer := C_SPLB_AWIDTH -1 ;
+ constant PIPE_SIZE_END : integer := C_SPLB_AWIDTH + C_SPLB_SIZE_WIDTH -1 ;
+ constant PIPE_TYPE_END : integer := C_SPLB_AWIDTH + C_SPLB_SIZE_WIDTH -1 ;
+ constant PIPE_BE_END : integer := C_SPLB_AWIDTH + C_SPLB_SIZE_WIDTH + C_SPLB_NATIVE_BE_WIDTH -1 ;
+ constant PIPE_MASTERID_END : integer := PIPELINE_DATA_WIDTH-2 ;
+
+ constant PIPE_STATUS_SELECT : integer := PIPELINE_DATA_WIDTH-1;
+
+ procedure vector_to_pdt( signal vector : in std_logic_vector;
+ signal pdt : out pipeline_data_type ) is
+ begin
+ pdt.PLB_Abus <= vector( PIPE_ABUS_START to PIPE_ABUS_END );
+ pdt.PLB_size <= vector( PIPE_SIZE_START to PIPE_SIZE_END );
+ pdt.PLB_BE <= vector( PIPE_BE_START to PIPE_BE_END );
+ pdt.PLB_masterID <= vector( PIPE_MASTERID_START to PIPE_MASTERID_END );
+ pdt.statusSelect <= vector( PIPE_STATUS_SELECT );
+ end procedure vector_to_pdt;
+
+
+ --
+ -- clear pipeline_data_type
+ procedure pdt_clear( signal data : out pipeline_data_type ) is
+ begin
+ data.PLB_ABus <= ( others => '0' );
+ data.PLB_size <= ( others => '0' );
+ data.PLB_BE <= ( others => '0' );
+ data.PLB_masterID <= ( others => '0' );
+ data.statusSelect <= '0';
+ end procedure pdt_clear;
+ -- |
+ ------------------------------------------------------|
+
+
+
+ constant ABUF_WIDTH : integer := C_SPLB_AWIDTH + C_SPLB_NATIVE_BE_WIDTH + C_SPLB_SIZE_WIDTH + C_SPLB_MID_WIDTH + 1;
+
+
+ ------------------------------------------------------|
+ -- |
+ -- Pipeline-FIFO signals
+ --
+ signal pipeline_in : pipeline_data_type;
+ signal pipe_data_in : std_logic_vector( 0 to PIPELINE_DATA_WIDTH-1 );
+
+ signal rpipe_rd : std_logic;
+ signal rpipe_wr : std_logic;
+ signal rpipe_data_out : std_logic_vector( 0 to PIPELINE_DATA_WIDTH-1 );
+ signal rpipe_out : pipeline_data_type;
+ signal rpipe_empty : std_logic;
+ signal rpipe_full : std_logic;
+ --
+ signal wpipe_rd : std_logic;
+ signal wpipe_wr : std_logic;
+ signal wpipe_data_out : std_logic_vector( 0 to PIPELINE_DATA_WIDTH-1 );
+ signal wpipe_out : pipeline_data_type;
+ signal wpipe_empty : std_logic;
+ signal wpipe_full : std_logic;
+
+ signal en_rpipe_outputs : std_logic;
+ -- |
+ ------------------------------------------------------|
+
+
+
+
+ ------------------------------------------------------|
+ -- |
+ -- Buffer-FIFO signals
+ --
+
+ signal abuf_dout : std_logic_vector( 0 to ABUF_WIDTH -1 );
+ signal abuf_din : std_logic_vector( 0 to ABUF_WIDTH -1 );
+ signal abuf_wr_en : std_logic;
+ -- |
+ ------------------------------------------------------|
+
+
+ signal BE_selected : std_logic_vector( 0 to C_SPLB_NATIVE_BE_WIDTH-1 );
+
+
+ signal AMU_deviceSelect_t : std_logic;
+ signal AMU_statusSelect_t : std_logic;
+
+ signal AMU_buf_size_t : std_logic_vector( C_SPLB_SIZE_WIDTH-1 downto 0 );
+
+
+begin
+
+
+
+ -- We ack. the secondary address, if we write to the write-address-pipe or read-address-pipe
+ AMU_addrAck <= rpipe_wr or wpipe_wr;
+
+
+ -------------
+ --
+ -- Comperator: device_select is '1' if PLB_ABus selects this IP
+ --
+ AMU_deviceSelect_t <= '1' when ( PLB_ABus >= C_BASEADDR and PLB_ABus <= C_HIGHADDR ) else
+ '0';
+
+ AMU_statusSelect_t <= '1' when ( PLB_ABus >= C_STATUS_BASEADDR and PLB_ABus <= C_STATUS_HIGHADDR ) else
+ '0';
+
+
+
+
+
+ AMU_deviceSelect <= AMU_deviceSelect_t;
+ AMU_statusSelect <= AMU_statusSelect_t;
+
+ AMU_buf_size <= AMU_buf_size_t;
+
+
+ -----
+ -- The selection of the Byte-Enable signals, according to spec:5.6.x
+ --
+ besel_p : process( PLB_BE, PLB_ABus(28 to 29) ) begin
+
+
+ -- 128-bit bridge on 128-bit PLB (default)
+ BE_selected <= PLB_BE( 0 to C_SPLB_NATIVE_BE_WIDTH-1 );
+
+ -- 32-bit bridge on 128-bit PLB
+ if C_SPLB_NATIVE_BE_WIDTH = 4 and C_SPLB_BE_WIDTH = 16 then
+ case PLB_ABus(28 to 29) is
+ when "00" => BE_selected <= PLB_BE( 0 to 3 );
+ when "01" => BE_selected <= PLB_BE( 4 to 7 );
+ when "10" => BE_selected <= PLB_BE( 8 to 11 );
+ when others => BE_selected <= PLB_BE( 12 to 15 );
+ end case;
+ end if;
+
+
+ -- 64-bit bridge on 128-bit PLB
+ if C_SPLB_NATIVE_BE_WIDTH = 8 and C_SPLB_BE_WIDTH = 16 then
+ case PLB_ABus(28) is
+ when '0' => BE_selected <= PLB_BE( 0 to 7 );
+ when others => BE_selected <= PLB_BE( 8 to 15 );
+ end case;
+ end if;
+
+
+ end process;
+
+
+
+
+ with_adr_pipelinig : if C_SPLB_SUPPORT_ADR_PIPE > 0 generate
+
+
+ -------------------------------
+ --
+ -- read and write pipe control signals
+ --
+ -- -> we only write to a pipeline, if the transfer is supported.
+ --
+ --
+ with_plb_bursts : if C_SPLB_SUPPORT_BUR_LINE > 0 generate
+
+ rpipe_wr <= '1' when PLB_SAValid = '1'
+ and PLB_RNW = '1'
+ and rpipe_full = '0'
+ and ( PLB_size( 0 to 1 ) = "00" or ( PLB_size = "1010" and PLB_BE( 0 to 3 ) /= "0000" ) )
+ and ( AMU_deviceSelect_t = '1' or AMU_statusSelect_t = '1' )
+ and ( PLB_type = "000" or PLB_type = "110" )
+ else '0';
+
+ wpipe_wr <= '1' when PLB_SAValid = '1'
+ and PLB_RNW = '0'
+ and wpipe_full = '0'
+ and ( PLB_size( 0 to 1 ) = "00" or ( PLB_size = "1010" and PLB_BE( 0 to 3 ) /= "0000" ) )
+ and ( AMU_deviceSelect_t = '1' or AMU_statusSelect_t = '1' )
+ and ( PLB_type = "000" or PLB_type = "110" )
+ else '0';
+
+ end generate with_plb_bursts;
+
+ without_plb_bursts : if C_SPLB_SUPPORT_BUR_LINE = 0 generate
+
+ rpipe_wr <= '1' when PLB_SAValid = '1'
+ and PLB_RNW = '1'
+ and rpipe_full = '0'
+ and PLB_size = "0000"
+ and ( AMU_deviceSelect_t = '1' or AMU_statusSelect_t = '1' )
+ and ( PLB_type = "000" or PLB_type = "110" )
+ else '0';
+
+ wpipe_wr <= '1' when PLB_SAValid = '1'
+ and PLB_RNW = '0'
+ and wpipe_full = '0'
+ and PLB_size = "0000"
+ and ( AMU_deviceSelect_t = '1' or AMU_statusSelect_t = '1' )
+ and ( PLB_type = "000" or PLB_type = "110" )
+ else '0';
+
+ end generate without_plb_bursts;
+
+
+
+
+ rpipe_rd <= TCU_rpipeRdEn;
+ wpipe_rd <= TCU_wpipeRdEn;
+ en_rpipe_outputs <= TCU_rpipeRdEn or TCU_stuWriteSA;
+
+
+ ------
+ --
+ -- read and write pipe inputs
+ --
+ vector_to_pdt( rpipe_data_out, rpipe_out );
+ vector_to_pdt( wpipe_data_out, wpipe_out );
+ pipeline_in.PLB_ABus <= PLB_ABus;
+ pipeline_in.PLB_size <= PLB_size;
+ pipeline_in.PLB_BE <= BE_selected;
+ pipeline_in.PLB_masterID <= PLB_masterID;
+ pipeline_in.statusSelect <= AMU_statusSelect_t;
+ pipe_data_in <= pdt_to_vector( pipeline_in );
+
+
+ -----
+ -- read and write pipe outputs
+ --
+ AMU_pipe_adr <= rpipe_out.PLB_Abus when en_rpipe_outputs = '1' else
+ wpipe_out.PLB_Abus;
+
+ AMU_pipe_BE <= rpipe_out.PLB_BE when en_rpipe_outputs = '1' else
+ wpipe_out.PLB_BE;
+
+ AMU_pipe_rmID <= rpipe_out.PLB_masterID;
+ AMU_pipe_wmID <= wpipe_out.PLB_masterID;
+
+ AMU_pipe_size <= rpipe_out.PLB_size when en_rpipe_outputs = '1' else
+ wpipe_out.PLB_size;
+
+ AMU_pipe_rStatusSelect <= rpipe_out.statusSelect;
+ AMU_pipe_wStatusSelect <= wpipe_out.statusSelect;
+
+ --
+ -- read pipe
+ --
+ read_pipeline : entity plb2wb_bridge_v1_00_a.plb2wb_fifo( IMP )
+ generic map(
+ DATA_W => PIPELINE_DATA_WIDTH,
+ ADDR_W => PIPELINE_DEPTH
+ )
+ port map(
+ rd_en => rpipe_rd,
+ wr_en => rpipe_wr,
+ full => rpipe_full,
+ empty => rpipe_empty,
+ clk => SPLB_Clk,
+ rst => plb2wb_rst,
+ dout => rpipe_data_out,
+ din => pipe_data_in
+ );
+
+ --
+ -- write pipe
+ --
+ write_pipeline : entity plb2wb_bridge_v1_00_a.plb2wb_fifo( IMP )
+ generic map(
+ DATA_W => PIPELINE_DATA_WIDTH,
+ ADDR_W => PIPELINE_DEPTH
+ )
+ port map(
+ rd_en => wpipe_rd,
+ wr_en => wpipe_wr,
+ full => wpipe_full,
+ empty => wpipe_empty,
+ clk => SPLB_Clk,
+ rst => plb2wb_rst,
+ dout => wpipe_data_out,
+ din => pipe_data_in
+ );
+
+ --
+ --
+ --------------------------
+
+
+ end generate with_adr_pipelinig;
+
+
+ without_adr_pipelining : if C_SPLB_SUPPORT_ADR_PIPE = 0 generate
+
+ pdt_clear( rpipe_out );
+ pdt_clear( wpipe_out );
+
+ wpipe_full <= '1';
+ rpipe_full <= '1';
+ wpipe_empty <= '1';
+ rpipe_empty <= '1';
+
+ end generate without_adr_pipelining;
+
+
+
+
+ --------------------------
+ --
+ -- address-buffer input
+ --
+ -- address byte enable size master-id rnw
+ abuf_din <= rpipe_out.PLB_ABus & rpipe_out.PLB_BE & rpipe_out.PLB_size & rpipe_out.PLB_masterID & "1" when TCU_rpipeRdEn = '1' else
+ wpipe_out.PLB_ABus & wpipe_out.PLB_BE & wpipe_out.PLB_size & rpipe_out.PLB_masterID & "0" when TCU_wpipeRdEn = '1' else
+ PLB_ABus & BE_selected & PLB_size & PLB_masterID & PLB_RNW;
+
+ ----------------
+ --
+ -- address-buffer outputs
+ --
+
+ -- address-output without offset
+ AMU_buf_adr_wo <= abuf_dout( 0 to C_SPLB_AWIDTH-1 );
+
+ -- address-output with offset (but offset is 0)
+ adr_offset_g1 : if WB_ADR_OFFSET = X"00000000" generate
+ AMU_buf_adr <= abuf_dout( 0 to C_SPLB_AWIDTH-1 );
+ end generate;
+
+ -- address-output with offset
+ adr_offset_g2 : if WB_ADR_OFFSET /= X"00000000" generate
+
+ -- negative offset
+ adr_offset_g3 : if WB_ADR_OFFSET_NEG = '1' generate
+ AMU_buf_adr <= std_logic_vector ( unsigned'(unsigned( abuf_dout( 0 to C_SPLB_AWIDTH-1 )) ) - unsigned'(unsigned( WB_ADR_OFFSET )) );
+ end generate;
+ -- positive offset
+ adr_offset_g4 : if WB_ADR_OFFSET_NEG = '0' generate
+ AMU_buf_adr <= std_logic_vector ( unsigned'(unsigned( abuf_dout( 0 to C_SPLB_AWIDTH-1 ) )) + unsigned'(unsigned( WB_ADR_OFFSET )) );
+ end generate;
+
+ end generate;
+
+
+ -- note: AMU_buf_BE and wb_sel_o is almoust the same, except the case that we have a burst transfer
+ --
+ AMU_buf_BE <= abuf_dout( C_SPLB_AWIDTH to C_SPLB_AWIDTH + C_SPLB_NATIVE_BE_WIDTH-1 );
+ -- note: wb_sel_o is "1111" if we have a burst transfer
+ wb_sel_o <= abuf_dout( C_SPLB_AWIDTH to C_SPLB_AWIDTH + C_SPLB_NATIVE_BE_WIDTH-1 )
+ when AMU_buf_size_t( 3 downto 2 ) = "00" else
+ ( others => '1' );
+
+ AMU_buf_size_t <= abuf_dout( C_SPLB_AWIDTH + C_SPLB_NATIVE_BE_WIDTH to C_SPLB_AWIDTH + C_SPLB_NATIVE_BE_WIDTH + C_SPLB_SIZE_WIDTH-1 );
+ AMU_buf_masterID <= abuf_dout( C_SPLB_AWIDTH + C_SPLB_NATIVE_BE_WIDTH + C_SPLB_SIZE_WIDTH to C_SPLB_AWIDTH + C_SPLB_NATIVE_BE_WIDTH + C_SPLB_SIZE_WIDTH + C_SPLB_MID_WIDTH -1 );
+ AMU_buf_RNW <= abuf_dout( C_SPLB_AWIDTH + C_SPLB_NATIVE_BE_WIDTH + C_SPLB_SIZE_WIDTH + C_SPLB_MID_WIDTH + 1 - 1 );
+
+
+ -----
+ --
+ -- address-buffer control signals
+ --
+ abuf_wr_en <= TCU_adrBufWEn;
+
+ --
+ -- address buffer
+ --
+ addr_buffer_e : entity plb2wb_bridge_v1_00_a.fifo_adr( IMP )
+ generic map
+ (
+ SYNCHRONY => SYNCHRONY,
+ C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH
+ )
+ port map(
+ rd_en => TCU_adrBufREn,
+ wr_en => abuf_wr_en,
+ full => AMU_bufFull,
+ empty => AMU_bufEmpty,
+ wr_clk => SPLB_Clk,
+ rst => plb2wb_rst,
+ rd_clk => wb_clk_i,
+ dout => abuf_dout,
+ din => abuf_din
+
+ );
+
+ --
+ --
+ --------------------------
+
+
+end IMP;
+
+
+
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_fifo.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_fifo.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_fifo.vhd (revision 2)
@@ -0,0 +1,166 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.ALL;
+
+
+
+entity plb2wb_fifo is
+ generic(
+ DATA_W : natural := 32;
+ ADDR_W : natural := 4
+ );
+ port(
+ clk : IN std_logic;
+ rst : IN std_logic;
+ rd_en : IN std_logic;
+ wr_en : IN std_logic;
+ din : IN std_logic_vector( DATA_W-1 downto 0 );
+ dout : OUT std_logic_vector( DATA_W-1 downto 0 );
+ empty : OUT std_logic;
+ full : OUT std_logic
+ );
+end entity plb2wb_fifo;
+
+
+architecture IMP of plb2wb_fifo is
+
+
+ type fifo_array_type is array( 2**ADDR_W-1 downto 0 )
+ of std_logic_vector( DATA_W-1 downto 0 );
+
+ type state_type is record
+ read_pointer : std_logic_vector( ADDR_W-1 downto 0 );
+ write_pointer : std_logic_vector( ADDR_W-1 downto 0 );
+ full : std_logic;
+ empty : std_logic;
+ end record;
+
+ signal current_state, next_state : state_type := -- to avoid modelsim warning at time: 0ps, iteration 0
+ ( read_pointer => ( others => '0' ), write_pointer => ( others => '0' ), full => '0', empty => '0' );
+ signal fifo_array : fifo_array_type;
+ signal read_write_select : std_logic_vector( 1 downto 0 );
+ signal rp_plus_1 : std_logic_vector( ADDR_W-1 downto 0 );
+ signal wp_plus_1 : std_logic_vector( ADDR_W-1 downto 0 );
+
+begin
+
+ n_state : process( clk, rst ) begin
+
+ if rst = '1' then
+ current_state.read_pointer <= ( others => '0' );
+ current_state.write_pointer <= ( others => '0' );
+ current_state.full <= '0';
+ current_state.empty <= '1';
+ elsif clk'event and clk='1' then
+ current_state <= next_state;
+ end if;
+
+ end process;
+
+
+ wp_plus_1 <= std_logic_vector( unsigned (current_state.write_pointer) +1 );
+ rp_plus_1 <= std_logic_vector( unsigned (current_state.read_pointer) +1 );
+ read_write_select <= wr_en & rd_en ;
+
+ states : process( current_state, read_write_select, wp_plus_1, rp_plus_1 ) begin
+
+ next_state <= current_state;
+
+ case read_write_select is
+ when "00" => -- nothing to do
+ when "01" => -- read
+
+ if current_state.empty /= '1' then
+ next_state.read_pointer <= rp_plus_1;
+ next_state.full <= '0';
+ if rp_plus_1 = current_state.write_pointer then
+ next_state.empty <= '1';
+ end if;
+ end if;
+
+ when "10" => -- write
+
+ if current_state.full /= '1' then
+ next_state.write_pointer <= wp_plus_1;
+ next_state.empty <= '0';
+ if wp_plus_1 = current_state.read_pointer then
+ next_state.full <= '1';
+ end if;
+ end if;
+
+ when others => -- read and write
+ next_state.write_pointer <= wp_plus_1;
+ next_state.read_pointer <= rp_plus_1;
+ end case;
+
+
+ end process;
+
+
+ write_fifo : process( clk, rst ) begin
+ if rst = '1' then
+ fifo_array <= ( others => ( others => '0' ) );
+ elsif clk'event and clk='1' then
+ if wr_en = '1' and current_state.full = '0' then
+ fifo_array( to_integer( unsigned( current_state.write_pointer ))) <= din;
+ end if;
+ end if;
+
+ end process;
+
+ dout <= fifo_array( to_integer( unsigned( current_state.read_pointer ) ) );
+ full <= current_state.full;
+ empty <= current_state.empty;
+
+
+end architecture IMP;
+
+
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_wbuf.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_wbuf.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_wbuf.vhd (revision 2)
@@ -0,0 +1,122 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+
+library plb2wb_bridge_v1_00_a;
+
+
+
+entity plb2wb_wbuf is
+
+ generic(
+ SYNCHRONY : boolean := true;
+ C_SPLB_DWIDTH : integer := 32;
+ C_SPLB_NATIVE_DWIDTH : integer := 32;
+ C_SPLB_SIZE_WIDTH : integer := 4
+ );
+ port(
+ wb_clk_i : IN std_logic;
+ SPLB_Clk : IN std_logic;
+ plb2wb_rst : IN std_logic;
+
+
+ PLB_size : in std_logic_vector( 0 to C_SPLB_SIZE_WIDTH-1 );
+ PLB_wrDBus : IN std_logic_vector( 0 to C_SPLB_DWIDTH-1 );
+
+
+ TCU_wbufWEn : in std_logic;
+ TCU_wbufREn : in std_logic;
+
+ WBF_empty : OUT std_logic;
+ WBF_full : OUT std_logic;
+ WBF_wBus : OUT std_logic_vector( 0 to C_SPLB_NATIVE_DWIDTH-1 )
+
+
+
+ );
+end entity plb2wb_wbuf;
+
+
+architecture IMP_32 of plb2wb_wbuf is
+
+ constant FIFO_IN_OUT_SIZE : integer := C_SPLB_NATIVE_DWIDTH ;
+
+ signal wbuf_dout : std_logic_vector( FIFO_IN_OUT_SIZE-1 downto 0 );
+ signal wbuf_din : std_logic_vector( FIFO_IN_OUT_SIZE-1 downto 0 );
+ signal wbuf_wen : std_logic;
+
+begin
+
+ --TODO: WBF_full must be or'ed with mid-buffer-full
+ -- and it must not be written to mid-buffer if it is full!
+
+
+ wbuf_wen <= TCU_wbufWEn;
+ wbuf_din <= PLB_wrDBus( 0 to 31 );
+ WBF_wBus <= wbuf_dout( 31 downto 0 );
+
+ wbuf : entity plb2wb_bridge_v1_00_a.fifo_wdat( IMP )
+ generic map(
+ SYNCHRONY => SYNCHRONY,
+ C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
+ )
+ port map(
+ rd_en => TCU_wbufREn,
+ wr_en => wbuf_wen,
+ full => WBF_full,
+ empty => WBF_empty,
+ wr_clk => SPLB_Clk,
+ rst => plb2wb_rst,
+ rd_clk => wb_clk_i,
+ dout => wbuf_dout,
+ din => wbuf_din
+ );
+
+end architecture IMP_32;
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_rdat.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_rdat.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_rdat.vhd (revision 2)
@@ -0,0 +1,159 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+
+library plb2wb_bridge_v1_00_a;
+use plb2wb_bridge_v1_00_a.plb2wb_pkg.all;
+
+
+
+
+
+entity fifo_rdat is
+ generic
+ (
+ SYNCHRONY : boolean := true; -- true = synchron
+ -- false = asynchron
+ WB_DWIDTH : integer range WB_DWIDTH_MIN to WB_DWIDTH_MAX := 32
+ );
+ port(
+ rd_en : in std_logic := 'X';
+ wr_en : in std_logic := 'X';
+ wr_clk : in std_logic := 'X';
+ rst : in std_logic := 'X';
+ rd_clk : in std_logic := 'X';
+ din : in std_logic_vector ( WB_DWIDTH+1-1 downto 0 );
+ dout : out std_logic_vector ( WB_DWIDTH+1-1 downto 0 );
+ full : out std_logic;
+ empty : out std_logic;
+ almost_empty : out std_logic
+ );
+end entity fifo_rdat;
+
+
+
+
+architecture IMP of fifo_rdat is
+
+
+
+component fifo_rdat_cc_32 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ almost_empty : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( RBUF_DWIDTH32-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( RBUF_DWIDTH32-1 downto 0 )
+ );
+end component fifo_rdat_cc_32;
+
+
+component fifo_rdat_ic_32 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ almost_empty : out STD_LOGIC;
+ wr_clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ rd_clk : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( RBUF_DWIDTH32-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( RBUF_DWIDTH32-1 downto 0 )
+ );
+end component fifo_rdat_ic_32;
+
+
+begin
+
+
+
+
+fifo1: if ( SYNCHRONY = true and WB_DWIDTH = RBUF_DWIDTH32-1 ) generate
+U_fifo_cc : fifo_rdat_cc_32
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ almost_empty => almost_empty,
+ clk => rd_clk, -- rd_clk must be the same than wr_clk
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo1;
+
+fifo2: if ( SYNCHRONY = false and WB_DWIDTH = RBUF_DWIDTH32-1 ) generate
+U_fifo_ic : fifo_rdat_ic_32
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ almost_empty => almost_empty,
+ rd_clk => rd_clk,
+ wr_clk => wr_clk,
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo2;
+
+
+
+
+end architecture IMP;
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb.vhd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb.vhd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb.vhd (revision 2)
@@ -0,0 +1,330 @@
+----------------------------------------------------------------------
+---- ----
+---- PLB2WB-Bridge ----
+---- ----
+---- This file is part of the PLB-to-WB-Bridge project ----
+---- http://opencores.org/project,plb2wbbridge ----
+---- ----
+---- Description ----
+---- Implementation of a PLB-to-WB-Bridge according to ----
+---- PLB-to-WB Bridge specification document. ----
+---- ----
+---- To Do: ----
+---- Nothing ----
+---- ----
+---- Author(s): ----
+---- - Christian Haettich ----
+---- feddischson@opencores.org ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2010 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library plb2wb_bridge_v1_00_a;
+use plb2wb_bridge_v1_00_a.plb2wb_pkg.all;
+
+
+entity fifo_stat2plb is
+ generic
+ (
+ SYNCHRONY : boolean := true; -- true = synchron
+ WB_DWIDTH : integer range WB_DWIDTH_MIN to WB_DWIDTH_MAX := 32;
+ WB_AWIDTH : integer range WB_AWIDTH_MIN to WB_AWIDTH_MAX := 32;
+ C_SPLB_MID_WIDTH : integer := 3
+
+ );
+ port(
+ rd_en : in std_logic := 'X';
+ wr_en : in std_logic := 'X';
+ full : out std_logic;
+ empty : out std_logic;
+ wr_clk : in std_logic := 'X';
+ rst : in std_logic := 'X';
+ rd_clk : in std_logic := 'X';
+ dout : out std_logic_vector ( IRQ_INFO_SIZE + WB_AWIDTH + WB_DWIDTH + C_SPLB_MID_WIDTH + STATUS2PLB_INFO_SIZE -1 downto 0 );
+ din : in std_logic_vector ( IRQ_INFO_SIZE + WB_AWIDTH + WB_DWIDTH + C_SPLB_MID_WIDTH + STATUS2PLB_INFO_SIZE -1 downto 0 )
+ );
+end entity fifo_stat2plb;
+
+
+
+architecture IMP of fifo_stat2plb is
+
+constant VEC_MIN_SIZE : integer := IRQ_INFO_SIZE + WB_AWIDTH + WB_DWIDTH + 1 + STATUS2PLB_INFO_SIZE;
+
+
+component fifo_stat2plb_cc_1 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( VEC_MIN_SIZE-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( VEC_MIN_SIZE-1 downto 0 )
+ );
+end component fifo_stat2plb_cc_1;
+
+
+component fifo_stat2plb_ic_1 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ wr_clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ rd_clk : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( VEC_MIN_SIZE-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( VEC_MIN_SIZE-1 downto 0 )
+ );
+end component fifo_stat2plb_ic_1;
+
+component fifo_stat2plb_cc_2 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( VEC_MIN_SIZE+1-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( VEC_MIN_SIZE+1-1 downto 0 )
+ );
+end component fifo_stat2plb_cc_2;
+
+
+component fifo_stat2plb_ic_2 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ wr_clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ rd_clk : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( VEC_MIN_SIZE+1-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( VEC_MIN_SIZE+1-1 downto 0 )
+ );
+end component fifo_stat2plb_ic_2;
+
+component fifo_stat2plb_cc_3 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( VEC_MIN_SIZE+2-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( VEC_MIN_SIZE+2-1 downto 0 )
+ );
+end component fifo_stat2plb_cc_3;
+
+
+component fifo_stat2plb_ic_3 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ wr_clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ rd_clk : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( VEC_MIN_SIZE+2-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( VEC_MIN_SIZE+2-1 downto 0 )
+ );
+end component fifo_stat2plb_ic_3;
+
+component fifo_stat2plb_cc_4 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( VEC_MIN_SIZE+3-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( VEC_MIN_SIZE+3-1 downto 0 )
+ );
+end component fifo_stat2plb_cc_4;
+
+
+component fifo_stat2plb_ic_4 is
+ port (
+ rd_en : in STD_LOGIC := 'X';
+ wr_en : in STD_LOGIC := 'X';
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ wr_clk : in STD_LOGIC := 'X';
+ rst : in STD_LOGIC := 'X';
+ rd_clk : in STD_LOGIC := 'X';
+ dout : out STD_LOGIC_VECTOR ( VEC_MIN_SIZE+3-1 downto 0 );
+ din : in STD_LOGIC_VECTOR ( VEC_MIN_SIZE+3-1 downto 0 )
+ );
+end component fifo_stat2plb_ic_4;
+
+
+
+begin
+
+fifo_cc_1: if ( SYNCHRONY = true and WB_DWIDTH = 32 and C_SPLB_MID_WIDTH = 1 ) generate
+U_fifo_cc : fifo_stat2plb_cc_1
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ clk => rd_clk, -- rd_clk must be the same than wr_clk
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_cc_1;
+
+
+fifo_cc_2: if ( SYNCHRONY = true and WB_DWIDTH = 32 and C_SPLB_MID_WIDTH = 2 ) generate
+U_fifo_cc : fifo_stat2plb_cc_2
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ clk => rd_clk, -- rd_clk must be the same than wr_clk
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_cc_2;
+
+
+fifo_cc_3: if ( SYNCHRONY = true and WB_DWIDTH = 32 and C_SPLB_MID_WIDTH = 3 ) generate
+U_fifo_cc : fifo_stat2plb_cc_3
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ clk => rd_clk, -- rd_clk must be the same than wr_clk
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_cc_3;
+
+
+fifo_cc_4: if ( SYNCHRONY = true and WB_DWIDTH = 32 and C_SPLB_MID_WIDTH = 4) generate
+U_fifo_cc : fifo_stat2plb_cc_4
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ clk => rd_clk, -- rd_clk must be the same than wr_clk
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_cc_4;
+
+
+
+
+fifo_ic_1: if ( SYNCHRONY = false and WB_DWIDTH = 32 and C_SPLB_MID_WIDTH = 1 ) generate
+U_fifo_ic : fifo_stat2plb_ic_1
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ rd_clk => rd_clk,
+ wr_clk => wr_clk,
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_ic_1;
+
+
+fifo_ic_2: if ( SYNCHRONY = false and WB_DWIDTH = 32 and C_SPLB_MID_WIDTH = 2 ) generate
+U_fifo_ic : fifo_stat2plb_ic_2
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ rd_clk => rd_clk,
+ wr_clk => wr_clk,
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_ic_2;
+
+
+fifo_ic_3: if ( SYNCHRONY = false and WB_DWIDTH = 32 and C_SPLB_MID_WIDTH = 3 ) generate
+U_fifo_ic : fifo_stat2plb_ic_3
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ rd_clk => rd_clk,
+ wr_clk => wr_clk,
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_ic_3;
+
+
+fifo_ic_4: if ( SYNCHRONY = false and WB_DWIDTH = 32 and C_SPLB_MID_WIDTH = 4 ) generate
+U_fifo_ic : fifo_stat2plb_ic_4
+ port map(
+ rd_en => rd_en,
+ wr_en => wr_en,
+ full => full,
+ empty => empty,
+ rd_clk => rd_clk,
+ wr_clk => wr_clk,
+ rst => rst,
+ dout => dout,
+ din => din
+ );
+end generate fifo_ic_4;
+
+
+
+
+
+end architecture IMP;
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/data/plb2wb_bridge_v2_1_0.pao
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/data/plb2wb_bridge_v2_1_0.pao (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/data/plb2wb_bridge_v2_1_0.pao (revision 2)
@@ -0,0 +1,36 @@
+lib plb2wb_bridge_v1_00_a plb2wb_pkg vhdl
+lib plb2wb_bridge_v1_00_a plb2wb_short_impulse vhdl
+lib plb2wb_bridge_v1_00_a fifo_adr_cc_4 vhdl
+lib plb2wb_bridge_v1_00_a fifo_adr_ic_4 vhdl
+lib plb2wb_bridge_v1_00_a fifo_adr_cc_3 vhdl
+lib plb2wb_bridge_v1_00_a fifo_adr_ic_3 vhdl
+lib plb2wb_bridge_v1_00_a fifo_adr_cc_2 vhdl
+lib plb2wb_bridge_v1_00_a fifo_adr_ic_2 vhdl
+lib plb2wb_bridge_v1_00_a fifo_adr_cc_1 vhdl
+lib plb2wb_bridge_v1_00_a fifo_adr_ic_1 vhdl
+lib plb2wb_bridge_v1_00_a fifo_adr vhdl
+lib plb2wb_bridge_v1_00_a fifo_rdat_cc_32 vhdl
+lib plb2wb_bridge_v1_00_a fifo_rdat_ic_32 vhdl
+lib plb2wb_bridge_v1_00_a fifo_rdat vhdl
+lib plb2wb_bridge_v1_00_a fifo_wdat_cc_32 vhdl
+lib plb2wb_bridge_v1_00_a fifo_wdat_ic_32 vhdl
+lib plb2wb_bridge_v1_00_a fifo_wdat vhdl
+lib plb2wb_bridge_v1_00_a fifo_stat2plb vhdl
+lib plb2wb_bridge_v1_00_a fifo_stat2plb_ic_4 vhdl
+lib plb2wb_bridge_v1_00_a fifo_stat2plb_cc_4 vhdl
+lib plb2wb_bridge_v1_00_a fifo_stat2plb_ic_3 vhdl
+lib plb2wb_bridge_v1_00_a fifo_stat2plb_cc_3 vhdl
+lib plb2wb_bridge_v1_00_a fifo_stat2plb_ic_2 vhdl
+lib plb2wb_bridge_v1_00_a fifo_stat2plb_cc_2 vhdl
+lib plb2wb_bridge_v1_00_a fifo_stat2plb_ic_1 vhdl
+lib plb2wb_bridge_v1_00_a fifo_stat2plb_cc_1 vhdl
+lib plb2wb_bridge_v1_00_a fifo_stat2wb vhdl
+lib plb2wb_bridge_v1_00_a fifo_stat2wb_ic vhdl
+lib plb2wb_bridge_v1_00_a fifo_stat2wb_cc vhdl
+lib plb2wb_bridge_v1_00_a plb2wb_fifo vhdl
+lib plb2wb_bridge_v1_00_a plb2wb_stu vhdl
+lib plb2wb_bridge_v1_00_a plb2wb_tcu vhdl
+lib plb2wb_bridge_v1_00_a plb2wb_amu vhdl
+lib plb2wb_bridge_v1_00_a plb2wb_rbuf vhdl
+lib plb2wb_bridge_v1_00_a plb2wb_wbuf vhdl
+lib plb2wb_bridge_v1_00_a plb2wb_bridge vhdl
Index: trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/data/plb2wb_bridge_v2_1_0.mpd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/data/plb2wb_bridge_v2_1_0.mpd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/data/plb2wb_bridge_v2_1_0.mpd (revision 2)
@@ -0,0 +1,114 @@
+BEGIN plb2wb_bridge
+
+## Peripheral Options
+OPTION IPTYPE = PERIPHERAL
+OPTION IMP_NETLIST = TRUE
+OPTION HDL = VHDL
+OPTION IP_GROUP = Bus and Bridge:MICROBLAZE
+OPTION DESC = Plb-to-wishbone bridge
+
+
+## Bus Interfaces
+BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
+
+BUS_INTERFACE BUS = MWB, BUS_STD = WB, BUS_TYPE = MASTER
+
+
+PARAMETER SYNCHRONY = true, DT = boolean, VALUES = ( true = synchron, false = asynchron )
+
+
+## Parameters for WB
+PARAMETER WB_DAT_W = 32, DT = INTEGER, ASSIGNMENT = CONSTANT
+PARAMETER WB_ADR_W = 32, DT = INTEGER, ASSIGNMENT = CONSTANT
+PARAMETER WB_ADR_OFFSET = 0x00000000, DT = std_logic_vector
+PARAMETER WB_ADR_OFFSET_NEG = 0, DT = std_logic, VALUES = ( 0 = false, 1 = true )
+PARAMETER WB_PIC_INTS = 1, DT = INTEGER, RANGE = (1 : 32),
+PARAMETER WB_PIC_INT_LEVEL = 1, DT = std_logic, VALUES = ( 0 = active_low, 1 = active_high )
+PARAMETER WB_TIMEOUT_CYCLES = 10, DT = integer, RANGE = (2 : 256 )
+PARAMETER WB_SUPPORT_BLOCK = 1, DT = integer, VALUES = ( 1 = supported, 0 = not supported )
+
+
+## Parameters for PLB
+PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
+PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
+
+PARAMETER C_STATUS_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_STATUS_HIGHADDR, ADDRESS = BASE, BUS = SPLB
+PARAMETER C_STATUS_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_STATUS_BASEADDR, ADDRESS = HIGH, BUS = SPLB
+
+
+PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
+PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
+PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
+PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_SUPPORT_BUR_LINE= 1, DT = INTEGER, BUS = SPLB, VALUES = ( 1 = supported, 0 = not supported )
+PARAMETER C_SPLB_SUPPORT_ADR_PIPE= 1, DT = INTEGER, BUS = SPLB, VALUES = ( 1 = supported, 0 = not supported )
+
+## Ports PLB
+PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
+PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
+PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
+PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
+PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
+PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
+PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
+PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
+PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
+PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
+PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
+PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
+PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
+PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
+PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
+PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
+PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
+PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
+PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
+PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
+PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
+PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
+PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
+PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
+PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
+PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
+PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
+PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
+PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
+PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
+PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
+PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
+PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
+PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
+PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT PLB2WB_IRQ = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH, INTERRUPT_PRIORITY = MEDIUM
+## Ports WB
+
+
+PORT wb_clk_i = "", DIR = I, SIGIS = CLK
+PORT wb_rst_i = "", DIR = I, SIGIS = RST
+PORT wb_pic_int_i= "", DIR = I, VEC = [ WB_PIC_INTS-1: 0 ], SIGIS = INTERRUPT
+PORT wb_dat_i = wb_m_dat_o, DIR = IN , VEC = [ WB_DAT_W-1 : 0 ], BUS = MWB
+PORT wb_dat_o = wb_m_dat_i, DIR = OUT, VEC = [ WB_DAT_W-1 : 0 ], BUS = MWB
+PORT wb_adr_o = wb_m_adr_i, DIR = OUT, VEC = [ WB_ADR_W-1 : 0 ], BUS = MWB
+PORT wb_sel_o = wb_m_sel_i, DIR = OUT, VEC = [ WB_DAT_W/8-1 : 0 ], BUS = MWB
+PORT wb_we_o = wb_m_we_i , DIR = OUT, BUS = MWB
+PORT wb_cyc_o = wb_m_cyc_i, DIR = OUT, BUS = MWB
+PORT wb_stb_o = wb_m_stb_i, DIR = OUT, BUS = MWB
+PORT wb_ack_i = wb_m_ack_o, DIR = IN , BUS = MWB
+PORT wb_err_i = wb_m_err_o, DIR = IN , BUS = MWB
+PORT wb_rty_i = wb_m_rty_o, DIR = IN , BUS = MWB
+
+# note: wb_lock_o is not used, because the arbiter doesn't support it.
+# if u want to use a WB with wb_lock, use the following line --,
+#PORT wb_lock_o = "wb_m_lock_i", DIR = OUT, BUS = MWB <---'
+PORT wb_lock_o = "", DIR = OUT,
+
+
+END
Index: trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/src/plb2wb_bridge.c
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/src/plb2wb_bridge.c (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/src/plb2wb_bridge.c (revision 2)
@@ -0,0 +1,289 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// PLB2WB-Bridge ////
+//// ////
+//// This file is part of the PLB-to-WB-Bridge project ////
+//// http://opencores.org/project,plb2wbbridge ////
+//// ////
+//// Description ////
+//// Implementation of a PLB-to-WB-Bridge according to ////
+//// PLB-to-WB Bridge specification document. ////
+//// ////
+//// To Do: ////
+//// Nothing ////
+//// ////
+//// Author(s): ////
+//// - Christian Haettich ////
+//// feddischson@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2010 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+#include "plb2wb_bridge.h"
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xio.h"
+
+
+
+static void WBResetStubHandler( void *CallBackRef )
+{
+ XASSERT_VOID( FALSE );
+}
+
+
+static void StubHandler( void *CallBackRef )
+{
+
+ XASSERT_VOID(CallBackRef != NULL);
+
+ ( (PLB2WB_Bridge *) CallBackRef )->UnhandledInterrupts++;
+}
+
+
+
+//
+// Note, this handlers MUST be implemented.
+// If no handler is implemented and interrupt is rised,
+// this stubs never return!!
+//
+//
+static void StubWBRstHandler( void *CallBackRef )
+{
+ XASSERT_VOID( FALSE );
+
+}
+
+static void StubWBWrHandler( void *CallBackRef )
+{
+ XASSERT_VOID( FALSE );
+}
+
+
+void PLB2WB_Bridge_DeviceInterruptHandler( void* ptr )
+{
+
+ u32 status_reg;
+ u32 irq_reg;
+ u32 addr_reg;
+ u32 datum_reg;
+ u8 i;
+ PLB2WB_Bridge_VectorTableEntry *entry;
+
+ PLB2WB_Bridge* InstancePtr = (PLB2WB_Bridge*) ptr;
+
+
+ status_reg = XIo_In32( InstancePtr->StatusBaseAddress + PLB2WB_STATUS );
+
+
+
+ // call write-error handler
+ if ( status_reg & PLB2WB_STATUS_WERR )
+ {
+ entry = &InstancePtr->WBWrErrorHandler;
+ entry->Handler( entry->CallBackRef );
+ }
+
+
+ // call irq-handler
+ if ( status_reg & PLB2WB_STATUS_WBIRQ )
+ {
+ irq_reg = XIo_In32( InstancePtr->StatusBaseAddress + PLB2WB_STATUS_IRQ );
+ for( i=0; i<32; i++ )
+ {
+ if( irq_reg & ( 1 << ( 31 - i ) ) )
+ {
+ entry = &InstancePtr->HandlerTable[i];
+ entry->Handler( entry->CallBackRef );
+ }
+ }
+ }
+
+
+ // call reset handler
+ if ( status_reg & PLB2WB_STATUS_WBRST )
+ {
+ entry = &InstancePtr->WBRstHandler;
+ entry->Handler( entry->CallBackRef );
+ }
+
+ // clear bridge-irq
+ XIo_Out32( InstancePtr->StatusBaseAddress + PLB2WB_STATUS, 0 );
+
+ // clear mb-irq
+ XIntc_Acknowledge( InstancePtr->xintcInstancePtr, InstancePtr->irqID );
+}
+
+
+
+
+
+PLB2WB_Bridge_Config *PLB2WB_Bridge_LookupConfig( u16 DeviceId )
+{
+ PLB2WB_Bridge_Config *CfgPtr = NULL;
+
+ int i;
+ for ( i = 0; i < XPAR_PLB2WB_BRIDGE_NUM_INSTANCES; i++ )
+ {
+ if ( PLB2WB_Bridge_ConfigTable[i].DeviceId == DeviceId )
+ {
+ CfgPtr = &PLB2WB_Bridge_ConfigTable[i];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+
+
+
+int PLB2WB_Bridge_Initialize( PLB2WB_Bridge * InstancePtr, u16 DeviceId, XIntc* xintcInstancePtr, u8 irqID )
+{
+ u8 i;
+
+ PLB2WB_Bridge_Config *ConfigPtr;
+
+ XASSERT_NONVOID( InstancePtr != NULL );
+
+ ConfigPtr = PLB2WB_Bridge_LookupConfig( DeviceId );
+
+ if ( ConfigPtr == ( PLB2WB_Bridge_Config * ) NULL )
+ {
+ InstancePtr->IsReady = 0;
+ return ( XST_DEVICE_NOT_FOUND );
+ }
+
+
+ InstancePtr->StatusBaseAddress = ConfigPtr->StatusBaseAddress;
+ InstancePtr->BaseAddress = ConfigPtr->BaseAddress;
+ InstancePtr->CfgPtr = ConfigPtr;
+
+ for( i=0; i < XPAR_PLB2WB_BRIDGE_0_WB_PIC_INTS; i++ )
+ {
+ InstancePtr->HandlerTable[i].Handler = StubHandler;
+ InstancePtr->HandlerTable[i].CallBackRef = InstancePtr;
+ }
+
+ InstancePtr->WBWrErrorHandler.Handler = StubWBWrHandler;
+ InstancePtr->WBWrErrorHandler.CallBackRef = StubWBWrHandler;
+
+ InstancePtr->WBRstHandler.Handler = StubWBRstHandler;
+ InstancePtr->WBRstHandler.CallBackRef = InstancePtr;
+
+
+
+ InstancePtr->xintcInstancePtr = xintcInstancePtr;
+ InstancePtr->irqID = irqID;
+ InstancePtr->IsReady = XCOMPONENT_IS_READY;
+
+ return XST_SUCCESS;
+}
+
+
+
+int PLB2WB_Bridge_Connect_WBRstHandler( PLB2WB_Bridge* InstancePtr,
+ XInterruptHandler Handler, void* CallBackRef )
+{
+ XASSERT_NONVOID( InstancePtr != NULL );
+ XASSERT_NONVOID( Handler != NULL );
+ XASSERT_NONVOID( InstancePtr->IsReady == XCOMPONENT_IS_READY );
+
+ InstancePtr->WBRstHandler.Handler = Handler;
+ InstancePtr->WBRstHandler.CallBackRef = CallBackRef;
+
+ return XST_SUCCESS;
+}
+
+int PLB2WB_Bridge_Connect_WBWrErrHandler( PLB2WB_Bridge* InstancePtr, XInterruptHandler Handler, void* CallBackRef )
+{
+ XASSERT_NONVOID( InstancePtr != NULL );
+ XASSERT_NONVOID( Handler != NULL );
+ XASSERT_NONVOID( InstancePtr->IsReady == XCOMPONENT_IS_READY );
+
+ InstancePtr->WBWrErrorHandler.Handler = Handler;
+ InstancePtr->WBWrErrorHandler.CallBackRef = CallBackRef;
+
+ return XST_SUCCESS;
+}
+
+
+int PLB2WB_Bridge_Connect( PLB2WB_Bridge* InstancePtr, u8 Id,
+ XInterruptHandler Handler, void* CallBackRef )
+{
+ XASSERT_NONVOID( InstancePtr != NULL );
+ XASSERT_NONVOID( Id < XPAR_PLB2WB_BRIDGE_0_WB_PIC_INTS );
+ XASSERT_NONVOID( Handler != NULL );
+ XASSERT_NONVOID( InstancePtr->IsReady == XCOMPONENT_IS_READY );
+
+ InstancePtr->HandlerTable[Id].Handler = Handler;
+ InstancePtr->HandlerTable[Id].CallBackRef = CallBackRef;
+
+ return XST_SUCCESS;
+}
+
+
+
+void PLB2WB_Bridge_Disconnect( PLB2WB_Bridge * InstancePtr, u8 Id )
+{
+ u32 CurrentIER;
+ u32 Mask;
+
+ XASSERT_VOID(InstancePtr != NULL);
+ XASSERT_VOID(Id < XPAR_PLB2WB_BRIDGE_0_WB_PIC_INTS );
+ XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+ InstancePtr->HandlerTable[Id].Handler = StubHandler;
+ InstancePtr->HandlerTable[Id].CallBackRef = InstancePtr;
+}
+
+
+
+void PLB2WB_Bridge_WBContinue ( PLB2WB_Bridge* InstancePtr )
+{
+ XASSERT_VOID(InstancePtr != NULL);
+
+ XIo_Out32( InstancePtr->StatusBaseAddress + PLB2WB_STATUS_CON, 0 );
+}
+
+
+
+void PLB2WB_Bridge_WBAbort ( PLB2WB_Bridge* InstancePtr )
+{
+ XASSERT_VOID(InstancePtr != NULL);
+
+ XIo_Out32( InstancePtr->StatusBaseAddress + PLB2WB_STATUS_ABO, 0 );
+}
+
+
+void PLB2WB_Bridge_SoftReset ( PLB2WB_Bridge* InstancePtr )
+{
+ XASSERT_VOID(InstancePtr != NULL);
+
+ XIo_Out32( InstancePtr->StatusBaseAddress + PLB2WB_STATUS_RST, 0 );
+}
+
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/src/plb2wb_bridge.h
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/src/plb2wb_bridge.h (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/src/plb2wb_bridge.h (revision 2)
@@ -0,0 +1,123 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// PLB2WB-Bridge ////
+//// ////
+//// This file is part of the PLB-to-WB-Bridge project ////
+//// http://opencores.org/project,plb2wbbridge ////
+//// ////
+//// Description ////
+//// Implementation of a PLB-to-WB-Bridge according to ////
+//// PLB-to-WB Bridge specification document. ////
+//// ////
+//// To Do: ////
+//// Nothing ////
+//// ////
+//// Author(s): ////
+//// - Christian Haettich ////
+//// feddischson@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2010 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+#ifndef PLB2WB_BRIDGE_H
+#define PLB2WB_BRIDGE_H
+
+#include "xparameters.h"
+#include "xbasic_types.h"
+#include "xintc.h"
+
+
+//
+// PLB2WB-Bridge registers and irq-id
+//
+#define PLB2WB_STATUS 0x00
+#define PLB2WB_STATUS_DAT 0x04
+#define PLB2WB_STATUS_ADR 0x08
+#define PLB2WB_STATUS_IRQ 0x0c
+#define PLB2WB_STATUS_CON 0x04
+#define PLB2WB_STATUS_ABO 0x08
+#define PLB2WB_STATUS_RST 0x0c
+
+#define PLB2WB_STATUS_WERR 0x20000000
+#define PLB2WB_STATUS_WBRST 0x40000000
+#define PLB2WB_STATUS_WBIRQ 0x80000000
+
+
+
+typedef struct {
+ XInterruptHandler Handler;
+ void *CallBackRef;
+} PLB2WB_Bridge_VectorTableEntry;
+
+
+typedef struct{
+
+ u32 BaseAddress;
+ u32 StatusBaseAddress;
+ u16 DeviceId;
+
+
+
+} PLB2WB_Bridge_Config;
+
+
+typedef struct{
+
+ u32 BaseAddress;
+ u32 StatusBaseAddress;
+ u32 IsReady;
+ u32 UnhandledInterrupts;
+ PLB2WB_Bridge_Config *CfgPtr;
+ u8 irqID;
+ XIntc* xintcInstancePtr;
+
+ PLB2WB_Bridge_VectorTableEntry HandlerTable[ XPAR_PLB2WB_BRIDGE_0_WB_PIC_INTS ]; // wishbone peripheral irqs
+ PLB2WB_Bridge_VectorTableEntry WBWrErrorHandler; // wishbone write error handler
+ PLB2WB_Bridge_VectorTableEntry WBRstHandler; // wishbone reset handler
+
+}PLB2WB_Bridge;
+
+extern PLB2WB_Bridge_Config PLB2WB_Bridge_ConfigTable[];
+
+int PLB2WB_Bridge_Initialize ( PLB2WB_Bridge* InstancePtr, u16 DeviceId,
+ XIntc* xintcInstancePtr, u8 irqID );
+int PLB2WB_Bridge_Connect ( PLB2WB_Bridge*, u8, XInterruptHandler, void* );
+void PLB2WB_Bridge_Disconnect ( PLB2WB_Bridge * InstancePtr, u8 Id );
+void PLB2WB_Bridge_DeviceInterruptHandler( void* ptr );
+
+int PLB2WB_Bridge_Connect_WBWrErrHandler( PLB2WB_Bridge* InstancePtr, XInterruptHandler Handler, void* CallBackRef );
+int PLB2WB_Bridge_Connect_WBRstHandler ( PLB2WB_Bridge* InstancePtr, XInterruptHandler Handler, void* CallBackRef );
+
+void PLB2WB_Bridge_WBContinue ( PLB2WB_Bridge* InstancePtr );
+void PLB2WB_Bridge_WBAbort ( PLB2WB_Bridge* InstancePtr );
+void PLB2WB_Bridge_SoftReset ( PLB2WB_Bridge* InstancePtr );
+
+
+
+
+#endif
Index: trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/src/Makefile
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/src/Makefile (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/src/Makefile (revision 2)
@@ -0,0 +1,27 @@
+
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS= -O0 -ggdb
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+ echo "Compiling or1200 cpu"
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+ make clean
+
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OUTS}
Index: trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/data/plb2wb_bridge_v2_1_0.tcl
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/data/plb2wb_bridge_v2_1_0.tcl (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/data/plb2wb_bridge_v2_1_0.tcl (revision 2)
@@ -0,0 +1,14 @@
+
+
+
+
+proc generate {drv_handle} {
+ xdefine_include_file $drv_handle "xparameters.h" "plb2wb_bridge" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_STATUS_BASEADDR" "C_STATUS_HIGHADDR" "WB_PIC_INTS"
+ xdefine_config_file $drv_handle "plb2wb_bridge_g.c" "PLB2WB_Bridge" "C_BASEADDR" "C_STATUS_BASEADDR" "DEVICE_ID"
+
+
+}
+
+
+
+
Index: trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/data/plb2wb_bridge_v2_1_0.mdd
===================================================================
--- trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/data/plb2wb_bridge_v2_1_0.mdd (nonexistent)
+++ trunk/systems/EDK_Libs/WishboneIPLib/drivers/plb2wb_bridge_v1_00_a/data/plb2wb_bridge_v2_1_0.mdd (revision 2)
@@ -0,0 +1,11 @@
+
+
+
+OPTION psf_version = 2.1.0;
+
+BEGIN DRIVER aclink
+
+ OPTION supported_peripherals = (plb2wb_bridge);
+ OPTION copyfiles = all;
+
+END DRIVER