Subversion Repositories powersupplysequencer

/vhdl/tb/clk_rst/clk_rst_wave.do File deleted

/vhdl/tb/clk_rst/doc/clk_rst_wave.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/vhdl/tb/clk_rst/doc/clk_rst_wave.png

vhdl/tb/clk_rst/doc/clk_rst_wave.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: vhdl/tb/clk_rst/clk_rst_tb.vhd =================================================================== --- vhdl/tb/clk_rst/clk_rst_tb.vhd (revision 2) +++ vhdl/tb/clk_rst/clk_rst_tb.vhd (nonexistent) @@ -1,34 +0,0 @@ --- --- testbed for entity clk_rst.vhd --- (c) jul 2007... Gerhard Hoffmann, opencores@hoffmann-hochfrequenz.de --- open source under BSD conditions - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.numeric_std.all; - - -entity clk_rst_tb is -end entity clk_rst_tb; - -architecture rtl of clk_rst_tb is - -signal tb_clk: std_logic; -signal tb_rst: std_logic; - -begin - -uut: entity work.clk_rst - generic map( - verbose => true, - clock_frequency => 100.0e6, - min_resetwidth => 153 ns - ) - port map( - clk => tb_clk, - rst => tb_rst - ); - - -end architecture rtl; - Index: vhdl/tb/clk_rst/clk_rst_tb.do =================================================================== --- vhdl/tb/clk_rst/clk_rst_tb.do (revision 2) +++ vhdl/tb/clk_rst/clk_rst_tb.do (nonexistent) @@ -1,4 +0,0 @@ -vsim clk_rst_tb -log -r /* -do clk_rst_wave.do -run 2.5 us Index: vhdl/tb/clk_rst/clk_rst.vhd =================================================================== --- vhdl/tb/clk_rst/clk_rst.vhd (revision 2) +++ vhdl/tb/clk_rst/clk_rst.vhd (nonexistent) @@ -1,112 +0,0 @@ ---! @file ---! @brief clock for simulation with selectable frequency and reset with selectable width. - --- (c) jul 2007... Gerhard Hoffmann opencores@hoffmann-hochfrequenz.de --- Published under BSD license --- V1.0 first published version --- ---! @details Solution to an everyday problem. ---! This module produces a clock for a simulation with selectable frequency ---! and a reset signal with selectable width. The duty cycle is 1:1. ---! The reset is active from the beginning and removed synchronously shortly ---! after a rising clock edge. ---! setting verbose to true gives some diagnostics. --- --- Make sure that your simulator has a time resolution of at least 1 ps. --- For modelsim, this is set up by the various modelsim.ini files --- and/or the project file (foobar.mpf) - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use ieee.math_real.all; - - - -entity clk_rst is - generic ( - verbose: boolean := false; - clock_frequency: real := 100.0e6; -- 100 MHz - min_resetwidth: time := 12 ns -- minimum resetwidth, is synchronized to clk - ); - port ( - clk: out std_logic; - rst: out std_logic - ); -end entity clk_rst; - - -architecture rtl of clk_rst is - - --- The clock frequency is given in Hz in floating point format. --- compute the equivalent half cycle time. - -function frequency2halfcycle(f: real; verbose: boolean) return time is - - variable picoseconds: real; - variable retval: time; - -begin - assert f > 1.0e-10 - report "clk_and_rst.vhd: requested clock frequency is unreasonably low or even negative - danger of 1/0.0" - severity error; - - picoseconds := (0.5 / f ) / 1.0e-12; - retval := integer(picoseconds) * 1 ps; - - if verbose then - report "function frequency2halfcycle() in clk_rst.vhd: picoseconds = " & real'image(picoseconds); - report "halfcycle = " & time'image(retval); - end if; - - assert retval > 0 ps - report "frequency2halfcycle(): length of halfcycle truncated to 0 ps. " - & "Set simulator resolution to 1 ps or smaller in modelsim.ini, foobar.mpf or whatever your simulator uses" - severity error; - - return retval; -end; - - -signal iclk: std_logic := '0'; -- entity-internal clk and rst -signal irst: std_logic := '1'; - -constant halfcycle: time := frequency2halfcycle(clock_frequency, verbose); - ----------------------------------------------------------------------------------------------------- -begin - --- --- generate the internal system clock - -u_sysclock: process is -begin - wait for halfcycle; - iclk <= '1'; - - wait for halfcycle; - iclk <= '0'; -end process u_sysclock; - - --- --- generate internal reset - -u_rst: process is -begin - irst <= '1'; - wait for min_resetwidth; - wait until rising_edge(iclk); - irst <= '0'; - wait; -- forever -end process u_rst; - --- make the local signals public - -clk <= iclk; -rst <= irst; - -end architecture rtl; - Index: vhdl/tb/PowerSupply/PowerSupply_tb.do =================================================================== --- vhdl/tb/PowerSupply/PowerSupply_tb.do (revision 2) +++ vhdl/tb/PowerSupply/PowerSupply_tb.do (nonexistent) @@ -1,6 +0,0 @@ -vcom -work work -2002 -explicit D:/lib/vhdl/tb/PowerSupply/PowerSupply.vhd -vcom -work work -2002 -explicit D:/lib/vhdl/tb/PowerSupply/PowerSupply_tb.vhd -vsim work.PowerSupply_tb -log -r /* -do PowerSupply_wave.do -run 60 ms Index: vhdl/tb/PowerSupply/doc/PowerSupply.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: vhdl/tb/PowerSupply/doc/PowerSupply.png =================================================================== --- vhdl/tb/PowerSupply/doc/PowerSupply.png (revision 2) +++ vhdl/tb/PowerSupply/doc/PowerSupply.png (nonexistent)

vhdl/tb/PowerSupply/doc/PowerSupply.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: vhdl/tb/PowerSupply/PowerSupply.vhd =================================================================== --- vhdl/tb/PowerSupply/PowerSupply.vhd (revision 2) +++ vhdl/tb/PowerSupply/PowerSupply.vhd (nonexistent) @@ -1,70 +0,0 @@ --- simple power supply model for testbeds. --- here we are not interested in line regulation. We just want to see --- the reaction to the enable signal, the rough behaviour of the output --- voltage and that it asserts powergood when the output voltage approaches --- the intended value. And it breaks on command. - --- (c) 2009.. Gerhard Hoffmann opencores@hoffmann-hochfrequenz.de --- published under BSD conditions. - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.all; -use ieee.math_real.all; - - - -entity PowerSupply is - generic ( - voltage: real := 3.3; - risetime: real := 1.0e-3 -- one millisecond - ); - - port ( - defective: in boolean; - ena: in std_logic; - pgood: out std_logic; - vout: out real - ); -end entity PowerSupply; - - - -architecture behave of PowerSupply is - - signal cur_voltage: real := 0.0; - signal voltage_goal: real := 0.0; - - - function bool2sl (b: boolean) return std_logic is - begin - if b then return '1'; else return '0'; end if; - end function bool2sl; - - - -begin - -u_regulate: process is -begin - - if ena = '1' - then - voltage_goal <= voltage; - else - voltage_goal <= 0.0; - end if; - - -- 1.0e-6 is for the 1 us timestep - cur_voltage <= cur_voltage + (voltage_goal - cur_voltage) * ((1.0e-6 * 3.0) / risetime); - - pgood <= bool2sl ( (cur_voltage > (0.95 * voltage)) and not defective); - vout <= cur_voltage; - - wait for 1 us; -end process u_regulate; - - -end architecture behave; - Index: vhdl/tb/PowerSupply/PowerSupply_wave.do =================================================================== --- vhdl/tb/PowerSupply/PowerSupply_wave.do (revision 2) +++ vhdl/tb/PowerSupply/PowerSupply_wave.do (nonexistent) @@ -1,32 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /powersupply_tb/defective -add wave -noupdate -format Logic /powersupply_tb/ena -add wave -noupdate -format Logic /powersupply_tb/pgood -add wave -noupdate -clampanalog 1 -format Analog-Step -height 100 -max 5.0 /powersupply_tb/vout -add wave -noupdate -divider -height 20 {New Divider} -add wave -noupdate -format Literal /powersupply_tb/uut/voltage -add wave -noupdate -format Literal /powersupply_tb/uut/risetime -add wave -noupdate -format Logic /powersupply_tb/uut/defective -add wave -noupdate -format Logic /powersupply_tb/uut/ena -add wave -noupdate -format Logic /powersupply_tb/uut/pgood -add wave -noupdate -format Literal /powersupply_tb/uut/vout -add wave -noupdate -format Literal /powersupply_tb/uut/cur_voltage -add wave -noupdate -format Literal /powersupply_tb/uut/voltage_goal -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {34944000000 ps} 0} -configure wave -namecolwidth 212 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ps -update -WaveRestoreZoom {11157444268 ps} {62570660828 ps} Index: vhdl/tb/PowerSupply/PowerSupply_tb.vhd =================================================================== --- vhdl/tb/PowerSupply/PowerSupply_tb.vhd (revision 2) +++ vhdl/tb/PowerSupply/PowerSupply_tb.vhd (nonexistent) @@ -1,43 +0,0 @@ --- Testbed for the power supply --- (c) 2009.. Gerhard Hoffmann opencores@hoffmann-hochfrequenz.de --- published under BSD conditions. - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.all; - - - -entity PowerSupply_tb is end entity PowerSupply_tb; - - -architecture tb of PowerSupply_tb is - - signal defective: boolean; - signal ena: std_logic; - signal pgood: std_logic; - signal vout: real; - -begin - -ena <= '0', '1' after 10 ms, '0' after 20 ms, '1' after 35 ms; -defective <= false, true after 50 ms; - - -uut: entity work.PowerSupply - -generic map ( - voltage => 3.3, - risetime => 2.0e-3 -) - -port map ( - defective => defective, - ena => ena, - pgood => pgood, - vout => vout -); - -end architecture tb; - Index: vhdl/msi/retrigg_timer/retrigg_timer.vhd =================================================================== --- vhdl/msi/retrigg_timer/retrigg_timer.vhd (revision 2) +++ vhdl/msi/retrigg_timer/retrigg_timer.vhd (nonexistent) @@ -1,87 +0,0 @@ --- retriggerable timer --- (c) 2005..2010 Gerhard Hoffmann opencores@hoffmann-hochfrequenz.de -.. V1.0 published under BSD license --- --- delivers a done pulse TICKS clocks after a do command. - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.all; - - - - -entity retrigg_timer is - generic ( - ticks: integer range 2 to integer'high -- clock ticks between do and done - ); - - port ( - - clk: in std_logic; - rst: in std_logic; - - do: in std_logic; - done: out std_logic; - running: out std_logic -); -end retrigg_timer; - - - - - -architecture rtl of retrigg_timer is - - signal tctr: integer range 0 to ticks; - signal irunning: std_logic; - signal idone: std_logic; - - - function bool2sl (b: boolean) return std_logic is - begin - if b then return '1'; else return '0'; end if; - end function bool2sl; - - -begin - -u_timer: process(clk) is -begin - if rising_edge(clk) - then - - if rst = '1' - then - tctr <= 0; - irunning <= '0'; - - elsif (do = '1') - then - tctr <= ticks -1; - irunning <= '1'; - - elsif ((irunning = '1') and (idone = '0')) - - then - tctr <= tctr - 1; - - elsif (idone = '1') - then - irunning <= '0'; - - end if; -- rst - - -- we are not done when a retrigger comes - -- just before the timeout - idone <= bool2sl((tctr = 1) and (do /= '1')); - - end if; -- rising_edge() -end process u_timer; - -done <= idone; -running <= irunning; - -end architecture rtl; - Index: vhdl/msi/retrigg_timer/doc/retrigg_timer.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: vhdl/msi/retrigg_timer/doc/retrigg_timer.png =================================================================== --- vhdl/msi/retrigg_timer/doc/retrigg_timer.png (revision 2) +++ vhdl/msi/retrigg_timer/doc/retrigg_timer.png (nonexistent)

vhdl/msi/retrigg_timer/doc/retrigg_timer.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: vhdl/msi/retrigg_timer/retrigg_timer_wave.do =================================================================== --- vhdl/msi/retrigg_timer/retrigg_timer_wave.do (revision 2) +++ vhdl/msi/retrigg_timer/retrigg_timer_wave.do (nonexistent) @@ -1,27 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /retrigg_timer_tb/rst -add wave -noupdate -format Logic /retrigg_timer_tb/clk -add wave -noupdate -format Logic /retrigg_timer_tb/do -add wave -noupdate -format Logic /retrigg_timer_tb/done -add wave -noupdate -format Logic /retrigg_timer_tb/running -add wave -noupdate -divider {New Divider} -add wave -noupdate -format Literal /retrigg_timer_tb/uut/ticks -add wave -noupdate -format Literal /retrigg_timer_tb/uut/tctr -add wave -noupdate -format Logic /retrigg_timer_tb/uut/running -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {300304 ps} 0} -configure wave -namecolwidth 268 -configure wave -valuecolwidth 52 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {188281 ps} {516407 ps} Index: vhdl/msi/retrigg_timer/retrigg_timer_tb.vhd =================================================================== --- vhdl/msi/retrigg_timer/retrigg_timer_tb.vhd (revision 2) +++ vhdl/msi/retrigg_timer/retrigg_timer_tb.vhd (nonexistent) @@ -1,68 +0,0 @@ ----------------------------------------------------------------------------------------------------- --- (c) 2005..2010 Gerhard Hoffmann opencores@hoffmann-hochfrequenz.de -.. V1.0 published under BSD license ----------------------------------------------------------------------------------------------------- --- Tool versions: Modelsim, ISE 6 .. 10 --- Description: testbed for retriggerable timer - --- calls lib: ieee standard --- calls entities: clk_rst, retrigg_timer ----------------------------------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.all; - -entity retrigg_timer_tb is begin end retrigg_timer_tb; - - -architecture tb of retrigg_timer_tb is - - signal rst, clk: std_logic; - signal do, done, running: std_logic; - -begin - - - -u_clk_rst: entity work.clk_rst - - generic map( - verbose => false, - clock_frequency => 100.0e6, - min_resetwidth => 46 ns - ) - - port map( - clk => clk, - rst => rst - ); - - - -do <= '0', - '1' after 95 ns, '0' after 105 ns, -- trigger first time - '1' after 205 ns, '0' after 215 ns, -- trigger second time - '1' after 245 ns, '0' after 255 ns; -- and once more to test retrigger - - - -uut: entity work.retrigg_timer - - generic map ( - ticks => 5 - ) - - port map ( - clk => clk, - rst => rst, - - do => do, - done => done, - running => running - ); - - -end tb; - - Index: vhdl/msi/retrigg_timer/retrigg_timer_tb.do =================================================================== --- vhdl/msi/retrigg_timer/retrigg_timer_tb.do (revision 2) +++ vhdl/msi/retrigg_timer/retrigg_timer_tb.do (nonexistent) @@ -1,7 +0,0 @@ -vcom -work work -2002 -explicit D:/lib/vhdl/tb/clk_rst/clk_rst.vhd -vcom -work work -2002 -explicit D:/lib/vhdl/msi/retrigg_timer/retrigg_timer.vhd -vcom -work work -2002 -explicit D:/lib/vhdl/msi/retrigg_timer/retrigg_timer_tb.vhd -vsim work.retrigg_timer_tb -log -r /* -do retrigg_timer_wave.do -run 250 ns Index: vhdl/msi/PowerSequencer/PowerSequencer.vhd =================================================================== --- vhdl/msi/PowerSequencer/PowerSequencer.vhd (revision 2) +++ vhdl/msi/PowerSequencer/PowerSequencer.vhd (nonexistent) @@ -1,260 +0,0 @@ --- PowerSequencerSlice - --- (c) 2009.. Gerhard Hoffmann opencores@hoffmann-hochfrequenz.de --- Published under BSD license --- V1.0 first published version --- --- CLK can be any clock you like. RST must be synchronous to it. --- Other inputs are synchronized internally unless generated by same type of slice. --- --- A high clock of, say 200 MHz will produce a lot of logic for the watchdog counter --- to time the millisecond events that happen in power supplies. --- A few KHz should be optimum. --- --- Ena_chain_async = '1' initiates a power up sequence. It will run to completion for the whole system, --- unless some supply fails. In case of supply failure, an ordered retreat is made. --- The supply that comes up last will go down first. --- Pulling ena_chain_async low switches all power supplies off, stage by stage. --- --- The generic "ticks" determines the number of clock ticks we are willing to wait --- until supply_good_async comes up after supply_ena is activated for a given supply. --- --- Do not forget PullDown resistors on supply_ena if the sequencer itself is, for example, --- in a FPGA that is not yet operational at the very first beginning. - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.all; - - - -entity PowerSequencer is - generic ( - ticks: natural; -- clock ticks we are willing to wait until a power supply has to be operational - last_in_chain: boolean := false - ); - - port ( - clk: in std_logic; - rst: in std_logic; - - ena_chain_async: in std_logic; -- enable this slice ( and the following ones if possible) - fail_chain_out: out std_logic; -- we've got a problem ( or one of the following slices) - pu_chain_out: out std_logic; -- power up status of _this_ slice and its slaves - - ena_next: out std_logic; -- cascade output to next slice - fail_chain_in: in std_logic; -- a cascaded slice has a problem - pu_chain_in: in std_logic; -- power up status of our slaves - - supply_ena: out std_logic; -- enable to the power supplies controlled by this slice - supply_good_async: in std_logic -- power good from the supplies controlled by this slice - ); -end PowerSequencer; - - - - - -architecture rtl of PowerSequencer is - - type ps_state is ( - s_idle, - s_powerup_trigger, - s_do_powerup, - s_check, - s_ena_next, - s_operating, - s_retreat_trigger, - s_retreat, - s_complain - ); - - signal current_state: ps_state; - - signal ena_chain: std_logic; - signal supply_good: std_logic; - - signal timer_do: std_logic; - signal timer_done: std_logic; - -begin - - - -u_synchronizer: process(clk) is -begin - if rising_edge(clk) - then - ena_chain <= ena_chain_async; - supply_good <= supply_good_async; - end if; -end process u_synchronizer; - - - -u_statemachine: process(clk) is -begin - - if rising_edge(clk) - then - - if rst = '1' - then - supply_ena <= '0'; - timer_do <= '0'; - fail_chain_out <= '0'; - ena_next <= '0'; - pu_chain_out <= '0'; - - current_state <= s_idle; - - else - case current_state is - - - when s_idle => -- reset / idle state - supply_ena <= '0'; - timer_do <= '0'; - fail_chain_out <= '0'; - ena_next <= '0'; - pu_chain_out <= '0'; - - if ena_chain = '1' - then - current_state <= s_powerup_trigger; - end if; - - - when s_powerup_trigger => -- waking up - supply_ena <= '1'; - timer_do <= '1'; - - current_state <= s_do_powerup; - - - - when s_do_powerup => -- we stay here for one timer cycle to allow OUR - timer_do <= '0'; -- power supply to build up the voltage. - - if timer_done = '1' - then - current_state <= s_check; - end if; - - - - when s_check => -- check wether our supply has come up as expected - if (supply_good = '1') and (ena_chain = '1') - then - ena_next <= '1'; - current_state <= s_ena_next; - else - current_state <= s_retreat_trigger; - end if; - - - - when s_ena_next => -- ok, enable rest of chain - - if (pu_chain_in = '1') or last_in_chain - then - pu_chain_out <= '1'; - current_state <= s_operating; - elsif (fail_chain_in = '1') - then - fail_chain_out <= '1'; -- fail must be communicated on the spot for data saving attempts - current_state <= s_operating; -- looks wrong only at first sight. don't panic. - end if; - - - - when s_operating => -- normal operation, but watch our supply and the slaves - - if (fail_chain_in = '1') or (supply_good = '0') - then - fail_chain_out <= '1'; -- fail must be communicated on the spot for data saving attempts - end if; - - if ((ena_chain = '0') or (supply_good = '0')) -- propagate SwitchOff if there is one - then - ena_next <= '0'; - end if; - - if (( last_in_chain and (ena_chain = '0')) - or (not last_in_chain and (pu_chain_in = '0'))) - then - current_state <= s_retreat_trigger; - else - -- normal operation all day long - null; - end if; - - - - - when s_retreat_trigger => -- start power down sequence - supply_ena <= '0'; - timer_do <= '1'; - - current_state <= s_retreat; - - - - when s_retreat => -- We stay here for one timer cycle to allow OUR - timer_do <= '0'; -- Power supply to drain - - if (timer_done = '1') - then - if (ena_chain = '1') -- don't complain if the user doesn't want the power anyway - then - current_state <= s_complain; -- switchoff because of failure - fail_chain_out <= '1'; - else - current_state <= s_idle; -- normal switchoff - end if; - end if; - - - - when s_complain => -- keep error status until switched off - - fail_chain_out <= '1'; - if (ena_chain = '0') - then - current_state <= s_idle; - end if; - - - - when others => -- whatever surprises the chosen state encoding might provide - current_state <= s_idle; - - - end case; - end if; -- not reset - end if; -- rising_edge(clk) -end process u_statemachine; - - - -uti: entity work.retrigg_timer - - generic map( - ticks => ticks - ) - - port map ( - clk => clk, - rst => rst, - do => timer_do, - done => timer_done, - running => open - ); - - - -end architecture rtl; - - - Index: vhdl/msi/PowerSequencer/PowerSequencer_wave.do =================================================================== --- vhdl/msi/PowerSequencer/PowerSequencer_wave.do (revision 2) +++ vhdl/msi/PowerSequencer/PowerSequencer_wave.do (nonexistent) @@ -1,55 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /powersequencer_tb/clk -add wave -noupdate -format Logic /powersequencer_tb/rst -add wave -noupdate -divider {Simulation testbed controls} -add wave -noupdate -format Logic /powersequencer_tb/ps1_defective -add wave -noupdate -format Logic /powersequencer_tb/ps2_defective -add wave -noupdate -format Logic /powersequencer_tb/ps3_defective -add wave -noupdate -divider {Control of entire PS array} -add wave -noupdate -format Logic /powersequencer_tb/power_up -add wave -noupdate -format Logic /powersequencer_tb/pu_chain123 -add wave -noupdate -format Logic /powersequencer_tb/fail_chain123 -add wave -noupdate -format Logic /powersequencer_tb/all_power_good -add wave -noupdate -divider {PS 1} -add wave -noupdate -format Logic /powersequencer_tb/ena_supply1 -add wave -noupdate -color Cyan -format Analog-Step -height 50 -max 3.5 /powersequencer_tb/vout1 -add wave -noupdate -format Logic /powersequencer_tb/supply1good -add wave -noupdate -format Logic /powersequencer_tb/ups1/timer_do -add wave -noupdate -format Logic /powersequencer_tb/ups1/timer_done -add wave -noupdate -format Literal /powersequencer_tb/ups1/current_state -add wave -noupdate -divider {Handshake between stage 1 and 2} -add wave -noupdate -format Logic /powersequencer_tb/ena_stage2 -add wave -noupdate -format Logic /powersequencer_tb/fail_chain23 -add wave -noupdate -format Logic /powersequencer_tb/pu_chain23 -add wave -noupdate -divider {PS 2} -add wave -noupdate -format Logic /powersequencer_tb/ena_supply2 -add wave -noupdate -color Cyan -format Analog-Step -height 50 -max 3.5 /powersequencer_tb/vout2 -add wave -noupdate -format Logic /powersequencer_tb/supply2good -add wave -noupdate -format Literal /powersequencer_tb/ups2/current_state -add wave -noupdate -divider {Handshake between stage 2 and 3} -add wave -noupdate -format Logic /powersequencer_tb/ena_stage3 -add wave -noupdate -format Logic /powersequencer_tb/fail_chain3 -add wave -noupdate -format Logic /powersequencer_tb/pu_chain3 -add wave -noupdate -divider {PS 3} -add wave -noupdate -format Logic /powersequencer_tb/ena_supply3 -add wave -noupdate -color Cyan -format Analog-Step -height 50 -max 3.5 /powersequencer_tb/vout3 -add wave -noupdate -format Logic /powersequencer_tb/supply3good -add wave -noupdate -format Literal /powersequencer_tb/ups3/current_state -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {43565703635 ps} 0} -configure wave -namecolwidth 287 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ps -update -WaveRestoreZoom {0 ps} {126 ms} Index: vhdl/msi/PowerSequencer/PowerSequencer_tb.vhd =================================================================== --- vhdl/msi/PowerSequencer/PowerSequencer_tb.vhd (revision 2) +++ vhdl/msi/PowerSequencer/PowerSequencer_tb.vhd (nonexistent) @@ -1,187 +0,0 @@ --- Test bed for power sequencer slice - --- (c) 2009.. Gerhard Hoffmann opencores@hoffmann-hochfrequenz.de --- Published under BSD license --- V1.0 first published version --- --- 3 sequencer slices and 3 simulated power supplies are connected together. --- --- A power-up --> normal operation --> power-down is performed. --- --- Then there is another power-up --> normal operation cycle that is --- aborted when the middle power supply decides to run too hot at t = 70 msec. - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.all; - - - -entity PowerSequencer_tb is end entity PowerSequencer_tb; - - -architecture tb of PowerSequencer_tb is - - constant ticks: integer := 30; -- Power supplies must be up within 30 10KHz clock cycles - - signal clk, rst: std_logic; - - signal ps1_defective: boolean; - signal ps2_defective: boolean; - signal ps3_defective: boolean; - - signal power_up: std_logic; -- the mains switch - signal all_power_good: std_logic; -- the green power lamp - - signal ena_stage2, ena_stage3: std_logic; -- mains switch for the slaves - signal fail_chain123, fail_chain23, fail_chain3: std_logic; -- fail outputs of the groups - signal pu_chain123, pu_chain23, pu_chain3: std_logic; -- power up status of the groups - signal vout1, vout2, vout3: real; -- output voltages of the supplies - - signal ena_supply1: std_logic; - signal supply1good: std_logic; - - signal ena_supply2: std_logic; - signal supply2good: std_logic; - - signal ena_supply3: std_logic; - signal supply3good: std_logic; - -begin - - -uck: entity work.clk_rst -- standard clock and reset source - - generic map( - clock_frequency => 10.0e3, -- 10 KHz - min_resetwidth => 5 ms, - verbose => false - ) - - port map( - clk => clk, - rst => rst - ); - - -power_up <= '0', - '1' after 10 ms, - '0' after 40 ms, - '1' after 70 ms, - '0' after 100 ms; - -ps1_defective <= false; -ps2_defective <= false, true after 90 ms; -ps3_defective <= false; - -all_power_good <= power_up and pu_chain123 and (not fail_chain123); - -uPS1: entity work.PowerSequencer -generic map ( - ticks => ticks, - last_in_chain => false -) -port map ( - clk => clk, - rst => rst, - - ena_chain_async => power_up, - fail_chain_out => fail_chain123, - pu_chain_out => pu_chain123, - - ena_next => ena_stage2, - fail_chain_in => fail_chain23, - pu_chain_ini => pu_chain23, - - supply_enai => ena_supply1, - supply_good_async => supply1good -); - - -uPS2: entity work.PowerSequencer -generic map ( - ticks => ticks, - last_in_chain => false - -port map ( - clk => clk, - rst => rst, - - ena_chain_async => ena_stage2, - fail_chain_out => fail_chain23, - pu_chain_out => pu_chain23, - - ena_next => ena_stage3, - fail_chain_in => fail_chain3, - pu_chain_in => pu_chain3, - - supply_ena => ena_supply2, - supply_good_async => supply2good -); - - -uPS3: entity work.PowerSequencer -generic map ( - ticks => ticks, - last_in_chain => true -) -port map ( - clk => clk, - rst => rst, - - ena_chain_async => ena_stage3, - fail_chain_out => fail_chain3, - pu_chain_out => pu_chain3, - - ena_next => open, - fail_chain_in => '0', - pu_chain_in => '0', - - supply_ena => ena_supply3, - supply_good_async => supply3good -); - -------------------------------------------------------------------------- - - -usup1: entity work.powersupply -generic map ( - voltage => 1.8, -- volts - risetime => 2.0e-3 -- seconds -) -port map ( - defective => ps1_defective, - ena => ena_supply1, - pgood => supply1good, - vout => vout1 -); - - -usup2: entity work.powersupply -generic map ( - voltage => 3.3, - risetime => 2.0e-3 -) -port map( - defective => ps2_defective, - ena => ena_supply2, - pgood => supply2good, - vout => vout2 -); - - -usup3:entity work.powersupply -generic map( - voltage => 1.1, - risetime => 2.0e-3 -) -port map( - defective => ps3_defective, - ena => ena_supply3, - pgood => supply3good, - vout => vout3 -); - -end architecture tb; - Index: vhdl/msi/PowerSequencer/PowerSequencer_tb.do =================================================================== --- vhdl/msi/PowerSequencer/PowerSequencer_tb.do (revision 2) +++ vhdl/msi/PowerSequencer/PowerSequencer_tb.do (nonexistent) @@ -1,9 +0,0 @@ -vcom -work work -2002 -explicit D:/lib/vhdl/tb/clk_rst/clk_rst.vhd -vcom -work work -2002 -explicit D:/lib/vhdl/tb/PowerSupply/PowerSupply.vhd -vcom -work work -2002 -explicit D:/lib/vhdl/msi/retrigg_timer/retrigg_timer.vhd -vcom -work work -2002 -explicit D:/lib/vhdl/msi/PowerSequencer/PowerSequencer.vhd -vcom -work work -2002 -explicit D:/lib/vhdl/msi/PowerSequencer/PowerSequencer_tb.vhd -vsim work.PowerSequencer_tb -log -r /* -do PowerSequencer_wave.do -run 120 ms Index: vhdl/msi/PowerSequencer/Makefile =================================================================== --- vhdl/msi/PowerSequencer/Makefile (revision 2) +++ vhdl/msi/PowerSequencer/Makefile (nonexistent) @@ -1,31 +0,0 @@ -DISTRI_ROOT="/d/lib/vhdl" -# -tarball: - tar -cvzf PowerSequencer.tgz \ - $(DISTRI_ROOT)/tb/clk_rst/clk_rst.vhd \ - $(DISTRI_ROOT)/tb/clk_rst/clk_rst_tb.vhd \ - $(DISTRI_ROOT)/tb/clk_rst/clk_rst_tb.do \ - $(DISTRI_ROOT)/tb/clk_rst/clk_rst_wave.do \ - $(DISTRI_ROOT)/tb/clk_rst/doc/clk_rst_wave.png \ - $(DISTRI_ROOT)/tb/PowerSupply/PowerSupply.vhd \ - $(DISTRI_ROOT)/tb/PowerSupply/PowerSupply_tb.vhd \ - $(DISTRI_ROOT)/tb/PowerSupply/PowerSupply_tb.do \ - $(DISTRI_ROOT)/tb/PowerSupply/PowerSupply_wave.do \ - $(DISTRI_ROOT)/tb/PowerSupply/doc/PowerSupply.png \ - $(DISTRI_ROOT)/msi/retrigg_timer/retrigg_timer.vhd \ - $(DISTRI_ROOT)/msi/retrigg_timer/retrigg_timer_tb.vhd \ - $(DISTRI_ROOT)/msi/retrigg_timer/retrigg_timer_tb.do \ - $(DISTRI_ROOT)/msi/retrigg_timer/retrigg_timer_wave.do \ - $(DISTRI_ROOT)/msi/retrigg_timer/doc/retrigg_timer.png \ - $(DISTRI_ROOT)/msi/PowerSequencer/Makefile \ - $(DISTRI_ROOT)/msi/PowerSequencer/PowerSequencer.vhd \ - $(DISTRI_ROOT)/msi/PowerSequencer/PowerSequencer_tb.vhd \ - $(DISTRI_ROOT)/msi/PowerSequencer/PowerSequencer_tb.do \ - $(DISTRI_ROOT)/msi/PowerSequencer/PowerSequencer_wave.do \ - $(DISTRI_ROOT)/msi/PowerSequencer/doc/ps_sequencer_usage.png \ - $(DISTRI_ROOT)/msi/PowerSequencer/doc/ResultOfSimulation.png \ - $(DISTRI_ROOT)/msi/PowerSequencer/doc/ZoomIntoPowerUp.png \ - $(DISTRI_ROOT)/msi/PowerSequencer/doc/ZoomIntoPowerDown.png \ - $(DISTRI_ROOT)/msi/PowerSequencer/doc/PS2DeclaresItselfFaultyAt90ms.png \ - $(DISTRI_ROOT)/msi/PowerSequencer/doc/PowerSequencer.odt - Index: vhdl/msi/PowerSequencer/doc/ResultOfSimulation.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: vhdl/msi/PowerSequencer/doc/ResultOfSimulation.png =================================================================== --- vhdl/msi/PowerSequencer/doc/ResultOfSimulation.png (revision 2) +++ vhdl/msi/PowerSequencer/doc/ResultOfSimulation.png (nonexistent)

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