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https://opencores.org/ocsvn/pwm/pwm/trunk
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/pwm/trunk
- from Rev 6 to Rev 5
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Rev 6 → Rev 5
/RTL/down_clocking_even.v
1,4 → 1,6
/*Down clocking module |
/*Author: Zhuxu |
m99a1@yahoo.cn |
Down clocking module |
Output clock frequency is the original frequency divided by an even number |
*/ |
module down_clocking_even( |
21,7 → 23,7
assign go=((i_divisor!=0)&&i_rst); |
reg [15:0]ct; |
reg clk; |
always@(posedge i_clk or negedge i_rst) |
always@(posedge i_clk or i_rst) |
if(!i_rst)begin |
ct<=0; |
clk<=0; |