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Rev 30 → Rev 29

/qaz_libs/trunk/axi4_lib/sim/libs/axi4_lib_verilog/axi4_stream_lib.f
5,5 → 5,9
# ${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/axis_video_debug.sv
${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/data_to_axis_fsm.sv
 
# ${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/axis_to_vid_fsm.sv
# ${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/camera_link_to_axis.sv
# ${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/camera_link_to_axis_fsm.sv
 
${ROOT_DIR}/qaz_libs/axi4_stream_lib/src/axis_register_slice.sv
 
/qaz_libs/trunk/axi4_stream_lib/src/axis_to_vid_fsm.sv
0,0 → 1,136
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module
axis_to_vid_fsm
(
input axis_to_vid_fsm_en,
input [31:0] reg_active_size,
input [15:0] reg_hblanking,
input [15:0] reg_vblanking,
 
input vid_sof,
input vid_eol,
input vid_stall_at_vblank,
 
output fifo_rd_en,
 
output vid_timing_fsm_idle,
output vid_active_video,
output vid_hblank,
output vid_vblank,
output vid_timing_fsm_error,
input vid_clk,
input vid_clk_en,
input vid_reset
);
 
// --------------------------------------------------------------------
//
reg [15:0] pixel_counter;
reg [15:0] line_counter;
wire [15:0] active_hsize = reg_active_size[15:0];
wire [15:0] active_vsize = reg_active_size[31:16];
 
 
//---------------------------------------------------
// state machine binary definitions
enum reg [4:0] {
IDLE_STATE = 5'b0_0001,
PIXEL_DATA = 5'b0_0010,
HORIZONTAL_BLANKING = 5'b0_0100,
VERTICAL_BLANKING = 5'b0_1000,
ERROR_STATE = 5'b1_0000
} state, next_state;
 
 
//---------------------------------------------------
// state machine flop
always_ff @(posedge vid_clk)
if(vid_reset)
state <= IDLE_STATE;
else if(vid_clk_en)
state <= next_state;
 
 
//---------------------------------------------------
// state machine
always_comb
case(state)
IDLE_STATE: if(axis_to_vid_fsm_en)
if(vid_stall_at_vblank)
next_state <= VERTICAL_BLANKING;
else
next_state <= PIXEL_DATA;
else
next_state <= IDLE_STATE;
 
PIXEL_DATA: if(vid_eol)
next_state <= HORIZONTAL_BLANKING;
else
next_state <= PIXEL_DATA;
 
HORIZONTAL_BLANKING: if(pixel_counter < reg_hblanking)
next_state <= HORIZONTAL_BLANKING;
else if(line_counter < active_vsize)
next_state <= PIXEL_DATA;
else
next_state <= VERTICAL_BLANKING;
 
VERTICAL_BLANKING: if(pixel_counter < reg_vblanking)
next_state <= VERTICAL_BLANKING;
else if(axis_to_vid_fsm_en)
if(vid_stall_at_vblank)
next_state <= VERTICAL_BLANKING;
else
next_state <= PIXEL_DATA;
else
next_state <= IDLE_STATE;
ERROR_STATE: next_state <= IDLE_STATE;
 
default: next_state <= ERROR_STATE;
 
endcase
 
 
// --------------------------------------------------------------------
//
wire pixel_counter_reset = vid_reset | (state == IDLE_STATE) | (state != next_state);
 
always_ff @(posedge vid_clk)
if(pixel_counter_reset)
pixel_counter <= 1;
else if(vid_clk_en)
pixel_counter <= pixel_counter + 1;
// --------------------------------------------------------------------
//
wire line_counter_reset = vid_reset |
(state == IDLE_STATE) |
(vid_sof & (state != next_state));
 
always_ff @(posedge vid_clk)
if(line_counter_reset)
line_counter <= 0;
else if(vid_clk_en & (state == PIXEL_DATA) & vid_eol)
line_counter <= line_counter + 1;
//---------------------------------------------------
// output
assign vid_timing_fsm_error = (state == ERROR_STATE);
assign vid_timing_fsm_idle = (state == IDLE_STATE);
assign vid_active_video = (state == PIXEL_DATA);
assign vid_hblank = (state == HORIZONTAL_BLANKING);
assign vid_vblank = (state == VERTICAL_BLANKING);
assign fifo_rd_en = vid_active_video;
 
endmodule
 
 
 
/qaz_libs/trunk/axi4_stream_lib/src/camera_link_to_axis.sv
0,0 → 1,59
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module
camera_link_to_axis
#(
DATA_IN_WIDTH = 64 // same as axis_out_bus.TDATA_WIDTH
)
(
axis_if.master axis_out_bus,
input [DATA_IN_WIDTH-1:0] cl_data_in,
input cl_frame_valid,
input cl_line_valid,
input cl_data_valid,
input cl_reset, // same as axis_out_bus.aresetn
input cl_clk // same as axis_out_bus.aclk
);
 
// --------------------------------------------------------------------
//
reg [DATA_IN_WIDTH-1:0] cl_data_in_r0;
reg cl_frame_valid_r0;
reg cl_line_valid_r0;
reg cl_data_valid_r0;
always @(posedge cl_clk)
begin
cl_data_in_r0 <= cl_data_in;
cl_frame_valid_r0 <= cl_frame_valid;
cl_line_valid_r0 <= cl_line_valid;
cl_data_valid_r0 <= cl_data_valid;
end
 
 
// --------------------------------------------------------------------
//
reg [DATA_IN_WIDTH-1:0] cl_data_in_r1;
reg cl_frame_valid_r1;
reg cl_line_valid_r1;
reg cl_data_valid_r1;
always @(posedge cl_clk)
begin
cl_data_in_r1 <= cl_data_in_r0;
cl_frame_valid_r1 <= cl_frame_valid_r0;
cl_line_valid_r1 <= cl_line_valid_r0;
cl_data_valid_r1 <= cl_data_valid_r0;
end
 
// --------------------------------------------------------------------
//
 
endmodule
 
 
/qaz_libs/trunk/axi4_stream_lib/src/camera_link_to_axis_fsm.sv
0,0 → 1,83
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module
camera_link_to_axis_fsm
(
input axis_en,
output axis_tvalid,
input axis_tready,
input fifo_almost_full,
input fifo_empty,
output fifo_rd_en,
output data_to_axis_fsm_error,
 
input aclk,
input aresetn
);
 
//---------------------------------------------------
// state machine binary definitions
enum reg [3:0] {
IDLE_STATE = 4'b0001,
TVALID = 4'b0010,
TREADY = 4'b0100,
ERROR_STATE = 4'b1000
} state, next_state;
 
 
//---------------------------------------------------
// state machine flop
always_ff @(posedge aclk)
if(~aresetn)
state <= IDLE_STATE;
else
state <= next_state;
 
 
//---------------------------------------------------
// state machine
always_comb
case(state)
IDLE_STATE: if(axis_en & fifo_almost_full)
if(axis_tready)
next_state <= TREADY;
else
next_state <= TVALID;
else
next_state <= IDLE_STATE;
 
TVALID: if(axis_tready) // wait for slave to be ready
next_state <= TREADY;
else
next_state <= TVALID;
 
TREADY: if(fifo_empty) // slave can accept data
next_state <= IDLE_STATE;
else if(axis_tready)
next_state <= TREADY;
else
next_state <= TVALID;
 
ERROR_STATE: next_state <= IDLE_STATE;
 
default: next_state <= ERROR_STATE;
 
endcase
 
 
//---------------------------------------------------
// outputs
assign axis_tvalid = (next_state == TVALID) | (next_state == TREADY);
assign fifo_rd_en = axis_tvalid & axis_tready;
assign data_to_axis_fsm_error = (state == ERROR_STATE);
 
endmodule
 
 
 

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