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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

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    /
    from Rev 33 to Rev 32
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  •

Rev 33 → Rev 32

/qaz_libs/trunk/PCIe/sim/src/pcie_bfm_pkg.sv
36,148 → 36,27
 
 
// --------------------------------------------------------------------
//
//
class altera_pcie_transaction;
 
tlp_header_class hd_h;
byte data[];
bit tlp_always_packed;
byte packet[];
 
 
//--------------------------------------------------------------------
//
function bit is_qword_aligned;
is_qword_aligned = ~hd_h.address[2];
endfunction: is_qword_aligned
 
 
//--------------------------------------------------------------------
//
function bit is_tlp_packed;
if(tlp_always_packed)
return(1);
if(hd_h.is_3_dw)
if(is_qword_aligned)
return(0);
function new(tlp_header_class hd_h, bit qword_aligned);
this.hd_h = hd_h;
if(qword_aligned & hd_h.fmt_type[5] == 0)
if(hd_h.length == 0)
this.packet = new[1024 + 1];
else
return(1);
else // is_4_dw
if(is_qword_aligned)
return(1);
this.packet = new[hd_h.length + 1];
else
if(hd_h.length == 0)
this.packet = new[1024];
else
return(0);
endfunction: is_tlp_packed
 
 
//--------------------------------------------------------------------
//
function void init(tlp_header_class hd_h);
this.hd_h = hd_h;
endfunction: init
 
 
// --------------------------------------------------------------------
// Memory Read Request
function void make_MRd
(
logic [63:0] address,
logic [9:0] length,
bit use_64_addr = 0
);
hd_h = new(use_64_addr ? DW_4_NO_DATA : DW_3_NO_DATA, MRd, length);
hd_h.set_address(address);
init(hd_h);
data.delete();
endfunction: make_MRd
 
 
// --------------------------------------------------------------------
// Memory Write Request
function void make_MWr
(
logic [63:0] address,
byte data[],
bit use_64_addr = 0
);
logic [9:0] length = (data.size() > 1023) ? 0 : data.size();
hd_h = new(use_64_addr ? DW_4_DATA : DW_3_DATA, MWr, length);
init(hd_h);
this.data = data;
hd_h.set_address(address);
endfunction: make_MWr
 
 
// --------------------------------------------------------------------
//
function tpl_packet_t make_packet;
byte h0[4] = {<<byte{hd_h.header[0:3]}}; // reverse bytes
byte h1[4] = {<<byte{hd_h.header[4:7]}};
byte h2[4] = {<<byte{hd_h.header[8:11]}};
byte h3[4] = {<<byte{hd_h.header[12:15]}};
byte pad[4] = '{8'hxx, 8'hxx, 8'hxx, 8'hxx};
byte header[];
if(hd_h.is_4_dw)
begin
h3 = {<<byte{hd_h.header[12:15]}};
header = {h0, h1, h2, h3};
end
else
header = {h0, h1, h2};
if(data.size() == 0)
make_packet = header;
else if(is_tlp_packed)
make_packet = {header, data};
else
make_packet = {header, pad, data};
// else if(hd_h.is_3_dw)
// if(is_qword_aligned)
// make_packet = {header, pad, data};
// else
// make_packet = {header, data};
// else // is_4_dw
// if(is_qword_aligned)
// make_packet = {header, data};
// else
// make_packet = {header, pad, data};
endfunction: make_packet
 
 
// --------------------------------------------------------------------
//
function tpl_packet_t get_MRd
(
logic [63:0] address,
logic [9:0] length,
bit use_64_addr = 0
);
make_MRd(address, length, use_64_addr);
return(make_packet());
endfunction: get_MRd
 
 
// --------------------------------------------------------------------
//
function tpl_packet_t get_counting_MWr
(
logic [63:0] address,
int size,
bit use_64_addr = 0
);
byte data[];
data = new[size];
foreach(data[i])
data[i] = i;
make_MWr(address, data, use_64_addr);
return(make_packet());
endfunction: get_counting_MWr
 
 
//--------------------------------------------------------------------
//
function new(bit tlp_always_packed = 0);
this.tlp_always_packed = tlp_always_packed;
this.packet = new[hd_h.length];
endfunction: new
 
 
184,8 → 63,8
// --------------------------------------------------------------------
//
endclass: altera_pcie_transaction
 
 
// // --------------------------------------------------------------------
// //
// class base_tlp_packet_class;
241,12 → 120,12
// endcase
 
// endfunction: get_tlp_type
 
 
// // --------------------------------------------------------------------
// //
// function tlp_routing_t get_tlp_routing(tlp_type_t tlp_type);
 
// case(tlp_type)
// MRd: get_tlp_routing = ADDRESS;
// MRdLk: get_tlp_routing = ADDRESS;
274,12 → 153,12
// endcase
 
// endfunction: get_tlp_routing
 
 
// // --------------------------------------------------------------------
// //
// function tlp_transaction_t get_tlp_transaction(tlp_type_t tlp_type);
 
// case(tlp_type)
// MRd: get_tlp_transaction = REQUESTER;
// MRdLk: get_tlp_transaction = REQUESTER;
307,27 → 186,27
// endcase
 
// endfunction: get_tlp_transaction
 
 
// // --------------------------------------------------------------------
// //
// function void display_tlp_cfg(tlp_type_t tlp_type);
 
// logic [5:0] Register_Number = header[11][7:2];
// logic [3:0] Extended_Register_Number = header[10][3:0];
 
// // $display("??? %16.t | Register_Number = %b", $time, Register_Number);
// // $display("??? %16.t | Extended_Register_Number = %b", $time, Extended_Register_Number);
// $display("??? %16.t | config offset = 0x%5.x",
// $display("??? %16.t | config offset = 0x%5.x",
// $time, {Extended_Register_Number, Register_Number, 2'b00});
 
// endfunction: display_tlp_cfg
 
 
// // --------------------------------------------------------------------
// //
// function void display_tlp_type(tlp_type_t tlp_type);
 
// case(tlp_type)
// // MRd: get_tlp_transaction = REQUESTER;
// // MRdLk: get_tlp_transaction = REQUESTER;
355,14 → 234,14
// endcase
 
// endfunction: display_tlp_type
 
 
// // --------------------------------------------------------------------
// //
// function void set_little_endian_header( logic [127:0] data);
 
// logic [2:0] fmt = data[7:5];
 
// if(fmt > 3'b011)
// begin
// $display("!!! %16.t | fmt 3'b%b not supported", $time, fmt);
370,7 → 249,7
// end
 
// header_is_4_dw = data[5];
 
// for(int i = 0; i < (header_is_4_dw ? 16 : 12); i += 4)
// {header[i + 0], header[i + 1], header[i + 2], header[i + 3]} = data[i*8 +: 32];
 
377,7 → 256,7
// header_type = get_tlp_type(header[0]);
// routing_type = get_tlp_routing(header_type);
// transaction_type = get_tlp_transaction(header_type);
 
// fmt_type = header[0];
// tc = header[1][6:4];
// th = header[1][0];
385,7 → 264,7
// td = header[2][7];
// ep = header[2][6];
// length = {header[2][1:0], header[3]};
 
// endfunction: set_little_endian_header
 
 
397,21 → 276,21
// $display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// // $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
// $display("??? %16.t | length = %d", $time, length);
// $display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
// $display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
// $time, tc, th, attr, td, ep);
 
// if(routing_type == ADDRESS)
// if(header_is_4_dw)
// $display("??? %16.t | address[63:0] = 0x%16.x", $time,
// { header[8], header[9], header[10], header[11],
// $display("??? %16.t | address[63:0] = 0x%16.x", $time,
// { header[8], header[9], header[10], header[11],
// header[12], header[13], header[14], header[15][7:2], 2'b00});
// else
// $display("??? %16.t | address[31:0] = 0x%8.x", $time,
// $display("??? %16.t | address[31:0] = 0x%8.x", $time,
// { header[8], header[9], header[10], header[11][7:2], 2'b00});
// else if(routing_type == ID)
// $display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
// $display("??? %16.t | bus = 0x%2.x | device = 0x%x | function = 0x%x", $time,
// header[8], header[9][7:3], header[9][2:0]);
 
// if(transaction_type == COMPLETER)
// begin
// $display("??? %16.t | Completer ID = %b", $time, {header[4], header[5]});
422,12 → 301,12
// begin
// $display("??? %16.t | requester ID = %b", $time, {header[4], header[5]});
// $display("??? %16.t | tag = %b", $time, header[6]);
// $display("??? %16.t | last DW BE = %b | first DW BE = %b",
// $display("??? %16.t | last DW BE = %b | first DW BE = %b",
// $time, header[7][7:4], header[7][3:0]);
// end
 
// display_tlp_type(header_type);
 
// $display("??? %16.t | ---------------------", $time);
 
// endfunction: display_header
/qaz_libs/trunk/PCIe/sim/src/pcie_common_pkg.sv
59,16 → 59,6
 
typedef enum
{
DW_3_NO_DATA,
DW_4_NO_DATA,
DW_3_DATA,
DW_4_DATA,
TPL_PREFIX,
RESERVED
} tlp_fmt_t;
 
typedef enum
{
ROUTING_UNKNOWN,
ADDRESS,
ID,
82,15 → 72,12
COMPLETER
} tlp_transaction_t;
 
typedef byte tpl_packet_t[];
 
 
// --------------------------------------------------------------------
//
class tlp_header_class;
 
tlp_fmt_t tlp_fmt;
tlp_type_t tlp_type;
tlp_type_t header_type;
logic [7:0] fmt_type;
logic [2:0] tc;
logic th;
98,134 → 85,44
logic td;
logic ep;
logic [9:0] length;
logic [63:0] address;
logic [1:0] ph;
byte header[];
logic [7:0] header[16];
logic header_is_4_dw;
 
 
// --------------------------------------------------------------------
//
function bit is_3_dw;
return(~this.fmt_type[5]);
endfunction: is_3_dw
 
 
// --------------------------------------------------------------------
//
function bit is_4_dw;
return(this.fmt_type[5]);
endfunction: is_4_dw
 
 
// --------------------------------------------------------------------
//
function void set_tc(logic [2:0] tc);
this.tc = tc;
header[1][6:4] = tc;
endfunction: set_tc
 
 
// --------------------------------------------------------------------
//
function void set_th(logic th);
this.th = th;
header[1][0] = th;
endfunction: set_th
 
 
// --------------------------------------------------------------------
//
function void set_attr(logic [2:0] attr);
this.attr = attr;
{header[1][2], header[2][5:4]} = attr;
endfunction: set_attr
 
 
// --------------------------------------------------------------------
//
function void set_td(logic td);
this.td = td;
header[2][7] = td;
endfunction: set_td
 
 
// --------------------------------------------------------------------
//
function void set_ep(logic ep);
this.ep = ep;
header[2][6] = ep;
endfunction: set_ep
 
 
// --------------------------------------------------------------------
//
function void set_address(logic [63:0] address);
this.address = address;
if(is_3_dw)
begin
header[8] = this.address[31:24];
header[9] = this.address[23:16];
header[10] = this.address[15:8];
header[11][7:2] = this.address[7:2];
end
else
begin
header[8] = this.address[63:56];
header[9] = this.address[55:48];
header[10] = this.address[47:40];
header[11] = this.address[39:32];
header[12] = this.address[31:24];
header[13] = this.address[23:16];
header[14] = this.address[15:8];
header[15][7:2] = this.address[7:2];
end
endfunction: set_address
 
 
// --------------------------------------------------------------------
//
function void set_ph(logic [1:0] ph);
this.ph = ph;
if(is_3_dw)
header[11][1:0] = ph;
else
header[15][1:0] = ph;
endfunction: set_ph
 
 
// --------------------------------------------------------------------
//
// function logic [7:0] get_fmt_type(tlp_type_t header_type);
function logic [7:0] get_fmt_type;
casez({tlp_fmt, tlp_type})
{DW_3_NO_DATA, MRd}: get_fmt_type = 8'b000_00000;
{DW_4_NO_DATA, MRd}: get_fmt_type = 8'b001_00000;
{DW_3_NO_DATA, MRdLk}: get_fmt_type = 8'b000_00001;
{DW_4_NO_DATA, MRdLk}: get_fmt_type = 8'b001_00001;
{DW_3_DATA, MWr}: get_fmt_type = 8'b010_00000;
{DW_4_DATA, MWr}: get_fmt_type = 8'b011_00000;
{DW_3_NO_DATA, IORd}: get_fmt_type = 8'b000_00010;
{DW_3_DATA, IOWr}: get_fmt_type = 8'b010_00010;
{DW_3_NO_DATA, CfgRd0}: get_fmt_type = 8'b000_00100;
{DW_3_DATA, CfgWr0}: get_fmt_type = 8'b010_00100;
{DW_3_NO_DATA, CfgRd1}: get_fmt_type = 8'b000_00101;
{DW_3_DATA, CfgWr1}: get_fmt_type = 8'b010_00101;
{DW_3_NO_DATA, TCfgRd}: get_fmt_type = 8'b000_11011;
{DW_3_DATA, TCfgWr}: get_fmt_type = 8'b010_11011;
{DW_4_NO_DATA, Msg}: get_fmt_type = 8'b001_10xxx;
{DW_4_DATA, MsgD}: get_fmt_type = 8'b011_10xxx;
{DW_3_NO_DATA, Cpl}: get_fmt_type = 8'b000_01010;
{DW_3_DATA, CplD}: get_fmt_type = 8'b010_01010;
{DW_3_NO_DATA, CplLk}: get_fmt_type = 8'b000_01011;
{DW_3_DATA, CplDLk}: get_fmt_type = 8'b010_01011;
{DW_3_DATA, FetchAdd}: get_fmt_type = 8'b010_01100;
{DW_4_DATA, FetchAdd}: get_fmt_type = 8'b011_01100;
{DW_3_DATA, Swap}: get_fmt_type = 8'b010_01101;
{DW_4_DATA, Swap}: get_fmt_type = 8'b011_01101;
{DW_3_DATA, CAS}: get_fmt_type = 8'b010_01110;
{DW_4_DATA, CAS}: get_fmt_type = 8'b011_01110;
{TPL_PREFIX, LPrfx}: get_fmt_type = 8'b100_0xxxx;
{TPL_PREFIX, EPrfx}: get_fmt_type = 8'b100_1xxxx;
default: get_fmt_type = Reserved;
casez(header_type)
MRd: get_fmt_type = 8'b000_00000;
MRd: get_fmt_type = 8'b001_00000;
MRdLk: get_fmt_type = 8'b000_00001;
MRdLk: get_fmt_type = 8'b001_00001;
MWr: get_fmt_type = 8'b010_00000;
MWr: get_fmt_type = 8'b011_00000;
IORd: get_fmt_type = 8'b000_00010;
IOWr: get_fmt_type = 8'b010_00010;
CfgRd0: get_fmt_type = 8'b000_00100;
CfgWr0: get_fmt_type = 8'b010_00100;
CfgRd1: get_fmt_type = 8'b000_00101;
CfgWr1: get_fmt_type = 8'b010_00101;
TCfgRd: get_fmt_type = 8'b000_11011;
TCfgWr: get_fmt_type = 8'b010_11011;
Msg: get_fmt_type = 8'b001_10xxx;
MsgD: get_fmt_type = 8'b011_10xxx;
Cpl: get_fmt_type = 8'b000_01010;
CplD: get_fmt_type = 8'b010_01010;
CplLk: get_fmt_type = 8'b000_01011;
CplDLk: get_fmt_type = 8'b010_01011;
FetchAdd: get_fmt_type = 8'b010_01100;
FetchAdd: get_fmt_type = 8'b011_01100;
Swap: get_fmt_type = 8'b010_01101;
Swap: get_fmt_type = 8'b011_01101;
CAS: get_fmt_type = 8'b010_01110;
CAS: get_fmt_type = 8'b011_01110;
LPrfx: get_fmt_type = 8'b100_0xxxx;
EPrfx: get_fmt_type = 8'b100_1xxxx;
default: get_fmt_type = Reserved;
endcase
endfunction: get_fmt_type
 
232,7 → 129,7
 
// --------------------------------------------------------------------
//
function tlp_type_t get_tlp_type;
function tlp_type_t get_tlp_type(logic [7:0] fmt_type);
casez(fmt_type)
8'b000_00000: get_tlp_type = MRd;
8'b001_00000: get_tlp_type = MRd;
269,9 → 166,10
 
// --------------------------------------------------------------------
//
// function tlp_routing_t get_tlp_routing(tlp_type_t header_type);
function tlp_routing_t get_tlp_routing;
 
case(tlp_type)
case(header_type)
MRd: get_tlp_routing = ADDRESS;
MRdLk: get_tlp_routing = ADDRESS;
MWr: get_tlp_routing = ADDRESS;
302,9 → 200,10
 
// --------------------------------------------------------------------
//
// function tlp_transaction_t get_tlp_transaction(tlp_type_t header_type);
function tlp_transaction_t get_tlp_transaction;
 
case(tlp_type)
case(header_type)
MRd: get_tlp_transaction = REQUESTER;
MRdLk: get_tlp_transaction = REQUESTER;
MWr: get_tlp_transaction = REQUESTER;
335,12 → 234,12
 
// --------------------------------------------------------------------
//
function void display_header(string str = "");
tlp_routing_t routing_type = get_tlp_routing();
function void display_header(string str);
tlp_routing_t routing_type = get_tlp_routing;
tlp_transaction_t transaction_type = get_tlp_transaction;
 
$display("??? %16.t | .....................", $time);
$display("??? %16.t | %s | TLP type | %s", $time, str, tlp_type.name);
$display("??? %16.t | %s | TLP type | %s", $time, str, header_type.name);
// $display("??? %16.t | fmt = %b | type = %b", $time, fmt_type[7:5], fmt_type[4:0]);
$display("??? %16.t | length = %d", $time, length);
$display("??? %16.t | tc = %b | th = %b | attr = %b | td = %b | ep = %b",
347,7 → 246,7
$time, tc, th, attr, td, ep);
 
if(routing_type == ADDRESS)
if(is_4_dw)
if(header_is_4_dw)
$display("??? %16.t | address[63:0] = 0x%16.x", $time,
{ header[8], header[9], header[10], header[11],
header[12], header[13], header[14], header[15][7:2], 2'b00});
372,7 → 271,7
$time, header[7][7:4], header[7][3:0]);
end
 
// display_tlp_type(tlp_type);
// display_tlp_type(header_type);
 
$display("??? %16.t | ---------------------", $time);
 
381,15 → 280,11
 
//--------------------------------------------------------------------
//
function new(tlp_fmt_t tlp_fmt, tlp_type_t tlp_type, logic [9:0] length);
this.tlp_fmt = tlp_fmt;
this.tlp_type = tlp_type;
this.fmt_type = get_fmt_type();
function new(tlp_type_t header_type, logic [9:0] length);
this.header_type = header_type;
this.fmt_type = get_fmt_type;
this.length = length;
if(is_3_dw)
this.header = new[12];
else
this.header = new[16];
this.header_is_4_dw = fmt_type[5];
this.header[0] = fmt_type;
this.header[3] = length[7:0];
this.header[2][1:0] = length[9:8];
/qaz_libs/trunk/PCIe/src/PCIe_debug.sv File deleted
/qaz_libs/trunk/PCIe/src/PCIe_debug_if.sv File deleted
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_register_file.sv
28,7 → 28,7
module
riffa_register_file
#(
// A, // address bus width
A, // address bus width
N, // data bus width in bytes
MW = 3 // mux select width
)
/qaz_libs/trunk/avalon_lib/sim/tests/tb_ast_monitor/tb_ast_monitor.sv
58,6 → 58,12
 
 
// --------------------------------------------------------------------
//
 
 
 
 
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
82,8 → 88,8
.ST_MAX_CHANNELS(ST_MAX_CHANNELS)
)
ast_monitor_i(.sink(src), .src(sink), .*);
 
 
// --------------------------------------------------------------------
//
ast_source
120,9 → 126,9
.ST_MAX_CHANNELS(ST_MAX_CHANNELS)
)
ast_sink_i(.*);
 
 
 
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
/qaz_libs/trunk/avalon_lib/sim/tests/tb_ast_monitor/the_test.sv
52,8 → 52,8
// --------------------------------------------------------------------
// set_verbosity(VERBOSITY_DEBUG);
tb_top.ast_source_i.bfm.init();
tb_top.ast_sink_i.bfm.init();
tb_top.ast_source_i.st_source_bfm_i.init();
tb_top.ast_sink_i.st_sink_bfm_i.init();
 
// --------------------------------------------------------------------
wait(~tb_rst);
60,51 → 60,30
 
// --------------------------------------------------------------------
#200ns;
tb_top.ast_source_i.bfm.set_transaction_data(32'h0000_0000);
tb_top.ast_source_i.bfm.set_transaction_sop(1);
tb_top.ast_source_i.bfm.set_transaction_eop(0);
tb_top.ast_source_i.bfm.push_transaction();
tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(0);
tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(1);
tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(0);
tb_top.ast_source_i.st_source_bfm_i.push_transaction();
tb_top.ast_source_i.bfm.set_transaction_data(32'h1111_1111);
tb_top.ast_source_i.bfm.set_transaction_sop(0);
tb_top.ast_source_i.bfm.set_transaction_eop(0);
tb_top.ast_source_i.bfm.push_transaction();
tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(1);
tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(0);
tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(0);
tb_top.ast_source_i.st_source_bfm_i.push_transaction();
tb_top.ast_source_i.bfm.set_transaction_data(32'h2222_2222);
tb_top.ast_source_i.bfm.set_transaction_sop(0);
tb_top.ast_source_i.bfm.set_transaction_eop(1);
tb_top.ast_source_i.bfm.push_transaction();
tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(2);
tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(0);
tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(1);
tb_top.ast_source_i.st_source_bfm_i.push_transaction();
tb_top.ast_source_i.bfm.set_transaction_data(32'h3333_3333);
tb_top.ast_source_i.bfm.set_transaction_sop(1);
tb_top.ast_source_i.bfm.set_transaction_eop(0);
tb_top.ast_source_i.bfm.push_transaction();
tb_top.ast_source_i.bfm.set_transaction_data(32'h4444_4444);
tb_top.ast_source_i.bfm.set_transaction_sop(0);
tb_top.ast_source_i.bfm.set_transaction_eop(0);
tb_top.ast_source_i.bfm.push_transaction();
tb_top.ast_source_i.bfm.set_transaction_data(32'h5555_5555);
tb_top.ast_source_i.bfm.set_transaction_sop(0);
tb_top.ast_source_i.bfm.set_transaction_eop(1);
tb_top.ast_source_i.bfm.push_transaction();
 
// --------------------------------------------------------------------
#200ns;
@(posedge tb_clk) tb_top.ast_sink_i.bfm.set_ready(1);
@(posedge tb_clk) tb_top.ast_sink_i.bfm.set_ready(0);
repeat(2) @(posedge tb_clk);
tb_top.ast_sink_i.bfm.set_ready(1);
@(posedge tb_clk) tb_top.ast_sink_i.bfm.set_ready(0);
repeat(3) @(posedge tb_clk);
tb_top.ast_sink_i.bfm.set_ready(1);
repeat(3) @(posedge tb_clk);
tb_top.ast_sink_i.bfm.set_ready(0);
repeat(10) @(posedge tb_clk);
tb_top.ast_sink_i.bfm.set_ready(1);
@(posedge tb_clk) tb_top.ast_sink_i.bfm.set_ready(0);
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1);
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0);
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1);
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0);
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1);
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0);
 
 
// --------------------------------------------------------------------
/qaz_libs/trunk/avalon_lib/src/ast_if.sv
32,8 → 32,8
EW = 1, // error signal width in bits.
CW = 1, // channel width in bits.
SW = 8, // Data symbol width in bits. Should be 8 for byte oriented interfaces.
NSB, // Numbers of symbols per beat
NSB_L = (NSB == 1) ? 1 : $clog2(NSB) // empty width
NSW, // Numbers of symbols per word
NSW_L = (NSW == 1) ? 1 : $clog2(NSW)
)
(
input reset,
40,12 → 40,12
input clk
);
 
wire [(SW*NSB)-1:0] data;
wire [(SW*NSW)-1:0] data;
wire valid;
wire ready;
wire startofpacket;
wire endofpacket;
wire [NSB_L-1:0] empty;
wire [NSW_L-1:0] empty;
wire [CW-1:0] channel;
wire [EW-1:0] error;
 
/qaz_libs/trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/altera_avalon_st_source_bfm.sv File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/verbosity_pkg.sv File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/avalon_utilities_pkg.sv File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_source.qsys File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_assertion.sv File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/avalon_utilities_pkg.sv File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_transactions.sv File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_coverage.sv File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor.sv File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/verbosity_pkg.sv File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/avalon_utilities_pkg.sv File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/altera_avalon_st_sink_bfm.sv File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/verbosity_pkg.sv File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_monitor.qsys File deleted
/qaz_libs/trunk/avalon_lib/syn/ast_sink.qsys File deleted
/qaz_libs/trunk/avalon_lib/docs/Avalon Verification IP Suite User Guide .pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/qaz_libs/trunk/avalon_lib/docs/Avalon Verification IP Suite User Guide .pdf
qaz_libs/trunk/avalon_lib/docs/Avalon Verification IP Suite User Guide .pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: qaz_libs/trunk/avalon_lib/docs/mnl_avalon_spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: qaz_libs/trunk/avalon_lib/docs/mnl_avalon_spec.pdf =================================================================== --- qaz_libs/trunk/avalon_lib/docs/mnl_avalon_spec.pdf (revision 33) +++ qaz_libs/trunk/avalon_lib/docs/mnl_avalon_spec.pdf (nonexistent)
qaz_libs/trunk/avalon_lib/docs/mnl_avalon_spec.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: qaz_libs/trunk/scripts/sim_procs.do =================================================================== --- qaz_libs/trunk/scripts/sim_procs.do (revision 33) +++ qaz_libs/trunk/scripts/sim_procs.do (revision 32) @@ -33,12 +33,12 @@ global env echo "INFO: compiling $target rtl" - + foreach filename [glob -nocomplain -directory ${lib}/sim/libs/${target}_verilog/ *.f] { echo "INFO: compiling $filename" vlog -f $filename } - + foreach filename [glob -nocomplain -directory ${lib}/sim/libs/${target}_VHDL/ *.f] { echo "INFO: compiling $filename" vcom -explicit -f $filename @@ -53,12 +53,12 @@ global env echo "INFO: compiling $target rtl" - + foreach filename [glob -nocomplain -directory ../../libs/${target}_verilog/ *.f] { echo "INFO: compiling $filename" vlog -f $filename } - + foreach filename [glob -nocomplain -directory ../../libs/${target}_VHDL/ *.f] { echo "INFO: compiling $filename" vcom -explicit -f $filename @@ -70,11 +70,6 @@ # proc sim_run_sim { } { - if { [file exists ./pre_sim.do] } { - echo "INFO: found ./pre_sim.do" - do ./pre_sim.do - } - if {[file exists ./sim.do]} { do ./sim.do } elseif {[file exists ../../libs/sim.do]} { @@ -84,15 +79,10 @@ } elseif {[file exists ../../libs/xilinx_sim.f]} { vsim -novopt -f ../../libs/xilinx_sim.f -l transcript.txt work.tb_top work.glbl } - + if { [file exists ./wave.do] } { do ./wave.do } - - if { [file exists ./post_sim.do] } { - echo "INFO: found ./post_sim.do" - do ./post_sim.do - } } @@ -128,12 +118,7 @@ echo "INFO: found ./wip.do" do ./wip.do } - - if { [file exists ./pre_sim.do] } { - echo "INFO: found ./pre_sim.do" - do ./pre_sim.do - } - + if { [string equal nodesign [runStatus]] } { sim_run_sim } else { @@ -141,12 +126,6 @@ } run -all - echo "INFO: run -all done." - - if { [file exists ./post_sim.do] } { - echo "INFO: found ./post_sim.do" - do ./post_sim.do - } } @@ -156,7 +135,7 @@ if {[file exists $lib/_info]} { echo "INFO: Simulation library $lib already exists" - + if { $rebuild != 0 } { echo "INFO: Rebuilding library. Deleting ./$lib and recompiling all" quit -sim @@ -164,7 +143,7 @@ vlib $lib vmap $lib $lib } - + } else { vlib $lib vmap $lib $lib

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