URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 37 to Rev 36
- ↔ Reverse comparison
Rev 37 → Rev 36
/qaz_libs/trunk/PCIe/sim/tests/tb_riffa_register_file/the_test.sv
67,15 → 67,9
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// -------------------------------------------------------------------- |
tb_top.a_h.queue_rx(RW*B, 0, 1); |
#200ns; |
tb_top.a_h.wait_for_rx(); |
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// -------------------------------------------------------------------- |
tb_top.a_h.tr_h = new(RW, 0, 1); |
tb_top.a_h.tr_h.constant(RW, 0, 1, 1); |
tb_top.a_h.queue_tx(tb_top.a_h.tr_h); |
tb_top.a_h.wait_for_tx(); |
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// -------------------------------------------------------------------- |
#200ns; |
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// -------------------------------------------------------------------- |
/qaz_libs/trunk/PCIe/sim/src/riffa_agent_class_pkg.sv
57,7 → 57,8
task queue_tx_constant(int len, int off, bit last, logic [(8*N)-1:0] value); |
tr_h = new(len, off, last); |
tr_h.constant(len, off, last, value); |
queue_tx(tr_h); |
tx_h.put(tr_h); |
tx_q.put(tr_h); |
endtask: queue_tx_constant |
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66,7 → 67,8
task queue_tx_counting(int len, int off, bit last); |
tr_h = new(len, off, last); |
tr_h.counting(len, off, last); |
queue_tx(tr_h); |
tx_h.put(tr_h); |
tx_q.put(tr_h); |
endtask: queue_tx_counting |
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75,7 → 77,8
task queue_tx_random(int len, int off, bit last); |
tr_h = new(len, off, last); |
tr_h.random(len, off, last); |
queue_tx(tr_h); |
tx_h.put(tr_h); |
tx_q.put(tr_h); |
endtask: queue_tx_random |
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/qaz_libs/trunk/PCIe/sim/src/riffa_bfm_class_pkg.sv
111,7 → 111,7
begin |
if(error_count > max_mismatches) |
break; |
if(this.data[i] !== to.data[i]) |
if(this.data[i] != to.data[i]) |
begin |
$display("!!! %16.t | ERROR! | 0x%x | this != to | 0x%x != 0x%x", $time, i, this.data[i], to.data[i]); |
error_count++; |
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_axis_test_pattern.sv
58,7 → 58,8
// |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*); |
|
axis_test_patern #(.N(N), .W(W), .WPB(WPB)) |
// axis_test_patern #(.N(N), .W(W), .WPB(WPB)) |
axis_test_patern #(.W(W), .WPB(WPB)) |
axis_test_patern_i(.*); |
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/qaz_libs/trunk/PCIe/src/RIFFA/riffa_register_file.sv
82,13 → 82,12
begin: register_j_gen |
for(k = 0; k < RW; k = k + 1) |
begin: register_k_gen |
assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j); |
assign r_if.wr_en[(j*RW) + k] = rd_en & register_select[(j*RW) + k]; |
assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j); |
|
always_ff @(posedge clk) |
if(reset) |
r_if.register_out[(j*RW) + k] <= 0; |
else if(r_if.wr_en[(j*RW) + k]) |
else if(rd_en & register_select[(j*RW) + k]) |
r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32]; |
end |
end |
103,8 → 102,7
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// -------------------------------------------------------------------- |
// |
// write to register[0][0] to enable reading |
wire tx_ready = r_if.wr_en[0] & rd_data[0]; |
wire tx_ready = 1; |
wire tx_last = 1; |
wire acked; |
wire [31:0] tx_len = RC; |
/qaz_libs/trunk/PCIe/src/RIFFA/riffa_register_if.sv
39,9 → 39,8
input reset |
); |
|
wire [31:0] register_in [RC-1:0]; |
reg [31:0] register_out [RC-1:0]; |
reg wr_en [RC-1:0]; |
wire [31:0] register_in [RC-1:0]; |
reg [31:0] register_out [RC-1:0]; |
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// -------------------------------------------------------------------- |
/qaz_libs/trunk/axi4_stream_lib/src/axis_catenate.sv
92,55 → 92,6
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// -------------------------------------------------------------------- |
// |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus[1:0](.*); |
genvar j; |
|
generate |
if(U_IS_EOP > -1) |
begin: u_is_eop_gen |
for(j = 0; j < U; j++) |
begin: for_tuser_gen |
if(j == U_IS_EOP) |
begin: choped_tuser_gen |
assign axis_bus[0].tuser[j] = 0; |
end |
else |
begin: tuser_gen |
assign axis_bus[0].tuser[j] = axis_in[0].tuser[j]; |
end |
end |
end |
else |
if(U_IS_EOP > -1) |
begin: tlast_gen |
assign axis_bus[0].tlast = axis_in[0].tlast; |
end |
else |
begin: choped_tlast_gen |
assign axis_bus[0].tlast = 0; |
end |
endgenerate |
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// -------------------------------------------------------------------- |
// |
assign axis_in[0].tready = axis_bus[0].tready; |
assign axis_bus[0].tvalid = axis_in[0].tvalid; |
assign axis_bus[0].tdata = axis_in[0].tdata; |
assign axis_bus[0].tstrb = axis_in[0].tstrb; |
assign axis_bus[0].tkeep = axis_in[0].tkeep; |
assign axis_bus[0].tid = axis_in[0].tid; |
assign axis_bus[0].tdest = axis_in[0].tdest; |
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// -------------------------------------------------------------------- |
// |
axis_alias |
axis_alias_i(axis_in[1], axis_bus[1]); |
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// -------------------------------------------------------------------- |
// |
defparam axis_mux_i.N = N; // why are needed these for recursive modules? |
defparam axis_mux_i.I = I; |
defparam axis_mux_i.D = D; |
147,7 → 98,7
defparam axis_mux_i.U = U; |
axis_mux |
// axis_mux #(.N(N), .I(I), .D(D), .U(U)) |
axis_mux_i(.axis_in(axis_bus), .*); |
axis_mux_i(.axis_in(axis_in), .*); |
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// -------------------------------------------------------------------- |
/qaz_libs/trunk/axi4_stream_lib/src/axis_map_fifo.sv
29,12 → 29,12
axis_map_fifo |
#( |
N, // data bus width in bytes |
I = 1, // TID width |
D = 1, // TDEST width |
I = 0, // TID width |
D = 0, // TDEST width |
U = 1, // TUSER width |
USE_TSTRB = 0, // set to 1 to enable, 0 to disable |
USE_TKEEP = 0, // set to 1 to enable, 0 to disable |
// USE_XID = 0, // set to 1 to enable, 0 to disable |
USE_XID = 0, // set to 1 to enable, 0 to disable |
W = 0 |
) |
( |
50,9 → 50,9
// synthesis translate_off |
initial |
begin |
// a_tid_unsuported: assert(I == 0) else $fatal; |
// a_tdest_unsuported: assert(D == 0) else $fatal; |
// a_xid_unsuported: assert(USE_XID == 0) else $fatal; |
a_tid_unsuported: assert(I == 0) else $fatal; |
a_tdest_unsuported: assert(D == 0) else $fatal; |
a_xid_unsuported: assert(USE_XID == 0) else $fatal; |
a_w: assert(W == (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1) else $fatal; |
end |
// synthesis translate_on |
67,19 → 67,19
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tstrb, |
axis_in.tkeep, |
axis_in.tdata |
axis_in.tkeep |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tstrb, |
axis_out.tkeep, |
axis_out.tdata |
axis_out.tkeep |
} = rd_data; |
end |
else if(USE_TSTRB) |
86,17 → 86,17
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tstrb, |
axis_in.tdata |
axis_in.tstrb |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tstrb, |
axis_out.tdata |
axis_out.tstrb |
} = rd_data; |
end |
else if(USE_TKEEP) |
103,17 → 103,17
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tkeep, |
axis_in.tdata |
axis_in.tkeep |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tkeep, |
axis_out.tdata |
axis_out.tkeep |
} = rd_data; |
end |
else |
120,15 → 120,15
begin |
assign wr_data = |
{ |
axis_in.tdata, |
axis_in.tlast, |
axis_in.tuser, |
axis_in.tdata |
axis_in.tuser |
}; |
assign |
{ |
axis_out.tdata, |
axis_out.tlast, |
axis_out.tuser, |
axis_out.tdata |
axis_out.tuser |
} = rd_data; |
end |
end |
/qaz_libs/trunk/axi4_stream_lib/src/axis_mux.sv
45,12 → 45,7
|
// -------------------------------------------------------------------- |
// |
defparam axis_mux_out.N = N; // why are needed these for recursive modules? |
defparam axis_mux_out.I = I; |
defparam axis_mux_out.D = D; |
defparam axis_mux_out.U = U; |
axis_if axis_mux_out(.*); |
// axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out(.*); |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out(.*); |
|
assign axis_in[0].tready = select ? 0 : axis_mux_out.tready; |
assign axis_in[1].tready = select ? axis_mux_out.tready : 0; |
67,19 → 62,15
|
// -------------------------------------------------------------------- |
// |
defparam axis_register_slice_i.N = N; // why are needed these for recursive modules? |
defparam axis_register_slice_i.I = I; |
defparam axis_register_slice_i.D = D; |
defparam axis_register_slice_i.U = U; |
axis_register_slice |
// #( |
// .N(N), |
// .I(I), |
// .D(D), |
// .U(U), |
// .USE_TSTRB(0), |
// .USE_TKEEP(0) |
// ) |
#( |
.N(N), |
.I(I), |
.D(D), |
.U(U), |
.USE_TSTRB(0), |
.USE_TKEEP(0) |
) |
axis_register_slice_i |
( |
.axis_in(axis_mux_out), // slave |
/qaz_libs/trunk/axi4_stream_lib/src/axis_switch_allocator.sv
46,6 → 46,21
|
// -------------------------------------------------------------------- |
// |
wire eop_in; |
|
axis_eop_set #(U_IS_EOP) |
axis_eop_set_i |
( |
.axis_in(axis_in), |
.tready(axis_switch_in.tready), |
.tvalid(axis_in.tvalid), |
.axis_eop(eop_in), |
.* |
); |
|
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// -------------------------------------------------------------------- |
// |
wire eop_out_mux; |
reg [SA-1:0] select; |
|
67,21 → 82,6
|
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// -------------------------------------------------------------------- |
// |
wire eop_in; |
|
axis_eop_set #(U_IS_EOP) |
axis_eop_set_i |
( |
.axis_in(axis_in), |
.tready(axis_switch_in.tready), |
.tvalid(axis_in.tvalid), |
.axis_eop(eop_in), |
.* |
); |
|
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// -------------------------------------------------------------------- |
// state machine binary definitions |
enum reg [3:0] |
{ |
116,9 → 116,9
next_state <= FLUSH; |
|
SWITCH: next_state <= SETTLE; |
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SETTLE: next_state <= ALLOT; // let select propagate to the switches |
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SETTLE: next_state <= ALLOT; // let select propagate to the switches |
|
default: next_state <= ALLOT; |
endcase |
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/qaz_libs/trunk/basal/src/RAM/bram_tdp.v
60,25 → 60,25
// -------------------------------------------------------------------- |
// Port A |
always @(posedge a_clk) |
if(a_wr) |
begin |
a_dout <= a_din; |
mem[a_addr] <= a_din; |
a_dout <= mem[a_addr]; |
if(a_wr) begin |
a_dout <= a_din; |
mem[a_addr] <= a_din; |
end |
end |
else |
a_dout <= mem[a_addr]; |
|
|
// -------------------------------------------------------------------- |
// Port B |
always @(posedge b_clk) |
if(b_wr) |
begin |
b_dout <= b_din; |
mem[b_addr] <= b_din; |
b_dout <= mem[b_addr]; |
if(b_wr) begin |
b_dout <= b_din; |
mem[b_addr] <= b_din; |
end |
end |
else |
b_dout <= mem[b_addr]; |
|
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// -------------------------------------------------------------------- |
/qaz_libs/trunk/sim/libs/axi4_lib_verilog/axi4_stream_base.f
6,7 → 6,6
${LIB_BASE_DIR}/axi4_stream_lib/src/data_to_axis_fsm.sv |
|
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_register_slice.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_map_fifo.sv |
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${LIB_BASE_DIR}/axi4_stream_lib/src/axis_mux.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_alias.sv |
16,6 → 15,3
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${LIB_BASE_DIR}/axi4_stream_lib/src/axis_eop_set.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_eop_mux.sv |
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${LIB_BASE_DIR}/axi4_stream_lib/src/axis_catenate.sv |
${LIB_BASE_DIR}/axi4_stream_lib/src/axis_switch.sv |
/qaz_libs/trunk/sim/libs/qaz_lib_verilog/basal.f
34,5 → 34,4
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${LIB_BASE_DIR}/basal/src/synchronize/synchronizer.v |
${LIB_BASE_DIR}/basal/src/synchronize/sync_reset.v |
${LIB_BASE_DIR}/basal/src/synchronize/pulse_synchronizer.v |
|
/qaz_libs/trunk/axi4_lite_lib/src/axi4_lite_register_file.sv
73,12 → 73,11
for(j = 0; j < MI; j = j + 1) |
begin: decoder_gen |
assign register_select[j] = (axi4_write_fifo.awaddr[UB:LB] == j) ? 1 : 0; |
assign r_if.wr_en[j] = rf_wr_en & register_select[j]; |
|
always_ff @(posedge aclk) |
if(~aresetn) |
r_if.register_out[j] <= 0; |
else if(r_if.wr_en[j]) |
else if(rf_wr_en & register_select[j]) |
r_if.register_out[j] <= axi4_write_fifo.wdata; |
end |
endgenerate |
/qaz_libs/trunk/axi4_lite_lib/src/axi4_lite_register_if.sv
40,7 → 40,6
|
wire [(N*8)-1:0] register_in [MI-1:0]; |
reg [(N*8)-1:0] register_out [MI-1:0]; |
wire wr_en [MI-1:0]; |
|
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// -------------------------------------------------------------------- |
47,8 → 46,8
// synthesis translate_off |
initial |
a_data_bus_width: assert((N == 8) | (N == 4)) else $fatal; |
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// synthesis translate_on |
// -------------------------------------------------------------------- |
|