URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/PCIe/src
- from Rev 34 to Rev 33
- ↔ Reverse comparison
Rev 34 → Rev 33
/RIFFA/riffa_axis_test_pattern.sv
File deleted
/RIFFA/riffa_register_file.sv
28,7 → 28,7
module |
riffa_register_file |
#( |
A, // address bus width |
// A, // address bus width |
N, // data bus width in bytes |
MW = 3 // mux select width |
) |
/RIFFA/riffa_chnl_rx.sv
33,7 → 33,7
( |
riffa_chnl_if chnl_in, |
output rx_done, |
output reg [30:0] rx_index, |
output reg [31:0] rx_index, |
output reg rx_last, |
output reg [31:0] rx_len, |
output reg [30:0] rx_off, |
48,6 → 48,11
|
// -------------------------------------------------------------------- |
// |
localparam RW = (N/4); // width of the bus in 32 bit words |
|
|
// -------------------------------------------------------------------- |
// |
riffa_chnl_rx_fsm |
riffa_chnl_rx_fsm_i |
( |
85,7 → 90,7
if(reset | rx_done) |
rx_index = 0; |
else if(rd_en) |
rx_index <= rx_index + (N/4); // increment by 32 bit words |
rx_index <= rx_index + RW; |
|
|
// -------------------------------------------------------------------- |
/RIFFA/riffa_chnl_tx.sv
28,14 → 28,14
module |
riffa_chn_tx |
#( |
N // data bus width in bytes |
N, // data bus width in bytes |
D = 2 // TX data fifo depth |
) |
( |
riffa_chnl_if chnl_in, |
input tx_ready, |
input tx_done, |
output acked, |
output reg [30:0] tx_index, |
output reg [31:0] tx_index, |
input tx_last, |
input [31:0] tx_len, |
input [30:0] tx_off, |
45,7 → 45,12
); |
|
// -------------------------------------------------------------------- |
// |
// |
localparam RW = (N/4); // width of the bus in 32 bit words |
|
|
// -------------------------------------------------------------------- |
// |
riffa_chnl_tx_fsm |
riffa_chnl_tx_fsm_i |
( |
58,10 → 63,10
// -------------------------------------------------------------------- |
// |
always_ff @(posedge clk) |
if(reset | ~chnl_in.tx | tx_done) |
if(reset | ~chnl_in.tx) |
tx_index = 0; |
else if(chnl_in.tx_data_valid & chnl_in.tx_data_ren) |
tx_index <= tx_index + (N/4); // increment by 32 bit words |
tx_index <= tx_index + RW; |
|
|
// -------------------------------------------------------------------- |
/RIFFA/riffa_chnl_tx_fsm.sv
30,7 → 30,6
( |
input tx_ready, |
output tx, |
output acked, |
input tx_ack, |
input tx_done, |
|
86,8 → 85,7
|
// -------------------------------------------------------------------- |
// |
assign tx = (state == ACK) | (state == TX); |
assign acked = (state == TX) | (next_state == TX); |
assign tx = (state == ACK) | (state == TX); |
|
|
// -------------------------------------------------------------------- |
/RIFFA/riffa_register_if.sv
30,9 → 30,8
riffa_register_if |
#( |
N, // data bus width in bytes |
B, // number of register banks |
RW = (N/4), // width of the bus in 32 bit words |
RC = RW * B // number of available registers |
MW, // mux select width |
MI = 2 ** MW // mux inputs |
) |
( |
input clk, |
39,8 → 38,8
input reset |
); |
|
wire [31:0] register_in [RC-1:0]; |
reg [31:0] register_out [RC-1:0]; |
wire [(N*8)-1:0] register_in [MI-1:0]; |
reg [(N*8)-1:0] register_out [MI-1:0]; |
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// -------------------------------------------------------------------- |