URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
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- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/PCIe
- from Rev 50 to Rev 49
- ↔ Reverse comparison
Rev 50 → Rev 49
/src/RIFFA/riffa_chnl_downsizer.sv
0,0 → 1,99
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
riffa_chnl_downsizer |
#( |
N, // PCIe IP data in width in bytes |
S // data out size divisor |
) |
( |
riffa_chnl_if chnl_in, |
riffa_chnl_if chnl_out |
); |
|
// -------------------------------------------------------------------- |
// |
riffa_chnl_xx_downsizer #(.N(N), .S(S)) |
riffa_chnl_xx_downsizer_i |
( |
.xx_in(chnl_in.rx), |
.ack_in(chnl_in.rx_ack), |
.last_in(chnl_in.rx_last), |
.len_in(chnl_in.rx_len), |
.off_in(chnl_in.rx_off), |
.data_in(chnl_in.rx_data), |
.data_valid_in(chnl_in.rx_data_valid), |
.data_ren_in(chnl_in.rx_data_ren), |
|
.last_out(chnl_out.rx_last), |
.len_out(chnl_out.rx_len), |
.off_out(chnl_out.rx_off), |
.data_out(chnl_out.rx_data), |
.data_valid_out(chnl_out.rx_data_valid), |
.data_ren_out(chnl_out.rx_data_ren), |
|
.reset(chnl_in.rx_reset), |
.clk(chnl_in.rx_clk) |
); |
|
|
// -------------------------------------------------------------------- |
// |
riffa_chnl_xx_upsizer #(.N(N/S), .S(S)) |
riffa_chnl_xx_upsizer_i |
( |
.xx_in(chnl_in.tx), |
.ack_in(chnl_in.tx_ack), |
.last_in(chnl_out.tx_last), |
.len_in(chnl_out.tx_len), |
.off_in(chnl_out.tx_off), |
.data_in(chnl_out.tx_data), |
.data_valid_in(chnl_out.tx_data_valid), |
.data_ren_in(chnl_out.tx_data_ren), |
|
.last_out(chnl_in.tx_last), |
.len_out(chnl_in.tx_len), |
.off_out(chnl_in.tx_off), |
.data_out(chnl_in.tx_data), |
.data_valid_out(chnl_in.tx_data_valid), |
.data_ren_out(chnl_in.tx_data_ren), |
|
.reset(chnl_in.tx_reset), |
.clk(chnl_in.tx_clk) |
); |
|
|
|
// -------------------------------------------------------------------- |
// |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/src/RIFFA/riffa_chnl_xx_downsizer.sv
0,0 → 1,137
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
riffa_chnl_xx_downsizer |
#( |
N, // PCIe IP data in width in bytes |
S // data out size divisor |
) |
( |
input xx_in, |
output ack_in, |
input last_in, |
input [31:0] len_in, |
input [30:0] off_in, |
input [(8*N)-1:0] data_in, |
input data_valid_in, |
output data_ren_in, |
|
output last_out, |
output reg [31:0] len_out, |
output reg [30:0] off_out, |
output [(8*N/S)-1:0] data_out, |
output data_valid_out, |
input data_ren_out, |
|
input reset, |
input clk |
); |
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
initial |
begin |
a_divisor: assert(S > 1) else $fatal; |
a_data_mod: assert(N % S == 0) else $fatal; |
end |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
wire [(8*N)-1:0] wr_data = data_in; |
wire wr_full; |
wire wr_en = data_ren_in & data_valid_in; |
wire rd_empty; |
wire [(8*N)-1:0] rd_data; |
wire rd_en; |
|
tiny_sync_fifo #(.W((8*N))) |
tiny_sync_fifo_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
localparam M_A = $clog2(S); |
localparam M_D = 2 ** M_A; |
localparam M_NW = (N*8)/ S; |
|
wire [M_A-1:0] select; |
|
riffa_chnl_xx_downsizer_fsm #(.N(N), .S(S), .M_A(M_A)) |
riffa_chnl_xx_downsizer_fsm_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
wire [M_NW-1:0] mux_in [M_D-1:0]; |
|
recursive_mux #(.A(M_A), .W(M_NW)) |
tdata_mux_i(.data_in(mux_in), .data_out(data_out), .*); |
|
|
// -------------------------------------------------------------------- |
// |
generate |
begin: rd_data_gen |
for(genvar j = 0; j < M_D; j++) |
assign mux_in[j] = rd_data[j*M_NW +: M_NW]; |
end |
endgenerate |
|
|
// -------------------------------------------------------------------- |
// |
reg last_in_r; |
|
always_ff @(posedge clk) |
if(xx_in & ack_in) |
begin |
last_in_r <= last_in; |
len_out <= len_in; |
off_out <= off_in; |
end |
|
|
// -------------------------------------------------------------------- |
// |
riffa_chnl_fsm |
riffa_chnl_fsm_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
assign last_out = (select == S - 1) ? last_in_r : 0; // need to fix |
assign data_ren_in = ~wr_full; |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/src/RIFFA/riffa_chnl_xx_downsizer_fsm.sv
0,0 → 1,118
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
riffa_chnl_xx_downsizer_fsm |
#( |
N, // PCIe IP data in width in bytes |
S, // data out size divisor |
M_A |
) |
( |
input rd_empty, |
input data_ren_out, |
|
output rd_en, |
output data_valid_out, |
output reg [M_A-1:0] select, |
|
input reset, |
input clk |
); |
|
// -------------------------------------------------------------------- |
// |
wire almost_last_word; |
|
|
//--------------------------------------------------- |
// state machine binary definitions |
enum reg [2:0] |
{ |
GET_WORD_IN = 3'b001, |
MUX_WORD_OUT = 3'b010, |
LAST_WORD_OUT = 3'b100 |
} state, next_state; |
|
|
//--------------------------------------------------- |
// state machine flop |
always_ff @(posedge clk) |
if(reset) |
state <= GET_WORD_IN; |
else |
state <= next_state; |
|
|
//--------------------------------------------------- |
// state machine |
always_comb |
case(state) |
GET_WORD_IN: if(~rd_empty) |
next_state <= MUX_WORD_OUT; |
else |
next_state <= GET_WORD_IN; |
|
MUX_WORD_OUT: if(rd_empty) |
next_state <= GET_WORD_IN; |
else if(almost_last_word & data_ren_out) |
next_state <= LAST_WORD_OUT; |
else |
next_state <= MUX_WORD_OUT; |
|
LAST_WORD_OUT: if(~data_ren_out) |
next_state <= LAST_WORD_OUT; |
else |
next_state <= MUX_WORD_OUT; |
|
default: next_state <= GET_WORD_IN; |
|
endcase |
|
|
// -------------------------------------------------------------------- |
// |
assign almost_last_word = (select == S - 2); |
|
always_ff @(posedge clk) |
if(reset | (state == GET_WORD_IN)) |
select <= 0; |
else if(data_valid_out & data_ren_out) |
select <= select + 1; |
|
|
// -------------------------------------------------------------------- |
// |
wire changing_state = (state != next_state); |
assign rd_en = (state == LAST_WORD_OUT) & changing_state; |
assign data_valid_out = (state != GET_WORD_IN) & ~rd_empty; |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/src/RIFFA/riffa_chnl_xx_upsizer.sv
0,0 → 1,73
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module |
riffa_chnl_xx_upsizer |
#( |
N, // PCIe IP data in width in bytes |
S // data out size multiplier |
) |
( |
input xx_in, |
output ack_in, |
input last_in, |
input [31:0] len_in, |
input [30:0] off_in, |
input [(8*N)-1:0] data_in, |
input data_valid_in, |
output data_ren_in, |
|
output last_out, |
output [31:0] len_out, |
output [30:0] off_out, |
output [(8*N*S)-1:0] data_out, |
output data_valid_out, |
input data_ren_out, |
|
input reset, |
input clk |
); |
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
initial |
begin |
a_multiplier: assert((S > 1) & (S % 2 == 0))else $fatal; |
end |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
|
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/sim/tests/tb_riffa_register_file/tb_files.f
File deleted
/sim/tests/tb_riffa_register_file/files.f
File deleted
/sim/tests/tb_riffa_register_file/tb_top_pkg.sv
File deleted
/sim/tests/tb_riffa_register_file/vs_debug.svh
File deleted
/sim/tests/tb_riffa_register_file/sim.f
File deleted
/sim/tests/tb_riffa_register_file/tb_top.sv
File deleted
/sim/tests/tb_riffa_register_file/tb_riffa_register_file.sv
0,0 → 1,146
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module tb_top(); |
|
// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_100mhz; |
wire tb_clk = clk_100mhz; |
wire tb_rst; |
|
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); |
|
|
// -------------------------------------------------------------------- |
// |
wire clk = tb_clk; |
wire reset; |
|
sync_reset sync_reset_i(tb_clk, tb_rst, reset); |
|
|
// -------------------------------------------------------------------- |
// |
import tb_riffa_register_file_pkg::*; |
|
|
// -------------------------------------------------------------------- |
// |
riffa_chnl_if #(.N(N)) chnl_bus(.*); |
riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers |
|
|
// -------------------------------------------------------------------- |
// |
riffa_register_file #(.N(N), .B(B)) |
dut(.*); |
|
|
// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
|
// -------------------------------------------------------------------- |
// |
for(genvar j = 0; j < r_if.RC; j++) |
assign r_if.register_in[j] = r_if.register_out[j]; |
|
|
// -------------------------------------------------------------------- |
// |
tb_riffa_register_file_class #(.N(N)) a_h; |
|
initial |
a_h = new(chnl_bus); |
|
|
// -------------------------------------------------------------------- |
// |
int rx_count = 0; |
wire rx_en = chnl_bus.rx_data_valid & chnl_bus.rx_data_ren; |
|
always_ff @(posedge chnl_bus.rx_clk) |
if(chnl_bus.rx) |
begin |
if(rx_en) |
rx_count++; |
end |
else |
rx_count = 0; |
|
|
// -------------------------------------------------------------------- |
// |
int tx_count = 0; |
wire tx_en = chnl_bus.tx_data_valid & chnl_bus.tx_data_ren; |
|
always_ff @(posedge chnl_bus.tx_clk) |
if(chnl_bus.tx) |
begin |
if(tx_en) |
tx_count++; |
end |
else |
tx_count = 0; |
|
|
|
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
|
|
|
// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
|
initial |
begin |
|
test.run_the_test(); |
|
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
|
$display("^^^---------------------------------"); |
|
$stop(); |
|
end |
|
endmodule |
|
|
|
/sim/tests/tb_riffa_register_file/the_test.sv
0,0 → 1,92
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`timescale 1ps/1ps |
|
|
module the_test(input tb_clk, input tb_rst); |
|
// -------------------------------------------------------------------- |
// |
import tb_riffa_register_file_pkg::*; |
import riffa_agent_class_pkg::*; |
import riffa_bfm_class_pkg::*; |
|
|
// -------------------------------------------------------------------- |
// |
task run_the_test; |
|
// -------------------------------------------------------------------- |
// insert test below |
// -------------------------------------------------------------------- |
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench begun.\n", $time); |
$display("^^^---------------------------------"); |
// -------------------------------------------------------------------- |
|
// -------------------------------------------------------------------- |
tb_top.tb.timeout_stop(5us); |
|
// -------------------------------------------------------------------- |
wait(~tb_rst); |
|
// -------------------------------------------------------------------- |
#200ns; |
|
// -------------------------------------------------------------------- |
tb_top.a_h.queue_tx_random(RW*B, 0, 1); |
tb_top.a_h.wait_for_tx(); |
|
// -------------------------------------------------------------------- |
#200ns; |
|
// -------------------------------------------------------------------- |
tb_top.a_h.queue_rx(RW*B, 0, 1); |
#200ns; |
|
// -------------------------------------------------------------------- |
tb_top.a_h.tr_h = new(RW, 0, 1); |
tb_top.a_h.tr_h.constant(RW, 0, 1, 1); |
tb_top.a_h.queue_tx(tb_top.a_h.tr_h); |
tb_top.a_h.wait_for_tx(); |
|
// -------------------------------------------------------------------- |
#200ns; |
|
// -------------------------------------------------------------------- |
$display("^^^ %16.t | q.num() = %d", $time, tb_top.a_h.tx_q.num()); |
|
// -------------------------------------------------------------------- |
// insert test above |
// -------------------------------------------------------------------- |
|
endtask |
|
|
endmodule |
|
/sim/tests/tb_riffa_register_file/tb_riffa_register_file_pkg.sv
0,0 → 1,70
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
package tb_riffa_register_file_pkg; |
|
// -------------------------------------------------------------------- |
// |
import riffa_agent_class_pkg::*; |
|
|
// -------------------------------------------------------------------- |
// |
localparam N = 16; // width of the bus in bytes |
localparam RW = (N/4); // width of the bus in 32 bit words |
localparam B = 5; // number of register banks |
|
|
// -------------------------------------------------------------------- |
// |
class tb_riffa_register_file_class #(N) |
extends riffa_agent_class #(.N(N)); |
|
|
//-------------------------------------------------------------------- |
// |
function new(virtual riffa_chnl_if #(.N(N)) chnl_bus); |
|
super.new(chnl_bus); |
|
endfunction: new |
|
|
// -------------------------------------------------------------------- |
// |
endclass: tb_riffa_register_file_class |
|
|
// -------------------------------------------------------------------- |
// |
endpackage: tb_riffa_register_file_pkg |
|
|
|
|
|
/sim/tests/tb_riffa_register_file/init_test.do
7,6 → 7,7
# setup environment |
do ../../../../scripts/sim_env.do |
set env(SIM_TARGET) fpga |
set env(SIM_TB) tb_riffa_register_file |
|
radix -hexadecimal |
|
18,8 → 19,18
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib |
sim_compile_lib $env(LIB_BASE_DIR) sim |
|
vlog -f ./tb_files.f |
vlog -f ./files.f |
|
# compile simulation files |
vlog -f ./$env(SIM_TB).f |
|
# simulation $root |
vlog ./$env(SIM_TB)_pkg.sv |
vlog ./$env(SIM_TB).sv |
|
# compile test last |
vlog ./the_test.sv |
|
# run the sim |
sim_run_test |
|
|
/sim/tests/tb_riffa_register_file/sim.do
3,8 → 3,9
|
quit -sim |
|
# vsim -suppress 12110 -novopt work.tb_top |
vsim -f ./sim.f work.tb_top |
vsim -novopt work.tb_top |
|
# log all signals |
log /* -r |
log -r * |
|
|
/sim/tests/tb_riffa_register_file/tb_riffa_register_file.f
0,0 → 1,14
# |
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${PROJECT_DIR}/sim/src/riffa_bfm_class_pkg.sv |
${PROJECT_DIR}/sim/src/riffa_agent_class_pkg.sv |
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${PROJECT_DIR}/src/RIFFA/riffa_chnl_if.sv |
${PROJECT_DIR}/src/RIFFA/riffa_register_if.sv |
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${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx_fsm.sv |
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx.sv |
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx_fsm.sv |
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx.sv |
${PROJECT_DIR}/src/RIFFA/riffa_register_file.sv |
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/sim/tests/tb_riffa_register_file/wip.do
1,5 → 1,13
# |
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vlog -f ./tb_files.f |
vlog -f ./files.f |
# compile simulation files |
vlog -f ./$env(SIM_TB).f |
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# simulation $root |
vlog ./$env(SIM_TB)_pkg.sv |
vlog ./$env(SIM_TB).sv |
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# compile test last |
vlog ./the_test.sv |
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/sim/src/RIFFA/s_riffa_rp_tx_api.svh
File deleted
/sim/src/RIFFA/riffa_rp_tx_driver.svh
File deleted
/sim/src/RIFFA/riffa_env.svh
File deleted
/sim/src/RIFFA/riffa_pkg.sv
File deleted
/sim/src/RIFFA/riffa_agent.svh
File deleted
/sim/src/RIFFA/riffa_config.svh
File deleted
/sim/src/RIFFA/s_riffa_rp_rx_api.svh
File deleted
/sim/src/RIFFA/riffa_rp_rx_driver.svh
File deleted
/sim/src/RIFFA/riffa_sequence_item.svh
File deleted
/sim/src/tb_riffa_debug/vs_top_base.svh
File deleted
/sim/src/tb_riffa_debug/t_debug.svh
File deleted
/sim/src/tb_riffa_debug/tb_env.svh
File deleted
/sim/src/tb_riffa_debug/t_top_base.svh
File deleted