URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
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- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/axi4_lib/src
- from Rev 31 to Rev 29
- ↔ Reverse comparison
Rev 31 → Rev 29
/axi4_to_axis_basic_dma.sv
File deleted
/axi4_m_to_read_fifos.sv
File deleted
/axi4_s_to_read_fifos.sv
File deleted
/axi4_m_to_write_fifos.sv
File deleted
/axi4_s_to_write_fifos.sv
File deleted
/axi4_if.sv
38,273 → 38,51
input aclk |
); |
|
wire [(A-1):0] araddr; |
wire [1:0] arburst; |
wire [3:0] arcache; |
wire [(I-1):0] arid; |
wire [7:0] arlen; |
wire arlock; |
wire [2:0] arprot; |
wire [3:0] arqos; |
wire arready; |
wire [3:0] arregion; |
wire [2:0] arsize; |
wire arvalid; |
wire [(A-1):0] awaddr; |
wire [1:0] awburst; |
wire [3:0] awcache; |
wire [(I-1):0] awid; |
wire [7:0] awlen; |
wire awlock; |
wire [2:0] awprot; |
wire [3:0] awqos; |
wire awready; |
wire [3:0] awregion; |
wire [2:0] awsize; |
wire awvalid; |
wire [(I-1):0] bid; |
wire bready; |
wire [1:0] bresp; |
wire bvalid; |
wire [(8*N)-1:0] rdata; |
wire [(I-1):0] rid; |
wire rlast; |
wire rready; |
wire [1:0] rresp; |
wire rvalid; |
wire [(8*N)-1:0] wdata; |
wire [(I-1):0] wid; |
wire wlast; |
wire wready; |
wire [N-1:0] wstrb; |
wire wvalid; |
logic [(A-1):0] araddr; |
logic [1:0] arburst; |
logic [3:0] arcache; |
logic [(I-1):0] arid; |
logic [7:0] arlen; |
logic arlock; |
logic [2:0] arprot; |
logic [3:0] arqos; |
logic arready; |
logic [3:0] arregion; |
logic [2:0] arsize; |
logic arvalid; |
logic [(A-1):0] awaddr; |
logic [1:0] awburst; |
logic [3:0] awcache; |
logic [(I-1):0] awid; |
logic [7:0] awlen; |
logic awlock; |
logic [2:0] awprot; |
logic [3:0] awqos; |
logic awready; |
logic [3:0] awregion; |
logic [2:0] awsize; |
logic awvalid; |
logic [(I-1):0] bid; |
logic bready; |
logic [1:0] bresp; |
logic bvalid; |
logic [(8*N)-1:0] rdata; |
logic [(I-1):0] rid; |
logic rlast; |
logic rready; |
logic [1:0] rresp; |
logic rvalid; |
logic [(8*N)-1:0] wdata; |
logic [(I-1):0] wid; |
logic wlast; |
logic wready; |
logic [N-1:0] wstrb; |
logic wvalid; |
|
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
clocking cb_s @(posedge aclk); |
input arid; |
input araddr; |
input arburst; |
input arcache; |
input awid; |
input arlen; |
input arlock; |
input arprot; |
input arqos; |
output arready; |
input arregion; |
input arsize; |
input arvalid; |
input awaddr; |
input awburst; |
input awcache; |
input awlen; |
input awlock; |
input awprot; |
input awqos; |
output awready; |
input awregion; |
input awsize; |
input awvalid; |
input bready; |
output bid; |
output bresp; |
output bvalid; |
output rdata; |
output rid; |
output rlast; |
input rready; |
output rresp; |
output rvalid; |
input wdata; |
input wid; |
input wlast; |
output wready; |
input wstrb; |
input wvalid; |
input aresetn; |
input aclk; |
endclocking |
|
|
// -------------------------------------------------------------------- |
// |
default clocking cb_m @(posedge aclk); |
output arid; |
output araddr; |
output arburst; |
output arcache; |
output awid; |
output arlen; |
output arlock; |
output arprot; |
output arqos; |
input arready; |
output arregion; |
output arsize; |
output arvalid; |
output awaddr; |
output awburst; |
output awcache; |
output awlen; |
output awlock; |
output awprot; |
output awqos; |
input awready; |
output awregion; |
output awsize; |
output awvalid; |
output bready; |
input bid; |
input bresp; |
input bvalid; |
input rdata; |
input rid; |
input rlast; |
output rready; |
input rresp; |
input rvalid; |
output wdata; |
output wid; |
output wlast; |
input wready; |
output wstrb; |
output wvalid; |
input aresetn; |
input aclk; |
endclocking |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
`ifdef USE_MOD_PORTS |
// -------------------------------------------------------------------- |
// |
modport |
slave |
( |
// -------------------------------------------------------------------- |
// synthesis translate_off |
clocking cb_s, |
// synthesis translate_on |
// -------------------------------------------------------------------- |
input arid, |
input araddr, |
input arburst, |
input arcache, |
input awid, |
input arlen, |
input arlock, |
input arprot, |
input arqos, |
output arready, |
input arregion, |
input arsize, |
input arvalid, |
input awaddr, |
input awburst, |
input awcache, |
input awlen, |
input awlock, |
input awprot, |
input awqos, |
output awready, |
input awregion, |
input awsize, |
input awvalid, |
input bready, |
output bid, |
output bresp, |
output bvalid, |
output rdata, |
output rid, |
output rlast, |
input rready, |
output rresp, |
output rvalid, |
input wdata, |
input wid, |
input wlast, |
output wready, |
input wstrb, |
input wvalid, |
input aresetn, |
input aclk |
); |
|
|
// -------------------------------------------------------------------- |
// |
modport |
master |
( |
// -------------------------------------------------------------------- |
// synthesis translate_off |
clocking cb_m, |
// synthesis translate_on |
// -------------------------------------------------------------------- |
output arid, |
output araddr, |
output arburst, |
output arcache, |
output awid, |
output arlen, |
output arlock, |
output arprot, |
output arqos, |
input arready, |
output arregion, |
output arsize, |
output arvalid, |
output awaddr, |
output awburst, |
output awcache, |
output awlen, |
output awlock, |
output awprot, |
output awqos, |
input awready, |
output awregion, |
output awsize, |
output awvalid, |
output bready, |
input bid, |
input bresp, |
input bvalid, |
input rdata, |
input rid, |
input rlast, |
output rready, |
input rresp, |
input rvalid, |
output wdata, |
output wlast, |
input wready, |
output wstrb, |
output wvalid, |
input aresetn, |
input aclk |
); |
`endif |
|
|
// -------------------------------------------------------------------- |
// synthesis translate_off |
task |
zero_cycle_delay; |
|
##0; |
|
endtask: zero_cycle_delay |
// synthesis translate_on |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// |
|
endinterface |
|
|
/axi4_register_slice.sv
53,16 → 53,14
|
// -------------------------------------------------------------------- |
// |
axi4_s_to_read_fifos |
axi4_to_read_fifos |
#( |
.A(A), |
.N(N), |
.I(I), |
.R_D(2), |
.AR_D(2), |
.USE_ADVANCED_PROTOCOL(USE_ADVANCED_PROTOCOL) |
) |
axi4_s_to_read_fifos_i(.*); |
axi4_to_read_fifos_i(.*); |
|
|
// -------------------------------------------------------------------- |
120,17 → 118,14
|
// -------------------------------------------------------------------- |
// |
axi4_s_to_write_fifos |
axi4_to_write_fifos |
#( |
.A(A), |
.N(N), |
.I(I), |
.W_D(2), |
.B_D(2), |
.AW_D(2), |
.USE_ADVANCED_PROTOCOL(USE_ADVANCED_PROTOCOL) |
) |
axi4_s_to_write_fifos_i(.*); |
axi4_to_write_fifos_i(.*); |
|
|
// -------------------------------------------------------------------- |