URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/axi4_lite_lib
- from Rev 31 to Rev 29
- ↔ Reverse comparison
Rev 31 → Rev 29
/sim/libs/axi4_lib_verilog/axi4_base.f
1,8 → 1,8
# |
|
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_if.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_s_to_read_fifos.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_s_to_write_fifos.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_to_read_fifos.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_to_write_fifos.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/src/axi4_register_slice.sv |
|
|
/sim/libs/packages_verilog/axi4_bfm.f
5,7 → 5,7
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/BP065-BU-01000-r0p1-00rel0/axi4_checker.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/BP065-BU-01000-r0p1-00rel0/sva/Axi4PC_ace.sv |
|
${ROOT_DIR}/qaz_libs/tb_class/src/tb_bfm_pkg.sv |
${ROOT_DIR}/rvs_lib/tb_class/src/tb_bfm_pkg.sv |
|
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/axi4_bfm/axi4_transaction_pkg.sv |
${ROOT_DIR}/qaz_libs/axi4_lib/sim/src/axi4_bfm/axi4_master_bfm_if.sv |
/src/axi4_lite_register_file.sv
30,8 → 30,7
#( |
A = 32, // address bus width, must be 32 or greater for axi lite |
N = 8, // data bus width in bytes, must be 4 or 8 for axi lite |
I = 1, // ID width |
MW = 3 // mux select width |
I = 1 // ID width |
) |
( |
axi4_if axi4_s, |
42,9 → 41,8
|
// -------------------------------------------------------------------- |
// |
localparam MI = 2 ** MW; // mux inputs |
localparam LB = (N == 8) ? 3 : 2; |
localparam UB = LB + MW - 1; |
localparam UB = LB + r_if.MW - 1; |
|
|
// -------------------------------------------------------------------- |
60,17 → 58,17
axi4_if #(.A(A), .N(N), .I(I)) |
axi4_write_fifo(.*); |
|
axi4_s_to_write_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0)) |
axi4_s_to_write_fifos_i(.*); |
axi4_to_write_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0)) |
axi4_to_write_fifos_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
wire register_select [MI-1:0]; |
wire register_select [r_if.MI-1:0]; |
genvar j; |
|
generate |
for(j = 0; j < MI; j = j + 1) |
for(j = 0; j < r_if.MI; j = j + 1) |
begin: decoder_gen |
assign register_select[j] = (axi4_write_fifo.awaddr[UB:LB] == j) ? 1 : 0; |
|
94,13 → 92,13
axi4_if #(.A(A), .N(N), .I(I)) |
axi4_read_fifo(.*); |
|
axi4_s_to_read_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0)) |
axi4_s_to_read_fifos_i(.*); |
axi4_to_read_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0)) |
axi4_to_read_fifos_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
recursive_mux #(.A(MW), .W(N*8)) |
recursive_mux #(.A(r_if.MW), .W(N*8)) |
recursive_mux_i |
( |
.select(axi4_read_fifo.araddr[UB:LB]), |
/src/axi4_lite_register_if.sv
46,8 → 46,6
// synthesis translate_off |
initial |
a_data_bus_width: assert((N == 8) | (N == 4)) else $fatal; |
|
|
// synthesis translate_on |
// -------------------------------------------------------------------- |
|