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  • This comparison shows the changes necessary to convert path 
    /qaz_libs/trunk/axi4_stream_lib
    from Rev 38 to Rev 37
    ↔ Reverse comparison
  •

Rev 38 → Rev 37

/src/axis_interleave.sv File deleted
/src/axis_catenate.sv
47,7 → 47,7
wire select;
wire axis_eop;
 
defparam axis_eop_mux_i.U_IS_EOP = U_IS_EOP; // why are these needed for recursive modules?
defparam axis_eop_mux_i.U_IS_EOP = U_IS_EOP; // why are needed these for recursive modules?
defparam axis_eop_mux_i.MA = 1;
axis_eop_mux
// axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(1))
141,7 → 141,7
 
// --------------------------------------------------------------------
//
defparam axis_mux_i.N = N; // why are these needed for recursive modules?
defparam axis_mux_i.N = N; // why are needed these for recursive modules?
defparam axis_mux_i.I = I;
defparam axis_mux_i.D = D;
defparam axis_mux_i.U = U;
/src/axis_map_fifo.sv
35,13 → 35,15
USE_TSTRB = 0, // set to 1 to enable, 0 to disable
USE_TKEEP = 0, // set to 1 to enable, 0 to disable
// USE_XID = 0, // set to 1 to enable, 0 to disable
W
W = 0
)
(
axis_if axis_in,
axis_if axis_out,
output [W-1:0] wr_data,
input [W-1:0] rd_data
input [W-1:0] rd_data,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
/src/axis_mux.sv
45,7 → 45,7
 
// --------------------------------------------------------------------
//
defparam axis_mux_out.N = N; // why are these needed for recursive modules?
defparam axis_mux_out.N = N; // why are needed these for recursive modules?
defparam axis_mux_out.I = I;
defparam axis_mux_out.D = D;
defparam axis_mux_out.U = U;
67,7 → 67,7
 
// --------------------------------------------------------------------
//
defparam axis_register_slice_i.N = N; // why are these needed for recursive modules?
defparam axis_register_slice_i.N = N; // why are needed these for recursive modules?
defparam axis_register_slice_i.I = I;
defparam axis_register_slice_i.D = D;
defparam axis_register_slice_i.U = U;
/src/axis_alias.sv
28,10 → 28,8
module
axis_alias
#(
CONNECT_TREADY = 1,
CONNECT_TVALID = 1,
CONNECT_TLAST = 1,
CONNECT_TUSER = 1
CONNECT_TREADY = 1,
CONNECT_TVALID = 1
)
(
axis_if axis_in,
60,31 → 58,13
 
// --------------------------------------------------------------------
//
generate
if(CONNECT_TLAST == 1)
begin: tlast_gen
assign axis_out.tlast = axis_in.tlast;
end
endgenerate
 
 
// --------------------------------------------------------------------
//
generate
if(CONNECT_TUSER == 1)
begin: tuser_gen
assign axis_out.tuser = axis_in.tuser;
end
endgenerate
 
 
// --------------------------------------------------------------------
//
assign axis_out.tdata = axis_in.tdata;
assign axis_out.tstrb = axis_in.tstrb;
assign axis_out.tkeep = axis_in.tkeep;
assign axis_out.tlast = axis_in.tlast;
assign axis_out.tid = axis_in.tid;
assign axis_out.tdest = axis_in.tdest;
assign axis_out.tuser = axis_in.tuser;
 
 
// --------------------------------------------------------------------
/src/axis_register_slice.sv
57,7 → 57,7
wire [W-1:0] rd_data;
wire rd_en;
 
defparam tiny_sync_fifo_i.W=W; // why are these needed for recursive modules?
defparam tiny_sync_fifo_i.W=W; // why are needed these for recursive modules?
tiny_sync_fifo
// tiny_sync_fifo #(W)
tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);
65,24 → 65,78
 
// --------------------------------------------------------------------
//
defparam axis_map_fifo_i.N=N; // why are these needed for recursive modules?
defparam axis_map_fifo_i.I=I;
defparam axis_map_fifo_i.D=D;
defparam axis_map_fifo_i.U=U;
defparam axis_map_fifo_i.USE_TSTRB=USE_TSTRB;
defparam axis_map_fifo_i.USE_TKEEP=USE_TKEEP;
defparam axis_map_fifo_i.W=W;
axis_map_fifo
// #(
// .N(N),
// .I(I),
// .D(D),
// .U(U),
// .USE_TSTRB(USE_TSTRB),
// .USE_TKEEP(USE_TKEEP),
// .W(W)
// )
axis_map_fifo_i(.*);
generate
begin: assign_gen
if(USE_TSTRB & USE_TKEEP)
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tstrb,
axis_in.tkeep
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tstrb,
axis_out.tkeep
} = rd_data;
end
else if(USE_TSTRB)
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tstrb
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tstrb
} = rd_data;
end
else if(USE_TKEEP)
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tkeep
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tkeep
} = rd_data;
end
else
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser
} = rd_data;
end
end
endgenerate
 
 
// --------------------------------------------------------------------
/src/axis_switch.sv
82,7 → 82,7
 
// --------------------------------------------------------------------
//
defparam axis_register_slice_lo.N = N; // why are these needed for recursive modules?
defparam axis_register_slice_lo.N = N; // why are needed these for recursive modules?
defparam axis_register_slice_lo.I = I;
defparam axis_register_slice_lo.D = D;
defparam axis_register_slice_lo.U = U;
/src/axis_synchronizer.sv
1,6 → 1,6
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2016 Authors and OPENCORES.ORG ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
28,23 → 28,33
module
axis_synchronizer
#(
N, // data bus width in bytes
I = 1, // TID width
D = 1, // TDEST width
N = 8, // data bus width in bytes
I = 0, // TID width
D = 0, // TDEST width
U = 1, // TUSER width
USE_TSTRB = 0, // set to 1 to enable, 0 to disable
USE_TKEEP = 0, // set to 1 to enable, 0 to disable
FD
USE_TKEEP = 0 // set to 1 to enable, 0 to disable
)
(
axis_if axis_in,
axis_if axis_out,
input aclk_in,
input aresetn_in,
input aclk_out,
input aresetn_out
input wr_clk,
input wr_reset,
input aclk,
input aresetn
);
 
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_tid_unsuported: assert(I == 0) else $fatal;
a_tdest_unsuported: assert(D == 0) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
58,50 → 68,94
 
wire rd_empty;
wire [W-1:0] rd_data;
wire rd_en;
wire rd_en;
tiny_async_fifo #(.W(W))
tiny_async_fifo_i(.rd_clk(aclk), .rd_reset(~aresetn), .*);
 
defparam async_fifo_i.W=W; // why are these needed for recursive modules?
defparam async_fifo_i.D=FD;
async_fifo
// async_fifo #(.W(W), .D(FD))
async_fifo_i
(
.wr_clk(aclk_in),
.wr_reset(~aresetn_in),
.rd_clk(aclk_out),
.rd_reset(~aresetn_out),
.*
);
 
 
// --------------------------------------------------------------------
//
defparam axis_map_fifo_i.N=N; // why are these needed for recursive modules?
defparam axis_map_fifo_i.I=I;
defparam axis_map_fifo_i.D=D;
defparam axis_map_fifo_i.U=U;
defparam axis_map_fifo_i.USE_TSTRB=USE_TSTRB;
defparam axis_map_fifo_i.USE_TKEEP=USE_TKEEP;
defparam axis_map_fifo_i.W=W;
axis_map_fifo
// #(
// .N(N),
// .I(I),
// .D(D),
// .U(U),
// .USE_TSTRB(USE_TSTRB),
// .USE_TKEEP(USE_TKEEP),
// .W(W)
// )
axis_map_fifo_i(.*);
generate
begin: assign_gen
if(USE_TSTRB & USE_TKEEP)
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tstrb,
axis_in.tkeep
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tstrb,
axis_out.tkeep
} = rd_data;
end
else if(USE_TSTRB)
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tstrb
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tstrb
} = rd_data;
end
else if(USE_TKEEP)
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser,
axis_in.tkeep
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser,
axis_out.tkeep
} = rd_data;
end
else
begin
assign wr_data =
{
axis_in.tdata,
axis_in.tlast,
axis_in.tuser
};
assign
{
axis_out.tdata,
axis_out.tlast,
axis_out.tuser
} = rd_data;
end
end
endgenerate
 
 
// --------------------------------------------------------------------
//
assign axis_in.tready = ~wr_full;
assign wr_en = axis_in.tvalid & ~wr_full;
assign wr_en = axis_in.tvalid & axis_in.tready;
assign axis_out.tvalid = ~rd_empty;
assign rd_en = axis_out.tready & ~rd_empty;
assign rd_en = axis_out.tvalid & axis_out.tready;
 
 
// --------------------------------------------------------------------

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