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/qaz_libs/trunk/axi4_stream_lib
- from Rev 38 to Rev 40
- ↔ Reverse comparison
Rev 38 → Rev 40
/sim/tests/tb_axis_gear_box/axis_pkg.sv
0,0 → 1,392
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// -------------------------------------------------------------------- |
// |
package axis_pkg; |
|
// -------------------------------------------------------------------- |
// |
import uvm_pkg::*; |
`include "uvm_macros.svh" |
import axis_pkg::*; |
|
// -------------------------------------------------------------------- |
// |
typedef struct packed |
{ |
int unsigned N; // data bus width in bytes |
int unsigned I; // TID width |
int unsigned D; // TDEST width |
int unsigned U; // TUSER width |
bit USE_TSTRB; // set to 1 to enable, 0 to disable |
bit USE_TKEEP; // set to 1 to enable, 0 to disable |
bit USE_ROUTING; // set to 1 to enable, 0 to disable |
} axis_config_t; |
|
// -------------------------------------------------------------------- |
// |
class axis_sequence_item #(axis_config_t cfg) |
extends uvm_sequence_item; |
`uvm_object_param_utils(axis_sequence_item #(cfg)) |
|
// -------------------------------------------------------------------- |
// |
localparam N = cfg.N; |
localparam I = cfg.I; |
localparam D = cfg.D; |
localparam U = cfg.U; |
localparam USE_TSTRB = cfg.USE_TSTRB; |
localparam USE_TKEEP = cfg.USE_TKEEP; |
localparam USE_ROUTING = cfg.USE_ROUTING; |
|
// -------------------------------------------------------------------- |
// |
rand logic [(8*N)-1:0] tdata; |
rand logic [N-1:0] tstrb; |
rand logic [N-1:0] tkeep; |
rand logic tlast; |
rand logic [I-1:0] tid; |
rand logic [D-1:0] tdest; |
rand logic [U-1:0] tuser; |
|
// -------------------------------------------------------------------- |
// |
function new(string name = ""); |
super.new(name); |
endfunction : new |
|
// -------------------------------------------------------------------- |
// |
function bit do_compare(uvm_object rhs, uvm_comparer comparer); |
axis_sequence_item #(cfg) tested; |
bit same; |
|
if (rhs==null) |
`uvm_fatal(get_type_name(), "| %m | comparison to a null pointer"); |
|
if (!$cast(tested,rhs)) |
same = 0; |
else |
same = super.do_compare(rhs, comparer) |
& (tested.tdata == tdata) |
& (USE_TSTRB ? (tested.tstrb == tstrb) : 1) |
& (USE_TKEEP ? (tested.tkeep == tkeep) : 1) |
& (tested.tlast == tlast) |
& (USE_ROUTING ? (tested.tid == tid) : 1) |
& (USE_ROUTING ? (tested.tdest == tdest) : 1) |
& (tested.tuser == tuser); |
return same; |
endfunction : do_compare |
|
// -------------------------------------------------------------------- |
// |
function void do_copy(uvm_object rhs); |
axis_sequence_item #(cfg) item; |
assert(rhs != null) else |
`uvm_fatal(get_type_name(), "| %m | copy null transaction"); |
super.do_copy(rhs); |
assert($cast(item,rhs)) else |
`uvm_fatal(get_type_name(), "| %m | failed cast"); |
tdata = item.tdata; |
tstrb = item.tstrb; |
tkeep = item.tkeep; |
tlast = item.tlast; |
tid = item.tid; |
tdest = item.tdest; |
tuser = item.tuser; |
endfunction : do_copy |
|
// -------------------------------------------------------------------- |
// |
function string convert2string(); |
string s0, s1; |
s0 = $sformatf("| tdata: %h\n" ,tdata); |
s1 = $sformatf("| tlast: %1h | tuser: %h" , tlast, tuser); |
return {s1, s0}; |
endfunction : convert2string |
|
// -------------------------------------------------------------------- |
// |
endclass : axis_sequence_item |
|
// -------------------------------------------------------------------- |
// |
class axis_driver #(parameter axis_config_t cfg) |
extends uvm_driver #(axis_sequence_item #(cfg)); |
`uvm_component_param_utils(axis_driver#(cfg)) |
|
// -------------------------------------------------------------------- |
// |
localparam N = cfg.N; |
localparam I = cfg.I; |
localparam D = cfg.D; |
localparam U = cfg.U; |
localparam USE_TSTRB = cfg.USE_TSTRB; |
localparam USE_TKEEP = cfg.USE_TKEEP; |
localparam USE_ROUTING = cfg.USE_ROUTING; |
|
// -------------------------------------------------------------------- |
// |
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus; |
|
//-------------------------------------------------------------------- |
// |
function void set_default; |
axis_bus.cb_m.tvalid <= 0; |
axis_bus.cb_m.tdata <= 'bx; |
axis_bus.cb_m.tstrb <= 'bx; |
axis_bus.cb_m.tkeep <= 'bx; |
axis_bus.cb_m.tlast <= 'bx; |
axis_bus.cb_m.tid <= 'bx; |
axis_bus.cb_m.tdest <= 'bx; |
axis_bus.cb_m.tuser <= 'bx; |
endfunction: set_default |
|
|
//-------------------------------------------------------------------- |
// |
virtual task run_phase(uvm_phase phase); |
axis_sequence_item #(cfg) item; |
super.run_phase(phase); |
|
$display("^^^ %16.t | %m | ", $time); |
|
set_default(); |
|
@(axis_bus.cb_m) forever |
begin |
// seq_item_port.try_next_item(item); |
seq_item_port.get_next_item(item); |
|
axis_bus.cb_m.tvalid <= 1; |
axis_bus.cb_m.tdata <= item.tdata; |
axis_bus.cb_m.tstrb <= 0; |
axis_bus.cb_m.tkeep <= 0; |
axis_bus.cb_m.tlast <= item.tlast; |
axis_bus.cb_m.tid <= 0; |
axis_bus.cb_m.tdest <= 0; |
axis_bus.cb_m.tuser <= item.tuser; |
|
@(axis_bus.cb_m); |
wait(axis_bus.cb_m.tready); |
// @(axis_bus.cb_m iff axis_bus.cb_m.tready); |
|
set_default(); |
|
seq_item_port.item_done(); |
end |
endtask : run_phase |
|
|
//-------------------------------------------------------------------- |
// |
function new(string name, uvm_component parent); |
super.new(name, parent); |
endfunction |
|
// -------------------------------------------------------------------- |
// |
endclass : axis_driver |
|
|
// -------------------------------------------------------------------- |
// |
class axis_sequencer #(axis_config_t cfg) |
extends uvm_sequencer #(axis_sequence_item #(cfg)); |
`uvm_component_param_utils(axis_sequencer #(cfg)) |
|
// -------------------------------------------------------------------- |
// |
function new(string name, uvm_component parent); |
super.new(name, parent); |
$display("^^^ %16.t | %m | ", $time); |
endfunction |
|
// -------------------------------------------------------------------- |
// |
endclass : axis_sequencer |
|
// -------------------------------------------------------------------- |
// |
class axis_counting_sequence #(axis_config_t cfg) |
extends uvm_sequence #(axis_sequence_item #(cfg)); |
`uvm_object_param_utils(axis_counting_sequence #(cfg)) |
|
// -------------------------------------------------------------------- |
// |
localparam LENGTH = 16; |
|
// -------------------------------------------------------------------- |
// |
virtual task body(); |
axis_sequence_item #(cfg) item; |
|
$display("^^^ %16.t | %m | ", $time); |
|
for(int i = 0; i < LENGTH; i++) |
begin |
item = axis_sequence_item #(cfg)::type_id::create("axis_sequence_item"); |
|
item.tdata = i; |
item.tlast = (i == LENGTH - 1); |
|
start_item (item); |
finish_item(item); |
end |
endtask |
|
// -------------------------------------------------------------------- |
// |
function new(string name = "axis_counting_sequence"); |
super.new(name); |
endfunction |
|
// -------------------------------------------------------------------- |
// |
endclass : axis_counting_sequence |
|
// -------------------------------------------------------------------- |
// |
class axis_agent #(axis_config_t cfg) |
extends uvm_agent; |
`uvm_component_param_utils(axis_agent #(cfg)) |
|
// -------------------------------------------------------------------- |
// |
localparam N = cfg.N; |
localparam I = cfg.I; |
localparam D = cfg.D; |
localparam U = cfg.U; |
localparam USE_TSTRB = cfg.USE_TSTRB; |
localparam USE_TKEEP = cfg.USE_TKEEP; |
localparam USE_ROUTING = cfg.USE_ROUTING; |
|
// -------------------------------------------------------------------- |
// |
// virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus; |
virtual tb_dut_if #(.IN_N(N), .OUT_N(N), .I(I), .D(D), .U(U)) dut_bus; |
|
axis_driver #(cfg) driver; |
// my_monitor #(cfg) monitor; |
axis_sequencer #(cfg) sequencer; |
|
// -------------------------------------------------------------------- |
// |
virtual function void build_phase(uvm_phase phase); |
super.build_phase(phase); |
|
$display("^^^ %16.t | %m | ", $time); |
|
if (!uvm_config_db #(virtual tb_dut_if #(.IN_N(N), .OUT_N(N), .I(I), .D(D), .U(U)))::get(this, "", "dut_bus", dut_bus)) |
`uvm_fatal(get_name(), "Could not get the virtual interface handle from the config database.") |
|
driver = axis_driver #(cfg)::type_id::create("driver", this); |
// monitor = my_monitor #(cfg)::type_id::create("monitor" , this); |
sequencer = axis_sequencer #(cfg)::type_id::create("sequencer", this); |
endfunction |
|
// -------------------------------------------------------------------- |
// |
virtual function void connect_phase(uvm_phase phase); |
super.connect_phase(phase); |
|
$display("^^^ %16.t | %m | ", $time); |
|
driver.axis_bus = dut_bus.axis_in; |
// monitor.vif = vif; |
|
driver.seq_item_port.connect(sequencer.seq_item_export); |
endfunction |
|
// -------------------------------------------------------------------- |
// |
function new(string name, uvm_component parent); |
super.new(name, parent); |
endfunction |
|
// -------------------------------------------------------------------- |
// |
endclass : axis_agent |
|
// -------------------------------------------------------------------- |
// |
|
class my_test extends uvm_test; |
`uvm_component_utils(my_test) |
|
localparam axis_config_t cfg_a = '{ 1, 1, 1, 1, 0, 0, 0}; |
|
axis_agent #(cfg_a) agent_h; |
// my_agent#(cfg_b) agent_b; |
|
function new(string name = "my_test", uvm_component parent); |
super.new(name, parent); |
endfunction |
|
virtual function void build_phase(uvm_phase phase); |
super.build_phase(phase); |
|
$display("^^^ %16.t | %m | ", $time); |
|
agent_h = axis_agent #(cfg_a)::type_id::create("agent_h", this); |
// agent_b = my_agent#(cfg_b)::type_id::create("agent_b", this); |
endfunction |
|
virtual function void end_of_elaboration_phase(uvm_phase phase); |
uvm_phase run_phase = uvm_run_phase::get(); |
run_phase.phase_done.set_drain_time(this, 300ns); |
endfunction |
|
virtual task run_phase(uvm_phase phase); |
axis_counting_sequence #(cfg_a) seq_a; |
super.run_phase(phase); |
|
$display("^^^ %16.t | %m | ", $time); |
|
phase.raise_objection(this); |
|
// fork |
// repeat (3) begin |
seq_a = axis_counting_sequence #(cfg_a)::type_id::create("seq_a"); |
seq_a.start(agent_h.sequencer); |
// end |
|
// repeat (3) begin |
// my_sequence#(cfg_b) seq_b = my_sequence#(cfg_b)::type_id::create("seq_b"); |
// seq_b.start(agent_b.sequencer); |
// end |
// join |
|
phase.drop_objection(this); |
endtask |
endclass |
|
|
// -------------------------------------------------------------------- |
// |
endpackage: axis_pkg |
/sim/tests/tb_axis_gear_box/init_test.do
0,0 → 1,40
# ------------------------------------ |
# |
# ------------------------------------ |
|
global env |
|
# setup environment |
do ../../../../scripts/sim_env.do |
set env(SIM_TARGET) fpga |
set env(SIM_TB) tb_axis_gear_box |
|
radix -hexadecimal |
|
make_lib work 1 |
|
sim_compile_lib $env(LIB_BASE_DIR) tb_packages |
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages |
sim_compile_lib $env(LIB_BASE_DIR) axi4_lib |
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib |
sim_compile_lib $env(LIB_BASE_DIR) sim |
|
# AXI4 streaming package |
vlog ./axis_pkg.sv |
|
vlog ./$env(SIM_TB)_pkg.sv |
vlog ./tests_pkg.sv |
|
# simulation $root |
vlog ./$env(SIM_TB).sv |
|
# compile simulation files |
vlog -f ./$env(SIM_TB).f |
|
# # compile test last |
# vlog ./the_test.sv |
|
# run the sim |
sim_run_test |
|
|
/sim/tests/tb_axis_gear_box/sim.do
0,0 → 1,11
# |
# |
|
quit -sim |
|
vsim -novopt work.tb_top |
# vsim -f ./sim.f work.tb_top |
|
# # log all signals |
# log -r * |
|
/sim/tests/tb_axis_gear_box/tb_axis_gear_box.f
0,0 → 1,6
# |
|
${PROJECT_DIR}/src/axis_gear_box.sv |
|
./axis_pkg.sv |
|
/sim/tests/tb_axis_gear_box/tb_axis_gear_box.sv
0,0 → 1,85
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// ---------------------------------------------------------------------------- |
|
import tb_axis_gear_box_pkg::*; |
import tests_pkg::*; |
import uvm_pkg::*; |
`include "uvm_macros.svh" |
|
module tb_top(); |
|
// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_100mhz; |
wire tb_clk = clk_100mhz; |
wire tb_rst; |
|
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); |
|
// -------------------------------------------------------------------- |
// |
wire tb_rst_s; |
wire aclk = tb_clk; |
wire aresetn = ~tb_rst_s; |
wire clk = tb_clk; |
wire reset = tb_rst_s; |
|
sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); |
|
// -------------------------------------------------------------------- |
// |
import tb_axis_gear_box_pkg::*; |
|
// -------------------------------------------------------------------- |
// |
tb_dut_if #(.IN_N(IN_N), .OUT_N(OUT_N), .I(I), .D(D), .U(U)) dut_bus(.*); |
|
// -------------------------------------------------------------------- |
// |
axis_gear_box |
dut |
( |
.axis_in(dut_bus.axis_in), |
.axis_out(dut_bus.axis_out), |
.aclk(dut_bus.aclk), |
.aresetn(dut_bus.aresetn) |
); |
|
// -------------------------------------------------------------------- |
// |
initial |
begin |
uvm_config_db #(virtual tb_dut_if)::set(null, "*", "dut_bus", dut_bus); |
// uvm_top.finish_on_completion = 0; |
// run_test("t_debug"); |
run_test("my_test"); |
end |
|
// -------------------------------------------------------------------- |
// |
endmodule |
/sim/tests/tb_axis_gear_box/tb_axis_gear_box_pkg.sv
0,0 → 1,125
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
interface |
tb_dut_if |
#( |
IN_N = 1, // data bus width in bytes. axis_in. |
OUT_N = 1, // data bus width in bytes. axis_out. |
I = 1, // TID width |
D = 1, // TDEST width |
U = 1 // TUSER width |
) |
( |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// |
// wire aclk; |
// wire aresetn; |
axis_if #(.N(IN_N), .I(I), .D(D), .U(U)) axis_in(.*); |
axis_if #(.N(OUT_N), .I(I), .D(D), .U(U)) axis_out(.*); |
|
// -------------------------------------------------------------------- |
// |
endinterface: tb_dut_if |
|
// -------------------------------------------------------------------- |
// |
package tb_axis_gear_box_pkg; |
|
// -------------------------------------------------------------------- |
// |
import uvm_pkg::*; |
`include "uvm_macros.svh" |
import axis_pkg::*; |
|
// -------------------------------------------------------------------- |
// |
localparam IN_N = 1; // data bus width in bytes. axis_in. |
localparam OUT_N = 1; // data bus width in bytes. axis_out. |
localparam I = 1; // TID width |
localparam D = 1; // TDEST width |
localparam U = 1; // TUSER width |
|
// -------------------------------------------------------------------- |
// |
class tb_env extends uvm_env; |
`uvm_component_utils(tb_env); |
|
// sequencer sequencer_h; |
// coverage coverage_h; |
// scoreboard scoreboard_h; |
// driver driver_h; |
// command_monitor command_monitor_h; |
// result_monitor result_monitor_h; |
|
// -------------------------------------------------------------------- |
// |
function new (string name, uvm_component parent); |
super.new(name,parent); |
endfunction : new |
|
// -------------------------------------------------------------------- |
// |
function void build_phase(uvm_phase phase); |
// // stimulus |
// sequencer_h = new("sequencer_h",this); |
// driver_h = driver::type_id::create("driver_h",this); |
// // monitors |
// command_monitor_h = command_monitor::type_id::create("command_monitor_h",this); |
// result_monitor_h = result_monitor::type_id::create("result_monitor",this); |
// // analysis |
// coverage_h = coverage::type_id::create ("coverage_h",this); |
// scoreboard_h = scoreboard::type_id::create("scoreboard",this); |
endfunction : build_phase |
|
// -------------------------------------------------------------------- |
// |
function void connect_phase(uvm_phase phase); |
|
// driver_h.seq_item_port.connect(sequencer_h.seq_item_export); |
|
// command_monitor_h.ap.connect(coverage_h.analysis_export); |
// command_monitor_h.ap.connect(scoreboard_h.cmd_f.analysis_export); |
// result_monitor_h.ap.connect(scoreboard_h.analysis_export); |
endfunction : connect_phase |
|
// -------------------------------------------------------------------- |
// |
endclass : tb_env |
|
// -------------------------------------------------------------------- |
// |
endpackage: tb_axis_gear_box_pkg |
|
|
|
|
|
/sim/tests/tb_axis_gear_box/tests_pkg.sv
0,0 → 1,105
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// -------------------------------------------------------------------- |
// |
package tests_pkg; |
|
// -------------------------------------------------------------------- |
// |
import uvm_pkg::*; |
`include "uvm_macros.svh" |
|
// -------------------------------------------------------------------- |
// |
virtual class test_base extends uvm_test; |
`uvm_component_utils(test_base); |
// tb_env env_h; |
|
// -------------------------------------------------------------------- |
// |
function void build_phase(uvm_phase phase); |
$display("^^^ %16.t | %m | ", $time); |
// env_h = tb_env::type_id::create("env_h",this); |
endfunction : build_phase |
|
// -------------------------------------------------------------------- |
// |
function void end_of_elaboration_phase(uvm_phase phase); |
$display("^^^ %16.t | %m | ", $time); |
// sequencer_h = env_h.sequencer_h; |
endfunction : end_of_elaboration_phase |
|
// -------------------------------------------------------------------- |
// |
function new (string name, uvm_component parent); |
super.new(name,parent); |
$display("^^^ %16.t | %m | ", $time); |
endfunction : new |
|
// -------------------------------------------------------------------- |
// |
endclass : test_base |
|
// -------------------------------------------------------------------- |
// |
class t_debug extends test_base; |
`uvm_component_utils(t_debug); |
|
// -------------------------------------------------------------------- |
// |
task run_phase(uvm_phase phase); |
$display("^^^ %16.t | %m | ", $time); |
// fibonacci_sequence fibonacci; |
// fibonacci = new("fibonacci"); |
|
// phase.raise_objection(this); |
// fibonacci.start(sequencer_h); |
// phase.drop_objection(this); |
endtask : run_phase |
|
// // -------------------------------------------------------------------- |
// // |
// task final_phase(uvm_phase phase); |
// super.final_phase(phase); |
// $display("^^^ %16.t | %m | ", $time); |
// $stop; |
// endtask : final_phase |
|
// -------------------------------------------------------------------- |
// |
function new(string name, uvm_component parent); |
super.new(name,parent); |
endfunction : new |
|
// -------------------------------------------------------------------- |
// |
endclass : t_debug |
|
// -------------------------------------------------------------------- |
// |
endpackage: tests_pkg |
/sim/tests/tb_axis_gear_box/wip.do
0,0 → 1,11
# |
|
# compile simulation files |
vlog -f ./$env(SIM_TB).f |
|
vlog ./$env(SIM_TB)_pkg.sv |
vlog ./tests_pkg.sv |
|
# simulation $root |
vlog ./$env(SIM_TB).sv |
|
/src/axis_gear_box.sv
0,0 → 1,57
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2017 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
axis_gear_box |
#( |
IN_N = 1, // data bus width in bytes. axis_in. |
IN_I = 1, // TID width |
IN_D = 1, // TDEST width |
IN_U = 1, // TUSER width |
USE_TSTRB = 0, // set to 1 to enable, 0 to disable |
USE_TKEEP = 0, // set to 1 to enable, 0 to disable |
ANTECEDENT = 7, // ANTECEDENT:CONSEQUENT ratio |
CONSEQUENT = 8 |
) |
( |
axis_if axis_in, |
axis_if axis_out, |
input aclk, |
input aresetn |
); |
|
// -------------------------------------------------------------------- |
// |
assign axis_in.tready = 1; |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
|