OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /qaz_libs
    from Rev 39 to Rev 38
    Reverse comparison

Rev 39 → Rev 38

/trunk/PCIe/sim/src/riffa_agent_class_pkg.sv
40,6 → 40,7
riffa_transaction_class #(N) tr_h;
rp_tx_bfm_class #(N) tx_h;
rp_rx_bfm_class #(N) rx_h;
// mailbox #(riffa_transaction_class #(N)) tx_q, rx_q;
mailbox #(riffa_transaction_class #(N)) tx_q;
 
 
71,15 → 72,6
 
// --------------------------------------------------------------------
//
task queue_tx_hex(string str, int off, bit last);
tr_h = new(1, off, last);
tr_h.hex(str, off, last);
queue_tx(tr_h);
endtask: queue_tx_hex
 
 
// --------------------------------------------------------------------
//
task queue_tx_random(int len, int off, bit last);
tr_h = new(len, off, last);
tr_h.random(len, off, last);
92,6 → 84,7
task queue_rx(int len, int off, bit last);
tr_h = new(len, off, last);
rx_h.put(tr_h);
// rx_q.put(tr_h);
endtask: queue_rx
 
 
115,6 → 108,7
tx_h = new(chnl_bus);
rx_h = new(chnl_bus);
this.tx_q = new;
// this.rx_q = new;
endfunction: new
 
 
/trunk/PCIe/sim/src/riffa_bfm_class_pkg.sv
46,10 → 46,8
//--------------------------------------------------------------------
//
function int get_data_size(int len);
int words = ((len * 4) % N == 0) ? ((len * 4) / N) : ((len * 4) / N) + 1;
// $display("^^^ %16.t | N = %d", $time, N);
// $display("^^^ %16.t | len = %d", $time, len);
// $display("^^^ %16.t | mod = %d", $time, (len * 4) % N);
// int words = $ceil(len/(N/4)); // need to fix
int words = len/(N/4);
// $display("^^^ %16.t | words = %d", $time, words);
return(words);
endfunction: get_data_size
81,31 → 79,6
 
//--------------------------------------------------------------------
//
function void hex(string str, int off, bit last);
string rev_str;
string char;
int w, c;
this.len = (str.len() % (2 * 4)) == 0
? (str.len() / (2 * 4))
: (str.len() / (2 * 4)) + 1;
this.data = new[get_data_size(this.len)];
this.off = off;
this.last = last;
rev_str = {<<8{str}}; // reverse string
for(w = 0; w < rev_str.len(); w += (N * 2))
for(c = 0; c < (N * 2); c++)
begin
char = string'(rev_str.getc(w + c));
if(char == "")
this.data[w / (N * 2)][(c * 4) +: 4] = 0;
else
this.data[w / (N * 2)][(c * 4) +: 4] = char.atohex();
end
endfunction: hex
 
 
//--------------------------------------------------------------------
//
function void random(int len, int off, bit last);
this.data = new[get_data_size(len)];
assert(this.randomize() with
279,16 → 252,20
chnl_bus.cb_rp_rx.tx_data_ren <= 1;
 
fork
@(chnl_bus.cb_rp_rx)
@(chnl_bus.cb_rp_tx)
chnl_bus.cb_rp_rx.tx_ack <= 0;
join_none
 
// foreach(tr_h.data[i])
// @(chnl_bus.cb_rp_tx)
// if(~chnl_bus.cb_rp_rx.tx)
// break;
// else if(chnl_bus.cb_rp_rx.tx_data_valid)
// tr_h.data[i] <= chnl_bus.cb_rp_rx.tx_data;
 
foreach(tr_h.data[i])
begin
@(chnl_bus.cb_rp_rx iff chnl_bus.cb_rp_rx.tx_data_valid)
@(chnl_bus.cb_rp_tx iff chnl_bus.cb_rp_rx.tx_data_valid)
tr_h.data[i] <= chnl_bus.cb_rp_rx.tx_data;
// $display("^^^ %16.t | %d | %h", $time, i, chnl_bus.cb_rp_rx.tx_data);
end
 
rx_q.put(tr_h);
set_default();
/trunk/PCIe/src/RIFFA/riffa_axis_test_pattern.sv
34,7 → 34,7
WPB = N / W // number of words per beat
)
(
riffa_chnl_if chnl_bus,
riffa_chnl_if chnl_in,
input [31:0] tx_len,
input clk,
input reset
77,20 → 77,20
 
// --------------------------------------------------------------------
//
assign axis_out.tready = chnl_bus.tx_data_ren & acked;
assign axis_out.tready = chnl_in.tx_data_ren & acked;
 
 
// --------------------------------------------------------------------
//
assign chnl_bus.rx_clk = clk;
assign chnl_bus.tx_clk = clk;
assign chnl_bus.rx_reset = reset;
assign chnl_bus.tx_reset = reset;
assign chnl_bus.tx_last = tx_last;
assign chnl_bus.tx_len = tx_len;
assign chnl_bus.tx_off = tx_off;
assign chnl_bus.tx_data_valid = axis_out.tvalid & acked;
assign chnl_bus.tx_data = axis_out.tdata;
assign chnl_in.rx_clk = clk;
assign chnl_in.tx_clk = clk;
assign chnl_in.rx_reset = reset;
assign chnl_in.tx_reset = reset;
assign chnl_in.tx_last = tx_last;
assign chnl_in.tx_len = tx_len;
assign chnl_in.tx_off = tx_off;
assign chnl_in.tx_data_valid = axis_out.tvalid & acked;
assign chnl_in.tx_data = axis_out.tdata;
 
// --------------------------------------------------------------------
//
/trunk/PCIe/src/RIFFA/riffa_register_file.sv
32,7 → 32,7
B // number of register banks
)
(
riffa_chnl_if chnl_bus,
riffa_chnl_if chnl_in,
riffa_register_if r_if,
input clk, // must be same clock domain as rx_clk & tx_clk
input reset // must be same clock domain as rx_clk & tx_clk
69,7 → 69,7
wire rd_en;
 
riffa_chn_rx #(.N(N))
riffa_chn_rx_i(.chnl_bus(chnl_bus), .*);
riffa_chn_rx_i(.chnl_bus(chnl_in), .*);
 
 
// --------------------------------------------------------------------
97,7 → 97,7
 
// --------------------------------------------------------------------
//
// assign chnl_bus.rx_data_ren = rx_data_ren;
// assign chnl_in.rx_data_ren = rx_data_ren;
assign rd_en = ~rd_empty;
 
 
104,13 → 104,13
// --------------------------------------------------------------------
//
// write to register[0][0] to enable reading
wire tx_ready = r_if.wr_en[0] & rd_data[0];
wire tx_ready = r_if.wr_en[0] & rd_data[0];
wire tx_last = 1;
wire acked;
wire [31:0] tx_len = RC;
wire [30:0] tx_off = 0;
wire [30:0] tx_index;
wire tx_done = (tx_index >= chnl_bus.tx_len - RW);
wire tx_done = (tx_index >= chnl_in.tx_len - RW);
 
riffa_chn_tx #(.N(N))
riffa_chn_tx_i(.*);
137,7 → 137,7
recursive_mux_i
(
.select(tx_index[$clog2(B) + $clog2(RW) - 1:$clog2(RW)]),
.data_out(chnl_bus.tx_data),
.data_out(chnl_in.tx_data),
.*
);
 
144,14 → 144,14
 
// --------------------------------------------------------------------
//
assign chnl_bus.rx_clk = clk;
assign chnl_bus.tx_clk = clk;
assign chnl_bus.rx_reset = reset;
assign chnl_bus.tx_reset = reset;
assign chnl_bus.tx_last = 1;
assign chnl_bus.tx_len = RC;
assign chnl_bus.tx_off = 0;
assign chnl_bus.tx_data_valid = acked;
assign chnl_in.rx_clk = clk;
assign chnl_in.tx_clk = clk;
assign chnl_in.rx_reset = reset;
assign chnl_in.tx_reset = reset;
assign chnl_in.tx_last = 1;
assign chnl_in.tx_len = RC;
assign chnl_in.tx_off = 0;
assign chnl_in.tx_data_valid = acked;
 
 
// --------------------------------------------------------------------
/trunk/PCIe/src/RIFFA/riffa_chnl_tx.sv
1,6 → 1,6
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
31,7 → 31,7
N // data bus width in bytes
)
(
riffa_chnl_if chnl_bus,
riffa_chnl_if chnl_in,
input tx_ready,
input tx_done,
output acked,
45,12 → 45,12
);
 
// --------------------------------------------------------------------
//
//
riffa_chnl_tx_fsm
riffa_chnl_tx_fsm_i
(
.tx(chnl_bus.tx),
.tx_ack(chnl_bus.tx_ack),
.tx(chnl_in.tx),
.tx_ack(chnl_in.tx_ack),
.*
);
 
58,9 → 58,9
// --------------------------------------------------------------------
//
always_ff @(posedge clk)
if(reset | ~chnl_bus.tx | tx_done)
if(reset | ~chnl_in.tx | tx_done)
tx_index = 0;
else if(chnl_bus.tx_data_valid & chnl_bus.tx_data_ren)
else if(chnl_in.tx_data_valid & chnl_in.tx_data_ren)
tx_index <= tx_index + (N/4); // increment by 32 bit words
 
 
/trunk/PCIe/src/RIFFA/riffa_chnl_w.sv
56,7 → 56,7
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN, // Channel write data has been received
 
riffa_chnl_if chnl_bus[C_NUM_CHNL]
riffa_chnl_if chnl_in[C_NUM_CHNL]
);
 
// --------------------------------------------------------------------
65,25 → 65,25
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1)
begin : channels
assign CHNL_RX_CLK[i] = chnl_bus[i].rx_clk;
assign chnl_bus[i].rx = CHNL_RX[i];
assign CHNL_RX_ACK[i] = chnl_bus[i].rx_ack;
assign chnl_bus[i].rx_last = CHNL_RX_LAST[i];
assign chnl_bus[i].rx_len = CHNL_RX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W];
assign chnl_bus[i].rx_off = CHNL_RX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W];
assign chnl_bus[i].rx_data = CHNL_RX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH];
assign chnl_bus[i].rx_data_valid = CHNL_RX_DATA_VALID[i];
assign CHNL_RX_DATA_REN[i] = chnl_bus[i].rx_data_ren;
assign CHNL_RX_CLK[i] = chnl_in[i].rx_clk;
assign chnl_in[i].rx = CHNL_RX[i];
assign CHNL_RX_ACK[i] = chnl_in[i].rx_ack;
assign chnl_in[i].rx_last = CHNL_RX_LAST[i];
assign chnl_in[i].rx_len = CHNL_RX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W];
assign chnl_in[i].rx_off = CHNL_RX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W];
assign chnl_in[i].rx_data = CHNL_RX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH];
assign chnl_in[i].rx_data_valid = CHNL_RX_DATA_VALID[i];
assign CHNL_RX_DATA_REN[i] = chnl_in[i].rx_data_ren;
 
assign CHNL_TX_CLK[i] = chnl_bus[i].tx_clk;
assign CHNL_TX[i] = chnl_bus[i].tx;
assign chnl_bus[i].tx_ack = CHNL_TX_ACK[i];
assign CHNL_TX_LAST[i] = chnl_bus[i].tx_last;
assign CHNL_TX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W] = chnl_bus[i].tx_len;
assign CHNL_TX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W] = chnl_bus[i].tx_off;
assign CHNL_TX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH] = chnl_bus[i].tx_data;
assign CHNL_TX_DATA_VALID[i] = chnl_bus[i].tx_data_valid;
assign chnl_bus[i].tx_data_ren = CHNL_TX_DATA_REN[i];
assign CHNL_TX_CLK[i] = chnl_in[i].tx_clk;
assign CHNL_TX[i] = chnl_in[i].tx;
assign chnl_in[i].tx_ack = CHNL_TX_ACK[i];
assign CHNL_TX_LAST[i] = chnl_in[i].tx_last;
assign CHNL_TX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W] = chnl_in[i].tx_len;
assign CHNL_TX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W] = chnl_in[i].tx_off;
assign CHNL_TX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH] = chnl_in[i].tx_data;
assign CHNL_TX_DATA_VALID[i] = chnl_in[i].tx_data_valid;
assign chnl_in[i].tx_data_ren = CHNL_TX_DATA_REN[i];
end
endgenerate
 
/trunk/sim/libs/qaz_lib_verilog/basal.f
5,6 → 5,7
 
${LIB_BASE_DIR}/basal/src/FIFOs/bc_sync_fifo.v
${LIB_BASE_DIR}/basal/src/FIFOs/sync_fifo.sv
${LIB_BASE_DIR}/basal/src/FIFOs/tiny_async_fifo.sv
${LIB_BASE_DIR}/basal/src/FIFOs/tiny_sync_fifo.sv
 
${LIB_BASE_DIR}/basal/src/misc/bit_connect_big_to_little.v

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.