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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

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  • This comparison shows the changes necessary to convert path 
    /qaz_libs/trunk/PCIe/src/RIFFA
    from Rev 33 to Rev 34
    ↔ Reverse comparison
  •

Rev 33 → Rev 34

/riffa_axis_test_pattern.sv
0,0 → 1,101
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module
riffa_axis_test_pattern
#(
N, // RIFFA data bus width in bytes
W = 4, // word width in bytes
WPB = N / W // number of words per beat
)
(
riffa_chnl_if chnl_in,
input [31:0] tx_len,
input clk,
input reset
);
 
// --------------------------------------------------------------------
//
localparam I = 0; // TID width
localparam D = 0; // TDEST width
localparam U = 3; // TUSER width
localparam RW = (N/4); // width of the RIFFA bus in 32 bit words
 
 
// --------------------------------------------------------------------
//
wire aclk = clk;
wire aresetn = ~reset;
 
 
// --------------------------------------------------------------------
//
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*);
 
axis_test_patern #(.N(N), .W(W), .WPB(WPB))
axis_test_patern_i(.*);
 
 
// --------------------------------------------------------------------
//
wire tx_ready = 1;
wire tx_last = 1;
wire acked;
wire [30:0] tx_off = 0;
wire [30:0] tx_index;
wire tx_done = (tx_index >= tx_len - RW);
 
riffa_chn_tx #(.N(N))
riffa_chn_tx_i(.*);
 
 
// --------------------------------------------------------------------
//
assign axis_out.tready = chnl_in.tx_data_ren & acked;
 
 
// --------------------------------------------------------------------
//
assign chnl_in.rx_clk = clk;
assign chnl_in.tx_clk = clk;
assign chnl_in.rx_reset = reset;
assign chnl_in.tx_reset = reset;
assign chnl_in.tx_last = tx_last;
assign chnl_in.tx_len = tx_len;
assign chnl_in.tx_off = tx_off;
assign chnl_in.tx_data_valid = axis_out.tvalid & acked;
assign chnl_in.tx_data = axis_out.tdata;
 
// --------------------------------------------------------------------
//
endmodule
 
 
 
 
/riffa_chnl_rx.sv
33,7 → 33,7
(
riffa_chnl_if chnl_in,
output rx_done,
output reg [31:0] rx_index,
output reg [30:0] rx_index,
output reg rx_last,
output reg [31:0] rx_len,
output reg [30:0] rx_off,
48,11 → 48,6
 
// --------------------------------------------------------------------
//
localparam RW = (N/4); // width of the bus in 32 bit words
 
 
// --------------------------------------------------------------------
//
riffa_chnl_rx_fsm
riffa_chnl_rx_fsm_i
(
90,7 → 85,7
if(reset | rx_done)
rx_index = 0;
else if(rd_en)
rx_index <= rx_index + RW;
rx_index <= rx_index + (N/4); // increment by 32 bit words
 
 
// --------------------------------------------------------------------
/riffa_chnl_tx.sv
28,14 → 28,14
module
riffa_chn_tx
#(
N, // data bus width in bytes
D = 2 // TX data fifo depth
N // data bus width in bytes
)
(
riffa_chnl_if chnl_in,
input tx_ready,
input tx_done,
output reg [31:0] tx_index,
output acked,
output reg [30:0] tx_index,
input tx_last,
input [31:0] tx_len,
input [30:0] tx_off,
45,12 → 45,7
);
 
// --------------------------------------------------------------------
//
localparam RW = (N/4); // width of the bus in 32 bit words
 
 
// --------------------------------------------------------------------
//
//
riffa_chnl_tx_fsm
riffa_chnl_tx_fsm_i
(
63,10 → 58,10
// --------------------------------------------------------------------
//
always_ff @(posedge clk)
if(reset | ~chnl_in.tx)
if(reset | ~chnl_in.tx | tx_done)
tx_index = 0;
else if(chnl_in.tx_data_valid & chnl_in.tx_data_ren)
tx_index <= tx_index + RW;
tx_index <= tx_index + (N/4); // increment by 32 bit words
 
 
// --------------------------------------------------------------------
/riffa_chnl_tx_fsm.sv
30,6 → 30,7
(
input tx_ready,
output tx,
output acked,
input tx_ack,
input tx_done,
 
85,7 → 86,8
 
// --------------------------------------------------------------------
//
assign tx = (state == ACK) | (state == TX);
assign tx = (state == ACK) | (state == TX);
assign acked = (state == TX) | (next_state == TX);
 
 
// --------------------------------------------------------------------
/riffa_register_file.sv
28,7 → 28,7
module
riffa_register_file
#(
// A, // address bus width
A, // address bus width
N, // data bus width in bytes
MW = 3 // mux select width
)
/riffa_register_if.sv
30,8 → 30,9
riffa_register_if
#(
N, // data bus width in bytes
MW, // mux select width
MI = 2 ** MW // mux inputs
B, // number of register banks
RW = (N/4), // width of the bus in 32 bit words
RC = RW * B // number of available registers
)
(
input clk,
38,8 → 39,8
input reset
);
 
wire [(N*8)-1:0] register_in [MI-1:0];
reg [(N*8)-1:0] register_out [MI-1:0];
wire [31:0] register_in [RC-1:0];
reg [31:0] register_out [RC-1:0];
 
 
// --------------------------------------------------------------------

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