URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/avalon_lib
- from Rev 31 to Rev 32
- ↔ Reverse comparison
Rev 31 → Rev 32
/sim/src/ast_monitor.sv
0,0 → 1,99
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`timescale 1 ps / 1 ps |
|
module |
ast_monitor |
#( |
ST_SYMBOL_W, |
ST_NUMSYMBOLS, |
USE_PACKET, |
ST_READY_LATENCY, |
USE_CHANNEL = 0, |
USE_ERROR = 0, |
USE_READY = 1, |
USE_VALID = 1, |
USE_EMPTY = 1, |
ST_ERROR_W = 1, |
ST_MAX_PACKET_SIZE = 1, |
ST_MAX_CHANNELS = 0, |
ST_CHANNEL_W = $clog2(ST_MAX_CHANNELS), |
ST_EMPTY_W = (ST_NUMSYMBOLS == 1) ? 1 : $clog2(ST_NUMSYMBOLS) |
) |
( |
ast_if src, |
ast_if sink, |
input clk, |
input reset |
); |
|
altera_avalon_st_monitor |
#( |
.USE_PACKET (USE_PACKET), |
.USE_CHANNEL (USE_CHANNEL), |
.USE_ERROR (USE_ERROR), |
.USE_READY (USE_READY), |
.USE_VALID (USE_VALID), |
.USE_EMPTY (USE_EMPTY), |
.ST_SYMBOL_W (ST_SYMBOL_W), |
.ST_NUMSYMBOLS (ST_NUMSYMBOLS), |
.ST_CHANNEL_W (ST_CHANNEL_W), |
.ST_ERROR_W (ST_ERROR_W), |
.ST_EMPTY_W (ST_EMPTY_W), |
.ST_READY_LATENCY (ST_READY_LATENCY), |
.ST_BEATSPERCYCLE (1), |
.ST_MAX_CHANNELS (ST_MAX_CHANNELS), |
.ST_MAX_PACKET_SIZE (ST_MAX_PACKET_SIZE), |
.VHDL_ID (0) |
) |
altera_avalon_st_monitor_i |
( |
.clk (clk), // clk.clk |
.reset (reset), // clk_reset.reset |
.src_data (src.data), // src.data |
.src_valid (src.valid), // .valid |
.src_ready (src.ready), // .ready |
.src_startofpacket (src.startofpacket), // .startofpacket |
.src_endofpacket (src.endofpacket), // .endofpacket |
.src_empty (src.empty), // .empty |
.src_channel (src.channel), // .channel |
.src_error (src.error), // .error |
.sink_data (sink.data), // sink.data |
.sink_valid (sink.valid), // .valid |
.sink_ready (sink.ready), // .ready |
.sink_startofpacket (sink.startofpacket), // .startofpacket |
.sink_endofpacket (sink.endofpacket), // .endofpacket |
.sink_empty (sink.empty), // .empty |
.sink_channel (sink.channel), // .channel |
.sink_error (sink.error) // .error |
); |
|
|
// -------------------------------------------------------------------- |
// |
endmodule |
/sim/src/ast_sink.sv
0,0 → 1,87
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`timescale 1 ps / 1 ps |
|
module |
ast_sink |
#( |
ST_SYMBOL_W, |
ST_NUMSYMBOLS, |
USE_PACKET, |
ST_READY_LATENCY, |
USE_CHANNEL = 0, |
USE_ERROR = 0, |
USE_READY = 1, |
USE_VALID = 1, |
USE_EMPTY = 1, |
ST_ERROR_W = 1, |
ST_MAX_CHANNELS = 0, |
ST_CHANNEL_W = $clog2(ST_MAX_CHANNELS), |
ST_EMPTY_W = $clog2(ST_NUMSYMBOLS) |
) |
( |
ast_if sink, |
input clk, |
input reset |
); |
|
altera_avalon_st_sink_bfm |
#( |
.USE_PACKET (USE_PACKET), |
.USE_CHANNEL (USE_CHANNEL), |
.USE_ERROR (USE_ERROR), |
.USE_READY (USE_READY), |
.USE_VALID (USE_VALID), |
.USE_EMPTY (USE_EMPTY), |
.ST_SYMBOL_W (ST_SYMBOL_W), |
.ST_NUMSYMBOLS (ST_NUMSYMBOLS), |
.ST_CHANNEL_W (ST_CHANNEL_W), |
.ST_ERROR_W (ST_ERROR_W), |
.ST_EMPTY_W (ST_EMPTY_W), |
.ST_READY_LATENCY (ST_READY_LATENCY), |
.ST_BEATSPERCYCLE (1), |
.ST_MAX_CHANNELS (ST_MAX_CHANNELS), |
.VHDL_ID (0) |
) |
bfm |
( |
.clk (clk), // clk.clk |
.reset (reset), // clk_reset.reset |
.sink_data (sink.data), // sink.data |
.sink_valid (sink.valid), // .valid |
.sink_ready (sink.ready), // .ready |
.sink_startofpacket (sink.startofpacket), // .startofpacket |
.sink_endofpacket (sink.endofpacket), // .endofpacket |
.sink_empty (sink.empty), // .empty |
.sink_channel (sink.channel), // .channel |
.sink_error (sink.error) // .error |
); |
|
// -------------------------------------------------------------------- |
// |
endmodule |
/sim/src/ast_source.sv
0,0 → 1,87
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`timescale 1 ps / 1 ps |
|
module |
ast_source |
#( |
ST_SYMBOL_W, |
ST_NUMSYMBOLS, |
USE_PACKET, |
ST_READY_LATENCY, |
USE_CHANNEL = 0, |
USE_ERROR = 0, |
USE_READY = 1, |
USE_VALID = 1, |
USE_EMPTY = 1, |
ST_ERROR_W = 1, |
ST_MAX_CHANNELS = 0, |
ST_CHANNEL_W = $clog2(ST_MAX_CHANNELS), |
ST_EMPTY_W = $clog2(ST_NUMSYMBOLS) |
) |
( |
ast_if src, |
input clk, |
input reset |
); |
|
altera_avalon_st_source_bfm |
#( |
.USE_PACKET (USE_PACKET), |
.USE_CHANNEL (USE_CHANNEL), |
.USE_ERROR (USE_ERROR), |
.USE_READY (USE_READY), |
.USE_VALID (USE_VALID), |
.USE_EMPTY (USE_EMPTY), |
.ST_SYMBOL_W (ST_SYMBOL_W), |
.ST_NUMSYMBOLS (ST_NUMSYMBOLS), |
.ST_CHANNEL_W (ST_CHANNEL_W), |
.ST_ERROR_W (ST_ERROR_W), |
.ST_EMPTY_W (ST_EMPTY_W), |
.ST_READY_LATENCY (ST_READY_LATENCY), |
.ST_BEATSPERCYCLE (1), |
.ST_MAX_CHANNELS (ST_MAX_CHANNELS), |
.VHDL_ID (0) |
) |
bfm |
( |
.clk (clk), // clk.clk |
.reset (reset), // clk_reset.reset |
.src_data (src.data), // src.data |
.src_valid (src.valid), // .valid |
.src_ready (src.ready), // .ready |
.src_startofpacket (src.startofpacket), // .startofpacket |
.src_endofpacket (src.endofpacket), // .endofpacket |
.src_empty (src.empty), // .empty |
.src_channel (src.channel), // .channel |
.src_error (src.error) // .error |
); |
|
// -------------------------------------------------------------------- |
// |
endmodule |
/sim/tests/tb_ast_monitor/init_test.do
0,0 → 1,36
# ------------------------------------ |
# |
# ------------------------------------ |
|
global env |
|
# setup environment |
do ../../../../scripts/sim_env.do |
set env(SIM_TARGET) fpga |
set env(SIM_TB) tb_ast_monitor |
|
radix -hexadecimal |
|
make_lib work 1 |
|
sim_compile_lib $env(LIB_BASE_DIR) tb_packages |
sim_compile_lib $env(LIB_BASE_DIR) bfm_packages |
sim_compile_lib $env(LIB_BASE_DIR) avalon_lib |
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib |
sim_compile_lib $env(LIB_BASE_DIR) sim |
|
|
# compile simulation files |
vlog -f ./$env(SIM_TB).f |
|
# simulation $root |
vlog ./$env(SIM_TB)_pkg.sv |
vlog ./$env(SIM_TB).sv |
|
# compile test last |
vlog ./the_test.sv |
|
# run the sim |
sim_run_test |
|
|
/sim/tests/tb_ast_monitor/sim.do
0,0 → 1,11
# |
# |
|
quit -sim |
|
vsim -novopt work.tb_top |
# vsim -f ./sim.f work.tb_top |
|
# log all signals |
# log -r * |
|
/sim/tests/tb_ast_monitor/tb_ast_monitor.f
0,0 → 1,8
# |
|
${PROJECT_DIR}/src/ast_if.sv |
|
${PROJECT_DIR}/sim/src/ast_monitor.sv |
${PROJECT_DIR}/sim/src/ast_sink.sv |
${PROJECT_DIR}/sim/src/ast_source.sv |
|
/sim/tests/tb_ast_monitor/tb_ast_monitor.sv
0,0 → 1,162
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module tb_top(); |
|
// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_100mhz; |
wire tb_clk = clk_100mhz; |
wire tb_rst; |
|
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); |
|
|
// -------------------------------------------------------------------- |
// |
wire tb_rst_s; |
wire clk = tb_clk; |
wire reset = tb_rst_s; |
|
sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); |
|
|
// -------------------------------------------------------------------- |
// |
import tb_ast_monitor_pkg::*; |
|
|
// -------------------------------------------------------------------- |
// |
ast_if #(EW, CW, SW, NSW) src(.*); |
ast_if #(EW, CW, SW, NSW) sink(.*); |
|
|
// -------------------------------------------------------------------- |
// |
|
|
|
|
// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
|
|
// -------------------------------------------------------------------- |
// |
ast_monitor |
#( |
.ST_SYMBOL_W(ST_SYMBOL_W), |
.ST_NUMSYMBOLS(ST_NUMSYMBOLS), |
.USE_PACKET(USE_PACKET), |
.ST_READY_LATENCY(ST_READY_LATENCY), |
.USE_CHANNEL(USE_CHANNEL), |
.USE_ERROR(USE_ERROR), |
.USE_READY(USE_READY), |
.USE_VALID(USE_VALID), |
.USE_EMPTY(USE_EMPTY), |
.ST_ERROR_W(ST_ERROR_W), |
.ST_MAX_PACKET_SIZE(ST_MAX_PACKET_SIZE), |
.ST_MAX_CHANNELS(ST_MAX_CHANNELS) |
) |
ast_monitor_i(.sink(src), .src(sink), .*); |
|
|
// -------------------------------------------------------------------- |
// |
ast_source |
#( |
.ST_SYMBOL_W(ST_SYMBOL_W), |
.ST_NUMSYMBOLS(ST_NUMSYMBOLS), |
.USE_PACKET(USE_PACKET), |
.ST_READY_LATENCY(ST_READY_LATENCY), |
.USE_CHANNEL(USE_CHANNEL), |
.USE_ERROR(USE_ERROR), |
.USE_READY(USE_READY), |
.USE_VALID(USE_VALID), |
.USE_EMPTY(USE_EMPTY), |
.ST_ERROR_W(ST_ERROR_W), |
.ST_MAX_CHANNELS(ST_MAX_CHANNELS) |
) |
ast_source_i(.*); |
|
|
// -------------------------------------------------------------------- |
// |
ast_sink |
#( |
.ST_SYMBOL_W(ST_SYMBOL_W), |
.ST_NUMSYMBOLS(ST_NUMSYMBOLS), |
.USE_PACKET(USE_PACKET), |
.ST_READY_LATENCY(ST_READY_LATENCY), |
.USE_CHANNEL(USE_CHANNEL), |
.USE_ERROR(USE_ERROR), |
.USE_READY(USE_READY), |
.USE_VALID(USE_VALID), |
.USE_EMPTY(USE_EMPTY), |
.ST_ERROR_W(ST_ERROR_W), |
.ST_MAX_CHANNELS(ST_MAX_CHANNELS) |
) |
ast_sink_i(.*); |
|
|
|
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
|
|
|
// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
|
initial |
begin |
|
test.run_the_test(); |
|
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
|
$display("^^^---------------------------------"); |
|
$stop(); |
|
end |
|
endmodule |
|
|
|
/sim/tests/tb_ast_monitor/tb_ast_monitor_pkg.sv
0,0 → 1,69
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
package tb_ast_monitor_pkg; |
|
// -------------------------------------------------------------------- |
// |
localparam EW = 1; |
localparam CW = 1; |
localparam SW = 8; |
localparam NSW = 4; |
|
localparam ST_SYMBOL_W = SW; |
localparam ST_NUMSYMBOLS = NSW; |
localparam USE_PACKET = 1; |
localparam ST_READY_LATENCY = 3; |
localparam USE_CHANNEL = 0; |
localparam USE_ERROR = 0; |
localparam USE_READY = 1; |
localparam USE_VALID = 1; |
localparam USE_EMPTY = 1; |
localparam ST_ERROR_W = EW; |
localparam ST_MAX_PACKET_SIZE = 1; |
localparam ST_MAX_CHANNELS = 0; |
|
// -------------------------------------------------------------------- |
// |
class tb_ast_monitor_class; |
|
|
|
// -------------------------------------------------------------------- |
// |
endclass: tb_ast_monitor_class |
|
|
// -------------------------------------------------------------------- |
// |
endpackage: tb_ast_monitor_pkg |
|
|
|
|
|
/sim/tests/tb_ast_monitor/the_test.sv
0,0 → 1,102
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`timescale 1ps/1ps |
|
|
module the_test(input tb_clk, input tb_rst); |
|
// -------------------------------------------------------------------- |
// |
import verbosity_pkg::*; |
|
|
// -------------------------------------------------------------------- |
// |
task run_the_test; |
|
// -------------------------------------------------------------------- |
// insert test below |
// -------------------------------------------------------------------- |
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench begun.\n", $time); |
$display("^^^---------------------------------"); |
// -------------------------------------------------------------------- |
|
// -------------------------------------------------------------------- |
tb_top.tb.timeout_stop(50us); |
|
// -------------------------------------------------------------------- |
// set_verbosity(VERBOSITY_DEBUG); |
tb_top.ast_source_i.st_source_bfm_i.init(); |
tb_top.ast_sink_i.st_sink_bfm_i.init(); |
|
// -------------------------------------------------------------------- |
wait(~tb_rst); |
|
// -------------------------------------------------------------------- |
#200ns; |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(0); |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(1); |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(0); |
tb_top.ast_source_i.st_source_bfm_i.push_transaction(); |
|
tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(1); |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(0); |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(0); |
tb_top.ast_source_i.st_source_bfm_i.push_transaction(); |
|
tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(2); |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(0); |
tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(1); |
tb_top.ast_source_i.st_source_bfm_i.push_transaction(); |
|
|
// -------------------------------------------------------------------- |
#200ns; |
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1); |
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0); |
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1); |
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0); |
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1); |
@(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0); |
|
|
// -------------------------------------------------------------------- |
#1us; |
|
|
// -------------------------------------------------------------------- |
// insert test above |
// -------------------------------------------------------------------- |
|
endtask |
|
// -------------------------------------------------------------------- |
// |
endmodule |
|
/src/ast_if.sv
0,0 → 1,57
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
interface |
ast_if |
#( |
EW = 1, // error signal width in bits. |
CW = 1, // channel width in bits. |
SW = 8, // Data symbol width in bits. Should be 8 for byte oriented interfaces. |
NSW, // Numbers of symbols per word |
NSW_L = (NSW == 1) ? 1 : $clog2(NSW) |
) |
( |
input reset, |
input clk |
); |
|
wire [(SW*NSW)-1:0] data; |
wire valid; |
wire ready; |
wire startofpacket; |
wire endofpacket; |
wire [NSW_L-1:0] empty; |
wire [CW-1:0] channel; |
wire [EW-1:0] error; |
|
|
// -------------------------------------------------------------------- |
// |
endinterface |
|
|
/src/ast_ready_cycle_fsm.sv
0,0 → 1,106
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
module |
ast_ready_cycle_fsm |
( |
input axis_en, |
output axis_tvalid, |
input axis_tready, |
|
input fifo_watermark, // OK to use fifo_almost_full if FIFO is synchronous, assert to flush also |
input fifo_empty, |
output fifo_rd_en, |
|
output data_to_axis_fsm_error, |
|
input aclk, |
input aresetn |
); |
|
//--------------------------------------------------- |
// state machine binary definitions |
enum reg [3:0] { |
IDLE_STATE = 4'b0001, |
TVALID = 4'b0010, |
TREADY = 4'b0100, |
ERROR_STATE = 4'b1000 |
} state, next_state; |
|
|
//--------------------------------------------------- |
// state machine flop |
always_ff @(posedge aclk) |
if(~aresetn) |
state <= IDLE_STATE; |
else |
state <= next_state; |
|
|
//--------------------------------------------------- |
// state machine |
always_comb |
case(state) |
IDLE_STATE: if(axis_en & fifo_watermark & ~fifo_empty) |
if(axis_tready) |
next_state <= TREADY; |
else |
next_state <= TVALID; |
else |
next_state <= IDLE_STATE; |
|
TVALID: if(axis_tready) // wait for slave to be ready |
next_state <= TREADY; |
else |
next_state <= TVALID; |
|
TREADY: if(fifo_empty) // slave can accept data |
next_state <= IDLE_STATE; |
else if(axis_tready) |
next_state <= TREADY; |
else |
next_state <= TVALID; |
|
ERROR_STATE: next_state <= IDLE_STATE; |
|
default: next_state <= ERROR_STATE; |
|
endcase |
|
|
//--------------------------------------------------- |
// outputs |
assign axis_tvalid = (next_state == TVALID) | (next_state == TREADY); |
assign fifo_rd_en = axis_tvalid & axis_tready; |
assign data_to_axis_fsm_error = (state == ERROR_STATE); |
|
|
//--------------------------------------------------- |
// |
endmodule |
|