URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
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- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/axi4_lib/sim
- from Rev 45 to Rev 50
- ↔ Reverse comparison
Rev 45 → Rev 50
/src/axi4_bfm_pkg.sv
File deleted
/src/tb_bfm.sv
File deleted
/src/axi4_bfm/axi4_transaction_pkg.sv
File deleted
/src/axi4_bfm/axi4_simple_agent_pkg.sv
File deleted
/src/axi4_bfm/axi4_slave_bfm_if.sv
File deleted
/src/axi4_bfm/axi4_master_bfm_if.sv
File deleted
/src/tb_axi4_memory.sv
File deleted
/src/tb_axi4_to_axis_agent_class_pkg.sv
File deleted
/src/tb_register_slice.sv
File deleted
/src/axi4_models/axi4_models_pkg.sv
File deleted
/src/axi4_models/axi4_arbiter_pkg.sv
File deleted
/src/axi4_models/axi4_memory_pkg.sv
File deleted
/src/axi4_models/tb_axi4_multi_port_memory.sv
File deleted
/src/legacy/tb_axi4_memory.sv
0,0 → 1,129
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
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module tb_top(); |
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// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_100mhz; |
wire tb_clk = clk_100mhz; |
wire tb_rst; |
wire aclk = tb_clk; |
wire aresetn = ~tb_rst; |
|
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); |
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// -------------------------------------------------------------------- |
// |
localparam A = 32; |
localparam N = 8; |
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// -------------------------------------------------------------------- |
// |
axi4_if #(.A(A), .N(N)) |
axi4_s(.*); |
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// -------------------------------------------------------------------- |
// |
|
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// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
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// -------------------------------------------------------------------- |
// |
axi4_checker #(.A(A), .N(N)) |
axi4_s_check(.axi4_in(axi4_s)); |
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// // -------------------------------------------------------------------- |
// // |
// axi4_master_bfm_if #(.A(A), .N(N)) |
// tb_axi4_m(.axi4_s(axi4_s), .*); |
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// -------------------------------------------------------------------- |
// |
import axi4_bfm_pkg::*; |
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axi4_master_bfm_class bfm; |
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initial |
bfm = new(axi4_s); |
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// -------------------------------------------------------------------- |
// |
import axi4_memory_pkg::*; |
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axi4_memory_class axi4_memory; |
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initial |
axi4_memory = new(axi4_s); |
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// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
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// -------------------------------------------------------------------- |
// debug wires |
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// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
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initial |
begin |
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test.run_the_test(); |
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$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
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$display("^^^---------------------------------"); |
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$stop(); |
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end |
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endmodule |
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/src/legacy/tb_axi4_to_axis_agent_class_pkg.sv
0,0 → 1,130
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
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package tb_axi4_to_axis_agent_class_pkg; |
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// -------------------------------------------------------------------- |
// |
import axi4_memory_pkg::*; |
import axis_bfm_pkg::*; |
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// -------------------------------------------------------------------- |
// |
class tb_axi4_to_axis_agent_class #(N, A, I, D, U); |
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axi4_memory_class #(A, N, I) m_h; |
axis_rx_bfm_class #(N, I, D, U) s_h; |
memory_tr_class #(A, N, I) m_tr_h, m_tr_clone_h; |
axis_tr_class #(N, I, D, U) s_tr_h; |
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virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m; |
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out; |
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mailbox #(memory_tr_class #(A, N, I)) q; |
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// -------------------------------------------------------------------- |
// |
task wait_for_sof; |
@(posedge axis_out.cb_s.tuser); |
$display("^^^ %16.t | %m", $time); |
endtask: wait_for_sof |
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// -------------------------------------------------------------------- |
// |
task random_transaction(int addr, int size); |
m_tr_h = new(); |
m_tr_h.random(addr, size); |
m_tr_clone_h = m_tr_h.clone(); |
q.put(m_tr_clone_h); |
m_h.load_words(addr, m_tr_h.data); |
endtask: random_transaction |
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// -------------------------------------------------------------------- |
// |
task automatic |
compare; |
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$display("^^^ %16.t | %m", $time); |
$display("^^^ %16.t | q.num = %d", $time, q.num); |
$display("^^^ %16.t | s_h.q.num = %d", $time, s_h.q.num); |
$display("^^^ %16.t | m_tr_h.data.size = %d", $time, m_tr_h.data.size); |
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q.get(m_tr_h); |
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for(int i = 0; i < m_tr_h.data.size; i += N) |
begin |
if(s_h.q.try_get(s_tr_h) == 0) |
begin |
$display("!!! %16.t | ERROR!!! try_get(s_tr_h) == 0", $time); |
break; |
end |
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for(int k = 0; k < N; k++) |
begin |
if(s_tr_h.tdata[k*8 +: 8] != m_tr_h.data[i + k]) |
begin |
$display("!!! %16.t | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^", $time); |
$display("!!! %16.t | ERROR!!! mismatch | i = %d | k = %d", $time, i, k); |
$display("!!! %16.t | %x | %x |", $time, s_tr_h.tdata[k*8 +: 8], m_tr_h.data[i + k]); |
$stop; |
end |
end |
end |
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$display("^^^ %16.t | %m | done!", $time); |
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endtask: compare |
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//-------------------------------------------------------------------- |
// |
function new |
( |
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m, |
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out |
); |
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this.axi4_m = axi4_m; |
this.axis_out = axis_out; |
m_h = new(axi4_m); |
s_h = new(axis_out); |
q = new(); |
endfunction: new |
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// -------------------------------------------------------------------- |
// |
endclass: tb_axi4_to_axis_agent_class |
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// -------------------------------------------------------------------- |
// |
endpackage: tb_axi4_to_axis_agent_class_pkg |
/src/legacy/tb_bfm.sv
0,0 → 1,119
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
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module tb_top(); |
|
// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_100mhz; |
wire tb_clk = clk_100mhz; |
wire tb_rst; |
wire aclk = tb_clk; |
wire aresetn = ~tb_rst; |
|
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); |
|
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// -------------------------------------------------------------------- |
// |
localparam A = 32; |
localparam N = 8; |
|
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// -------------------------------------------------------------------- |
// |
axi4_if #(.A(A), .N(N)) |
axi4_bus(.*); |
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axi4_checker #(.A(A), .N(N)) |
axi4_in_check(.axi4_in(axi4_bus)); |
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// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
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// -------------------------------------------------------------------- |
// |
import axi4_simple_agent_pkg::*; |
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// -------------------------------------------------------------------- |
// |
axi4_master_bfm_if #(.A(A), .N(N)) |
axi4_m(.axi4_s(axi4_bus), .*); |
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axi4_slave_bfm_if #(.A(A), .N(N)) |
axi4_s(.axi4_m(axi4_bus), .*); |
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// -------------------------------------------------------------------- |
// |
axi4_simple_agent_class bfm; |
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initial |
bfm = new(axi4_m, axi4_s); |
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// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
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// -------------------------------------------------------------------- |
// debug wires |
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// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
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initial |
begin |
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test.run_the_test(); |
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$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
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$display("^^^---------------------------------"); |
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$stop(); |
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end |
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endmodule |
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/src/legacy/tb_register_slice.sv
0,0 → 1,133
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
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module tb_top(); |
|
// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_100mhz; |
wire tb_clk = clk_100mhz; |
wire tb_rst; |
wire aclk = tb_clk; |
wire aresetn = ~tb_rst; |
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tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); |
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// -------------------------------------------------------------------- |
// |
localparam A = 32; |
localparam N = 8; |
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// -------------------------------------------------------------------- |
// |
axi4_if #(.A(A), .N(N)) |
axi4_s(.*); |
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axi4_if #(.A(A), .N(N)) |
axi4_m(.*); |
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// -------------------------------------------------------------------- |
// |
axi4_register_slice #(.A(A), .N(N)) |
dut(.*); |
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// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
|
// -------------------------------------------------------------------- |
// |
axi4_checker #(.A(A), .N(N)) |
axi4_s_check(.axi4_in(axi4_s)); |
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axi4_checker #(.A(A), .N(N)) |
axi4_m_check(.axi4_in(axi4_m)); |
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// -------------------------------------------------------------------- |
// |
import axi4_simple_agent_pkg::*; |
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// -------------------------------------------------------------------- |
// |
axi4_master_bfm_if #(.A(A), .N(N)) |
tb_axi4_m(.axi4_s(axi4_s), .*); |
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axi4_slave_bfm_if #(.A(A), .N(N)) |
tb_axi4_s(.axi4_m(axi4_m), .*); |
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// -------------------------------------------------------------------- |
// |
axi4_simple_agent_class bfm; |
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initial |
bfm = new(tb_axi4_m, tb_axi4_s); |
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// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
|
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// -------------------------------------------------------------------- |
// debug wires |
|
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// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
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initial |
begin |
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test.run_the_test(); |
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$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
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$display("^^^---------------------------------"); |
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$stop(); |
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end |
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endmodule |
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