URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk
- from Rev 13 to Rev 14
- ↔ Reverse comparison
Rev 13 → Rev 14
/AXI/src/wb_axi4lite_read_fsm.v
22,6 → 22,7
output axi_arready, |
output axi_rvalid, |
output fsm_error, |
input wb_read, |
|
input axi_aclk, |
input axi_aresetn |
28,10 → 29,11
); |
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//--------------------------------------------------- |
// |
wire wb_xfer_in_progress = wb_cyc_o & wb_stb_o; |
// |
wire wb_xfer_in_progress = wb_cyc_o & wb_stb_o; |
wire wb_read_ack = wb_read & wb_ack_i; |
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|
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//--------------------------------------------------- |
// state machine binary definitions |
parameter IDLE_STATE = 4'b0001; |
39,11 → 41,11
parameter READ_READY_STATE = 4'b0100; |
parameter ERROR_STATE = 4'b1000; |
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|
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//--------------------------------------------------- |
// common next state logic |
reg [3:0] axi_next_state; |
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|
always @(*) |
if( axi_rready ) |
if( axi_arvalid ) |
55,8 → 57,8
axi_next_state <= IDLE_STATE; |
else |
axi_next_state <= READ_READY_STATE; |
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|
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//--------------------------------------------------- |
// state machine flop |
reg [3:0] state; |
78,7 → 80,7
else |
next_state <= IDLE_STATE; |
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READ_VALID_STATE: if( wb_ack_i ) // wait for wb slave to return data |
READ_VALID_STATE: if( wb_read_ack ) // wait for wb slave to return data |
next_state <= axi_next_state; |
else |
next_state <= READ_VALID_STATE; |
93,10 → 95,21
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//--------------------------------------------------- |
// |
reg axi_rvalid_r; |
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always @(posedge axi_aclk) |
if( ~axi_aresetn | axi_rready ) |
axi_rvalid_r <= 0; |
else if( (state != IDLE_STATE) & wb_read_ack ) |
axi_rvalid_r <= 1; |
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//--------------------------------------------------- |
// outputs |
assign fsm_error = (state == ERROR_STATE); |
assign axi_arready = (state != READ_VALID_STATE) | (next_state != READ_VALID_STATE); |
assign axi_rvalid = (state != IDLE_STATE) & wb_ack_i; |
assign axi_rvalid = axi_rvalid_r | wb_read_ack; |
assign read_idle = (state == IDLE_STATE); |
assign read_waiting_for_slave = (state == READ_VALID_STATE) | (next_state == READ_VALID_STATE); |
assign read_waiting_for_master = (state == READ_READY_STATE) | (next_state == READ_READY_STATE); |
/AXI/src/wb_axi4lite_bridge.v
88,6 → 88,7
wire read_idle; |
wire read_waiting_for_slave; |
wire read_waiting_for_master; |
wire wb_read; |
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(* KEEP = "TRUE" *) wire read_fsm_error; |
|
110,6 → 111,7
.axi_arready(axi_arready), |
.axi_rvalid(axi_rvalid), |
.fsm_error(read_fsm_error), |
.wb_read(wb_read), |
|
.axi_aclk(axi_aclk), |
.axi_aresetn(axi_aresetn) |
122,6 → 124,9
wire write_idle; |
wire write_waiting_for_slave; |
wire write_waiting_for_master; |
wire wb_write; |
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(* KEEP = "TRUE" *) wire write_fsm_error; |
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wb_axi4lite_write_fsm |
wb_axi4lite_write_fsm_i |
129,7 → 134,6
.axi_awvalid(axi_awvalid), |
.axi_wvalid(axi_wvalid), |
.axi_bready(axi_bready), |
.axi_rready(axi_rready), |
|
.wb_ack_i(wb_ack_i), |
.wb_err_i(wb_err_i), |
144,7 → 148,8
.axi_awready(axi_awready), |
.axi_wready(axi_wready), |
.axi_bvalid(axi_bvalid), |
.fsm_error(fsm_error), |
.fsm_error(write_fsm_error), |
.wb_write(wb_write), |
|
.axi_aclk(axi_aclk), |
.axi_aresetn(axi_aresetn) |
153,6 → 158,8
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//--------------------------------------------------- |
// |
(* KEEP = "TRUE" *) wire wb_master_fsm_error; |
|
wb_master_fsm |
wb_master_fsm_i |
( |
168,7 → 175,11
.write_idle(write_idle), |
.write_waiting_for_slave(write_waiting_for_slave), |
.write_waiting_for_master(write_waiting_for_master), |
.wb_read(wb_read), |
.wb_write(wb_write), |
.fsm_error(wb_master_fsm_error), |
|
|
.axi_aclk(axi_aclk), |
.axi_aresetn(axi_aresetn) |
); |
/AXI/src/wb_master_fsm.v
18,6 → 18,9
input write_idle, |
input write_waiting_for_slave, |
input write_waiting_for_master, |
output wb_read, |
output wb_write, |
output fsm_error, |
|
input axi_aclk, |
input axi_aresetn |
104,7 → 107,9
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//--------------------------------------------------- |
// outputs |
assign fsm_error = (state == ERROR_STATE); |
assign fsm_error = (state == ERROR_STATE); |
assign wb_read = (state == WB_READ_STATE); |
assign wb_write = (state == WB_WRITE_STATE); |
|
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endmodule |
/AXI/src/wb_axi4lite_write_fsm.v
9,7 → 9,6
input axi_awvalid, |
input axi_wvalid, |
input axi_bready, |
input axi_rready, |
|
input wb_ack_i, |
input wb_err_i, |
25,6 → 24,7
output axi_wready, |
output axi_bvalid, |
output fsm_error, |
input wb_write, |
|
input axi_aclk, |
input axi_aresetn |
32,7 → 32,8
|
//--------------------------------------------------- |
// |
wire wb_xfer_in_progress = wb_cyc_o & wb_stb_o; |
wire wb_xfer_in_progress = wb_cyc_o & wb_stb_o; |
wire wb_write_ack = wb_write & wb_ack_i; |
|
|
//--------------------------------------------------- |
78,7 → 79,7
else |
next_state <= IDLE_STATE; |
|
WRITE_VALID_STATE: if( axi_wvalid & wb_ack_i ) // wait for wb slave to accept data |
WRITE_VALID_STATE: if( axi_wvalid & wb_write_ack ) // wait for wb slave to accept data |
if( axi_bready ) |
next_state <= axi_next_state; |
else |
86,7 → 87,7
else |
next_state <= WRITE_VALID_STATE; |
|
WRITE_READY_STATE: if( wb_ack_i ) // wait for master to accept wb slave response |
WRITE_READY_STATE: if( axi_bready ) // wait for master to accept wb slave response |
next_state <= axi_next_state; |
else |
next_state <= WRITE_READY_STATE; |
104,8 → 105,8
assign write_waiting_for_slave = (state == WRITE_VALID_STATE); |
assign write_waiting_for_master = (state == WRITE_READY_STATE); |
assign axi_awready = (state != WRITE_READY_STATE); |
assign axi_wready = (state != IDLE_STATE) & wb_ack_i; |
assign axi_bvalid = (state != IDLE_STATE) & wb_ack_i; |
assign axi_wready = (state != IDLE_STATE) & wb_write_ack; |
assign axi_bvalid = (state != IDLE_STATE) & wb_write_ack; |
assign fsm_error = (state == ERROR_STATE); |
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/AXI/sim/src/tb_axi4lite_bfm_if.sv
162,7 → 162,7
output axi_awuser; |
endclocking |
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// -------------------------------------------------------------------- |
// |
class qaz_axi4_bfm extends v_qaz_axi4_bfm; |
170,6 → 170,33
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// -------------------------------------------------------------------- |
// |
rand int axi_rready_delay; |
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constraint axi_rready_delay_c |
{ |
axi_rready_delay < 16; |
axi_rready_delay >= 0; |
} |
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rand int axi_wvalid_delay; |
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constraint axi_wvalid_delay_c |
{ |
axi_wvalid_delay < 16; |
axi_wvalid_delay >= 0; |
} |
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rand int axi_bready_delay; |
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constraint axi_bready_delay_c |
{ |
axi_bready_delay < 16; |
axi_bready_delay >= 0; |
} |
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// -------------------------------------------------------------------- |
// |
task init; |
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cb.axi_araddr <= 0; |
199,10 → 226,10
axi_rid <= 0; |
axi_bid <= 0; |
axi_buser <= 0; |
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cb.axi_wlast <= 1; |
cb.axi_wuser <= 0; |
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cb.axi_awburst <= 1; |
cb.axi_awcache <= 0; |
cb.axi_awid <= 0; |
229,27 → 256,41
output int data |
); |
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cb.axi_araddr <= addr; |
cb.axi_arprot <= 0; |
assert( this.randomize() ); |
// $strobe("^^^ %16.t | %m | axi_rready_delay = %d", $time, axi_rready_delay ); |
|
##0; |
cb.axi_arvalid <= 1; |
##1; |
fork |
begin |
##0; |
cb.axi_araddr <= addr; |
cb.axi_arprot <= 0; |
cb.axi_arvalid <= 1; |
|
wait( cb.axi_arready ); |
cb.axi_arvalid <= 0; |
if( cb.axi_arready ) // axi_arvalid must be asserted for at least one clock |
##1; |
|
// optional delay here |
cb.axi_rready <= 1; |
##1; |
wait( cb.axi_arready ); |
cb.axi_arvalid <= 0; |
end |
join_none |
|
wait( cb.axi_rvalid ); |
data = axi_rdata; |
fork |
begin |
// wait( cb.axi_arready ); |
##(axi_rready_delay); |
cb.axi_rready <= 1; |
|
// optional delay here |
cb.axi_rready <= 0; |
wait( cb.axi_rvalid ); |
data = axi_rdata; |
|
##1; |
cb.axi_rready <= 0; |
end |
join_none |
|
wait( cb.axi_rvalid & axi_rready ); |
$strobe("^^^ %16.t | %m | 0x%h @ 0x%h", $time, data, addr ); |
##1; |
|
endtask: read |
|
264,40 → 305,55
input int wstrb |
); |
|
$strobe("^^^ %16.t | %m | 0x%h @ 0x%h | %b", $time, data, addr, wstrb ); |
fork |
begin |
##0; |
cb.axi_awaddr <= addr; |
cb.axi_awprot <= 0; |
cb.axi_awvalid <= 1; |
|
cb.axi_bready <= 0; |
cb.axi_awaddr <= addr; |
cb.axi_wstrb <= wstrb; |
cb.axi_awprot <= 0; |
cb.axi_awvalid <= 0; |
if( cb.axi_awready ) // axi_awvalid must be asserted for at least one clock |
##1; |
|
##0; |
cb.axi_awvalid <= 1; |
##1; |
wait( cb.axi_awready ); |
cb.axi_awvalid <= 0; |
end |
join_none |
|
// optional delay here |
axi_wdata = data; |
cb.axi_wvalid <= 1; |
|
wait( cb.axi_awready ); |
cb.axi_awvalid <= 0; |
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wait( cb.axi_wready ); |
cb.axi_wvalid <= 0; |
fork |
begin |
// optional delay here |
##(axi_wvalid_delay); |
axi_wdata = data; |
cb.axi_wstrb <= wstrb; |
cb.axi_wvalid <= 1; |
|
wait( cb.axi_bvalid ); |
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// optional delay here |
cb.axi_bready <= 1; |
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if( cb.axi_wready ) // axi_wvalid must be asserted for at least one clock |
##1; |
|
wait( cb.axi_wready ); |
cb.axi_wvalid <= 0; |
end |
join_none |
|
fork |
begin |
##1; |
// optional delay here |
##(axi_bready_delay); |
axi_bready <= 1; |
|
if( cb.axi_bvalid ) // axi_bready must be asserted for at least one clock |
##1; |
|
wait( cb.axi_bvalid ); |
cb.axi_bready <= 0; |
end |
join_none |
|
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wait( cb.axi_bvalid & axi_bready ); |
$strobe("^^^ %16.t | %m | 0x%h @ 0x%h | %b", $time, data, addr, wstrb ); |
##1; |
|
endtask: write |
|
endclass: qaz_axi4_bfm |