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URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

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  • This comparison shows the changes necessary to convert path 
    /qaz_libs
    from Rev 49 to Rev 50
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  •

Rev 49 → Rev 50

/trunk/BFM/sim/tests/tb_video_frame_dpi/py_raw_to_frame.py File deleted \ No newline at end of file
/trunk/BFM/src/SPI/spi_agent.svh
25,32 → 25,24
//// ////
//////////////////////////////////////////////////////////////////////
 
class spi_agent
class spi_agent #(N=1)
extends uvm_agent;
`uvm_component_utils(spi_agent)
`uvm_component_param_utils(spi_agent #(N))
 
// --------------------------------------------------------------------
virtual spi_if vif;
spi_driver driver_h;
virtual spi_if #(N) vif;
spi_driver #(N) driver_h;
spi_sequencer sequencer_h;
// spi_monitor monitor_h;
 
// --------------------------------------------------------------------
virtual function void build_phase(uvm_phase phase);
// super.build_phase(phase);
driver_h = spi_driver::type_id::create("driver_h", this);
// monitor_h = spi_monitor ::type_id::create("monitor_h", this);
driver_h = spi_driver #(N)::type_id::create("driver_h", this);
sequencer_h = spi_sequencer::type_id::create("sequencer_h", this);
 
endfunction
 
// --------------------------------------------------------------------
virtual function void connect_phase(uvm_phase phase);
// super.connect_phase(phase);
 
driver_h.vif = vif;
// monitor_h.vif = vif;
 
driver_h.seq_item_port.connect(sequencer_h.seq_item_export);
endfunction
 
60,4 → 52,4
endfunction
 
// --------------------------------------------------------------------
endclass : spi_agent
endclass
/trunk/BFM/src/SPI/spi_driver.svh
25,17 → 25,17
//// ////
//////////////////////////////////////////////////////////////////////
 
class spi_driver
class spi_driver #(N)
extends uvm_driver #(spi_sequence_item);
`uvm_component_utils(spi_driver)
`uvm_component_param_utils(spi_driver #(N))
 
// --------------------------------------------------------------------
virtual spi_if vif;
virtual spi_if #(N) vif;
 
//--------------------------------------------------------------------
function void set_default;
vif.sclk <= 0;
vif.ss_n <= 1;
vif.ss_n <= '1;
vif.mosi <= 'x;
endfunction: set_default
 
51,7 → 51,8
index = 0;
seq_item_port.get_next_item(item);
 
vif.ss_n <= 0;
vif.ss_n <= ~(1 << item.ss_index);
 
vif.mosi <= item.mosi_data[index];
#(vif.period / 2);
 
75,7 → 76,7
end
 
#(vif.period / 2);
vif.ss_n <= 1;
vif.ss_n <= '1;
 
set_default();
seq_item_port.item_done();
89,4 → 90,4
endfunction
 
// --------------------------------------------------------------------
endclass : spi_driver
endclass
/trunk/BFM/src/SPI/spi_if.sv
25,8 → 25,7
//// ////
//////////////////////////////////////////////////////////////////////
 
interface
spi_if();
interface spi_if #(N=1);
import uvm_pkg::*;
`include "uvm_macros.svh"
import tb_spi_pkg::*;
33,7 → 32,7
 
// --------------------------------------------------------------------
logic sclk;
logic ss_n;
logic [N-1:0] ss_n;
logic mosi;
logic miso;
 
/trunk/BFM/src/SPI/spi_sequence_item.svh
35,6 → 35,7
// --------------------------------------------------------------------
logic miso_data[]; // data from slave to master
logic mosi_data[]; // data from master to slave
int ss_index = 0;
bit read;
bit write;
 
56,38 → 57,34
mosi_data[i] = 0;
endfunction : init
 
// // --------------------------------------------------------------------
// function bit do_compare(uvm_object rhs, uvm_comparer comparer);
// spi_sequence_item tested;
// bit same;
// --------------------------------------------------------------------
function void load_mosi_from_file(string file_name);
byte buffer;
integer fd;
integer code;
integer size;
 
// if (rhs==null)
// `uvm_fatal(get_type_name(), "| %m | comparison to a null pointer");
fd = $fopen(file_name, "rb");
code = $fseek(fd, 0, 2); // SEEK_END
size = $ftell(fd);
code = $rewind(fd);
data_width = size*8;
mosi_data = new[data_width];
write = 1;
 
// if (!$cast(tested,rhs))
// same = 0;
// else
// same = super.do_compare(rhs, comparer);
for(int i = 0; i < size; i++) begin
code = $fread(buffer, fd);
mosi_data[i*8 +: 8] = {>>{buffer}};
end
 
// return same;
// endfunction : do_compare
$fclose(fd);
endfunction
 
// // --------------------------------------------------------------------
// function void do_copy(uvm_object rhs);
// spi_sequence_item item;
// assert(rhs != null) else
// `uvm_fatal(get_type_name(), "| %m | copy null transaction");
// super.do_copy(rhs);
// assert($cast(item,rhs)) else
// `uvm_fatal(get_type_name(), "| %m | failed cast");
// delay = item.delay;
// command = item.command;
// wr_full = item.wr_full;
// rd_empty = item.rd_empty;
// wr_data = item.wr_data;
// rd_data = item.rd_data;
// count = item.count;
// endfunction : do_copy
// --------------------------------------------------------------------
function void load_mosi_from_byte_array(byte byte_array[]);
foreach(byte_array[i])
mosi_data[i*8 +: 8] = {>>{byte_array[i]}};
endfunction
 
// --------------------------------------------------------------------
function string convert2string();
102,8 → 99,7
);
s0 = {s0, s1};
 
if(read)
begin
if(read) begin
data = {>>{miso_data}};
 
foreach(data[i])
113,8 → 109,7
s0 = {s0, s2};
end
 
if(write)
begin
if(write) begin
data = {>>{mosi_data}};
 
foreach(data[i])
128,4 → 123,4
endfunction : convert2string
 
// --------------------------------------------------------------------
endclass : spi_sequence_item
endclass
/trunk/BFM/src/SPI/tb_spi_pkg.sv
28,28 → 28,12
package tb_spi_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
import bfm_pkg::*;
 
// // --------------------------------------------------------------------
// localparam W = 16;
// localparam D = 8;
// localparam UB = $clog2(D);
 
// --------------------------------------------------------------------
// typedef enum {FIFO_RD, FIFO_WR, FIFO_BOTH, FIFO_NULL} fifo_command_t;
 
// --------------------------------------------------------------------
`include "spi_sequence_item.svh"
typedef uvm_sequencer #(spi_sequence_item) spi_sequencer;
`include "spi_driver.svh"
// `include "spi_monitor.svh"
// `include "spi_scoreboard.svh"
`include "spi_agent.svh"
// `include "tb_env.svh"
// `include "s_debug.svh"
// `include "t_top_base.svh"
// `include "t_debug.svh"
 
// --------------------------------------------------------------------
endpackage : tb_spi_pkg
endpackage
/trunk/BFM/src/axis_video_frame/axis_video_frame_bfm_pkg.sv File deleted
/trunk/BFM/src/axis_video_frame/avf_agent_class_pkg.sv File deleted
/trunk/BFM/src/axis_video_frame/avf_rx.sv File deleted
/trunk/BFM/src/axis_video_frame/avf_agent.sv File deleted
/trunk/BFM/src/axis_video_frame/avf_tx.sv File deleted
/trunk/BFM/src/tb/tb_bfm_pkg.sv File deleted
/trunk/BFM/src/tb/bfm_pkg.sv File deleted
/trunk/BFM/src/tb/tb_clk_pkg.sv File deleted
/trunk/BFM/src/tb/q_pkg.sv File deleted
/trunk/BFM/src/tb/tb_clk_class.sv File deleted
/trunk/BFM/src/tb/logger_pkg.sv File deleted
/trunk/BFM/src/tb/tb_clk.sv File deleted
/trunk/BFM/src/tb/legacy/bfm_pkg.sv
0,0 → 1,106
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package bfm_pkg;
 
// --------------------------------------------------------------------
//
typedef enum
{
NONE,
REGULAR
// BURSTY
} traffic_type_e;
 
// --------------------------------------------------------------------
//
class delay_class;
 
rand int unsigned delay = 0;
 
// --------------------------------------------------------------------
//
virtual function void set_delay(traffic_type_e kind = REGULAR);
case(kind)
NONE: delay = 0;
REGULAR: assert(this.randomize() with{delay dist {0 := 60, [1:3] := 30, [4:7] := 10};});
default: delay = 0;
endcase
endfunction: set_delay
 
// --------------------------------------------------------------------
//
virtual function int next(traffic_type_e kind = REGULAR);
set_delay(kind);
return(delay);
endfunction: next
 
// --------------------------------------------------------------------
//
endclass: delay_class
 
// --------------------------------------------------------------------
//
virtual class transaction_class #(parameter type TR_T);
 
delay_class delay_h;
 
// --------------------------------------------------------------------
//
function void random;
assert(this.randomize());
endfunction: random
 
//--------------------------------------------------------------------
//
function new;
delay_h = new();
endfunction: new
 
// --------------------------------------------------------------------
//
pure virtual function void copy(TR_T from);
 
// --------------------------------------------------------------------
//
function automatic TR_T clone;
TR_T child;
clone = new();
$cast(child, this);
clone.copy(child);
return(clone);
endfunction: clone
 
// --------------------------------------------------------------------
//
endclass: transaction_class
 
//--------------------------------------------------------------------
//
endpackage: bfm_pkg
 
/trunk/BFM/src/tb/legacy/logger_pkg.sv
0,0 → 1,136
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package logger_pkg;
 
// --------------------------------------------------------------------
//
typedef enum
{
FATAL,
ERROR,
WARNING,
INFO
} logger_severity_t;
 
 
// --------------------------------------------------------------------
//
class logger_class;
 
logger_severity_t verbosity = WARNING;
bit log_debug = 0;
string time_string;
int error_count = 0;
int max_error_display = 8;
bit stop_at_max_error = 1;
 
// --------------------------------------------------------------------
//
function void
set_verbosity(logger_severity_t level);
verbosity = level;
endfunction: set_verbosity
 
 
// --------------------------------------------------------------------
//
function void
debug_enable;
log_debug = 1;
endfunction: debug_enable
 
 
// --------------------------------------------------------------------
//
function void debug(string message);
time_string = $sformatf("??? %16.t | ", $time);
if(log_debug == 1)
$display({time_string, message});
endfunction: debug
 
 
// --------------------------------------------------------------------
//
function void display(string message);
time_string = $sformatf("--- %16.t | ", $time);
$display({time_string, message});
endfunction: display
 
 
// --------------------------------------------------------------------
//
function void info(string message);
time_string = $sformatf("^^^ %16.t | ", $time);
if(verbosity >= INFO)
$display({time_string, message});
endfunction: info
 
 
// --------------------------------------------------------------------
//
function void warning(string message);
time_string = $sformatf("*** %16.t | ", $time);
if(verbosity >= WARNING)
$display({time_string, message});
endfunction: warning
 
 
// --------------------------------------------------------------------
//
function void error(string message);
time_string = $sformatf("!!! %16.t | ", $time);
error_count++;
if(error_count > max_error_display)
if(stop_at_max_error)
$stop;
else
return;
if(verbosity >= ERROR)
$display({time_string, message});
endfunction: error
 
 
// --------------------------------------------------------------------
//
function void fatal(string message);
if(verbosity >= FATAL)
$fatal(1, message);
endfunction: fatal
 
 
//--------------------------------------------------------------------
//
endclass: logger_class
 
 
//--------------------------------------------------------------------
//
endpackage: logger_pkg
 
/trunk/BFM/src/tb/legacy/q_pkg.sv
0,0 → 1,147
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package q_pkg;
 
// --------------------------------------------------------------------
//
virtual class q_base_class #(parameter type Q_T = logic);
 
Q_T tr_h;
mailbox #(Q_T) q;
 
// --------------------------------------------------------------------
//
pure virtual task run_q;
 
 
// --------------------------------------------------------------------
//
task put(ref Q_T tr_h);
q.put(tr_h);
endtask: put
 
 
// --------------------------------------------------------------------
//
task get(ref Q_T tr_h);
q.get(tr_h);
endtask: get
 
 
//--------------------------------------------------------------------
function new;
this.q = new();
fork
forever
run_q();
join_none
endfunction: new
 
 
// --------------------------------------------------------------------
//
endclass: q_base_class
 
 
// --------------------------------------------------------------------
//
virtual class nonblocking_transmission_q_class #(parameter type Q_T = logic)
extends q_base_class #(Q_T);
 
// --------------------------------------------------------------------
//
pure virtual task transmit(ref Q_T tr_h);
pure virtual task idle();
 
 
// --------------------------------------------------------------------
//
task automatic run_q;
if(q.try_get(tr_h) != 0)
transmit(tr_h);
else
idle();
endtask: run_q
 
 
// --------------------------------------------------------------------
//
endclass: nonblocking_transmission_q_class
 
 
// --------------------------------------------------------------------
//
virtual class blocking_transmission_q_class #(parameter type Q_T = logic)
extends q_base_class #(Q_T);
 
// --------------------------------------------------------------------
//
pure virtual task transmit(ref Q_T tr_h);
 
 
// --------------------------------------------------------------------
//
task run_q;
q.get(tr_h);
transmit(tr_h);
endtask: run_q
 
 
// --------------------------------------------------------------------
//
endclass: blocking_transmission_q_class
 
 
// --------------------------------------------------------------------
//
virtual class blocking_receiver_q_class #(parameter type Q_T = logic)
extends q_base_class #(Q_T);
 
// --------------------------------------------------------------------
//
pure virtual task receive(ref Q_T tr_h);
 
 
// --------------------------------------------------------------------
//
task run_q;
receive(tr_h);
q.put(tr_h);
endtask: run_q
 
 
//--------------------------------------------------------------------
//
endclass: blocking_receiver_q_class
 
 
//--------------------------------------------------------------------
//
endpackage: q_pkg
 
/trunk/BFM/src/tb/legacy/tb_base.sv
0,0 → 1,106
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
import tb_clk_pkg::*;
 
 
module
tb_base
#(
parameter PERIOD = 0,
parameter ASSERT_TIME = 0
)
(
output clock,
output reg reset
);
 
// --------------------------------------------------------------------
//
task assert_reset
(
input time reset_assert
);
 
reset = 1;
$display( "-#- %16.t | %m | reset asserted!", $time );
 
#reset_assert;
 
reset = 0;
$display( "-#- %16.t | %m | reset deasserted!", $time );
 
endtask
 
 
// --------------------------------------------------------------------
//
task timeout_stop
(
input time timeout
);
 
$display("-#- %16.t | %m | timeout_stop at %t", $time, timeout);
 
fork
#(timeout) $stop;
join_none
 
endtask
 
 
// --------------------------------------------------------------------
//
tb_clk_class tb_clk_c;
tb_clk_if tb_clk_driver();
assign clock = tb_clk_driver.clk;
time reset_assert = (PERIOD * 5) + (PERIOD / 3);
logic init_done = 0;
 
initial
begin
 
reset = 1;
 
tb_clk_c = new( tb_clk_driver );
 
if( PERIOD != 0 )
tb_clk_c.init_basic_clock( PERIOD );
 
if( ASSERT_TIME != 0 )
assert_reset( ASSERT_TIME );
else if( reset_assert != 0 )
assert_reset( reset_assert );
 
init_done = 1;
 
end
endmodule
 
 
/trunk/BFM/src/tb/legacy/tb_bfm_pkg.sv
0,0 → 1,230
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
package tb_bfm_pkg;
 
// --------------------------------------------------------------------
//
class tb_nonblocking_transaction_q_class #(parameter type T = logic);
 
T tr_h;
mailbox #(T) q;
semaphore q_semaphore;
 
//--------------------------------------------------------------------
function new;
 
this.q = new();
this.q_semaphore = new(1);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
event start;
event done;
 
virtual task automatic
transaction
(
ref T tr_h
);
 
->start;
 
$display("^^^ %16.t | %m | ERROR! Task not defined |", $time);
 
->done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
virtual task automatic
idle;
 
$display("^^^ %16.t | %m | ERROR! Task not defined |", $time);
 
endtask: idle
 
 
// --------------------------------------------------------------------
//
task
put
(
ref T tr_h
);
 
$display("^^^ %16.t | %m | ", $time);
 
q.put(tr_h);
 
endtask: put
 
 
// --------------------------------------------------------------------
//
task automatic
run_q;
 
if(q_semaphore.try_get() == 0)
begin
$display("^^^ %16.t | %m | ERROR! Aready active |", $time);
return;
end
 
$display("^^^ %16.t | %m is active |", $time);
 
run_q_fork : fork
forever
if(q.try_get(tr_h) != 0)
transaction(tr_h);
else
idle();
join_none
 
#0;
 
endtask: run_q
 
 
// --------------------------------------------------------------------
//
function void
init;
 
fork
run_q();
join_none
 
$display("^^^ %16.t | %m | initialization", $time);
 
endfunction: init
 
endclass: tb_nonblocking_transaction_q_class
 
 
// --------------------------------------------------------------------
//
class tb_blocking_transaction_q_class #(parameter type T = logic);
 
T tr_h;
mailbox #(T) q;
semaphore q_semaphore;
 
//--------------------------------------------------------------------
function new;
 
this.q = new();
this.q_semaphore = new(1);
 
endfunction: new
 
 
// --------------------------------------------------------------------
//
event start;
event done;
 
virtual task automatic
transaction
(
ref T tr_h
);
 
->start;
 
$display("^^^ %16.t | %m | ERROR! Task not defined |", $time);
 
->done;
 
endtask: transaction
 
 
// --------------------------------------------------------------------
//
task
put
(
ref T tr_h
);
 
q.put(tr_h);
 
endtask: put
 
 
// --------------------------------------------------------------------
//
task automatic
run_q;
 
if(q_semaphore.try_get() == 0)
begin
$display("^^^ %16.t | %m | ERROR! Aready active |", $time);
return;
end
 
$display("^^^ %16.t | %m is active |", $time);
 
this.q = new();
 
run_q_fork : fork
forever
begin
q.get(tr_h);
transaction(tr_h);
end
join_none
 
#0;
 
endtask: run_q
 
 
// --------------------------------------------------------------------
//
function void
init;
 
fork
run_q();
join_none
 
$display("^^^ %16.t | %m | initialization", $time);
 
endfunction: init
 
endclass: tb_blocking_transaction_q_class
 
 
endpackage: tb_bfm_pkg
 
/trunk/BFM/src/tb/legacy/tb_clk.sv
0,0 → 1,55
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
import tb_clk_pkg::*;
 
module
tb_clk
#(
parameter PERIOD = 0
)
(
output clock
);
 
tb_clk_class tb_clk_c;
tb_clk_if tb_clk_driver();
assign clock = tb_clk_driver.clk;
 
initial
begin
 
tb_clk_c = new( tb_clk_driver );
 
if( PERIOD != 0 )
tb_clk_c.init_basic_clock( PERIOD );
 
end
 
endmodule
 
 
/trunk/BFM/src/tb/legacy/tb_clk_class.sv
0,0 → 1,110
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
// --------------------------------------------------------------------
//
interface tb_clk_if;
logic clk = 0;
logic enable = 0;
time period;
event clk_rise;
event clk_fall;
modport tb_m
(
output clk
);
endinterface: tb_clk_if
 
 
// --------------------------------------------------------------------
//
class
tb_clk_class;
virtual tb_clk_if tb;
 
// --------------------------------------------------------------------
//
function
new
(
virtual tb_clk_if tb
);
this.tb = tb;
endfunction: new
 
// --------------------------------------------------------------------
//
task
init_basic_clock
(
time period
);
tb.period = period;
tb.enable = 1;
$display( "^^^ %16.t | %m | Starting clock with period %t.", $time, period );
fork
forever
if( tb.enable )
begin
#(period/2) tb.clk = 1;
-> tb.clk_rise;
#(period/2) tb.clk = 0;
-> tb.clk_fall;
end
join_none
endtask: init_basic_clock
// --------------------------------------------------------------------
//
task
enable_clock
(
logic enable
);
tb.enable = enable;
$display( "^^^ %16.t | %m | Clock Enable = %h.", $time, enable );
endtask: enable_clock
endclass: tb_clk_class
 
 
/trunk/BFM/src/tb/legacy/tb_clk_pkg.sv
0,0 → 1,118
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
 
// --------------------------------------------------------------------
//
interface tb_clk_if;
logic clk = 0;
logic enable = 0;
time period;
event clk_rise;
event clk_fall;
modport tb_m
(
output clk
);
endinterface: tb_clk_if
 
 
// --------------------------------------------------------------------
//
package tb_clk_pkg;
 
// --------------------------------------------------------------------
//
class
tb_clk_class;
virtual tb_clk_if tb;
 
// --------------------------------------------------------------------
//
function
new
(
virtual tb_clk_if tb
);
this.tb = tb;
endfunction: new
 
// --------------------------------------------------------------------
//
task
init_basic_clock
(
time period
);
tb.period = period;
tb.enable = 1;
$display( "^^^ %16.t | %m | Starting clock with period %t.", $time, period );
fork
forever
if( tb.enable )
begin
#(period/2) tb.clk = 1;
-> tb.clk_rise;
#(period/2) tb.clk = 0;
-> tb.clk_fall;
end
join_none
endtask: init_basic_clock
// --------------------------------------------------------------------
//
task
enable_clock
(
logic enable
);
tb.enable = enable;
$display( "^^^ %16.t | %m | Clock Enable = %h.", $time, enable );
endtask: enable_clock
// --------------------------------------------------------------------
//
endclass: tb_clk_class
//--------------------------------------------------------------------
//
endpackage: tb_clk_pkg
 
/trunk/BFM/src/tb/tb_base.sv
1,6 → 1,6
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
25,82 → 25,62
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ps/1ps
 
import tb_clk_pkg::*;
 
 
module
tb_base
#(
parameter PERIOD = 0,
parameter ASSERT_TIME = 0
N = 1,
realtime PERIODS[N],
realtime ASSERT_TIME = (PERIODS[0] * 5) + (PERIODS[0] / 3)
)
(
output clock,
output reg reset
output bit tb_clk[N],
output bit tb_aresetn,
output bit tb_reset[N]
);
timeunit 1ns;
timeprecision 100ps;
 
// --------------------------------------------------------------------
//
task assert_reset
(
input time reset_assert
);
function void assert_reset(realtime reset_assert=ASSERT_TIME);
fork
begin
tb_aresetn = 0;
#reset_assert;
tb_aresetn = 1;
end
join_none
endfunction
 
reset = 1;
$display( "-#- %16.t | %m | reset asserted!", $time );
// --------------------------------------------------------------------
bit disable_clks[N];
 
#reset_assert;
generate
for(genvar j = 0; j < N; j++) begin
always
if(disable_clks[j])
tb_clk[j] = 0;
else
#(PERIODS[j]/2) tb_clk[j] = ~tb_clk[j];
end
endgenerate
 
reset = 0;
$display( "-#- %16.t | %m | reset deasserted!", $time );
 
endtask
 
 
// --------------------------------------------------------------------
//
task timeout_stop
(
input time timeout
);
generate
for(genvar j = 0; j < N; j++) begin
bit reset = 1;
assign tb_reset[j] = reset;
 
$display("-#- %16.t | %m | timeout_stop at %t", $time, timeout);
always @(posedge tb_clk[j] or negedge tb_aresetn)
if(~tb_aresetn)
reset = 1;
else
reset = 0;
end
endgenerate
 
fork
#(timeout) $stop;
join_none
 
endtask
 
 
// --------------------------------------------------------------------
//
tb_clk_class tb_clk_c;
tb_clk_if tb_clk_driver();
assign clock = tb_clk_driver.clk;
time reset_assert = (PERIOD * 5) + (PERIOD / 3);
logic init_done = 0;
 
initial
begin
assert_reset();
 
reset = 1;
 
tb_clk_c = new( tb_clk_driver );
 
if( PERIOD != 0 )
tb_clk_c.init_basic_clock( PERIOD );
 
if( ASSERT_TIME != 0 )
assert_reset( ASSERT_TIME );
else if( reset_assert != 0 )
assert_reset( reset_assert );
 
init_done = 1;
 
end
// --------------------------------------------------------------------
endmodule
 
 
/trunk/BFM/src/tb/tb_pkg.sv
31,4 → 31,4
`include "random_delay.svh"
 
// --------------------------------------------------------------------
endpackage : tb_pkg
endpackage
/trunk/BFM/src/video_frame/video_frame_class.svh
27,7 → 27,6
 
// --------------------------------------------------------------------
class video_frame_class;
logger_class log;
rand int frame_id;
rand int pixels_per_line;
rand int lines_per_frame;
59,7 → 58,6
 
//--------------------------------------------------------------------
function new;
this.log = new;
this.frame_id = 0;
endfunction: new
 
72,7 → 70,6
int pixels_per_clk = 1,
string name = ""
);
log.info($sformatf("%m"));
this.pixels_per_line = pixels_per_line;
this.lines_per_frame = lines_per_frame;
this.bits_per_pixel = bits_per_pixel;
113,7 → 110,6
 
// --------------------------------------------------------------------
function void make_constant(int pixel);
log.info($sformatf("%m"));
this.lines = new[lines_per_frame];
 
foreach(this.lines[l])
129,7 → 125,6
 
// --------------------------------------------------------------------
function void make_counting(int offset = 0);
log.info($sformatf("%m"));
this.lines = new[lines_per_frame];
 
foreach(this.lines[l])
145,7 → 140,6
 
// --------------------------------------------------------------------
function void make_horizontal();
log.info($sformatf("%m"));
this.lines = new[lines_per_frame];
 
foreach(this.lines[l])
161,7 → 155,6
 
// --------------------------------------------------------------------
function void make_vertical();
log.info($sformatf("%m"));
this.lines = new[lines_per_frame];
 
foreach(this.lines[l])
177,7 → 170,6
 
// --------------------------------------------------------------------
function void make_random();
log.info($sformatf("%m"));
this.lines = new[lines_per_frame];
 
foreach(this.lines[l])
193,7 → 185,6
 
// --------------------------------------------------------------------
function void copy(video_frame_class from);
log.info($sformatf("%m"));
this.frame_id = from.frame_id;
this.pixels_per_line = from.pixels_per_line;
this.lines_per_frame = from.lines_per_frame;
212,7 → 203,6
 
// --------------------------------------------------------------------
virtual function video_frame_class clone;
log.info($sformatf("%m"));
clone = new();
clone.copy(this);
endfunction: clone
219,7 → 209,6
 
// --------------------------------------------------------------------
function video_frame_class catenate_horizontally(video_frame_class tail);
log.info($sformatf("%m"));
 
if(this.lines_per_frame != tail.lines_per_frame)
return(null);
248,7 → 237,6
 
// --------------------------------------------------------------------
function void shift_right(ref line_s column);
log.info($sformatf("%m"));
 
foreach(this.lines[l])
for(int p = pixels_per_line - 1; p > 0; p--)
258,114 → 246,127
this.lines[l].pixel[0] = column.pixel[l];
endfunction: shift_right
 
// --------------------------------------------------------------------
function int compare_line
( int line
, int max_mismatches
, video_frame_class to
);
int mismatch_count = 0;
// // --------------------------------------------------------------------
// function int compare_line
// ( int line
// , int max_mismatches
// , video_frame_class to
// );
// int mismatch_count = 0;
 
if(to.bits_per_pixel != this.bits_per_pixel)
begin
log.error($sformatf("to.bits_per_pixel != this.bits_per_pixel | %s", name));
return(-3);
end
// if(to.bits_per_pixel != this.bits_per_pixel)
// begin
// log.error($sformatf("to.bits_per_pixel != this.bits_per_pixel | %s", name));
// return(-3);
// end
 
foreach(this.lines[line].pixel[p])
if(to.lines[line].pixel[p] != this.lines[line].pixel[p])
begin
// foreach(this.lines[line].pixel[p])
// if(to.lines[line].pixel[p] != this.lines[line].pixel[p])
// begin
 
if(max_mismatches > 0)
mismatch_count++;
// if(max_mismatches > 0)
// mismatch_count++;
 
log.error($sformatf("mismatch @ frame[%4h][%4h] | to == %4h | this == %4h | %s",
line, p, to.lines[line].pixel[p], this.lines[line].pixel[p], name));
// log.error($sformatf("mismatch @ frame[%4h][%4h] | to == %4h | this == %4h | %s",
// line, p, to.lines[line].pixel[p], this.lines[line].pixel[p], name));
 
if(mismatch_count > max_mismatches)
return(mismatch_count);
end
// if(mismatch_count > max_mismatches)
// return(mismatch_count);
// end
 
return(mismatch_count);
endfunction: compare_line
// return(mismatch_count);
// endfunction: compare_line
 
// --------------------------------------------------------------------
function int compare(int max_mismatches, video_frame_class to);
int mismatch_count = 0;
log.info($sformatf("%m"));
// // --------------------------------------------------------------------
// function int compare(int max_mismatches, video_frame_class to);
// int mismatch_count = 0;
// log.info($sformatf("%m"));
 
if(to.pixels_per_line != this.pixels_per_line)
begin
log.error($sformatf("to.pixels_per_line != this.pixels_per_line | %s", name));
return(-1);
end
// if(to.pixels_per_line != this.pixels_per_line)
// begin
// log.error($sformatf("to.pixels_per_line != this.pixels_per_line | %s", name));
// return(-1);
// end
 
if(to.lines_per_frame != this.lines_per_frame)
begin
log.error($sformatf("to.lines_per_frame != this.lines_per_frame | %s", name));
return(-2);
end
// if(to.lines_per_frame != this.lines_per_frame)
// begin
// log.error($sformatf("to.lines_per_frame != this.lines_per_frame | %s", name));
// return(-2);
// end
 
if(to.bits_per_pixel != this.bits_per_pixel)
begin
log.error($sformatf("to.bits_per_pixel != this.bits_per_pixel | %s", name));
return(-3);
end
// if(to.bits_per_pixel != this.bits_per_pixel)
// begin
// log.error($sformatf("to.bits_per_pixel != this.bits_per_pixel | %s", name));
// return(-3);
// end
 
foreach(this.lines[l])
begin
foreach(this.lines[l].pixel[p])
if(to.lines[l].pixel[p] != this.lines[l].pixel[p])
begin
if(max_mismatches > 0)
mismatch_count++;
// foreach(this.lines[l])
// begin
// foreach(this.lines[l].pixel[p])
// if(to.lines[l].pixel[p] != this.lines[l].pixel[p])
// begin
// if(max_mismatches > 0)
// mismatch_count++;
 
log.error($sformatf("mismatch @ frame[%4h][%4h] | to == %4h | this == %4h | %s", l, p, to.lines[l].pixel[p], this.lines[l].pixel[p], name));
// log.error($sformatf("mismatch @ frame[%4h][%4h] | to == %4h | this == %4h | %s", l, p, to.lines[l].pixel[p], this.lines[l].pixel[p], name));
 
if(mismatch_count > max_mismatches)
return(mismatch_count);
end
end
// if(mismatch_count > max_mismatches)
// return(mismatch_count);
// end
// end
 
return(mismatch_count);
endfunction: compare
// return(mismatch_count);
// endfunction: compare
 
// --------------------------------------------------------------------
function void print_line(int line, int pixel, int count);
log.info($sformatf("%m"));
// // --------------------------------------------------------------------
// function void print_line(int line, int pixel, int count);
// log.info($sformatf("%m"));
 
for(int i = 0; i < count; i++)
log.display($sformatf("%4h @ frame[%4h][%4h] | %s", this.lines[line].pixel[(pixel + i)], line, (pixel + i), name));
endfunction: print_line
// for(int i = 0; i < count; i++)
// log.display($sformatf("%4h @ frame[%4h][%4h] | %s", this.lines[line].pixel[(pixel + i)], line, (pixel + i), name));
// endfunction: print_line
 
// // --------------------------------------------------------------------
// function void print_config();
// log.display($sformatf("%m | frame_id = %06d | %s", frame_id, name));
// log.display($sformatf("%m | pixels_per_line = %06d | %s", pixels_per_line, name));
// log.display($sformatf("%m | lines_per_frame = %06d | %s", lines_per_frame, name));
// log.display($sformatf("%m | bits_per_pixel = %06d | %s", bits_per_pixel, name));
// log.display($sformatf("%m | pixels_per_clk = %06d | %s", pixels_per_clk, name));
// log.display($sformatf("%m | pattern = %s | %s", pattern, name));
// endfunction: print_config
 
// --------------------------------------------------------------------
function void print_config();
log.display($sformatf("%m | frame_id = %06d | %s", frame_id, name));
log.display($sformatf("%m | pixels_per_line = %06d | %s", pixels_per_line, name));
log.display($sformatf("%m | lines_per_frame = %06d | %s", lines_per_frame, name));
log.display($sformatf("%m | bits_per_pixel = %06d | %s", bits_per_pixel, name));
log.display($sformatf("%m | pixels_per_clk = %06d | %s", pixels_per_clk, name));
log.display($sformatf("%m | pattern = %s | %s", pattern, name));
$display($sformatf("%m | frame_id = %06d | %s", frame_id, name));
$display($sformatf("%m | pixels_per_line = %06d | %s", pixels_per_line, name));
$display($sformatf("%m | lines_per_frame = %06d | %s", lines_per_frame, name));
$display($sformatf("%m | bits_per_pixel = %06d | %s", bits_per_pixel, name));
$display($sformatf("%m | pixels_per_clk = %06d | %s", pixels_per_clk, name));
$display($sformatf("%m | pattern = %s | %s", pattern, name));
endfunction: print_config
 
// --------------------------------------------------------------------
function string convert2string(int grid=8);
string s;
string s0, s1;
string f ="";
string fs = $sformatf("%%s%%%0d.h" , (bits_per_pixel % 4 == 0)
? bits_per_pixel / 4
: (bits_per_pixel / 4) + 1
);
foreach(this.lines[l])
begin
s = $sformatf("[%4.d]", l);
foreach(this.lines[l].pixel[p])
s = {s, $sformatf(fs, (p % grid == 0) ? "!" : "|", this.lines[l].pixel[p])};
int nibbles = ( bits_per_pixel % 4 == 0)
? bits_per_pixel / 4
: (bits_per_pixel / 4) + 1;
 
f = {f, s, "|\n"};
foreach(this.lines[l]) begin
s0 = $sformatf("[%4.d]", l);
foreach(this.lines[l].pixel[p]) begin
s1 = $sformatf("%.h", this.lines[l].pixel[p]);
s1 = s1.substr(nibbles, s1.len()-1);
s0 = {s0, (p % grid == 0) ? "!" : "|", s1};
end
 
f = {f, s0, "|\n"};
end
 
return f;
endfunction: convert2string
 
// --------------------------------------------------------------------
endclass: video_frame_class
endclass
/trunk/BFM/src/video_frame/video_frame_config.svh
57,4 → 57,4
endfunction : init
 
// --------------------------------------------------------------------
endclass: video_frame_config
endclass
/trunk/BFM/src/video_frame/video_frame_pkg.sv
26,7 → 26,6
//////////////////////////////////////////////////////////////////////
 
package video_frame_pkg;
import logger_pkg::*;
 
// --------------------------------------------------------------------
typedef struct
50,4 → 49,4
`include "video_frame_class.svh"
 
// --------------------------------------------------------------------
endpackage: video_frame_pkg
endpackage
/trunk/PCIe/sim/src/RIFFA/riffa_agent.svh
0,0 → 1,65
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class riffa_agent #(N) extends uvm_agent;
`uvm_component_param_utils(riffa_agent #(N))
 
// --------------------------------------------------------------------
virtual riffa_chnl_if #(N) vif;
riffa_rp_tx_driver #(N) rp_tx_driver_h;
riffa_rp_rx_driver #(N) rp_rx_driver_h;
riffa_rp_tx_sequencer rp_tx_sequencer_h;
riffa_rp_rx_sequencer rp_rx_sequencer_h;
// fifo_monitor monitor_h;
 
// --------------------------------------------------------------------
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
rp_tx_driver_h = riffa_rp_tx_driver #(N)::type_id::create("rp_tx_driver_h", this);
rp_rx_driver_h = riffa_rp_rx_driver #(N)::type_id::create("rp_rx_driver_h", this);
rp_tx_sequencer_h = riffa_rp_tx_sequencer::type_id::create("rp_tx_sequencer_h", this);
rp_rx_sequencer_h = riffa_rp_rx_sequencer::type_id::create("rp_rx_sequencer_h", this);
// monitor_h = fifo_monitor ::type_id::create("monitor_h", this);
endfunction
 
// --------------------------------------------------------------------
virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
rp_tx_driver_h.vif = vif;
rp_rx_driver_h.vif = vif;
// monitor_h.vif = vif;
rp_tx_driver_h.seq_item_port.connect(rp_tx_sequencer_h.seq_item_export);
rp_rx_driver_h.seq_item_port.connect(rp_rx_sequencer_h.seq_item_export);
endfunction
 
// --------------------------------------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/src/RIFFA/riffa_config.svh
0,0 → 1,49
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class riffa_config #(N);
 
virtual riffa_chnl_if #(N) vif;
 
// --------------------------------------------------------------------
uvm_active_passive_enum is_active;
 
function uvm_active_passive_enum get_is_active();
return is_active;
endfunction : get_is_active
 
// --------------------------------------------------------------------
function new
( virtual riffa_chnl_if #(N) vif
, uvm_active_passive_enum is_active = UVM_ACTIVE
);
this.vif = vif;
this.is_active = is_active;
endfunction : new
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/src/RIFFA/riffa_env.svh
0,0 → 1,54
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class riffa_env #(N) extends uvm_env;
`uvm_component_param_utils(riffa_env #(N));
 
// --------------------------------------------------------------------
riffa_config #(N) cfg_h;
// riffa_scoreboard scoreboard_h;
riffa_agent #(N) agent_h;
 
// --------------------------------------------------------------------
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction : new
 
// --------------------------------------------------------------------
function void build_phase(uvm_phase phase);
agent_h = riffa_agent #(N)::type_id::create("agent_h", this);
agent_h.vif = cfg_h.vif;
// scoreboard_h = riffa_scoreboard::type_id::create("scoreboard_h", this);
endfunction : build_phase
 
// // --------------------------------------------------------------------
// function void connect_phase(uvm_phase phase);
// agent_h.monitor_h.ap.connect(scoreboard_h.analysis_export);
// endfunction : connect_phase
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/src/RIFFA/riffa_pkg.sv
0,0 → 1,50
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
package riffa_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
 
// --------------------------------------------------------------------
typedef enum { RIFFA_TX_PAYLOAD // PCIe root RX from RIFFA
, RIFFA_RX_PAYLOAD // PCIe root TX to RIFFA
} riffa_transaction_t;
 
// --------------------------------------------------------------------
`include "riffa_config.svh"
`include "riffa_sequence_item.svh"
typedef uvm_sequencer #(riffa_sequence_item) riffa_rp_tx_sequencer;
typedef uvm_sequencer #(riffa_sequence_item) riffa_rp_rx_sequencer;
`include "riffa_rp_tx_driver.svh"
`include "riffa_rp_rx_driver.svh"
`include "riffa_agent.svh"
`include "riffa_env.svh"
`include "s_riffa_rp_tx_api.svh"
`include "s_riffa_rp_rx_api.svh"
 
// --------------------------------------------------------------------
endpackage
/trunk/PCIe/sim/src/RIFFA/riffa_rp_rx_driver.svh
0,0 → 1,86
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class riffa_rp_rx_driver #(N) extends uvm_driver #(riffa_sequence_item);
`uvm_component_param_utils(riffa_rp_rx_driver #(N))
 
// --------------------------------------------------------------------
virtual riffa_chnl_if #(N) vif;
 
//--------------------------------------------------------------------
function void set_default;
vif.cb_rp_rx.tx_ack <= 0;
vif.cb_rp_rx.tx_data_ren <= 0;
endfunction: set_default
 
//--------------------------------------------------------------------
virtual task run_phase(uvm_phase phase);
riffa_sequence_item item;
super.run_phase(phase);
 
set_default();
 
forever
begin
wait(~vif.tx_reset);
seq_item_port.get_next_item(item);
 
@(vif.cb_rp_rx iff vif.cb_rp_rx.tx);
 
item.init( N
, vif.cb_rp_rx.tx_len
, vif.cb_rp_rx.tx_off
, vif.cb_rp_rx.tx_last);
 
vif.cb_rp_rx.tx_ack <= 1;
vif.cb_rp_rx.tx_data_ren <= 1;
 
fork
@(vif.cb_rp_rx)
vif.cb_rp_rx.tx_ack <= 0;
join_none
 
for(int i = 0; i < item.beats; i++)
begin
@(vif.cb_rp_rx iff vif.cb_rp_rx.tx_data_valid)
{<<byte{item.data[i*N +: N]}} = vif.cb_rp_rx.tx_data;
 
// $display("^^^^^ %16.t | TX | %d | %h", $time, i, vif.cb_rp_rx.tx_data);
end
 
set_default();
seq_item_port.item_done();
end
endtask : run_phase
 
//--------------------------------------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/src/RIFFA/riffa_rp_tx_driver.svh
0,0 → 1,85
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class riffa_rp_tx_driver #(N) extends uvm_driver #(riffa_sequence_item);
`uvm_component_param_utils(riffa_rp_tx_driver #(N))
 
// --------------------------------------------------------------------
virtual riffa_chnl_if #(N) vif;
 
//--------------------------------------------------------------------
function void set_default;
vif.cb_rp_tx.rx <= 0;
vif.cb_rp_tx.rx_last <= 'bx;
vif.cb_rp_tx.rx_len <= 'bx;
vif.cb_rp_tx.rx_off <= 'bx;
vif.cb_rp_tx.rx_data <= 'bx;
vif.cb_rp_tx.rx_data_valid <= 0;
endfunction: set_default
 
//--------------------------------------------------------------------
virtual task run_phase(uvm_phase phase);
riffa_sequence_item item;
reg [(8*N)-1:0] rx_data;
super.run_phase(phase);
 
set_default();
 
forever
begin
wait(~vif.rx_reset);
seq_item_port.get_next_item(item);
 
@(vif.cb_rp_tx);
vif.cb_rp_tx.rx_len <= item.len; // must be => 4
vif.cb_rp_tx.rx_off <= item.off;
vif.cb_rp_tx.rx_last <= item.last;
vif.cb_rp_tx.rx <= 1;
 
@(vif.cb_rp_tx iff vif.cb_rp_tx.rx_ack);
vif.cb_rp_tx.rx_data_valid <= 1;
 
for(int i = 0; i < item.beats; i++)
begin
{<<byte{rx_data}} = item.data[i*N +: N];
vif.cb_rp_tx.rx_data <= rx_data;
@(vif.cb_rp_tx iff vif.cb_rp_tx.rx_data_ren);
// $display("^^^^^ %16.t | RX | %d | %h", $time, i, vif.cb_rp_tx.rx_data);
end
 
set_default();
seq_item_port.item_done();
end
endtask : run_phase
 
//--------------------------------------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/src/RIFFA/riffa_sequence_item.svh
0,0 → 1,118
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class riffa_sequence_item extends uvm_sequence_item;
`uvm_object_utils(riffa_sequence_item)
 
// --------------------------------------------------------------------
riffa_transaction_t tr;
int dwidth;
bit [31:0] len; // length in 4 byte words
bit [30:0] off;
bit last;
byte data[];
int beats;
 
// --------------------------------------------------------------------
int size;
int index = 0;
 
// --------------------------------------------------------------------
function void init(int dwidth, bit [31:0] len, bit [30:0] off, bit last);
this.dwidth = dwidth;
this.len = len;
this.size = len * 4;
this.data = new[size];
this.beats = ((size % dwidth) == 0) ? (size / dwidth) : (size / dwidth) + 1;
endfunction : init
 
// // --------------------------------------------------------------------
// function bit do_compare(uvm_object rhs, uvm_comparer comparer);
// riffa_sequence_item tested;
// bit same;
 
// if (rhs==null)
// `uvm_fatal(get_type_name(), "| %m | comparison to a null pointer");
 
// if (!$cast(tested,rhs))
// same = 0;
// else
// same = super.do_compare(rhs, comparer);
 
// return same;
// endfunction : do_compare
 
// --------------------------------------------------------------------
function void do_copy(uvm_object rhs);
riffa_sequence_item item;
assert(rhs != null) else
`uvm_fatal(get_type_name(), "| %m | copy null transaction");
super.do_copy(rhs);
assert($cast(item,rhs)) else
`uvm_fatal(get_type_name(), "| %m | failed cast");
 
tr = item.tr ;
dwidth = item.dwidth;
len = item.len ;
off = item.off ;
last = item.last ;
data = item.data ;
beats = item.beats ;
size = item.size ;
index = item.index ;
endfunction : do_copy
 
// // --------------------------------------------------------------------
// function string convert2string();
// string s0, s1, s2, s3;
// s0 = $sformatf( "| %m | wr | rd | full | empty |\n");
// s1 = $sformatf( "| %m | %1h | %1h | %1h | %1h |\n"
// , (command == FIFO_WR) || (command == FIFO_BOTH)
// , (command == FIFO_RD) || (command == FIFO_BOTH)
// , wr_full
// , rd_empty
// );
// s2 = $sformatf("| %m | wr_data: %h\n" , wr_data);
// s3 = $sformatf("| %m | rd_data: %h\n" , rd_data);
 
// if(command == FIFO_NULL)
// return {s1, s0};
// else if(command == FIFO_BOTH)
// return {s3, s2, s1, s0};
// else if(command == FIFO_WR)
// return {s2, s1, s0};
// else if(command == FIFO_RD)
// return {s3, s1, s0};
// endfunction : convert2string
 
// --------------------------------------------------------------------
function new(string name = "");
super.new(name);
endfunction : new
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/src/RIFFA/s_riffa_rp_rx_api.svh
0,0 → 1,50
// --------------------------------------------------------------------
class s_riffa_rp_rx_api extends uvm_sequence #(riffa_sequence_item);
`uvm_object_utils(s_riffa_rp_rx_api)
 
// --------------------------------------------------------------------
riffa_sequence_item item;
int dwidth;
// mailbox #(riffa_sequence_item) q;
 
// --------------------------------------------------------------------
uvm_sequencer_base o_seqr;
uvm_sequence_base o_parent;
 
function void init(uvm_sequencer_base o_seqr, uvm_sequence_base o_parent, int dwidth);
this.o_seqr = o_seqr;
this.o_parent = o_parent;
this.dwidth = dwidth;
endfunction : init
 
// --------------------------------------------------------------------
task display(bit [31:0] len, bit [30:0] off, bit last=1);
item = riffa_sequence_item::type_id::create("riffa_sequence_item");
item.tr = RIFFA_TX_PAYLOAD;
this.start(o_seqr, o_parent);
 
foreach(item.data[i])
$display("##### %d | 0x%h", i, item.data[i]);
endtask
 
// --------------------------------------------------------------------
task get(bit [31:0] len, bit [30:0] off, bit last=1);
item = riffa_sequence_item::type_id::create("riffa_sequence_item");
item.tr = RIFFA_TX_PAYLOAD;
this.start(o_seqr, o_parent);
endtask
 
// --------------------------------------------------------------------
task body();
start_item(item);
finish_item(item);
endtask
 
// --------------------------------------------------------------------
function new(string name = "s_riffa_rp_rx_api");
super.new(name);
// q = new;
endfunction
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/src/RIFFA/s_riffa_rp_tx_api.svh
0,0 → 1,66
// --------------------------------------------------------------------
class s_riffa_rp_tx_api extends uvm_sequence #(riffa_sequence_item);
`uvm_object_utils(s_riffa_rp_tx_api)
 
// --------------------------------------------------------------------
riffa_sequence_item item;
int dwidth;
// mailbox #(riffa_sequence_item) q;
 
// --------------------------------------------------------------------
uvm_sequencer_base o_seqr;
uvm_sequence_base o_parent;
 
function void init(uvm_sequencer_base o_seqr, uvm_sequence_base o_parent, int dwidth);
this.o_seqr = o_seqr;
this.o_parent = o_parent;
this.dwidth = dwidth;
endfunction : init
 
// --------------------------------------------------------------------
task counting(bit [31:0] len, bit [30:0] off, bit last=1);
item = riffa_sequence_item::type_id::create("riffa_sequence_item");
item.tr = RIFFA_RX_PAYLOAD;
item.init(dwidth, len, off, last);
 
foreach(item.data[i])
item.data[i] = i + 1;
 
this.start(o_seqr, o_parent);
endtask
 
// --------------------------------------------------------------------
task binary_file
( string file_name
, bit [31:0] len
, bit [30:0] off
, bit last=1);
 
integer fd;
integer code;
item = riffa_sequence_item::type_id::create("riffa_sequence_item");
item.tr = RIFFA_RX_PAYLOAD;
item.init(dwidth, len, off, last);
 
fd = $fopen(file_name, "rb");
code = $fread(item.data, fd);
$display("##### code = %x #####", code);
$fclose(fd);
 
this.start(o_seqr, o_parent);
endtask
 
// --------------------------------------------------------------------
task body();
start_item(item);
finish_item(item);
endtask
 
// --------------------------------------------------------------------
function new(string name = "s_riffa_rp_tx_api");
super.new(name);
// q = new;
endfunction
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/src/tb_riffa_debug/t_debug.svh
0,0 → 1,59
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class t_debug extends t_top_base;
`uvm_component_utils(t_debug)
 
// --------------------------------------------------------------------
function new(string name = "t_debug", uvm_component parent);
super.new(name, parent);
endfunction
 
// --------------------------------------------------------------------
function void end_of_elaboration_phase(uvm_phase phase);
uvm_phase run_phase = uvm_run_phase::get();
run_phase.phase_done.set_drain_time(this, 100ns);
endfunction
 
// --------------------------------------------------------------------
function void final_phase(uvm_phase phase);
super.final_phase(phase);
$display("^^^ %16.t | %m | Test Done!!!", $time);
$stop;
endfunction : final_phase
 
// --------------------------------------------------------------------
virtual task run_phase(uvm_phase phase);
vs_debug vseq = vs_debug::type_id::create("vseq");
phase.raise_objection(this);
vseq.init(env_h.riffa_env_h);
vseq.start(null);
phase.drop_objection(this);
endtask : run_phase
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/src/tb_riffa_debug/t_top_base.svh
0,0 → 1,43
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
virtual class t_top_base extends uvm_test;
`uvm_component_utils(t_top_base);
tb_env env_h;
 
// --------------------------------------------------------------------
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction : new
 
// --------------------------------------------------------------------
function void build_phase(uvm_phase phase);
env_h = tb_env::type_id::create("env_h",this);
endfunction : build_phase
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/src/tb_riffa_debug/tb_env.svh
0,0 → 1,50
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
class tb_env extends uvm_env;
`uvm_component_utils(tb_env);
 
// --------------------------------------------------------------------
riffa_env #(N) riffa_env_h;
riffa_config #(N) cfg_h;
 
// --------------------------------------------------------------------
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction : new
 
// --------------------------------------------------------------------
function void build_phase(uvm_phase phase);
if (!uvm_config_db#(riffa_config #(N))::get(this, "", "riffa_config", cfg_h))
`uvm_fatal(get_name(), "Couldn't get config object!")
 
riffa_env_h = riffa_env #(N)::type_id::create("riffa_env_h", this);
riffa_env_h.cfg_h = cfg_h;
endfunction : build_phase
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/src/tb_riffa_debug/vs_top_base.svh
0,0 → 1,26
// --------------------------------------------------------------------
class vs_top_base
extends uvm_sequence #(uvm_sequence_item);
`uvm_object_utils(vs_top_base)
 
// --------------------------------------------------------------------
riffa_rp_tx_sequencer tx_h;
riffa_rp_rx_sequencer rx_h;
s_riffa_rp_rx_api rx_api_h;
s_riffa_rp_tx_api tx_api_h;
 
// --------------------------------------------------------------------
task init(riffa_env #(N) env_h);
this.tx_h = env_h.agent_h.rp_tx_sequencer_h;
this.rx_h = env_h.agent_h.rp_rx_sequencer_h;
this.rx_api_h = s_riffa_rp_rx_api::type_id::create("rx_api_h");
this.tx_api_h = s_riffa_rp_tx_api::type_id::create("tx_api_h");
endtask: init
 
// --------------------------------------------------------------------
function new(string name = "vs_top_base");
super.new(name);
endfunction
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_riffa_register_file.sv File deleted
/trunk/PCIe/sim/tests/tb_riffa_register_file/the_test.sv File deleted
/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_riffa_register_file.f File deleted
/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_riffa_register_file_pkg.sv File deleted
/trunk/PCIe/sim/tests/tb_riffa_register_file/files.f
0,0 → 1,14
#
 
# ${PROJECT_DIR}/sim/src/riffa_bfm_class_pkg.sv
# ${PROJECT_DIR}/sim/src/riffa_agent_class_pkg.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_if.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_if.sv
 
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_tx.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx_fsm.sv
${PROJECT_DIR}/src/RIFFA/riffa_chnl_rx.sv
${PROJECT_DIR}/src/RIFFA/riffa_register_file.sv
 
/trunk/PCIe/sim/tests/tb_riffa_register_file/init_test.do
7,7 → 7,6
# setup environment
do ../../../../scripts/sim_env.do
set env(SIM_TARGET) fpga
set env(SIM_TB) tb_riffa_register_file
 
radix -hexadecimal
 
19,18 → 18,8
sim_compile_lib $env(LIB_BASE_DIR) qaz_lib
sim_compile_lib $env(LIB_BASE_DIR) sim
 
vlog -f ./tb_files.f
vlog -f ./files.f
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
# run the sim
sim_run_test
 
 
/trunk/PCIe/sim/tests/tb_riffa_register_file/sim.do
3,9 → 3,8
 
quit -sim
 
vsim -novopt work.tb_top
# vsim -suppress 12110 -novopt work.tb_top
vsim -f ./sim.f work.tb_top
 
# log all signals
log -r *
 
 
log /* -r
/trunk/PCIe/sim/tests/tb_riffa_register_file/sim.f
0,0 → 1,10
#
#
 
# +UVM_VERBOSITY=UVM_DEBUG
+UVM_VERBOSITY=UVM_HIGH
 
-voptargs=+acc=npr+/tb_top
-voptargs=+acc=npr+/tb_top/dut
 
 
/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_files.f
0,0 → 1,9
#
 
# +incdir+../../src/RIFFA
 
../../src/RIFFA/riffa_pkg.sv
 
./tb_top_pkg.sv
 
./tb_top.sv
/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_top.sv
0,0 → 1,69
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module tb_top;
import uvm_pkg::*;
import tb_top_pkg::*;
import riffa_pkg::*;
`include "uvm_macros.svh"
 
// --------------------------------------------------------------------
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
wire clk_1000mhz;
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
// --------------------------------------------------------------------
wire clk = clk_100mhz;
wire reset;
 
sync_reset sync_reset_i(tb_clk, tb_rst, reset);
 
// --------------------------------------------------------------------
riffa_chnl_if #(N) chnl_bus(.*);
riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers
 
riffa_register_file #(.N(N), .B(B))
dut(.*);
 
// --------------------------------------------------------------------
for(genvar j = 0; j < r_if.RC; j++)
assign r_if.register_in[j] = r_if.register_out[j];
 
// --------------------------------------------------------------------
riffa_config #(N) cfg_h = new(chnl_bus);
 
initial
begin
uvm_config_db #(riffa_config #(N))::set(null, "*", "riffa_config", cfg_h);
run_test("t_debug");
end
 
// --------------------------------------------------------------------
endmodule
/trunk/PCIe/sim/tests/tb_riffa_register_file/tb_top_pkg.sv
0,0 → 1,47
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
package tb_top_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
import riffa_pkg::*;
 
// --------------------------------------------------------------------
localparam N = 16; // width of the bus in bytes
localparam RW = (N/4); // width of the bus in 32 bit words
localparam B = 5; // number of register banks
 
// --------------------------------------------------------------------
`include "../../src/tb_riffa_debug/vs_top_base.svh"
`include "vs_debug.svh"
`include "../../src/tb_riffa_debug/tb_env.svh"
`include "../../src/tb_riffa_debug/t_top_base.svh"
`include "../../src/tb_riffa_debug/t_debug.svh"
 
 
// --------------------------------------------------------------------
endpackage
/trunk/PCIe/sim/tests/tb_riffa_register_file/vs_debug.svh
0,0 → 1,22
// --------------------------------------------------------------------
class vs_debug extends vs_top_base;
`uvm_object_utils(vs_debug)
 
// --------------------------------------------------------------------
function new(string name = "vs_debug");
super.new(name);
endfunction
 
// --------------------------------------------------------------------
task body();
int size = B * (N / 4);
tx_api_h.init(tx_h, this, N);
rx_api_h.init(rx_h, this, N);
 
tx_api_h.counting(N , size, 0);
// rx_api_h.display(N , size, 0);
rx_api_h.get(N , size, 0);
endtask: body
 
// --------------------------------------------------------------------
endclass
/trunk/PCIe/sim/tests/tb_riffa_register_file/wip.do
1,13 → 1,5
#
 
# compile simulation files
vlog -f ./$env(SIM_TB).f
vlog -f ./tb_files.f
vlog -f ./files.f
 
# simulation $root
vlog ./$env(SIM_TB)_pkg.sv
vlog ./$env(SIM_TB).sv
 
# compile test last
vlog ./the_test.sv
 
/trunk/PCIe/src/RIFFA/riffa_chnl_xx_upsizer.sv File deleted
/trunk/PCIe/src/RIFFA/riffa_chnl_xx_downsizer_fsm.sv File deleted
/trunk/PCIe/src/RIFFA/riffa_chnl_xx_downsizer.sv File deleted
/trunk/PCIe/src/RIFFA/riffa_chnl_downsizer.sv File deleted
/trunk/avalon_lib/docs/Avalon Verification IP Suite User Guide .pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/avalon_lib/docs/Avalon Verification IP Suite User Guide .pdf
trunk/avalon_lib/docs/Avalon Verification IP Suite User Guide .pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/avalon_lib/docs/mnl_avalon_spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/avalon_lib/docs/mnl_avalon_spec.pdf =================================================================== --- trunk/avalon_lib/docs/mnl_avalon_spec.pdf (revision 49) +++ trunk/avalon_lib/docs/mnl_avalon_spec.pdf (nonexistent)
trunk/avalon_lib/docs/mnl_avalon_spec.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/avalon_lib/src/ast_ready_cycle_fsm.sv =================================================================== --- trunk/avalon_lib/src/ast_ready_cycle_fsm.sv (revision 49) +++ trunk/avalon_lib/src/ast_ready_cycle_fsm.sv (nonexistent) @@ -1,106 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -module - ast_ready_cycle_fsm - ( - input axis_en, - output axis_tvalid, - input axis_tready, - - input fifo_watermark, // OK to use fifo_almost_full if FIFO is synchronous, assert to flush also - input fifo_empty, - output fifo_rd_en, - - output data_to_axis_fsm_error, - - input aclk, - input aresetn - ); - - //--------------------------------------------------- - // state machine binary definitions - enum reg [3:0] { - IDLE_STATE = 4'b0001, - TVALID = 4'b0010, - TREADY = 4'b0100, - ERROR_STATE = 4'b1000 - } state, next_state; - - - //--------------------------------------------------- - // state machine flop - always_ff @(posedge aclk) - if(~aresetn) - state <= IDLE_STATE; - else - state <= next_state; - - - //--------------------------------------------------- - // state machine - always_comb - case(state) - IDLE_STATE: if(axis_en & fifo_watermark & ~fifo_empty) - if(axis_tready) - next_state <= TREADY; - else - next_state <= TVALID; - else - next_state <= IDLE_STATE; - - TVALID: if(axis_tready) // wait for slave to be ready - next_state <= TREADY; - else - next_state <= TVALID; - - TREADY: if(fifo_empty) // slave can accept data - next_state <= IDLE_STATE; - else if(axis_tready) - next_state <= TREADY; - else - next_state <= TVALID; - - ERROR_STATE: next_state <= IDLE_STATE; - - default: next_state <= ERROR_STATE; - - endcase - - - //--------------------------------------------------- - // outputs - assign axis_tvalid = (next_state == TVALID) | (next_state == TREADY); - assign fifo_rd_en = axis_tvalid & axis_tready; - assign data_to_axis_fsm_error = (state == ERROR_STATE); - - -//--------------------------------------------------- -// -endmodule - Index: trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/verbosity_pkg.sv =================================================================== --- trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/verbosity_pkg.sv (revision 49) +++ trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/verbosity_pkg.sv (nonexistent) @@ -1,193 +0,0 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/17.1std/ip/sopc/components/verification/lib/verbosity_pkg.sv#1 $ -// $Revision: #1 $ -// $Date: 2017/07/30 $ -//----------------------------------------------------------------------------- -// =head1 NAME -// verbosity_pkg -// =head1 SYNOPSIS -// Package for controlling verbosity of messages sent to the console -//----------------------------------------------------------------------------- -// =head1 COPYRIGHT -// Copyright (c) 2008 Altera Corporation. All Rights Reserved. -// The information contained in this file is the property of Altera -// Corporation. Except as specifically authorized in writing by Altera -// Corporation, the holder of this file shall keep all information -// contained herein confidential and shall protect same in whole or in part -// from disclosure and dissemination to all third parties. Use of this -// program confirms your agreement with the terms of this license. -//----------------------------------------------------------------------------- -// =head1 DESCRIPTION -// This module will dump diagnostic messages to the console during -// simulation. The level of verbosity can be controlled in the test -// bench by using the *set_verbosity* method in the imported package -// verbosity_pkg. For a given setting, message at that level and all -// lower levels are dumped. For example, setting VERBOSITY_DEBUG level -// causes all messages to be dumped, while VERBOSITY_FAILURE restricts -// only failure messages and those tagged as VERBOSITY_NONE to be -// dumped. -// The different levels are: -// =over 4 -// =item 1 VERBOSITY_NONE -// Messages tagged with this level are always dumped to the console. -// =item 2 VERBOSITY_FAILURE -// A fatal simulation error has occurred and the simulator will exit. -// =item 3 VERBOSITY_ERROR -// A non-fatal error has occured. An example is a data comparison mismatch. -// =item 4 VERBOSITY_WARNING -// Warn the user that a potential error has occurred. -// =item 5 VERBOSITY_INFO -// Informational message. -// =item 6 VERBOSITY_DEBUG -// Dump enough state to diagnose problem scenarios. -// =back - - -`ifndef _AVALON_VERBOSITY_PKG_ -`define _AVALON_VERBOSITY_PKG_ - -package verbosity_pkg; - - timeunit 1ps; - timeprecision 1ps; - - typedef enum int {VERBOSITY_NONE, - VERBOSITY_FAILURE, - VERBOSITY_ERROR, - VERBOSITY_WARNING, - VERBOSITY_INFO, - VERBOSITY_DEBUG} Verbosity_t; - - Verbosity_t verbosity = VERBOSITY_INFO; - string message = ""; - int dump_file; - int dump = 0; - - //-------------------------------------------------------------------------- - // =head1 Public Methods API - // =pod - // This section describes the public methods in the application programming - // interface (API). In this case the application program is the test bench - // or component which imports this package. - // =cut - //-------------------------------------------------------------------------- - - function automatic Verbosity_t get_verbosity(); // public - // Returns the global verbosity setting. - return verbosity; - endfunction - - function automatic void set_verbosity ( // public - Verbosity_t v - ); - // Sets the global verbosity setting. - - string verbosity_str; - verbosity = v; - - case(verbosity) - VERBOSITY_NONE: verbosity_str = "VERBOSITY_"; - VERBOSITY_FAILURE: verbosity_str = "VERBOSITY_FAILURE"; - VERBOSITY_ERROR: verbosity_str = "VERBOSITY_ERROR"; - VERBOSITY_WARNING: verbosity_str = "VERBOSITY_WARNING"; - VERBOSITY_INFO: verbosity_str = "VERBOSITY_INFO"; - VERBOSITY_DEBUG: verbosity_str = "VERBOSITY_DEBUG"; - default: verbosity_str = "UNKNOWN"; - endcase - $sformat(message, "%m: Setting Verbosity level=%0d (%s)", - verbosity, verbosity_str); - print(VERBOSITY_NONE, message); - endfunction - - function automatic void print( // public - Verbosity_t level, - string message - ); - // Print a message to the console if the verbosity argument - // is less than or equal to the global verbosity setting. - string level_str; - - if (level <= verbosity) begin - case(level) - VERBOSITY_NONE: level_str = ""; - VERBOSITY_FAILURE: level_str = "FAILURE:"; - VERBOSITY_ERROR: level_str = "ERROR:"; - VERBOSITY_WARNING: level_str = "WARNING:"; - VERBOSITY_INFO: level_str = "INFO:"; - VERBOSITY_DEBUG: level_str = "DEBUG:"; - default: level_str = "UNKNOWN:"; - endcase - - $display("%t: %s %s",$time, level_str, message); - if (dump) begin - $fdisplay(dump_file, "%t: %s %s",$time, level_str, message); - end - end - endfunction - - function automatic void print_divider( // public - Verbosity_t level - ); - // Prints a divider line to the console to make a block of related text - // easier to identify and read. - string message; - $sformat(message, - "------------------------------------------------------------"); - print(level, message); - endfunction - - function automatic void open_dump_file ( // public - string dump_file_name = "avalon_bfm_sim.log" - ); - // Opens a dump file which collects console messages. - - if (dump) begin - $sformat(message, "%m: Dump file already open - ignoring open."); - print(VERBOSITY_ERROR, message); - end else begin - dump_file = $fopen(dump_file_name, "w"); - $fdisplay(dump_file, "testing dump file"); - $sformat(message, "%m: Opening dump file: %s", dump_file_name); - print(VERBOSITY_INFO, message); - dump = 1; - end - endfunction - - function automatic void close_dump_file(); // public - // Close the console message dump file. - if (!dump) begin - $sformat(message, "%m: No open dump file - ignoring close."); - print(VERBOSITY_ERROR, message); - end else begin - dump = 0; - $fclose(dump_file); - $sformat(message, "%m: Closing dump file"); - print(VERBOSITY_INFO, message); - end - endfunction - - function automatic void abort_simulation(); - string message; - $sformat(message, "%m: Abort the simulation due to fatal error incident."); - print(VERBOSITY_FAILURE, message); - $stop; - endfunction - -endpackage - -// =cut - -`endif - Index: trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/avalon_utilities_pkg.sv =================================================================== --- trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/avalon_utilities_pkg.sv (revision 49) +++ trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/avalon_utilities_pkg.sv (nonexistent) @@ -1,80 +0,0 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/17.1std/ip/sopc/components/verification/lib/avalon_utilities_pkg.sv#1 $ -// $Revision: #1 $ -// $Date: 2017/07/30 $ -//----------------------------------------------------------------------------- -// =head1 NAME -// avalon_utilities_pkg -// =head1 SYNOPSIS -// Package for shared types and functions -//----------------------------------------------------------------------------- -// =head1 COPYRIGHT -// Copyright (c) 2008 Altera Corporation. All Rights Reserved. -// The information contained in this file is the property of Altera -// Corporation. Except as specifically authorized in writing by Altera -// Corporation, the holder of this file shall keep all information -// contained herein confidential and shall protect same in whole or in part -// from disclosure and dissemination to all third parties. Use of this -// program confirms your agreement with the terms of this license. -//----------------------------------------------------------------------------- -// =head1 DESCRIPTION -// This package contains shared types and functions. -// =cut -`timescale 1ns / 1ns - -`ifndef _AVALON_UTILITIES_PKG_ -`define _AVALON_UTILITIES_PKG_ - -package avalon_utilities_pkg; - - function automatic int clog2( - bit [31:0] Depth - ); - int i= Depth; - for(clog2 = 0; i > 0; clog2 = clog2 + 1) - i = i >> 1; - - return clog2; - endfunction - - function automatic int max( - bit [31:0] one, - bit [31:0] two - ); - if(one > two) - return one; - else - return two; - endfunction - - function automatic int lindex( - bit [31:0] width - ); - // returns the left index for a vector having a declared width - // when width is 0, then the left index is set to 0 rather than -1 - lindex = (width > 0) ? (width-1) : 0; - endfunction - - typedef enum int { - LOW = 0, - HIGH = 1, - RANDOM = 2, - UNKNOWN = 3 - } IdleOutputValue_t; - -endpackage - -`endif - Index: trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/altera_avalon_st_source_bfm.sv =================================================================== --- trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/altera_avalon_st_source_bfm.sv (revision 49) +++ trunk/avalon_lib/syn/ast_source/altera_avalon_st_source_bfm_171/sim/altera_avalon_st_source_bfm.sv (nonexistent) @@ -1,908 +0,0 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $File: //acds/rel/17.1std/ip/sopc/components/verification/altera_avalon_st_source_bfm/altera_avalon_st_source_bfm.sv $ -// $Revision: #1 $ -// $Date: 2017/07/30 $ -// $Author: swbranch $ -//----------------------------------------------------------------------------- -// =head1 NAME -// altera_avalon_st_source_bfm -// =head1 SYNOPSIS -// Bus Functional Model (BFM) for a Avalon Streaming Source -//----------------------------------------------------------------------------- -// =head1 DESCRIPTION -// This is a Bus Functional Model (BFM) for a Avalon Streaming Source. -// The behavior of each clock cycle of the ST protocol on the interface -// is governed by a transaction. Transactions are constructed using the -// the public API methods provided and are then pushed into a dispatch -// queue, either one at a time or as entire sequences. Response transactions -// are popped out of a separate response queue and inform the client of -// statistics such as back pressure latency. -//----------------------------------------------------------------------------- -`timescale 1ps / 1ps - -module altera_avalon_st_source_bfm ( - clk, - reset, - - src_data, - src_channel, - src_valid, - src_startofpacket, - src_endofpacket, - src_error, - src_empty, - src_ready - ); - - // =head1 PARAMETERS - parameter ST_SYMBOL_W = 8; // Data symbol width in bits - parameter ST_NUMSYMBOLS = 4; // Number of symbols per word - parameter ST_CHANNEL_W = 0; // Channel width in bits - parameter ST_ERROR_W = 0; // Error width in bits - parameter ST_EMPTY_W = 0; // Empty width in bits - - parameter ST_READY_LATENCY = 0; // Number of cycles latency after ready - parameter ST_MAX_CHANNELS = 1; // Maximum number of channels - - parameter USE_PACKET = 0; // Use packet pins on interface - parameter USE_CHANNEL = 0; // Use channel pins on interface - parameter USE_ERROR = 0; // Use error pin on interface - parameter USE_READY = 1; // Use ready pin on interface - parameter USE_VALID = 1; // Use valid pin on interface - parameter USE_EMPTY = 0; // Use empty pin on interface - - parameter ST_BEATSPERCYCLE = 1; // Max number of packets per cycle - parameter VHDL_ID = 0; // VHDL BFM ID number - - localparam ST_DATA_W = ST_SYMBOL_W * ST_NUMSYMBOLS; - localparam ST_MDATA_W = ST_BEATSPERCYCLE * ST_DATA_W; - localparam ST_MCHANNEL_W = ST_BEATSPERCYCLE * ST_CHANNEL_W; - localparam ST_MERROR_W = ST_BEATSPERCYCLE * ST_ERROR_W; - localparam ST_MEMPTY_W = ST_BEATSPERCYCLE * ST_EMPTY_W; - - // =head1 PINS - // =head2 Clock Interface - input clk; - input reset; - - // =head2 Avalon Streaming Source Interface - output [lindex(ST_MDATA_W): 0] src_data; - output [lindex(ST_MCHANNEL_W): 0] src_channel; - output [ST_BEATSPERCYCLE-1: 0] src_valid; - output [ST_BEATSPERCYCLE-1: 0] src_startofpacket; - output [ST_BEATSPERCYCLE-1: 0] src_endofpacket; - output [lindex(ST_MERROR_W): 0] src_error; - output [lindex(ST_MEMPTY_W): 0] src_empty; - input src_ready; - - // =cut - - function int lindex; - // returns the left index for a vector having a declared width - // when width is 0, then the left index is set to 0 rather than -1 - input [31:0] width; - lindex = (width > 0) ? (width-1) : 0; - endfunction - -// synthesis translate_off - import verbosity_pkg::*; - import avalon_utilities_pkg::*; - - typedef logic [lindex(ST_DATA_W) :0] STData_t; - typedef logic [lindex(ST_CHANNEL_W) :0] STChannel_t; - typedef logic [lindex(ST_EMPTY_W) :0] STEmpty_t; - typedef logic [lindex(ST_ERROR_W) :0] STError_t; - typedef logic [ST_BEATSPERCYCLE-1 :0] STBeats_t; - - logic [ST_BEATSPERCYCLE-1 :0] src_valid; - logic [lindex(ST_MDATA_W) :0] src_data; - logic [lindex(ST_MCHANNEL_W) :0] src_channel; - logic [lindex(ST_MERROR_W) :0] src_error; - logic [lindex(ST_MEMPTY_W) :0] src_empty; - logic [ST_BEATSPERCYCLE-1 :0] src_startofpacket; - logic [ST_BEATSPERCYCLE-1 :0] src_endofpacket; - - logic [ST_BEATSPERCYCLE-1 :0] src_valid_temp; - logic [lindex(ST_MDATA_W) :0] src_data_temp, src_data_slices; - logic [lindex(ST_MCHANNEL_W) :0] src_channel_temp, src_channel_slices; - logic [lindex(ST_MERROR_W) :0] src_error_temp, src_error_slices; - logic [lindex(ST_MEMPTY_W) :0] src_empty_temp, src_empty_slices; - logic [ST_BEATSPERCYCLE-1 :0] src_startofpacket_temp; - logic [ST_BEATSPERCYCLE-1 :0] src_endofpacket_temp; - - //-------------------------------------------------------------------------- - // Private Types and Variables - //-------------------------------------------------------------------------- - typedef struct packed - { - bit [31:0] idles; - logic startofpacket; - logic endofpacket; - STChannel_t channel; - STData_t data; - STError_t error; - STEmpty_t empty; - bit valid; - } Transaction_t; - - typedef struct packed - { - int latency; - int count; - } Response_t; - - Transaction_t new_transaction; - Transaction_t current_transaction[ST_BEATSPERCYCLE]; - Transaction_t transaction_queue[$]; - - Response_t current_response; - Response_t new_response; - Response_t response_queue[$]; - - int response_timeout = 100; - string message = ""; - - int idle_ctr = 0; - bit idle_state = 0; - int ready_latency_ctr = 0; - bit transaction_pending = 0; - int transaction_queue_size = 0; - int transaction_ctr = 0; - int max_transaction_queue_size = 256; - int min_transaction_queue_size = 2; - - bit start = 0; - bit complete = 0; - - logic src_ready_qualified; - logic src_is_now_ready; - logic load_transaction = 0; - STBeats_t src_valid_local; - - IdleOutputValue_t idle_output_config = UNKNOWN; - - localparam MAX_READY_DELAY = 8; - logic [MAX_READY_DELAY-1:0] src_ready_delayed; - - //-------------------------------------------------------------------------- - // Private Methods - //-------------------------------------------------------------------------- - function int __floor( - int arg - ); - // returns the arg if it is greater than 0, else returns 0 - return (arg > 0) ? arg : 0; - endfunction - - task __drive_temp_interface_idle(); - case (idle_output_config) - LOW: begin - src_valid_temp <= 0; - src_startofpacket_temp <= '0; - src_endofpacket_temp <= '0; - src_channel_temp <= '0; - src_data_temp <= '0; - src_error_temp <= '0; - src_empty_temp <= '0; - end - HIGH: begin - src_valid_temp <= 0; - src_startofpacket_temp <= '1; - src_endofpacket_temp <= '1; - src_channel_temp <= '1; - src_data_temp <= '1; - src_error_temp <= '1; - src_empty_temp <= '1; - end - RANDOM: begin - src_valid_temp <= 0; - src_startofpacket_temp <= $random; - src_endofpacket_temp <= $random; - src_channel_temp <= $random; - src_data_temp <= $random; - src_error_temp <= $random; - src_empty_temp <= $random; - end - UNKNOWN: begin - src_valid_temp <= 0; - src_startofpacket_temp <= 'x; - src_endofpacket_temp <= 'x; - src_channel_temp <= 'x; - src_data_temp <= 'x; - src_error_temp <= 'x; - src_empty_temp <= 'x; - end - default: begin - src_valid_temp <= 0; - src_startofpacket_temp <= 'x; - src_endofpacket_temp <= 'x; - src_channel_temp <= 'x; - src_data_temp <= 'x; - src_error_temp <= 'x; - src_empty_temp <= 'x; - end - endcase - endtask - - task __drive_interface_idle(); - case (idle_output_config) - LOW: begin - src_valid = '0; - src_startofpacket = '0; - src_endofpacket = '0; - src_data = '0; - src_channel = '0; - src_error = '0; - src_empty = '0; - end - HIGH: begin - src_valid = '0; - src_startofpacket = '1; - src_endofpacket = '1; - src_data = '1; - src_channel = '1; - src_error = '1; - src_empty = '1; - end - RANDOM: begin - src_valid = '0; - src_startofpacket = $random; - src_endofpacket = $random; - src_data = $random; - src_channel = $random; - src_error = $random; - src_empty = $random; - end - UNKNOWN: begin - src_valid = '0; - src_startofpacket = 'x; - src_endofpacket = 'x; - src_data = 'x; - src_channel = 'x; - src_error = 'x; - src_empty = 'x; - end - default: begin - src_valid = '0; - src_startofpacket = 'x; - src_endofpacket = 'x; - src_data = 'x; - src_channel = 'x; - src_error = 'x; - src_empty = 'x; - end - endcase - endtask - - function automatic void __hello(); - // Introduction Message to console - $sformat(message, "%m: - Hello from altera_avalon_st_source_bfm."); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - $Revision: #1 $"); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - $Date: 2017/07/30 $"); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_SYMBOL_W = %0d", - ST_SYMBOL_W); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_NUMSYMBOLS = %0d", - ST_NUMSYMBOLS); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_CHANNEL_W = %0d", - ST_CHANNEL_W); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_ERROR_W = %0d", - ST_ERROR_W); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_EMPTY_W = %0d", - ST_EMPTY_W); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_READY_LATENCY = %0d", - ST_READY_LATENCY); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_MAX_CHANNELS = %0d", - ST_MAX_CHANNELS); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_BEATSPERCYCLE = %0d", - ST_BEATSPERCYCLE); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - USE_PACKET = %0d", - USE_PACKET); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - USE_CHANNEL = %0d", - USE_CHANNEL); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - USE_ERROR = %0d", - USE_ERROR); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - USE_READY = %0d", - USE_READY); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - USE_VALID = %0d", - USE_VALID); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - USE_EMPTY = %0d", - USE_EMPTY); - print(VERBOSITY_INFO, message); - print_divider(VERBOSITY_INFO); - endfunction - - //-------------------------------------------------------------------------- - // =head1 Public Methods API - // =pod - // This section describes the public methods in the application programming - // interface (API). In this case the application program is the test bench - // which instantiates and controls and queries state in this BFM component. - // Test programs must only use these public access methods and events to - // communicate with this BFM component. The API and the module pins - // are the only interfaces in this component that are guaranteed to be - // stable. The API will be maintained for the life of the product. - // While we cannot prevent a test program from directly accessing local - // tasks, functions, or data private to the BFM, there is no guarantee that - // these will be present in the future. In fact, it is best for the user - // to assume that the underlying implementation of this component can - // and will change. - // =cut - //-------------------------------------------------------------------------- - event signal_fatal_error; // public - // Signal that a fatal error has occurred. Terminates simulation. - - event signal_response_done; // public - // Signal - - event signal_src_ready; // public - // Signal the assertion of the src_ready port. - - event signal_src_not_ready; // public - // Signal the deassertion of the src_ready port implying sink backpressure - - event signal_src_transaction_complete; // public - // Signal that all pending transactions have completed - - event signal_src_transaction_almost_complete; // public - // Signal that BFM is driving the last pending transaction - - event signal_src_driving_transaction; // public - // Signal that the source is driving the transaction onto the bus - - event signal_max_transaction_queue_size; // public - // This event signals that the pending transaction queue size - // threshold has been exceeded - - event signal_min_transaction_queue_size; // public - // This event signals that the pending transaction queue size - // is below the minimum threshold - - function automatic string get_version(); // public - // Return BFM version string. For example, version 9.1 sp1 is "9.1sp1" - string ret_version = "17.1"; - return ret_version; - endfunction - - function automatic void set_idle_state_output_configuration( // public - // Set the configuration of output signal value during interface idle - IdleOutputValue_t output_config - ); - $sformat(message, "%m: method called"); - print(VERBOSITY_DEBUG, message); - - idle_output_config = output_config; - endfunction - - function automatic IdleOutputValue_t get_idle_state_output_configuration(); - // Get the configuration of output signal value during interface idle - $sformat(message, "%m: method called"); - print(VERBOSITY_DEBUG, message); - - return idle_output_config; - endfunction - - function automatic bit get_src_transaction_complete(); // public - // Return the transaction complete status - $sformat(message, "%m: called get_src_transaction_complete"); - print(VERBOSITY_DEBUG, message); - return complete; - endfunction - - function automatic logic get_src_ready(); // public - // Return the value of the src_ready port. - $sformat(message, "%m: called get_src_ready"); - print(VERBOSITY_DEBUG, message); - return src_ready; - endfunction - - function automatic void set_response_timeout( // public - int cycles = 100 - ); - // Set the number of cycles that may elapse during backpressure before - // the time out error is asserted. Disable the timeout by setting - // the cycles argument to zero. - response_timeout = cycles; - $sformat(message, "%m: called set_response_timeout"); - print(VERBOSITY_DEBUG, message); - - $sformat(message, "%m: Response timeout set to %0d cycles", response_timeout); - print(VERBOSITY_INFO, message); - endfunction - - task automatic init(); // public - // Drive interface to idle state. - $sformat(message, "%m: called init"); - print(VERBOSITY_DEBUG, message); - __drive_temp_interface_idle(); - endtask - - function automatic void push_transaction(); // public - // Push a new transaction into the local transaction queue. - // The BFM will drive the appropriate signals on the ST bus - // according to the transaction field values. - Transaction_t idle_transaction; - - $sformat(message, "%m: called push_transaction"); - print(VERBOSITY_DEBUG, message); - - if (reset) begin - $sformat(message, "%m: Illegal command while reset asserted"); - print(VERBOSITY_ERROR, message); - ->signal_fatal_error; - end - - // Idle cycles, defined as preceding the actual transaction are - // converted to an equal number of dummy transactions with the - // valid field set to 0. These are pushed into the queue before - // the actual transaction. - - if (USE_VALID == 1) begin - idle_transaction.idles = 0; - idle_transaction.valid = 1'b0; - for (int i=0; i 0) begin - $sformat(message, "%m: called set_transaction_idles - %h", - idle_cycles); - print(VERBOSITY_DEBUG, message); - new_transaction.idles = idle_cycles; - end else begin - $sformat(message, "%m: Ignored. Idles set to 0 when USE_VALID == 0"); - print(VERBOSITY_WARNING, message); - new_transaction.idles = 0; - end - endfunction - - function automatic void set_transaction_sop( // public - bit sop - ); - // Set the transaction start of packet value - $sformat(message, "%m: called set_transaction_sop - %b", sop); - print(VERBOSITY_DEBUG, message); - new_transaction.startofpacket = sop; - endfunction - - function automatic void set_transaction_eop( // public - bit eop - ); - // Set the transaction end of packet value - $sformat(message, "%m: called set_transaction_eop - %b", eop); - print(VERBOSITY_DEBUG, message); - new_transaction.endofpacket = eop; - endfunction - - function automatic void set_transaction_error( // public - bit [ST_ERROR_W-1:0] error - ); - // Set the transaction error value - $sformat(message, "%m: called set_transaction_error - %h", error); - print(VERBOSITY_DEBUG, message); - new_transaction.error = error; - endfunction - - function automatic void set_transaction_empty( // public - bit [ST_EMPTY_W-1:0] empty - ); - // Set the transaction empty value - $sformat(message, "%m: called set_transaction_empty - %h", empty); - print(VERBOSITY_DEBUG, message); - new_transaction.empty = empty; - endfunction - - function automatic void pop_response(); // public - // Pop the response transaction from the queue before querying contents - string message; - - $sformat(message, "%m: called pop_response - queue depth %0d", - response_queue.size()); - print(VERBOSITY_DEBUG, message); - - if (response_queue.size() == 0) begin - $sformat(message, "%m: Illegal command: response queue is empty"); - print(VERBOSITY_ERROR, message); - ->signal_fatal_error; - end - - current_response = response_queue.pop_front(); - endfunction - - function automatic int get_response_latency(); // public - // Return the response latency due to back pressure for a - // transaction. The value is in terms of clock cycles. - $sformat(message, "%m: called get_response_latency - %0d", - current_response.latency); - print(VERBOSITY_DEBUG, message); - return current_response.latency; - endfunction - - function automatic void set_max_transaction_queue_size( // public - int size - ); - // Set the pending transaction maximum queue size threshold. - // The public event signal_max_transaction_queue_size - // will fire when the threshold is exceeded. - max_transaction_queue_size = size; - endfunction - - function automatic void set_min_transaction_queue_size( // public - int size - ); - // Set the pending transaction minimum queue size threshold. - // The public event signal_min_transaction_queue_size - // will fire when the queue level is below this threshold. - min_transaction_queue_size = size; - endfunction - - //=cut - - initial begin - __hello(); - end - - always @(posedge clk) begin - if (transaction_queue.size() > max_transaction_queue_size) begin - ->signal_max_transaction_queue_size; - end else if (transaction_queue.size() < min_transaction_queue_size) begin - ->signal_min_transaction_queue_size; - end - end - - always @(signal_fatal_error) abort_simulation(); - - - // The ST_BEATSPERCYCLE parameter complicates the driving of transactions - // somewhat as not all beats in a given cycle need to be valid. - // The following scenarios are possible: - // Transactions with no idle cycles: - // 1 There are an integral multiple of ST_BEATSPERCYCLE transactions - // in the pending transaction queue: - // All transactions fit neatly into an integral number of cycles - // with all beats valid and no resulting bubbles. - // 2 There are a non integral multiple of ST_BEATSPERCYCLE transactions - // in the pending transaction queue: - // The final pending transaction(s) in the queue need to be driven - // out with unused beats being marked as invalid i.e. there are one - // or more bubbles (invalid beats) at the end of the transaction - // sequence. - // A transaction with idle cycles defined is decomposed into a sequence of - // transactions. First there is a sequence of non valid, empty transaction - // beats which define the idle cycles or bubbles. And finally, there is - // one valid transaction beat. - - // delay chain for src_ready back pressure input to account for latency - always @(posedge clk or posedge reset) begin - if (reset) begin - src_ready_delayed <= 0; - end else begin - src_ready_delayed <= {src_ready_delayed[6:0], src_ready}; - end - end - - assign src_ready_qualified = (USE_READY == 0)? 1'b1 : - (ST_READY_LATENCY == 0)? src_ready : - src_ready_delayed[__floor(ST_READY_LATENCY-1)]; - - assign src_is_now_ready = (USE_READY == 0)? 1'b1 : - (ST_READY_LATENCY <= 1)? src_ready : - src_ready_delayed[__floor(ST_READY_LATENCY-2)]; - - always @(*) begin - src_valid_local = src_valid_temp; - - if (USE_VALID > 0) begin - if (USE_READY == 0 || ST_READY_LATENCY == 0) begin - src_valid = src_valid_temp; - src_startofpacket = src_startofpacket_temp; - src_endofpacket = src_endofpacket_temp; - src_data = src_data_temp; - src_channel = src_channel_temp; - src_error = src_error_temp; - src_empty = src_empty_temp; - end else begin - if (src_ready_qualified) begin - src_valid = src_valid_temp; - src_startofpacket = src_startofpacket_temp; - src_endofpacket = src_endofpacket_temp; - src_data = src_data_temp; - src_channel = src_channel_temp; - src_error = src_error_temp; - src_empty = src_empty_temp; - end else begin - __drive_interface_idle(); - end - end - end else begin - src_valid = 0; - src_startofpacket = src_startofpacket_temp; - src_endofpacket = src_endofpacket_temp; - src_data = src_data_temp; - src_channel = src_channel_temp; - src_error = src_error_temp; - src_empty = src_empty_temp; - end - - end - - bit pending; - int response_transaction_ctr; - - always @(posedge clk or posedge reset) begin - if (reset) begin - ready_latency_ctr <= 0; - complete <= 0; - response_transaction_ctr = 0; - new_response = 0; - current_response = 0; - response_queue = {}; - end else begin - if (src_ready_qualified && ((src_valid != 0) || (USE_VALID == 0))) begin - ready_latency_ctr <= 0; - - if (transaction_pending) begin - new_response.count = response_transaction_ctr++; - new_response.latency = ready_latency_ctr; - response_queue.push_back(new_response); - ->signal_response_done; - end - - end else begin - if (transaction_pending && ((src_valid != 0) || (USE_VALID == 0))) - ready_latency_ctr <= ready_latency_ctr + 1; - end - - if ((get_transaction_queue_size() == 0) && src_ready_qualified && - (USE_READY == 0 || src_valid != 0)) begin - complete <= 1; - ->signal_src_transaction_complete; - end else if (complete && - ((get_transaction_queue_size() > 0) || transaction_pending)) begin - complete <= 0; - end - - if ((response_timeout != 0) && (ready_latency_ctr > response_timeout)) begin - $sformat(message, "%m: Response Timeout"); - print(VERBOSITY_FAILURE, message); - ->signal_fatal_error; - end - - end - end - - always @(posedge clk or posedge reset) begin - if (reset) begin - idle_ctr <= 0; - transaction_pending = 0; // keep blocking - - __drive_temp_interface_idle(); - - new_transaction = 0; - transaction_queue = {}; - for (int i=0; i 0 && src_ready_qualified == 1) begin - transaction_pending = 0; - end - - if (~transaction_pending && get_transaction_queue_size() > 0) begin - transaction_pending = 1; - load_transaction = 1; - - // initialize all beats to be invalid - for (int i=0; isignal_src_driving_transaction; - load_transaction = 0; - end else if (ST_READY_LATENCY > 0 && src_is_now_ready == 1) begin - ->signal_src_driving_transaction; - load_transaction = 0; - end - end - end - end - join_none - end else begin - idle_ctr = idle_ctr - 1; - end - end - - end - end - - always@(signal_src_driving_transaction) begin - if (get_transaction_queue_size() == 0) - -> signal_src_transaction_almost_complete; - end - - always @(posedge src_ready_qualified or negedge src_ready_qualified) begin - if (src_ready_qualified) - ->signal_src_ready; - else - ->signal_src_not_ready; - end -// synthesis translate_on - -endmodule - -// =head1 SEE ALSO -// avalon_st_sink_bfm -// =cut - - - - - - - - Index: trunk/avalon_lib/syn/ast_source.qsys =================================================================== --- trunk/avalon_lib/syn/ast_source.qsys (revision 49) +++ trunk/avalon_lib/syn/ast_source.qsys (nonexistent) @@ -1,91 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_assertion.sv =================================================================== --- trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_assertion.sv (revision 49) +++ trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_assertion.sv (nonexistent) @@ -1,550 +0,0 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $File: //acds/main/ip/sopc/components/verification/altera_avalon_st_monitor_bfm/altera_avalon_st_monitor_tap.sv $ -// $Revision: #7 $ -// $Date: 2009/04/16 $ -// $Author: pscheidt $ -//----------------------------------------------------------------------------- -// =head1 NAME -// altera_avalon_st_monitor_assertion -// =head1 SYNOPSIS -// Streaming Avalon Bus Protocol Checker -//----------------------------------------------------------------------------- -// =head1 DESCRIPTION -// This module implements Avalon ST protocol assertion checking for simulation. -//----------------------------------------------------------------------------- - -`timescale 1ns / 1ns - -module altera_avalon_st_monitor_assertion( - clk, - reset, - tap - ); - - // =head1 PARAMETERS - parameter ST_SYMBOL_W = 8; // number of bits in one symbols - parameter ST_NUMSYMBOLS = 4; // number of symbols in one data - parameter ST_CHANNEL_W = 0; // width of channel signal - parameter ST_ERROR_W = 0; // width of error signal - parameter ST_EMPTY_W = 0; // width of empty signal, ST_EMPTY_W = log2(`ST_NUMSYMBOLS) - - parameter ST_READY_LATENCY = 0; // fixed ready latency in cycles - parameter ST_MAX_CHANNELS = 1; // maximum number of channels - - parameter USE_PACKET = 0; // data transfer in packet format - parameter USE_CHANNEL = 0; // use channel port - parameter USE_ERROR = 0; // use error port - parameter USE_READY = 1; // use ready port - parameter USE_VALID = 1; // use valid port - parameter USE_EMPTY = 0; // use empty port - parameter ST_BEATSPERCYCLE = 1; // Max number of packets per cycle - - localparam ST_DATA_W = ST_SYMBOL_W * ST_NUMSYMBOLS; - localparam ST_MAX_EMPTY = 2**(ST_EMPTY_W) - 1; - localparam NUM_CHANNEL = ST_MAX_CHANNELS+1; - - localparam TAP_W = ((ST_DATA_W == 0)? 1:ST_DATA_W) + // data - ((ST_CHANNEL_W == 0)? 1:ST_CHANNEL_W) + // channel - 1 + // valid - 1 + // startofpacket - 1 + // endofpacket - ((ST_ERROR_W == 0)? 1:ST_ERROR_W) + // error - ((ST_EMPTY_W == 0)? 1:ST_EMPTY_W) + // empty - 1; // ready - - // =head1 PINS - // =head2 Clock Interface - input clk; - input reset; - - // =head2 Avalon Monitor Interface - will be defined as Streaming Sink - input [(TAP_W*ST_BEATSPERCYCLE)-ST_BEATSPERCYCLE:0] tap; - - // =cut - - function int lindex; - // returns the left index for a vector having a declared width - // when width is 0, then the left index is set to 0 rather than -1 - input [31:0] width; - lindex = (width > 0) ? (width-1) : 0; - endfunction - - //-------------------------------------------------------------------------- - // synthesis translate_off - - import verbosity_pkg::*; - - typedef bit [lindex(ST_DATA_W) :0] STData_t; - typedef bit [lindex(ST_CHANNEL_W) :0] STChannel_t; - typedef bit [lindex(ST_EMPTY_W) :0] STEmpty_t; - typedef bit [lindex(ST_ERROR_W) :0] STError_t; - - event signal_fatal_error; - - event event_a_valid_legal; - event event_a_empty_legal; - event event_a_no_data_outside_packet; - event event_a_non_missing_endofpacket; - event event_a_non_missing_startofpacket; - event event_a_less_than_max_channel; - - string fatal_message = "*unitialized*"; - string message = "*unitialized*"; - - bit enable_a_valid_legal = 1; - bit enable_a_empty_legal = 1; - bit enable_a_no_data_outside_packet = 1; - bit enable_a_non_missing_endofpacket = 1; - bit enable_a_non_missing_startofpacket = 1; - bit enable_a_less_than_max_channel = 1; - - //-------------------------------------------------------------------------- - // unpack Avalon bus interface tap into individual port signals - logic ready; - logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_DATA_W):0] data; - logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_CHANNEL_W):0] channel; - logic [lindex(ST_BEATSPERCYCLE):0] valid; - logic [lindex(ST_BEATSPERCYCLE):0] startofpacket; - logic [lindex(ST_BEATSPERCYCLE):0] endofpacket; - logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_ERROR_W):0] error; - logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_EMPTY_W):0] empty; - - always_comb begin - data <= tap[lindex(ST_DATA_W*ST_BEATSPERCYCLE)+lindex(ST_CHANNEL_W*ST_BEATSPERCYCLE)+ - lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+4: - lindex(ST_CHANNEL_W*ST_BEATSPERCYCLE)+lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+4]; - - channel <= (USE_CHANNEL == 1)? - tap[lindex(ST_CHANNEL_W*ST_BEATSPERCYCLE)+lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+ - lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+3: - lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+3] : 0; - - valid <= (USE_VALID == 1)? - tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+2: - lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2*ST_BEATSPERCYCLE+3] : 1; - - startofpacket <= (USE_PACKET == 1)? - tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2*ST_BEATSPERCYCLE+2: - lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+ST_BEATSPERCYCLE+3] : 0; - - endofpacket <= (USE_PACKET == 1)? - tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+ST_BEATSPERCYCLE+2: - lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3] : 0; - - error <= (USE_ERROR == 1)? - tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2: - lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2] : 0; - - empty <= (USE_EMPTY == 1)? tap[lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+1:1] : 0; - - ready <= (USE_READY == 1)? tap[0:0] : 1; - end - - //-------------------------------------------------------------------------- - // General Statistics Counters - //-------------------------------------------------------------------------- - - logic [31:0] clock_counter; - logic [31:0] sop_counter; - logic [31:0] eop_counter; - - logic sop_counter_reset = 0; - logic eop_counter_reset = 0; - logic [255:0] sop_channel_used = '0; - logic [255:0] eop_channel_used = '1; - logic [lindex(ST_BEATSPERCYCLE):0] sop_error_in_channel = '0; - logic [lindex(ST_BEATSPERCYCLE):0] eop_error_in_channel = '0; - logic [lindex(ST_BEATSPERCYCLE):0] data_outside_packet = '0; - - always @(posedge clk) begin - if (reset) - clock_counter <= 0; - else - clock_counter <= clock_counter + 1; - end - - always @(posedge clk) begin - if (reset) begin - sop_counter <= 0; - end else if (sop_counter_reset) begin - sop_counter_reset <= 0; - sop_counter <= 0; - end else begin - for (int i=0; i 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin - sop_counter <= (USE_PACKET && valid[i] && startofpacket[i]) ? sop_counter + 1 : sop_counter; - end - end - end - end - end - - always @(posedge clk) begin - if (reset) begin - eop_counter <= 0; - end else if (eop_counter_reset) begin - eop_counter_reset <= 0; - eop_counter <= 0; - end else begin - for (int i=0; i 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin - eop_counter <= (USE_PACKET && valid[i] && endofpacket[i]) ? eop_counter + 1 : eop_counter; - end - end - end - end - end - - //-------------------------------------------------------------------------- - // Private Methods - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - // =head1 Public Methods API - // This section describes the public methods in the application programming - // interface (API). In this case the application program is the test bench - // which instantiates and controls and queries state of this component. - // Test programs must only use these public access methods and events to - // communicate with this BFM component. The API and the module pins - // are the only interfaces in this component that are guaranteed to be - // stable. The API will be maintained for the life of the product. - // While we cannot prevent a test program from directly accessing internal - // tasks, functions, or data private to the BFM, there is no guarantee that - // these will be present in the future. In fact, it is best for the user - // to assume that the underlying implementation of this component can - // and will change. - // =cut - //-------------------------------------------------------------------------- - // Master Assertions API - function automatic void set_enable_a_valid_legal( // public - bit assert_enable - ); - // enable or disable a_valid_legal assertion - - enable_a_valid_legal = assert_enable; - endfunction - - function automatic void set_enable_a_empty_legal( // public - bit assert_enable - ); - // enable or disable a_empty_legal assertion - - enable_a_empty_legal = assert_enable; - endfunction - - function automatic void set_enable_a_no_data_outside_packet( // public - bit assert_enable - ); - // enable or disable a_no_data_outside_packet assertion - - enable_a_no_data_outside_packet = assert_enable; - endfunction - - function automatic void set_enable_a_non_missing_endofpacket( // public - bit assert_enable - ); - // enable or disable a_non_missing_endofpacket assertion - - enable_a_non_missing_endofpacket = assert_enable; - endfunction - - function automatic void set_enable_a_non_missing_startofpacket( // public - bit assert_enable - ); - // enable or disable a_non_missing_startofpacket assertion - - enable_a_non_missing_startofpacket = assert_enable; - endfunction - - function automatic void set_enable_a_less_than_max_channel( // public - bit assert_enable - ); - // enable or disable a_less_than_max_channel assertion - - enable_a_less_than_max_channel = assert_enable; - endfunction - // =cut - - function automatic logic [31:0] get_sop_counter(); - return sop_counter; - if (USE_PACKET == 0) begin - $sformat(message, "%m: No packet signals in this stream (USE_PACKET=0)."); - print(VERBOSITY_WARNING, message); - end - endfunction - - function automatic void reset_sop_counter(); - sop_counter_reset = 1'b1; - endfunction - - function automatic logic [31:0] get_eop_counter(); - return eop_counter; - if (USE_PACKET == 0) begin - $sformat(message, "%m: No packet signals in this stream (USE_PACKET=0)."); - print(VERBOSITY_WARNING, message); - end - endfunction - - function automatic void reset_eop_counter(); - eop_counter_reset = 1'b1; - endfunction - - // remaining API declarations will go here - //-------------------------------------------------------------------------- - event fatal_error; - - always @(fatal_error) begin - $sformat(message, "%m: Terminate simulation."); - print(VERBOSITY_FAILURE, message); - abort_simulation(); - end - - //-------------------------------------------------------------------------- - // =head1 Assertion Checkers and Coverage Monitors - // The assertion checkers in this module are only executable on simulators - // supporting the SystemVerilog Assertion (SVA) language. - // Mentor Modelsim AE and SE do not support this. - // Simulators that are supported include: Synopsys VCS and Mentor questasim. - // The assertion checking logic in this module must be explicitly enabled - // so that designs using this module can still be compiled on Modelsim without - // changes. To disable assertions define the following macro in the testbench - // or on the command line with: +define+DISABLE_ALTERA_AVALON_SIM_SVA. - // =cut - //-------------------------------------------------------------------------- - - function automatic void print_assertion( - string message_in - ); - string message_out; - $sformat(message_out, "ASSERTION: %s", message_in); - print(VERBOSITY_FAILURE, message_out); - endfunction - - - // Counter for general assertion counters - always @(posedge clk) - begin - for (int i=0; i 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin - check_sop_eop_valid(i); - end - end else begin - data_outside_packet[i] = 0; - end - end - end - - always @(posedge clk) - begin - if (reset) begin - sop_channel_used = '0; - eop_channel_used = '1; - sop_error_in_channel = '0; - eop_error_in_channel = '0; - data_outside_packet = '0; - end - end - - task automatic check_sop_eop_valid(int current_beat); - if (startofpacket[current_beat]) begin - if (sop_channel_used[channel[current_beat]] == 1) - sop_error_in_channel[current_beat] = 1; - else begin - sop_channel_used[channel[current_beat]] = 1; - sop_error_in_channel[current_beat] = 0; - end - eop_channel_used[channel[current_beat]] = 0; - end - - if (endofpacket[current_beat]) begin - if (eop_channel_used[channel[current_beat]] == 1) - eop_error_in_channel[current_beat] = 1; - else begin - eop_channel_used[channel[current_beat]] = 1; - eop_error_in_channel[current_beat] = 0; - end - sop_channel_used[channel[current_beat]] = 0; - end - - if (!startofpacket[current_beat] && !endofpacket[current_beat]) begin - if (!sop_channel_used[channel[current_beat]]) begin - data_outside_packet[current_beat] = 1; - end else begin - data_outside_packet[current_beat] = 0; - end - end else begin - data_outside_packet[current_beat] = 0; - end - - endtask - - - // SVA assertion code lives within the following section block - // which is disabled when the macro DISABLE_ALTERA_AVALON_SIM_SVA is defined - - `ifdef DISABLE_ALTERA_AVALON_SIM_SVA - // SVA assertion code has been disabled - - `else - //-------------------------------------------------------------------------- - // ASSERTION CODE BEGIN - //-------------------------------------------------------------------------- - //------------------------------------------------------------------------------- - // =head2 Avalon Streaming Assertions - // The following are the assertions code focus on Streaming Source and Sink - // component checking - //------------------------------------------------------------------------------- - - //------------------------------------------------------------------------------------ - // =head3 p_valid_legal - // This property check if valid is not deasserted ST_READY_LATENCY cycle after ready - // is deasserted. - //------------------------------------------------------------------------------------ - property p_valid_legal(current_beat); - @(posedge clk && enable_a_valid_legal && USE_VALID && USE_READY && ST_READY_LATENCY > 0) - disable iff (reset) - !ready |-> ##ST_READY_LATENCY !valid[current_beat]; - endproperty - - genvar i; - for (i=0; i event_a_valid_legal; - print_assertion("valid asserted after ready deasserted"); - end - end - - //------------------------------------------------------------------------------------ - // =head3 p_empty_legal - // This property check if empty non zero while endofpacket is asserted or empty value - // larger or equal to ST_NUMSYMBOLS - //------------------------------------------------------------------------------------ - property p_empty_legal(current_beat); - @(posedge clk && enable_a_empty_legal && USE_EMPTY && USE_PACKET) - disable iff (reset) - valid[current_beat] && (empty[current_beat] > 0) && (clock_counter > 0) && - ((USE_READY && (ST_READY_LATENCY == 0) && ready) || - !USE_READY || (ST_READY_LATENCY > 0)) - |-> endofpacket[current_beat] && (empty[current_beat] < ST_NUMSYMBOLS); - endproperty - - for (i=0; i event_a_empty_legal; - print_assertion("illegal empty value"); - end - end - - //------------------------------------------------------------------------------------ - // =head3 p_no_data_outside_packet - // This property check if that valid is asserted outside the packet transfer - //------------------------------------------------------------------------------------ - property p_no_data_outside_packet(current_beat); - @(posedge clk && enable_a_no_data_outside_packet && USE_VALID && USE_PACKET) - disable iff (reset) - valid[current_beat] && !startofpacket[current_beat] && !endofpacket[current_beat] && - ((USE_READY && (ST_READY_LATENCY == 0) && ready) || - !USE_READY || (ST_READY_LATENCY > 0)) - |-> ##1 !data_outside_packet[current_beat]; - endproperty - - for (i=0; i event_a_no_data_outside_packet; - print_assertion("valid is asserted outside the packet transfer"); - end - end - - //------------------------------------------------------------------------------------ - // =head3 p_non_missing_endofpacket - // This property check if consecutive startofpacket without endofpacket occurs - //------------------------------------------------------------------------------------ - property p_non_missing_endofpacket(current_beat); - @(posedge clk && enable_a_non_missing_endofpacket && USE_PACKET) - disable iff (reset) - startofpacket[current_beat] && valid[current_beat] && - ((USE_READY && (ST_READY_LATENCY == 0) && ready) || - !USE_READY || (ST_READY_LATENCY > 0)) - |-> ##1 !sop_error_in_channel[current_beat]; - endproperty - - for (i=0; i event_a_non_missing_endofpacket; - print_assertion("consecutive startofpacket without endofpacket"); - end - end - - //------------------------------------------------------------------------------------ - // =head3 p_non_missing_startofpacket - // This property check if consecutive endofpacket without endofpacket occurs - //------------------------------------------------------------------------------------ - property p_non_missing_startofpacket(current_beat); - @(posedge clk && enable_a_non_missing_startofpacket && USE_PACKET) - disable iff (reset) - endofpacket[current_beat] && valid[current_beat] && !startofpacket[current_beat] && - ((USE_READY && (ST_READY_LATENCY == 0) && ready) || - !USE_READY || (ST_READY_LATENCY > 0)) - |-> ##1 !eop_error_in_channel[current_beat]; - endproperty - - for (i=0; i event_a_non_missing_startofpacket; - print_assertion("consecutive endofpacket without startofpacket"); - end - end - - //------------------------------------------------------------------------------------ - // =head3 p_less_than_max_channel - // This property checks if channel size is less than ST_MAX_CHANNELS - //------------------------------------------------------------------------------------ - property p_less_than_max_channel(current_beat); - @(posedge clk && enable_a_less_than_max_channel && USE_CHANNEL) - disable iff (reset) - valid[current_beat] && (channel[current_beat] > 0) && (clock_counter > 0) && - ((USE_READY && (ST_READY_LATENCY == 0) && ready) || - !USE_READY || (ST_READY_LATENCY > 0)) - |-> (channel[current_beat] <= ST_MAX_CHANNELS); - endproperty - - for (i=0; i event_a_less_than_max_channel; - print_assertion("channel size must be within ST_MAX_CHANNELS"); - end - end - - // =cut - - //-------------------------------------------------------------------------- - // ASSERTION CODE END - //-------------------------------------------------------------------------- - `endif - - // synthesis translate_on - -endmodule - - Index: trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/avalon_utilities_pkg.sv =================================================================== --- trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/avalon_utilities_pkg.sv (revision 49) +++ trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/avalon_utilities_pkg.sv (nonexistent) @@ -1,80 +0,0 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/17.1std/ip/sopc/components/verification/lib/avalon_utilities_pkg.sv#1 $ -// $Revision: #1 $ -// $Date: 2017/07/30 $ -//----------------------------------------------------------------------------- -// =head1 NAME -// avalon_utilities_pkg -// =head1 SYNOPSIS -// Package for shared types and functions -//----------------------------------------------------------------------------- -// =head1 COPYRIGHT -// Copyright (c) 2008 Altera Corporation. All Rights Reserved. -// The information contained in this file is the property of Altera -// Corporation. Except as specifically authorized in writing by Altera -// Corporation, the holder of this file shall keep all information -// contained herein confidential and shall protect same in whole or in part -// from disclosure and dissemination to all third parties. Use of this -// program confirms your agreement with the terms of this license. -//----------------------------------------------------------------------------- -// =head1 DESCRIPTION -// This package contains shared types and functions. -// =cut -`timescale 1ns / 1ns - -`ifndef _AVALON_UTILITIES_PKG_ -`define _AVALON_UTILITIES_PKG_ - -package avalon_utilities_pkg; - - function automatic int clog2( - bit [31:0] Depth - ); - int i= Depth; - for(clog2 = 0; i > 0; clog2 = clog2 + 1) - i = i >> 1; - - return clog2; - endfunction - - function automatic int max( - bit [31:0] one, - bit [31:0] two - ); - if(one > two) - return one; - else - return two; - endfunction - - function automatic int lindex( - bit [31:0] width - ); - // returns the left index for a vector having a declared width - // when width is 0, then the left index is set to 0 rather than -1 - lindex = (width > 0) ? (width-1) : 0; - endfunction - - typedef enum int { - LOW = 0, - HIGH = 1, - RANDOM = 2, - UNKNOWN = 3 - } IdleOutputValue_t; - -endpackage - -`endif - Index: trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_transactions.sv =================================================================== --- trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_transactions.sv (revision 49) +++ trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor_transactions.sv (nonexistent) @@ -1,404 +0,0 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $File: //acds/rel/17.1std/ip/sopc/components/verification/altera_avalon_st_monitor_bfm/altera_avalon_st_monitor_transactions.sv $ -// $Revision: #1 $ -// $Date: 2017/07/30 $ -// $Author: swbranch $ -//----------------------------------------------------------------------------- -// =head1 NAME -// altera_avalon_st_monitor_transactions -// =head1 SYNOPSIS -// Streaming Avalon Bus Protocol Checker -//----------------------------------------------------------------------------- -// =head1 DESCRIPTION -// This module implements Avalon ST protocol transaction recording. -//----------------------------------------------------------------------------- - -`timescale 1ns / 1ns - -module altera_avalon_st_monitor_transactions( - clk, - reset, - tap - ); - - // =head1 PARAMETERS - parameter ST_SYMBOL_W = 8; // number of bits in one symbols - parameter ST_NUMSYMBOLS = 4; // number of symbols in one data - parameter ST_CHANNEL_W = 0; // width of channel signal - parameter ST_ERROR_W = 0; // width of error signal - parameter ST_EMPTY_W = 0; // width of empty signal - - parameter ST_READY_LATENCY = 0; // fixed ready latency in cycles - parameter ST_MAX_CHANNELS = 1; // maximum number of channels - - parameter USE_PACKET = 0; // data transfer in packet format - parameter USE_CHANNEL = 0; // use channel port - parameter USE_ERROR = 0; // use error port - parameter USE_READY = 1; // use ready port - parameter USE_VALID = 1; // use valid port - parameter USE_EMPTY = 0; // use empty port - parameter ST_BEATSPERCYCLE = 1; // Max number of packets per cycle - - parameter ST_MAX_PACKET_SIZE = 1; // Max number of packet size covered - - localparam ST_DATA_W = ST_SYMBOL_W * ST_NUMSYMBOLS; - localparam ST_MDATA_W = ST_BEATSPERCYCLE * ST_DATA_W; - localparam ST_MCHANNEL_W = ST_BEATSPERCYCLE * ST_CHANNEL_W; - localparam ST_MERROR_W = ST_BEATSPERCYCLE * ST_ERROR_W; - localparam ST_MEMPTY_W = ST_BEATSPERCYCLE * ST_EMPTY_W; - - localparam ST_MAX_EMPTY = 2**(ST_EMPTY_W) - 1; - localparam NUM_CHANNEL = (ST_MAX_CHANNELS > 1)? ST_MAX_CHANNELS:1; - localparam FIFO_MAX_LEVEL = 100; - localparam FIFO_THRESHOLD = 50; - - localparam TAP_W = ((ST_DATA_W == 0)? 1:ST_DATA_W) + // data - ((ST_CHANNEL_W == 0)? 1:ST_CHANNEL_W) + // channel - 1 + // valid - 1 + // startofpacket - 1 + // endofpacket - ((ST_ERROR_W == 0)? 1:ST_ERROR_W) + // error - ((ST_EMPTY_W == 0)? 1:ST_EMPTY_W) + // empty - 1; // ready - - // =head1 PINS - // =head2 Clock Interface - input clk; - input reset; - - // =head2 Avalon Monitor Interface - will be defined as Streaming Sink - input [(TAP_W*ST_BEATSPERCYCLE)-ST_BEATSPERCYCLE:0] tap; - - // =cut - - function int lindex; - // returns the left index for a vector having a declared width - // when width is 0, then the left index is set to 0 rather than -1 - input [31:0] width; - lindex = (width > 0) ? (width-1) : 0; - endfunction - - //-------------------------------------------------------------------------- - // synthesis translate_off - - import verbosity_pkg::*; - - //-------------------------------------------------------------------------- - // Private Types and Variables - //-------------------------------------------------------------------------- - - typedef logic [lindex(ST_DATA_W) :0] STData_t; - typedef logic [lindex(ST_CHANNEL_W) :0] STChannel_t; - typedef logic [lindex(ST_EMPTY_W) :0] STEmpty_t; - typedef logic [lindex(ST_ERROR_W) :0] STError_t; - - typedef logic [lindex(ST_MDATA_W) :0] STMData_t; - typedef logic [lindex(ST_MCHANNEL_W) :0] STMChannel_t; - typedef logic [lindex(ST_MEMPTY_W) :0] STMEmpty_t; - typedef logic [lindex(ST_MERROR_W) :0] STMError_t; - typedef logic [ST_BEATSPERCYCLE-1 :0] STBeats_t; - - typedef struct packed - { - bit [31:0] idles; - logic startofpacket; - logic endofpacket; - STChannel_t channel; - STData_t data; - STError_t error; - STEmpty_t empty; - } Transaction_t; - - Transaction_t current_transaction[ST_BEATSPERCYCLE]; - Transaction_t query_transaction; - Transaction_t transaction_queue[$]; - - // unpack Avalon bus interface tap into individual port signals - logic [lindex(ST_MDATA_W): 0] sink_data; - logic [lindex(ST_MCHANNEL_W): 0] sink_channel; - logic [ST_BEATSPERCYCLE-1: 0] sink_valid; - logic [ST_BEATSPERCYCLE-1: 0] sink_startofpacket; - logic [ST_BEATSPERCYCLE-1: 0] sink_endofpacket; - logic [lindex(ST_MERROR_W): 0] sink_error; - logic [lindex(ST_MEMPTY_W): 0] sink_empty; - logic sink_ready; - - string message = "*uninitialized*"; - logic ready = 0; - int idle_ctr = 0; - int transaction_fifo_max = FIFO_MAX_LEVEL; - int transaction_fifo_threshold = FIFO_THRESHOLD; - - STBeats_t sink_valid_qualified; - logic sink_ready_qualified; - - localparam MAX_READY_DELAY = 8; - logic [MAX_READY_DELAY-1:0] sink_ready_delayed; - - //-------------------------------------------------------------------------- - // Private Functions - //-------------------------------------------------------------------------- - - function int __floor(int arg); - // returns the arg if it is greater than 0, else returns 0 - return (arg > 0) ? arg : 0; - endfunction - - //-------------------------------------------------------------------------- - // =head1 Public Methods API - // This section describes the public methods in the application programming - // interface (API). In this case the application program is the test bench - // which instantiates and controls and queries state of this component. - // Test programs must only use these public access methods and events to - // communicate with this BFM component. The API and the module pins - // are the only interfaces in this component that are guaranteed to be - // stable. The API will be maintained for the life of the product. - // While we cannot prevent a test program from directly accessing internal - // tasks, functions, or data private to the BFM, there is no guarantee that - // these will be present in the future. In fact, it is best for the user - // to assume that the underlying implementation of this component can - // and will change. - //-------------------------------------------------------------------------- - event signal_fatal_error; // public - // Signal that a fatal error has occurred. Terminates simulation. - - event signal_transaction_received; //public - // Signal that a transaction has been received and queued. - - event signal_transaction_fifo_threshold; // public - // Signal that the transaction FIFO threshold level has been exceeded - - event signal_transaction_fifo_overflow; // public - // Signal that the FIFO is full and further transactions are being dropped - - function automatic string get_version(); // public - // Return component version as a string of three integers separated by periods. - // For example, version 9.1 sp1 is encoded as "9.1.1". - string ret_version = "17.1"; - return ret_version; - endfunction - - function automatic void set_transaction_fifo_max( // public - int level - ); - // Set the maximum fullness level of the FIFO. The event - // signal_transaction_fifo_max is triggered when this - // level is exceeded. - transaction_fifo_max = level; - endfunction - - function automatic int get_transaction_fifo_max(); - // Get the maximum transaction FIFO depth. - return transaction_fifo_max; - endfunction - - function automatic void set_transaction_fifo_threshold( // public - int level - ); - // Set the threshold alert level of the FIFO. The event - // signal_transaction_fifo_threshold is triggered when this - // level is exceeded. - transaction_fifo_threshold = level; - endfunction - - function automatic int get_transaction_fifo_threshold(); - // Get the transaction FIFO threshold level. - return transaction_fifo_threshold; - endfunction - - function automatic void pop_transaction(); // public - // Pop the transaction descriptor from the queue so that it can be - // queried with the get_transaction methods by the test bench. - if (reset) begin - $sformat(message, "%m: Illegal command while reset asserted"); - print(VERBOSITY_ERROR, message); - ->signal_fatal_error; - end - - query_transaction = transaction_queue.pop_back(); - - $sformat(message, "%m: called pop_transaction"); - print(VERBOSITY_DEBUG, message); - $sformat(message, "%m: Data: %x", query_transaction.data); - print(VERBOSITY_DEBUG, message); - $sformat(message, "%m: Channel: %0d", query_transaction.channel); - print(VERBOSITY_DEBUG, message); - $sformat(message, "%m: SOP: %0d EOP: %0d", - query_transaction.startofpacket, - query_transaction.endofpacket); - print(VERBOSITY_DEBUG, message); - endfunction - - function automatic bit[31:0] get_transaction_idles(); // public - // Return the number of idle cycles in the transaction - $sformat(message, "%m: called get_transaction_idles"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.idles; - endfunction - - function automatic logic [ST_DATA_W-1:0] get_transaction_data(); // public - // Return the data in the transaction - $sformat(message, "%m: called get_transaction_data"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.data; - endfunction - - function automatic logic [ST_CHANNEL_W-1:0] get_transaction_channel(); // public - // Return the channel identifier in the transaction - $sformat(message, "%m: called get_transaction_channel"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.channel; - endfunction - - function automatic logic get_transaction_sop(); // public - // Return the start of packet status in the transaction - $sformat(message, "%m: called get_transaction_sop"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.startofpacket; - endfunction - - function automatic logic get_transaction_eop(); // public - // Return the end of packet status in the transaction - $sformat(message, "%m: called get_transaction_eop"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.endofpacket; - endfunction - - function automatic logic [ST_ERROR_W-1:0] get_transaction_error(); // public - // Return the error status in the transaction - $sformat(message, "%m: called get_transaction_error"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.error; - endfunction - - function automatic logic [ST_EMPTY_W-1:0] get_transaction_empty(); // public - // Return the number of empty symbols in the transaction - $sformat(message, "%m: called get_transaction_empty"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.empty; - endfunction - - function automatic int get_transaction_queue_size(); // public - // Return the length of the queue holding received transactions - $sformat(message, "%m: called get_transaction_queue_size"); - print(VERBOSITY_DEBUG, message); - - // Return the number of transactions in the internal queues. - return transaction_queue.size(); - endfunction - - // =cut - - //-------------------------------------------------------------------------- - // Local Machinery - //-------------------------------------------------------------------------- - always @(signal_fatal_error) abort_simulation(); - - always @(*) begin - { - sink_data, - sink_channel, - sink_valid, - sink_startofpacket, - sink_endofpacket, - sink_error, - sink_empty, - sink_ready - } <= tap; - end - - // delay chain for sink_ready back pressure output to account for latency - always @(posedge clk or posedge reset) begin - if (reset) begin - sink_ready_delayed <= 0; - end else begin - sink_ready_delayed <= {sink_ready_delayed[6:0], sink_ready}; - end - end - - always @(*) begin - if (USE_READY == 0) - sink_ready_qualified = 1'b1; - else begin - if (ST_READY_LATENCY == 0) - sink_ready_qualified = sink_ready; - else - sink_ready_qualified = sink_ready_delayed[__floor(ST_READY_LATENCY-1)]; - end - end - - always @(sink_valid) begin - if (USE_VALID > 0) - sink_valid_qualified = sink_valid; - else - sink_valid_qualified = '1; - end - - always @(posedge clk or posedge reset) begin - if (reset) begin - for (int i=0; i 0) ? (width-1) : 0; - endfunction - - function automatic int __floor1( - bit [31:0] arg - ); - __floor1 = (arg <1) ? 1 : arg; - endfunction - - - //-------------------------------------------------------------------------- - // synthesis translate_off - - import verbosity_pkg::*; - - typedef bit [lindex(ST_DATA_W) :0] STData_t; - typedef bit [lindex(ST_CHANNEL_W) :0] STChannel_t; - typedef bit [lindex(ST_EMPTY_W) :0] STEmpty_t; - typedef bit [lindex(ST_ERROR_W) :0] STError_t; - - string message = "*unitialized*"; - - bit covergroup_settings_changed_flag = 0; - bit enable_c_packet_no_idles_no_back_pressure = 1; - bit enable_c_packet_with_idles = 1; - bit enable_c_packet_with_back_pressure = 1; - bit enable_c_channel_change_in_packet = 1; - bit enable_c_empty = 1; - bit enable_c_transfer = 1; - bit enable_c_error = 1; - bit enable_c_packet = 1; - bit enable_c_b2b_packet_different_channel = 1; - bit enable_c_b2b_packet_same_channel = 1; - bit enable_c_b2b_data_different_channel = 1; - bit enable_c_b2b_data_same_channel = 1; - bit enable_c_valid_non_ready = 1; - bit enable_c_non_valid_ready = 1; - bit enable_c_non_valid_non_ready = 1; - bit enable_c_transaction_after_reset = 1; - bit enable_c_packet_size = 1; - bit enable_c_multiple_packet_per_cycle = 1; - bit enable_c_single_packet_per_cycle = 1; - bit enable_c_idle_beat_between_packet = 1; - bit enable_c_all_idle_beats = 1; - bit enable_c_all_valid_beats = 1; - bit enable_c_partial_valid_beats = 1; - bit enable_c_b2b_packet_within_single_cycle = 1; - bit enable_c_b2b_packet_in_different_cycle = 1; - bit enable_c_error_in_middle_of_packet = 1; - - //-------------------------------------------------------------------------- - // unpack Avalon bus interface tap into individual port signals - logic ready; - logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_DATA_W):0] data; - logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_CHANNEL_W):0] channel; - logic [lindex(ST_BEATSPERCYCLE):0] valid; - logic [lindex(ST_BEATSPERCYCLE):0] startofpacket; - logic [lindex(ST_BEATSPERCYCLE):0] endofpacket; - logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_ERROR_W):0] error; - logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_EMPTY_W):0] empty; - - always_comb begin - data <= tap[lindex(ST_DATA_W*ST_BEATSPERCYCLE)+lindex(ST_CHANNEL_W*ST_BEATSPERCYCLE)+ - lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+4: - lindex(ST_CHANNEL_W*ST_BEATSPERCYCLE)+lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+4]; - - channel <= (USE_CHANNEL == 1)? - tap[lindex(ST_CHANNEL_W*ST_BEATSPERCYCLE)+lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+ - lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+3: - lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+3] : 0; - - valid <= (USE_VALID == 1)? - tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3*ST_BEATSPERCYCLE+2: - lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2*ST_BEATSPERCYCLE+3] : - (reset == 1)? 'x: 1; - - startofpacket <= (USE_PACKET == 1)? - tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2*ST_BEATSPERCYCLE+2: - lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+ST_BEATSPERCYCLE+3] : 0; - - endofpacket <= (USE_PACKET == 1)? - tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+ST_BEATSPERCYCLE+2: - lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+3] : 0; - - error <= (USE_ERROR == 1)? - tap[lindex(ST_ERROR_W*ST_BEATSPERCYCLE)+lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2: - lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+2] : 0; - - empty <= (USE_EMPTY == 1)? tap[lindex(ST_EMPTY_W*ST_BEATSPERCYCLE)+1:1] : 0; - - ready <= (USE_READY == 1)? tap[0:0] : 1; - end - - //-------------------------------------------------------------------------- - // General Statistics Counters - //-------------------------------------------------------------------------- - - logic [31:0] clock_counter; - logic [31:0] sop_counter; - logic [31:0] eop_counter; - - logic sop_counter_reset = 0; - logic eop_counter_reset = 0; - - logic [lindex(NUM_CHANNEL):0] packet_no_idles_no_back_pressure_flag = '1; - logic [lindex(NUM_CHANNEL):0] packet_with_back_pressure_flag = 0; - logic [lindex(NUM_CHANNEL):0] channel_change_in_packet_flag = 0; - logic [lindex(NUM_CHANNEL):0] packet_with_idles_flag = 0; - logic [31:0] idles_between_b2b_packet_same_channel_counter = 0; - logic [31:0] idles_between_b2b_packet_different_channel_counter = 0; - logic [31:0] idles_between_b2b_data_same_channel_counter = 0; - logic [31:0] idles_between_b2b_data_different_channel_counter = 0; - logic [lindex(NUM_CHANNEL):0] current_packet = 0; - logic [lindex(ST_BEATSPERCYCLE):0][lindex(ST_CHANNEL_W):0] past_channel = 0; - logic [lindex(ST_BEATSPERCYCLE):0] past_endofpacket = 0; - logic idles_between_packet_same_channel_sampled = 0; - logic idles_between_packet_different_channel_sampled = 0; - logic non_valid_ready_sampled = 0; - logic non_valid_non_ready_sampled = 0; - logic [lindex(ST_BEATSPERCYCLE):0] current_beat = 0; - logic [lindex(ST_BEATSPERCYCLE):0] current_beat_2 = 0; - logic [31:0] error_bit_num = 0; - logic [31:0] changed_channel = 0; - logic transaction_after_reset = 0; - logic all_valid_beats_flag = 0; - logic all_invalid_beats_flag = 0; - logic partial_valid_beats_flag = 0; - logic [31:0] idles_between_b2b_packet_transaction_counter = 0; - logic [31:0] idles_between_packet_within_single_transaction_sampled = 0; - logic [31:0] packet_per_transaction = 0; - logic [lindex(NUM_CHANNEL):0][31:0] packet_size = 0; - logic [31:0] error_in_middle_of_packet = 0; - logic [31:0] idles_between_packet_in_different_transaction_sampled = 0; - logic [31:0] invalid_beat_between_packet = 0; - logic packet_per_transaction_flag = 0; - logic channel_change = 0; - logic reset_status = 0; - - always @(posedge clk) begin - if (reset) - clock_counter <= 0; - else - clock_counter <= clock_counter + 1; - end - - always @(posedge clk) begin - if (reset) begin - sop_counter <= 0; - end else if (sop_counter_reset) begin - sop_counter_reset <= 0; - sop_counter <= 0; - end else begin - sop_counter <= (USE_PACKET && valid && startofpacket) ? - sop_counter + 1 : - sop_counter; - end - end - - always @(posedge clk) begin - if (reset) begin - eop_counter <= 0; - end else if (eop_counter_reset) begin - eop_counter_reset <= 0; - eop_counter <= 0; - end else begin - eop_counter <= (USE_PACKET && valid && endofpacket) ? - eop_counter + 1 : eop_counter; - end - end - - //-------------------------------------------------------------------------- - // =head1 Public Methods API - // This section describes the public methods in the application programming - // interface (API). In this case the application program is the test bench - // which instantiates and controls and queries state of this component. - // Test programs must only use these public access methods and events to - // communicate with this BFM component. The API and the module pins - // are the only interfaces in this component that are guaranteed to be - // stable. The API will be maintained for the life of the product. - // While we cannot prevent a test program from directly accessing internal - // tasks, functions, or data private to the BFM, there is no guarantee that - // these will be present in the future. In fact, it is best for the user - // to assume that the underlying implementation of this component can - // and will change. - // =cut - //-------------------------------------------------------------------------- - - // ST Coverage API - function automatic void set_enable_c_packet_no_idles_no_back_pressure( // public - bit cover_enable - ); - // enable or disable c_packet_no_idles_no_back_pressure cover group - - enable_c_packet_no_idles_no_back_pressure = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_packet_no_idles_no_back_pressure"); - endfunction - - function automatic void set_enable_c_packet_with_idles( // public - bit cover_enable - ); - // enable or disable c_packet_with_idles cover group - - enable_c_packet_with_idles = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_packet_with_idles"); - endfunction - - function automatic void set_enable_c_packet_with_back_pressure( // public - bit cover_enable - ); - // enable or disable c_packet_with_back_pressure cover group - - enable_c_packet_with_back_pressure = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_packet_with_back_pressure"); - endfunction - - function automatic void set_enable_c_channel_change_in_packet( // public - bit cover_enable - ); - // enable or disable c_channel_change_in_packet cover group - - enable_c_channel_change_in_packet = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_channel_change_in_packet"); - endfunction - - function automatic void set_enable_c_empty( // public - bit cover_enable - ); - // enable or disable c_empty cover group - - enable_c_empty = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_empty"); - endfunction - - function automatic void set_enable_c_transfer( // public - bit cover_enable - ); - // enable or disable c_transfer cover group - - enable_c_transfer = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_transfer"); - endfunction - - function automatic void set_enable_c_error( // public - bit cover_enable - ); - // enable or disable c_error cover group - - enable_c_error = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_error"); - endfunction - - function automatic void set_enable_c_packet( // public - bit cover_enable - ); - // enable or disable c_packet cover group - - enable_c_packet = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_packet"); - endfunction - - function automatic void set_enable_c_b2b_packet_different_channel( // public - bit cover_enable - ); - // enable or disable c_b2b_packet_different_channel cover group - - enable_c_b2b_packet_different_channel = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_packet_different_channel"); - endfunction - - function automatic void set_enable_c_b2b_packet_same_channel( // public - bit cover_enable - ); - // enable or disable c_b2b_packet_same_channel cover group - - enable_c_b2b_packet_same_channel = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_packet_same_channel"); - endfunction - - function automatic void set_enable_c_b2b_data_different_channel( // public - bit cover_enable - ); - // enable or disable c_b2b_data_different_channel cover group - - enable_c_b2b_data_different_channel = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_data_different_channel"); - endfunction - - function automatic void set_enable_c_b2b_data_same_channel( // public - bit cover_enable - ); - // enable or disable c_b2b_data_same_channel cover group - - enable_c_b2b_data_same_channel = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_data_same_channel"); - endfunction - - function automatic void set_enable_c_valid_non_ready( // public - bit cover_enable - ); - // enable or disable c_valid_non_ready cover group - - enable_c_valid_non_ready = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_valid_non_ready"); - endfunction - - function automatic void set_enable_c_non_valid_ready( // public - bit cover_enable - ); - // enable or disable c_non_valid_ready cover group - - enable_c_non_valid_ready = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_non_valid_ready"); - endfunction - - function automatic void set_enable_c_non_valid_non_ready( // public - bit cover_enable - ); - // enable or disable c_non_valid_non_ready cover group - - enable_c_non_valid_non_ready = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_non_valid_non_ready"); - endfunction - - function automatic void set_enable_c_transaction_after_reset( // public - bit cover_enable - ); - // enable or disable transaction_after_reset cover group - - enable_c_transaction_after_reset = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_transaction_after_reset"); - endfunction - - function automatic void set_enable_c_packet_size( // public - bit cover_enable - ); - // enable or disable c_packet_size cover group - - enable_c_packet_size = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_packet_size"); - endfunction - - function automatic void set_enable_c_multiple_packet_per_cycle( // public - bit cover_enable - ); - // enable or disable c_multiple_packet_per_cycle cover group - - enable_c_multiple_packet_per_cycle = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_multiple_packet_per_cycle"); - endfunction - - function automatic void set_enable_c_single_packet_per_cycle( // public - bit cover_enable - ); - // enable or disable c_single_packet_per_cycle cover group - - enable_c_single_packet_per_cycle = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_single_packet_per_cycle"); - endfunction - - function automatic void set_enable_c_idle_beat_between_packet( // public - bit cover_enable - ); - // enable or disable c_idle_beat_between_packet cover group - - enable_c_idle_beat_between_packet = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_idle_beat_between_packet"); - endfunction - - function automatic void set_enable_c_all_valid_beats( // public - bit cover_enable - ); - // enable or disable c_all_valid_beats cover group - - enable_c_all_valid_beats = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_all_valid_beats"); - endfunction - - function automatic void set_enable_c_all_idle_beats( // public - bit cover_enable - ); - // enable or disable c_all_idle_beats cover group - - enable_c_all_idle_beats = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_all_idle_beats"); - endfunction - - function automatic void set_enable_c_partial_valid_beats( // public - bit cover_enable - ); - // enable or disable c_partial_valid_beats cover group - - enable_c_partial_valid_beats = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_partial_valid_beats"); - endfunction - - function automatic void set_enable_c_b2b_packet_within_single_cycle( // public - bit cover_enable - ); - // enable or disable c_b2b_packet_within_single_cycle cover group - - enable_c_b2b_packet_within_single_cycle = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_packet_within_single_cycle"); - endfunction - - function automatic void set_enable_c_b2b_packet_in_different_transaction( // public - bit cover_enable - ); - // enable or disable c_b2b_packet_in_different_transaction cover group - - enable_c_b2b_packet_in_different_cycle = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_packet_in_different_cycle"); - endfunction - - function automatic void set_enable_c_error_in_middle_of_packet( // public - bit cover_enable - ); - // enable or disable c_error_in_middle_of_packet cover group - - enable_c_error_in_middle_of_packet = cover_enable; - coverage_settings_check(covergroup_settings_changed_flag, "c_error_in_middle_of_packet"); - endfunction - - // =cut - - function automatic logic [31:0] get_sop_counter(); - return sop_counter; - if (USE_PACKET == 0) begin - $sformat(message, "%m: No packet signals in this stream (USE_PACKET = 0)."); - print(VERBOSITY_WARNING, message); - end - endfunction - - function automatic void reset_sop_counter(); - sop_counter_reset = 1'b1; - endfunction - - function automatic logic [31:0] get_eop_counter(); - return eop_counter; - if (USE_PACKET == 0) begin - $sformat(message, "%m: No packet signals in this stream (USE_PACKET = 0)."); - print(VERBOSITY_WARNING, message); - end - endfunction - - function automatic void reset_eop_counter(); - eop_counter_reset = 1'b1; - endfunction - - function void coverage_settings_check( - bit cover_flag, - string cover_name - ); - string message; - if (cover_flag) begin - $sformat(message, "%m: - Changing %s covergroup settings during run-time will not be reflected", - cover_name); - print(VERBOSITY_WARNING, message); - end - endfunction - - `ifdef DISABLE_ALTERA_AVALON_SIM_SVA - // SVA coverage code is disabled when this macro is defined - `else - //-------------------------------------------------------------------------- - // COVERAGE CODE BEGIN - //-------------------------------------------------------------------------- - - function automatic void print_assertion( //private - string message_in - ); - string message_out; - $sformat(message_out, "ASSERTION: %s", message_in); - print(VERBOSITY_FAILURE, message_out); - endfunction - - function logic [1023:0] pow( //private - input int power_value - ); - // This method return the maximum supported value for the port width. - pow = (2**(power_value) - 1); - endfunction - - function automatic logic [31:0] count_ones ( //private - input logic [1023:0] value - ); - // This method return number of 1 bits - if (value == 0) - count_ones = 0; - else if (value == 'x) begin - count_ones = 'x; - end else begin - for( count_ones = 0; value!= 0; value = value >> 1 ) - count_ones += value & 1'b1; - end - endfunction - - function integer log2( //private - input int value - ); - // Mathematic logarithm function with base as 2. - value = value-1; - for (log2=0; value>0; log2=log2+1) - begin - value = value>>1; - end - endfunction - - task sample_non_valid_ready(); - fork - begin - repeat(ST_READY_LATENCY) begin - @(posedge clk); - end - non_valid_ready_sampled = 1; - end - join_none - endtask - - //-------------------------------------------------------------------------- - // =head1 Assertion Checkers and Coverage Monitors - // The assertion checkers in this module are only executable on simulators - // supporting the SystemVerilog Assertion (SVA) language. - // Mentor Modelsim AE and SE do not support this. - // Simulators that are supported include: Synopsys VCS and Mentor questasim. - // The assertion checking logic in this module must be explicitly enabled - // so that designs using this module can still be compiled on Modelsim without - // changes. To disable assertions define the following macro in the testbench - // or on the command line with: +define+DISABLE_ALTERA_AVALON_SIM_SVA. - // =cut - //-------------------------------------------------------------------------- - - - always @(posedge clk) - begin - if (!reset) begin - for (int i=0; i 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin - - if (enable_c_transaction_after_reset && USE_VALID) begin - c_transaction_after_reset.sample(); - transaction_after_reset = 0; - end - - if (enable_c_transfer && USE_VALID && USE_READY) begin - c_transfer.sample(); - end - - if (enable_c_empty && USE_EMPTY) begin - c_empty.sample(); - end - - if (enable_c_error && USE_ERROR) begin - for (int j = 0; j < ST_ERROR_W; j++) begin - if (error[current_beat][j] == 1) begin - error_bit_num = j; - c_error.sample(); - end - end - end - - if (startofpacket[i]) begin - if (!endofpacket[i]) begin - current_packet[channel[i]] = 1; - end else begin - packet_size[channel[i]]++; - end - - if (error[i] > 0) begin - error_in_middle_of_packet = 1; - end else begin - error_in_middle_of_packet = 0; - end - - if (enable_c_error_in_middle_of_packet && USE_ERROR && USE_PACKET) begin - c_error_in_middle_of_packet.sample(); - error_in_middle_of_packet = 0; - end - - packet_no_idles_no_back_pressure_flag[channel[i]] = 1; - - //counter to determine time to sample signal - if (i == 0) begin - if (channel[i] != past_channel[ST_BEATSPERCYCLE-1]) begin - idles_between_packet_same_channel_sampled = 0; - if (past_endofpacket[ST_BEATSPERCYCLE-1] == 1) begin - idles_between_packet_different_channel_sampled = 1; - idles_between_packet_in_different_transaction_sampled = 1; - end else begin - idles_between_packet_different_channel_sampled = 0; - idles_between_packet_in_different_transaction_sampled = 0; - end - end else begin - idles_between_packet_different_channel_sampled = 0; - if (past_endofpacket[ST_BEATSPERCYCLE-1] == 1) begin - idles_between_packet_same_channel_sampled = 1; - idles_between_packet_in_different_transaction_sampled = 1; - end else begin - idles_between_packet_same_channel_sampled = 0; - idles_between_packet_in_different_transaction_sampled = 0; - end - end - idles_between_packet_within_single_transaction_sampled = 0; - end else begin - if (channel[i] != channel[i-1]) begin - idles_between_packet_same_channel_sampled = 0; - if (endofpacket[i-1] == 1) begin - idles_between_packet_different_channel_sampled = 1; - idles_between_packet_within_single_transaction_sampled = 1; - end else begin - idles_between_packet_different_channel_sampled = 0; - idles_between_packet_within_single_transaction_sampled = 0; - end - end else begin - idles_between_packet_different_channel_sampled = 0; - if (endofpacket[i-1] == 1) begin - idles_between_packet_same_channel_sampled = 1; - idles_between_packet_within_single_transaction_sampled = 1; - end else begin - idles_between_packet_same_channel_sampled = 0; - idles_between_packet_within_single_transaction_sampled = 0; - end - end - idles_between_packet_in_different_transaction_sampled = 0; - end - - if (enable_c_b2b_packet_different_channel && USE_CHANNEL && USE_PACKET && USE_VALID && (ST_MAX_CHANNELS > 0)) begin - if (idles_between_packet_different_channel_sampled) begin - c_b2b_packet_different_channel.sample(); - end - end - - if (enable_c_b2b_packet_same_channel && USE_PACKET && USE_VALID) begin - if (idles_between_packet_same_channel_sampled) begin - c_b2b_packet_same_channel.sample(); - end - end - - if (enable_c_b2b_packet_within_single_cycle && USE_PACKET && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin - if (idles_between_packet_within_single_transaction_sampled) begin - c_b2b_packet_within_single_cycle.sample(); - end - end - - if (enable_c_b2b_packet_in_different_cycle && USE_PACKET && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin - if (idles_between_packet_in_different_transaction_sampled) begin - c_b2b_packet_in_different_cycle.sample(); - end - end - - if ((count_ones(current_packet) == 1) || ((count_ones(current_packet) == 0) &&(endofpacket[i]))) begin - if (enable_c_idle_beat_between_packet && USE_VALID && USE_PACKET && (ST_BEATSPERCYCLE > 1)) begin - c_idle_beat_between_packet.sample(); - invalid_beat_between_packet = 0; - end - end - end - - for (int j = 0; j 0)) begin - c_channel_change_in_packet.sample(); - channel_change_in_packet_flag[channel[i]] = 0; - end - - if (enable_c_packet_with_back_pressure && USE_READY && USE_PACKET) begin - c_packet_with_back_pressure.sample(); - packet_with_back_pressure_flag[channel[i]] = 0; - end - - if (enable_c_packet_size && USE_PACKET) begin - c_packet_size.sample(); - packet_size[channel[i]] = 0; - end - - end - - if (i == 0) begin - if (channel[i] != past_channel[ST_BEATSPERCYCLE-1]) begin - if (((count_ones(current_packet) == 1) && !startofpacket[i]) || - (count_ones(current_packet) > 1)) begin - if(current_packet[past_channel[ST_BEATSPERCYCLE-1]] == 1) begin - channel_change_in_packet_flag[past_channel[ST_BEATSPERCYCLE-1]] = 1; - end - end - end - end else begin - if (channel[i] != channel[i-1]) begin - if (((count_ones(current_packet) == 1) && !startofpacket[i]) || - (count_ones(current_packet) > 1)) begin - if(current_packet[channel[i-1]] == 1) begin - channel_change_in_packet_flag[channel[i-1]] = 1; - end - end - end - end - - end else begin - if (count_ones(current_packet) == 0) begin - invalid_beat_between_packet = 1; - end - end - end else if (USE_VALID && (valid[i] == 0)) begin - if (count_ones(current_packet) == 0) begin - invalid_beat_between_packet = 1; - end - end - - //counter for idles transaction - if (!valid[i]) begin - for (int j = 0; j 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin - if (endofpacket[i]) begin - idles_between_b2b_packet_same_channel_counter = 0; - idles_between_b2b_packet_different_channel_counter = 0; - idles_between_b2b_packet_transaction_counter = 0; - end - end - - if ((!startofpacket[i] && !endofpacket[i]) || (USE_READY && (ST_READY_LATENCY == 0) && !ready)) begin - idles_between_b2b_packet_different_channel_counter++; - idles_between_b2b_packet_transaction_counter++; - end - end - - if (((USE_VALID && valid[i]) || !USE_VALID)) begin - if ((ST_READY_LATENCY > 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin - if (enable_c_b2b_data_different_channel && USE_CHANNEL && USE_VALID && (ST_MAX_CHANNELS > 0)) begin - c_b2b_data_different_channel.sample(); - idles_between_b2b_data_different_channel_counter = 0; - end - - if (enable_c_b2b_data_same_channel && USE_VALID) begin - c_b2b_data_same_channel.sample(); - idles_between_b2b_data_same_channel_counter = 0; - end - end - end - - if (!reset_status) - transaction_after_reset = 0; - end - - // counter to capture previous cycle signal value - for (int i=0; i 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin - past_endofpacket[i] <= endofpacket[i]; - for (int k = i; k < ST_BEATSPERCYCLE; k++) begin - past_channel[k] <= channel[k]; - end - end else - past_endofpacket[i] <= 0; - end else begin - past_endofpacket[i] <= 0; - end - end - reset_status = 0; - end - end - - always @(posedge clk) - begin - if (!reset) begin - if (ready) begin - if (ST_READY_LATENCY == 0) begin - non_valid_ready_sampled = 1; - end else begin - sample_non_valid_ready(); - end - end - - if (enable_c_valid_non_ready && USE_READY && USE_VALID && (ST_READY_LATENCY == 0)) begin - for (int i=0; i 1)) begin - if ((ST_READY_LATENCY > 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin - if (count_ones(valid) == ST_BEATSPERCYCLE) begin - all_valid_beats_flag = 1; - end else begin - all_valid_beats_flag = 0; - end - - if ((count_ones(valid) == 0) && (valid[0] == 0)) begin - all_invalid_beats_flag = 1; - end else begin - all_invalid_beats_flag = 0; - end - - if ((count_ones(valid) > 0) && (count_ones(valid) < ST_BEATSPERCYCLE)) begin - partial_valid_beats_flag = 1; - end else begin - partial_valid_beats_flag = 0; - end - - if (enable_c_all_valid_beats && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin - c_all_valid_beats.sample(); - end - if (enable_c_all_idle_beats && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin - c_all_idle_beats.sample(); - end - if (enable_c_partial_valid_beats && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin - c_partial_valid_beats.sample(); - end - end - end - - if (USE_PACKET && (ST_BEATSPERCYCLE > 1)) begin - for (int i=0; i 0) || (USE_READY && (ST_READY_LATENCY == 0) && ready) || !USE_READY) begin - if (((USE_VALID && valid[i]) || !USE_VALID)) begin - if (i > 0) begin - for (int j = 0; j < i; j++) begin - if (valid[j] == 1) begin - packet_per_transaction_flag = 1; - end - if ((channel[i] != channel[j]) && valid[j]) begin - channel_change = 1; - end - end - if (channel_change && packet_per_transaction_flag) begin - packet_per_transaction++; - end else begin - if ((startofpacket[i]) && packet_per_transaction_flag) begin - packet_per_transaction++; - end - end - channel_change = 0; - end - end - - if (i == (ST_BEATSPERCYCLE-1)) begin - if (enable_c_multiple_packet_per_cycle && USE_PACKET && (ST_BEATSPERCYCLE > 1)) begin - c_multiple_packet_per_cycle.sample(); - end - - if (enable_c_single_packet_per_cycle && USE_PACKET && (ST_BEATSPERCYCLE > 1)) begin - if ((valid > 0)) begin - c_single_packet_per_cycle.sample(); - end - end - packet_per_transaction = 0; - end - end - end - packet_per_transaction_flag = 0; - end - end - end - - - always @(negedge reset) - begin - non_valid_non_ready_sampled = 1; - end - - //counter while reset - always @(posedge clk) - begin - if (reset) begin - non_valid_ready_sampled = 0; - non_valid_non_ready_sampled = 0; - packet_no_idles_no_back_pressure_flag = '1; - packet_with_back_pressure_flag = 0; - idles_between_b2b_packet_same_channel_counter = 0; - idles_between_b2b_packet_different_channel_counter = 0; - channel_change_in_packet_flag = 0; - packet_with_idles_flag = 0; - idles_between_packet_same_channel_sampled = 0; - idles_between_packet_different_channel_sampled = 0; - current_packet = 0; - idles_between_b2b_data_same_channel_counter = 0; - idles_between_b2b_data_different_channel_counter = 0; - past_channel = 0; - past_endofpacket = 0; - transaction_after_reset = 1; - current_beat = 0; - current_beat_2 = 0; - changed_channel = 0; - all_valid_beats_flag = 0; - all_invalid_beats_flag = 0; - partial_valid_beats_flag = 0; - idles_between_b2b_packet_transaction_counter = 0; - idles_between_packet_within_single_transaction_sampled = 0; - packet_per_transaction = 0; - packet_size = 0; - error_in_middle_of_packet = 0; - idles_between_packet_in_different_transaction_sampled = 0; - invalid_beat_between_packet = 0; - packet_per_transaction_flag = 0; - reset_status = 1; - channel_change = 0; - end - end - - // Flag for initial coverage settings - initial begin - #1 covergroup_settings_changed_flag = 1; - end - - //------------------------------------------------------------------------------- - // =head2 Streaming Coverages - // The following are the cover group code focus on ST Monitor component coverage - //------------------------------------------------------------------------------- - - //------------------------------------------------------------------------------- - // =head3 c_empty - // This cover group covers the different empty value - //------------------------------------------------------------------------------- - - covergroup cg_empty; - cp_empty: coverpoint empty[current_beat] - { - bins cg_empty_cp_empty [] = {[0:ST_MAX_EMPTY]}; - } - option.per_instance = 1; - endgroup - - cg_empty c_empty; - - initial begin - #1 if (enable_c_empty && USE_EMPTY) begin - c_empty = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_error - // This cover group covers the different error value - //------------------------------------------------------------------------------- - - covergroup cg_error; - cp_error: coverpoint error_bit_num - { - bins cg_error_cp_error [] = {[0:lindex(ST_ERROR_W)]}; - } - option.per_instance = 1; - endgroup - - cg_error c_error; - - initial begin - #1 if (enable_c_error && USE_ERROR) begin - c_error = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_transfer - // This cover group covers valid is asserted for different channel. - //------------------------------------------------------------------------------- - - covergroup cg_transfer; - cp_transfer: coverpoint (channel[current_beat]) - { - bins cg_transfer_cp_transfer [] = {[0:(USE_CHANNEL == 0? 0:lindex(NUM_CHANNEL))]}; - } - option.per_instance = 1; - endgroup - - cg_transfer c_transfer; - - initial begin - #1 if (enable_c_transfer && USE_VALID && USE_READY) begin - c_transfer = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_packet - // This cover group covers packet transfer for different channel. - //------------------------------------------------------------------------------- - - covergroup cg_packet; - cp_packet: coverpoint (channel[current_beat]) - { - bins cg_packet_cp_packet [] = {[0:(USE_CHANNEL == 0? 0:lindex(NUM_CHANNEL))]}; - } - option.per_instance = 1; - endgroup - - cg_packet c_packet; - - initial begin - #1 if (enable_c_packet && USE_PACKET) begin - c_packet = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_valid_non_ready - // This cover group covers valid is asserted while ready is deasserted. - //------------------------------------------------------------------------------- - - covergroup cg_valid_non_ready; - cp_valid_non_ready: coverpoint ready - { - bins cg_valid_non_ready_cp_valid_non_ready = {0}; - } - option.per_instance = 1; - endgroup - - cg_valid_non_ready c_valid_non_ready; - - initial begin - #1 if (enable_c_valid_non_ready && USE_READY - && USE_VALID && (ST_READY_LATENCY == 0)) begin - c_valid_non_ready = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_non_valid_ready - // This cover group covers valid is deasserted at the N+ST_READ_LATENCY - // clock cycle if ready is asserted at N clock cycle. - //------------------------------------------------------------------------------- - - covergroup cg_non_valid_ready; - cp_non_valid_ready: coverpoint valid[current_beat_2] - { - bins cg_non_valid_ready_cp_non_valid_ready = {0}; - } - option.per_instance = 1; - endgroup - - cg_non_valid_ready c_non_valid_ready; - - initial begin - #1 if (enable_c_non_valid_ready && USE_READY && USE_VALID) begin - c_non_valid_ready = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_non_valid_non_ready - // This cover group covers idle cycle. - //------------------------------------------------------------------------------- - - covergroup cg_non_valid_non_ready; - cp_non_valid_non_ready: coverpoint ready - { - bins cg_non_valid_non_ready_cp_non_valid_non_ready = {0}; - } - option.per_instance = 1; - endgroup - - cg_non_valid_non_ready c_non_valid_non_ready; - - initial begin - #1 if (enable_c_non_valid_non_ready && USE_READY && USE_VALID) begin - c_non_valid_non_ready = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_packet_no_idles_no_back_pressure - // This cover group covers packet transaction without back pressure and idle - // cycles. - //------------------------------------------------------------------------------- - - covergroup cg_packet_no_idles_no_back_pressure; - cp_packet_no_idles_no_back_pressure: coverpoint packet_no_idles_no_back_pressure_flag[channel[current_beat]] - { - bins cg_packet_no_idles_no_back_pressure_cp_packet_no_idles_no_back_pressure = {1}; - } - option.per_instance = 1; - endgroup - - cg_packet_no_idles_no_back_pressure c_packet_no_idles_no_back_pressure; - - initial begin - #1 if (enable_c_packet_no_idles_no_back_pressure && USE_READY && USE_VALID && USE_PACKET) begin - c_packet_no_idles_no_back_pressure = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_packet_with_back_pressure - // This cover group covers packet transaction being back pressured. - //------------------------------------------------------------------------------- - - covergroup cg_packet_with_back_pressure; - cp_packet_with_back_pressure: coverpoint packet_with_back_pressure_flag[channel[current_beat]] - { - bins cg_packet_with_back_pressure_cp_packet_with_back_pressure = {1}; - } - option.per_instance = 1; - endgroup - - cg_packet_with_back_pressure c_packet_with_back_pressure; - - initial begin - #1 if (enable_c_packet_with_back_pressure && USE_READY && USE_PACKET) begin - c_packet_with_back_pressure = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_packet_with_idles - // This cover group covers covers packet transaction with idle cycles - //------------------------------------------------------------------------------- - - covergroup cg_packet_with_idles; - cp_packet_with_idles: coverpoint packet_with_idles_flag[channel[current_beat]] - { - bins cg_packet_with_idles_cp_packet_with_idles = {1}; - } - option.per_instance = 1; - endgroup - - cg_packet_with_idles c_packet_with_idles; - - initial begin - #1 if (enable_c_packet_with_idles && USE_PACKET && USE_VALID) begin - c_packet_with_idles = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_channel_change_in_packet - // This cover group covers changing channel within a packet transaction. - //------------------------------------------------------------------------------- - - covergroup cg_channel_change_in_packet; - cp_channel_change_in_packet: coverpoint channel_change_in_packet_flag[channel[current_beat]] - { - bins cg_channel_change_in_packet_cp_channel_change_in_packet = {1}; - } - option.per_instance = 1; - endgroup - - cg_channel_change_in_packet c_channel_change_in_packet; - - initial begin - #1 if (enable_c_channel_change_in_packet && USE_CHANNEL && USE_PACKET && (ST_MAX_CHANNELS > 0)) begin - c_channel_change_in_packet = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_b2b_packet_different_channel - // This cover group covers back to back packet transfer for different channel. - //------------------------------------------------------------------------------- - - covergroup cg_b2b_packet_different_channel; - cp_b2b_packet_different_channel: coverpoint idles_between_b2b_packet_different_channel_counter - { - bins cg_b2b_packet_different_channel_cp_b2b_packet_different_channel = {0}; - } - option.per_instance = 1; - endgroup - - cg_b2b_packet_different_channel c_b2b_packet_different_channel; - - initial begin - #1 if (enable_c_b2b_packet_different_channel && USE_CHANNEL && USE_PACKET && USE_VALID && (ST_MAX_CHANNELS > 0)) begin - c_b2b_packet_different_channel = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_b2b_packet_same_channel - // This cover group covers back to back packet transfer for same channel. - //------------------------------------------------------------------------------- - - covergroup cg_b2b_packet_same_channel; - cp_b2b_packet_same_channel: coverpoint idles_between_b2b_packet_same_channel_counter - { - bins cg_b2b_packet_same_channel_cp_b2b_packet_same_channel = {0}; - } - option.per_instance = 1; - endgroup - - cg_b2b_packet_same_channel c_b2b_packet_same_channel; - - initial begin - #1 if (enable_c_b2b_packet_same_channel && USE_PACKET && USE_VALID) begin - c_b2b_packet_same_channel = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_b2b_data_different_channel - // This cover group covers back to back data transfer for different channel. - //------------------------------------------------------------------------------- - - covergroup cg_b2b_data_different_channel; - cp_b2b_data_different_channel: coverpoint idles_between_b2b_data_different_channel_counter - { - bins cg_b2b_data_different_channel_cp_b2b_data_different_channel = {0}; - } - option.per_instance = 1; - endgroup - - cg_b2b_data_different_channel c_b2b_data_different_channel; - - initial begin - #1 if (enable_c_b2b_data_different_channel && USE_CHANNEL && USE_VALID && (ST_MAX_CHANNELS > 0)) begin - c_b2b_data_different_channel = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_b2b_data_same_channel - // This cover group covers back to back data transfer for same channel. - //------------------------------------------------------------------------------- - - covergroup cg_b2b_data_same_channel; - cp_b2b_data_same_channel: coverpoint idles_between_b2b_data_same_channel_counter - { - bins cg_b2b_data_same_channel_cp_b2b_data_same_channel = {0}; - } - option.per_instance = 1; - endgroup - - cg_b2b_data_same_channel c_b2b_data_same_channel; - - initial begin - #1 if (enable_c_b2b_data_same_channel && USE_VALID) begin - c_b2b_data_same_channel = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_transaction_after_reset - // This cover group covers first transaction after reset. - //------------------------------------------------------------------------------- - - covergroup cg_transaction_after_reset; - cp_transaction_after_reset: coverpoint transaction_after_reset - { - bins cg_transaction_after_reset_cp_transaction_after_reset = {1}; - } - option.per_instance = 1; - endgroup - - cg_transaction_after_reset c_transaction_after_reset; - - initial begin - #1 if (enable_c_transaction_after_reset && USE_VALID) begin - c_transaction_after_reset = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_packet_size - // This covers different size of packet from one until parameter - // ST_MAX_PACKET_SIZE. For the transaction larger than ST_MAX_PACKET_SIZE will - // count into another bin. - //------------------------------------------------------------------------------- - - covergroup cg_packet_size; - cp_packet_size: coverpoint packet_size[channel[current_beat]] - { - bins cg_packet_size_cp_packet_size [] = {[1:(ST_MAX_PACKET_SIZE < 1)? 1:ST_MAX_PACKET_SIZE]}; - bins cg_packet_size_cp_packet_size_high = {[(ST_MAX_PACKET_SIZE < 1)? 2:ST_MAX_PACKET_SIZE+1:$]}; - } - option.per_instance = 1; - endgroup - - cg_packet_size c_packet_size; - - initial begin - #1 if (enable_c_packet_size && USE_PACKET) begin - c_packet_size = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_multiple_packet_per_cycle - // This cover group covers number of transactions that carry multiple packets - // per single cycle. - //------------------------------------------------------------------------------- - - covergroup cg_multiple_packet_per_cycle; - cp_multiple_packet_per_cycle: coverpoint packet_per_transaction - { - bins cg_multiple_packet_per_cycle_cp_multiple_packet_per_cycle = {[1:(ST_BEATSPERCYCLE > 1)?ST_BEATSPERCYCLE:1]}; - } - option.per_instance = 1; - endgroup - - cg_multiple_packet_per_cycle c_multiple_packet_per_cycle; - - initial begin - #1 if (enable_c_multiple_packet_per_cycle && USE_PACKET && ST_BEATSPERCYCLE > 1) begin - c_multiple_packet_per_cycle = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_single_packet_per_cycle - // This cover group covers number of transactions that carry one packet - // per single cycle. - //------------------------------------------------------------------------------- - - covergroup cg_single_packet_per_cycle; - cp_single_packet_per_cycle: coverpoint packet_per_transaction - { - bins cg_single_packet_per_cycle_cp_single_packet_per_cycle = {0}; - } - option.per_instance = 1; - endgroup - - cg_single_packet_per_cycle c_single_packet_per_cycle; - - initial begin - #1 if (enable_c_single_packet_per_cycle && USE_PACKET && ST_BEATSPERCYCLE > 1) begin - c_single_packet_per_cycle = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_idle_beat_between_packet - // This cover group covers packet transaction that owns idle beats in between. - //------------------------------------------------------------------------------- - - covergroup cg_idle_beat_between_packet; - cp_idle_beat_between_packet: coverpoint invalid_beat_between_packet - { - bins cg_idle_beat_between_packet_cp_idle_beat_between_packet = {1}; - } - option.per_instance = 1; - endgroup - - cg_idle_beat_between_packet c_idle_beat_between_packet; - - initial begin - #1 if (enable_c_idle_beat_between_packet && USE_PACKET && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin - c_idle_beat_between_packet = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_all_valid_beats - // This cover group covers number of transaction with all beats are valid. - //------------------------------------------------------------------------------- - - covergroup cg_all_valid_beats; - cp_all_valid_beats: coverpoint all_valid_beats_flag - { - bins cg_all_valid_beats_cp_all_valid_beats = {1}; - } - option.per_instance = 1; - endgroup - - cg_all_valid_beats c_all_valid_beats; - - initial begin - #1 if (enable_c_all_valid_beats && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin - c_all_valid_beats = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_all_idle_beats - // This cover group covers number of transaction with all beats are idle. - //------------------------------------------------------------------------------- - - covergroup cg_all_idle_beats; - cp_all_idle_beats: coverpoint all_invalid_beats_flag - { - bins cg_all_idle_beats_cp_all_idle_beats = {1}; - } - option.per_instance = 1; - endgroup - - cg_all_idle_beats c_all_idle_beats; - - initial begin - #1 if (enable_c_all_idle_beats && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin - c_all_idle_beats = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_partial_valid_beats - // This cover group covers number of transaction with some beats are invalid and - // some beats are valid. - //------------------------------------------------------------------------------- - - covergroup cg_partial_valid_beats; - cp_partial_valid_beats: coverpoint partial_valid_beats_flag - { - bins cg_partial_valid_beats_cp_partial_valid_beats = {1}; - } - option.per_instance = 1; - endgroup - - cg_partial_valid_beats c_partial_valid_beats; - - initial begin - #1 if (enable_c_partial_valid_beats && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin - c_partial_valid_beats = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_b2b_packet_within_single_cycle - // This cover group covers back to back packet transfer within single cycle. - //------------------------------------------------------------------------------- - - covergroup cg_b2b_packet_within_single_cycle; - cp_b2b_packet_within_single_cycle: coverpoint idles_between_b2b_packet_transaction_counter - { - bins cg_b2b_packet_within_single_cycle_cp_b2b_packet_within_single_cycle = {0}; - } - option.per_instance = 1; - endgroup - - cg_b2b_packet_within_single_cycle c_b2b_packet_within_single_cycle; - - initial begin - #1 if (enable_c_b2b_packet_within_single_cycle && USE_PACKET && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin - c_b2b_packet_within_single_cycle = new(); - end - end - - - //------------------------------------------------------------------------------- - // =head3 c_b2b_packet_in_different_cycle - // This cover group covers back to back packet transfer in different cycle. - //------------------------------------------------------------------------------- - - covergroup cg_b2b_packet_in_different_cycle; - cp_b2b_packet_in_different_cycle: coverpoint idles_between_b2b_packet_transaction_counter - { - bins cg_b2b_packet_in_different_cycle_cp_b2b_packet_in_different_cycle = {0}; - } - option.per_instance = 1; - endgroup - - cg_b2b_packet_in_different_cycle c_b2b_packet_in_different_cycle; - - initial begin - #1 if (enable_c_b2b_packet_in_different_cycle && USE_PACKET && USE_VALID && (ST_BEATSPERCYCLE > 1)) begin - c_b2b_packet_in_different_cycle = new(); - end - end - - //------------------------------------------------------------------------------- - // =head3 c_error_in_middle_of_packet - // This cover group covers assert error in the middle of a packet. - //------------------------------------------------------------------------------- - - covergroup cg_error_in_middle_of_packet; - cp_error_in_middle_of_packet: coverpoint error_in_middle_of_packet - { - bins cg_error_in_middle_of_packet_cp_error_in_middle_of_packet = {1}; - } - option.per_instance = 1; - endgroup - - cg_error_in_middle_of_packet c_error_in_middle_of_packet; - - initial begin - #1 if (enable_c_error_in_middle_of_packet && USE_PACKET && USE_ERROR) begin - c_error_in_middle_of_packet = new(); - end - end - - // =cut - - //-------------------------------------------------------------------------- - // COVERAGE CODE END - //-------------------------------------------------------------------------- - `endif - // synthesis translate_on - -endmodule - - Index: trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor.sv =================================================================== --- trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor.sv (revision 49) +++ trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/altera_avalon_st_monitor.sv (nonexistent) @@ -1,292 +0,0 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/17.1std/ip/sopc/components/verification/altera_avalon_st_monitor_bfm/altera_avalon_st_monitor.sv#1 $ -// $Revision: #1 $ -// $Date: 2017/07/30 $ -//----------------------------------------------------------------------------- -// =head1 NAME -// altera_avalon_st_monitor -// =head1 SYNOPSIS -// Bridge with Avalon Bus Protocol Assertion Checker -//----------------------------------------------------------------------------- -// =head1 DESCRIPTION -// This module implements Avalon ST protocol assertion checking for simulation. -// The component acts as a simple repeater with Avalon bus signals -// passed through from the sink to source interface. -// The instantiated altera_avalon_st_monitor snoops all passing Avalon -// bus signals and performs assertion checking and measures coverage on -// Avalon Streaming protocol properties. -// Transactions in transit may also be captured in a transaction buffer and -// extracted from the monitor via the API. -// The macro ALTERA_AVALON_SIM_SVA is defined to disable SVA processing -// The macro ENABLE_ALTERA_AVALON_TRANSACTION_RECORDING must be defined to -// enable transaction monitoring -//----------------------------------------------------------------------------- - -`timescale 1ps / 1ps - -module altera_avalon_st_monitor( - clk, - reset, - - sink_data, - sink_channel, - sink_valid, - sink_startofpacket, - sink_endofpacket, - sink_error, - sink_empty, - sink_ready, - - src_data, - src_channel, - src_valid, - src_startofpacket, - src_endofpacket, - src_error, - src_empty, - src_ready - ); - - // =head1 PARAMETERS - parameter ST_SYMBOL_W = 8; // number of bits in one symbols - parameter ST_NUMSYMBOLS = 4; // number of symbols in one data - parameter ST_CHANNEL_W = 0; // width of channel signal - parameter ST_ERROR_W = 0; // width of error signal - parameter ST_EMPTY_W = 0; // width of empty signal, ST_EMPTY_W = log2(`ST_NUMSYMBOLS) - - parameter ST_READY_LATENCY = 0; // fixed ready latency in cycles - parameter ST_MAX_CHANNELS = 1; // maximum number of channels - - parameter USE_PACKET = 0; // data transfer in packet format - parameter USE_CHANNEL = 0; // use channel port - parameter USE_ERROR = 0; // use error port - parameter USE_READY = 1; // use ready port - parameter USE_VALID = 1; // use valid port - parameter USE_EMPTY = 0; // use empty port - parameter ST_BEATSPERCYCLE = 1; // Max number of packets per cycle - - parameter ST_MAX_PACKET_SIZE = 1; // Max number of packet size covered - parameter VHDL_ID = 0; // VHDL BFM ID number - - localparam ST_DATA_W = ST_SYMBOL_W * ST_NUMSYMBOLS; - localparam ST_MDATA_W = ST_BEATSPERCYCLE * ST_DATA_W; - localparam ST_MCHANNEL_W = ST_BEATSPERCYCLE * ST_CHANNEL_W; - localparam ST_MERROR_W = ST_BEATSPERCYCLE * ST_ERROR_W; - localparam ST_MEMPTY_W = ST_BEATSPERCYCLE * ST_EMPTY_W; - - localparam TAP_W = ((ST_DATA_W == 0)? 1:ST_DATA_W) + // data - ((ST_CHANNEL_W == 0)? 1:ST_CHANNEL_W) + // channel - 1 + // valid - 1 + // startofpacket - 1 + // endofpacket - ((ST_ERROR_W == 0)? 1:ST_ERROR_W) + // error - ((ST_EMPTY_W == 0)? 1:ST_EMPTY_W) + // empty - 1; // ready - - localparam MTAP_W = ST_BEATSPERCYCLE*TAP_W; - - // =head1 PINS - // =head2 Clock Interface - input clk; - input reset; - - // =head2 Avalon Streaming Sink Interface - input [lindex(ST_MDATA_W) : 0] sink_data; - input [lindex(ST_MCHANNEL_W) : 0] sink_channel; - input [lindex(ST_BEATSPERCYCLE) : 0] sink_valid; - input [lindex(ST_BEATSPERCYCLE) : 0] sink_startofpacket; - input [lindex(ST_BEATSPERCYCLE) : 0] sink_endofpacket; - input [lindex(ST_MERROR_W) : 0] sink_error; - input [lindex(ST_MEMPTY_W) : 0] sink_empty; - output sink_ready; - - // =head2 Avalon Streaming Source Interface - output [lindex(ST_MDATA_W) : 0] src_data; - output [lindex(ST_MCHANNEL_W) : 0] src_channel; - output [lindex(ST_BEATSPERCYCLE) : 0] src_valid; - output [lindex(ST_BEATSPERCYCLE) : 0] src_startofpacket; - output [lindex(ST_BEATSPERCYCLE) : 0] src_endofpacket; - output [lindex(ST_MERROR_W) : 0] src_error; - output [lindex(ST_MEMPTY_W) : 0] src_empty; - input src_ready; - - // =cut - - function int lindex; - // returns the left index for a vector having a declared width - // when width is 0, then the left index is set to 0 rather than -1 - input [31:0] width; - lindex = (width > 0) ? (width-1) : 0; - endfunction - - // outputs - logic sink_ready; - logic [lindex(ST_MDATA_W) : 0] src_data; - logic [lindex(ST_MCHANNEL_W) : 0] src_channel; - logic [lindex(ST_BEATSPERCYCLE) : 0] src_valid; - logic [lindex(ST_BEATSPERCYCLE) : 0] src_startofpacket; - logic [lindex(ST_BEATSPERCYCLE) : 0] src_endofpacket; - logic [lindex(ST_MERROR_W) : 0] src_error; - logic [lindex(ST_MEMPTY_W) : 0] src_empty; - - logic [(MTAP_W)-ST_BEATSPERCYCLE : 0] tap; - - always @(*) begin - sink_ready <= src_ready; - src_data <= sink_data; - src_channel <= sink_channel; - src_valid <= sink_valid; - src_startofpacket <= sink_startofpacket; - src_endofpacket <= sink_endofpacket; - src_error <= sink_error; - src_empty <= sink_empty; - - tap <= { - sink_data, - sink_channel, - sink_valid, - sink_startofpacket, - sink_endofpacket, - sink_error, - sink_empty, - src_ready - }; - end - - //-------------------------------------------------------------------------- - // =head1 ALTERA_AVALON_ST_MONITOR_ASSERTION - // This module implements Avalon-ST protocol simulation assertion checkers - // =cut - //-------------------------------------------------------------------------- - altera_avalon_st_monitor_assertion - #( - .ST_SYMBOL_W (ST_SYMBOL_W), - .ST_NUMSYMBOLS (ST_NUMSYMBOLS), - .ST_CHANNEL_W (ST_CHANNEL_W), - .ST_ERROR_W (ST_ERROR_W), - .ST_EMPTY_W (ST_EMPTY_W), - - .ST_READY_LATENCY(ST_READY_LATENCY), - .ST_MAX_CHANNELS (ST_MAX_CHANNELS), - .ST_BEATSPERCYCLE(ST_BEATSPERCYCLE), - - .USE_PACKET (USE_PACKET), - .USE_CHANNEL (USE_CHANNEL), - .USE_ERROR (USE_ERROR), - .USE_READY (USE_READY), - .USE_VALID (USE_VALID), - .USE_EMPTY (USE_EMPTY) - ) - monitor_assertion ( - .clk (clk), - .reset (reset), - .tap (tap) - ); - - //-------------------------------------------------------------------------- - // =head1 ALTERA_AVALON_ST_MONITOR_COVERAGE - // This module implements Avalon-ST protocol functional coverage measurements - // =cut - //-------------------------------------------------------------------------- - altera_avalon_st_monitor_coverage - #( - .ST_SYMBOL_W (ST_SYMBOL_W), - .ST_NUMSYMBOLS (ST_NUMSYMBOLS), - .ST_CHANNEL_W (ST_CHANNEL_W), - .ST_ERROR_W (ST_ERROR_W), - .ST_EMPTY_W (ST_EMPTY_W), - .ST_BEATSPERCYCLE (ST_BEATSPERCYCLE), - - .ST_READY_LATENCY (ST_READY_LATENCY), - .ST_MAX_CHANNELS (ST_MAX_CHANNELS), - - .USE_PACKET (USE_PACKET), - .USE_CHANNEL (USE_CHANNEL), - .USE_ERROR (USE_ERROR), - .USE_READY (USE_READY), - .USE_VALID (USE_VALID), - .USE_EMPTY (USE_EMPTY), - .ST_MAX_PACKET_SIZE (ST_MAX_PACKET_SIZE) - ) - monitor_coverage ( - .clk (clk), - .reset (reset), - .tap (tap) - ); - - //-------------------------------------------------------------------------- - // =head1 ALTERA_AVALON_ST_MONITOR_TRANSACTIONS - // This module implements Avalon-ST the transaction recorder. - // =cut - //-------------------------------------------------------------------------- - - `ifdef ENABLE_ALTERA_AVALON_TRANSACTION_RECORDING - altera_avalon_st_monitor_transactions - #( - .ST_SYMBOL_W (ST_SYMBOL_W), - .ST_NUMSYMBOLS (ST_NUMSYMBOLS), - .ST_CHANNEL_W (ST_CHANNEL_W), - .ST_ERROR_W (ST_ERROR_W), - .ST_EMPTY_W (ST_EMPTY_W), - .ST_BEATSPERCYCLE (ST_BEATSPERCYCLE), - - .ST_READY_LATENCY (ST_READY_LATENCY), - .ST_MAX_CHANNELS (ST_MAX_CHANNELS), - - .USE_PACKET (USE_PACKET), - .USE_CHANNEL (USE_CHANNEL), - .USE_ERROR (USE_ERROR), - .USE_READY (USE_READY), - .USE_VALID (USE_VALID), - .USE_EMPTY (USE_EMPTY), - .ST_MAX_PACKET_SIZE (ST_MAX_PACKET_SIZE) - ) - monitor_trans ( - .clk (clk), - .reset (reset), - .tap (tap) - ); - `endif - - // synthesis translate_off - import verbosity_pkg::*; - - localparam VERSION = "17.1"; - - function automatic void hello(); - // introduction message to the console - string message; - $sformat(message, "%m: - Hello from altera_avalon_st_monitor"); - print(VERBOSITY_INFO, message); - `ifdef DISABLE_ALTERA_AVALON_SIM_SVA - $sformat(message, "%m: - Assertions disabled (DISABLE_ALTERA_AVALON_SIM_SVA defined)"); - `else - $sformat(message, "%m: - Assertions enabled (DISABLE_ALTERA_AVALON_SIM_SVA undefined)"); - `endif - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - $Revision: #1 $"); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - $Date: 2017/07/30 $"); - print(VERBOSITY_INFO, message); - print_divider(VERBOSITY_INFO); - endfunction - - initial begin - hello(); - end - - // synthesis translate_on - -endmodule Index: trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/verbosity_pkg.sv =================================================================== --- trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/verbosity_pkg.sv (revision 49) +++ trunk/avalon_lib/syn/ast_monitor/altera_avalon_st_monitor_171/sim/verbosity_pkg.sv (nonexistent) @@ -1,193 +0,0 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/17.1std/ip/sopc/components/verification/lib/verbosity_pkg.sv#1 $ -// $Revision: #1 $ -// $Date: 2017/07/30 $ -//----------------------------------------------------------------------------- -// =head1 NAME -// verbosity_pkg -// =head1 SYNOPSIS -// Package for controlling verbosity of messages sent to the console -//----------------------------------------------------------------------------- -// =head1 COPYRIGHT -// Copyright (c) 2008 Altera Corporation. All Rights Reserved. -// The information contained in this file is the property of Altera -// Corporation. Except as specifically authorized in writing by Altera -// Corporation, the holder of this file shall keep all information -// contained herein confidential and shall protect same in whole or in part -// from disclosure and dissemination to all third parties. Use of this -// program confirms your agreement with the terms of this license. -//----------------------------------------------------------------------------- -// =head1 DESCRIPTION -// This module will dump diagnostic messages to the console during -// simulation. The level of verbosity can be controlled in the test -// bench by using the *set_verbosity* method in the imported package -// verbosity_pkg. For a given setting, message at that level and all -// lower levels are dumped. For example, setting VERBOSITY_DEBUG level -// causes all messages to be dumped, while VERBOSITY_FAILURE restricts -// only failure messages and those tagged as VERBOSITY_NONE to be -// dumped. -// The different levels are: -// =over 4 -// =item 1 VERBOSITY_NONE -// Messages tagged with this level are always dumped to the console. -// =item 2 VERBOSITY_FAILURE -// A fatal simulation error has occurred and the simulator will exit. -// =item 3 VERBOSITY_ERROR -// A non-fatal error has occured. An example is a data comparison mismatch. -// =item 4 VERBOSITY_WARNING -// Warn the user that a potential error has occurred. -// =item 5 VERBOSITY_INFO -// Informational message. -// =item 6 VERBOSITY_DEBUG -// Dump enough state to diagnose problem scenarios. -// =back - - -`ifndef _AVALON_VERBOSITY_PKG_ -`define _AVALON_VERBOSITY_PKG_ - -package verbosity_pkg; - - timeunit 1ps; - timeprecision 1ps; - - typedef enum int {VERBOSITY_NONE, - VERBOSITY_FAILURE, - VERBOSITY_ERROR, - VERBOSITY_WARNING, - VERBOSITY_INFO, - VERBOSITY_DEBUG} Verbosity_t; - - Verbosity_t verbosity = VERBOSITY_INFO; - string message = ""; - int dump_file; - int dump = 0; - - //-------------------------------------------------------------------------- - // =head1 Public Methods API - // =pod - // This section describes the public methods in the application programming - // interface (API). In this case the application program is the test bench - // or component which imports this package. - // =cut - //-------------------------------------------------------------------------- - - function automatic Verbosity_t get_verbosity(); // public - // Returns the global verbosity setting. - return verbosity; - endfunction - - function automatic void set_verbosity ( // public - Verbosity_t v - ); - // Sets the global verbosity setting. - - string verbosity_str; - verbosity = v; - - case(verbosity) - VERBOSITY_NONE: verbosity_str = "VERBOSITY_"; - VERBOSITY_FAILURE: verbosity_str = "VERBOSITY_FAILURE"; - VERBOSITY_ERROR: verbosity_str = "VERBOSITY_ERROR"; - VERBOSITY_WARNING: verbosity_str = "VERBOSITY_WARNING"; - VERBOSITY_INFO: verbosity_str = "VERBOSITY_INFO"; - VERBOSITY_DEBUG: verbosity_str = "VERBOSITY_DEBUG"; - default: verbosity_str = "UNKNOWN"; - endcase - $sformat(message, "%m: Setting Verbosity level=%0d (%s)", - verbosity, verbosity_str); - print(VERBOSITY_NONE, message); - endfunction - - function automatic void print( // public - Verbosity_t level, - string message - ); - // Print a message to the console if the verbosity argument - // is less than or equal to the global verbosity setting. - string level_str; - - if (level <= verbosity) begin - case(level) - VERBOSITY_NONE: level_str = ""; - VERBOSITY_FAILURE: level_str = "FAILURE:"; - VERBOSITY_ERROR: level_str = "ERROR:"; - VERBOSITY_WARNING: level_str = "WARNING:"; - VERBOSITY_INFO: level_str = "INFO:"; - VERBOSITY_DEBUG: level_str = "DEBUG:"; - default: level_str = "UNKNOWN:"; - endcase - - $display("%t: %s %s",$time, level_str, message); - if (dump) begin - $fdisplay(dump_file, "%t: %s %s",$time, level_str, message); - end - end - endfunction - - function automatic void print_divider( // public - Verbosity_t level - ); - // Prints a divider line to the console to make a block of related text - // easier to identify and read. - string message; - $sformat(message, - "------------------------------------------------------------"); - print(level, message); - endfunction - - function automatic void open_dump_file ( // public - string dump_file_name = "avalon_bfm_sim.log" - ); - // Opens a dump file which collects console messages. - - if (dump) begin - $sformat(message, "%m: Dump file already open - ignoring open."); - print(VERBOSITY_ERROR, message); - end else begin - dump_file = $fopen(dump_file_name, "w"); - $fdisplay(dump_file, "testing dump file"); - $sformat(message, "%m: Opening dump file: %s", dump_file_name); - print(VERBOSITY_INFO, message); - dump = 1; - end - endfunction - - function automatic void close_dump_file(); // public - // Close the console message dump file. - if (!dump) begin - $sformat(message, "%m: No open dump file - ignoring close."); - print(VERBOSITY_ERROR, message); - end else begin - dump = 0; - $fclose(dump_file); - $sformat(message, "%m: Closing dump file"); - print(VERBOSITY_INFO, message); - end - endfunction - - function automatic void abort_simulation(); - string message; - $sformat(message, "%m: Abort the simulation due to fatal error incident."); - print(VERBOSITY_FAILURE, message); - $stop; - endfunction - -endpackage - -// =cut - -`endif - Index: trunk/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/altera_avalon_st_sink_bfm.sv =================================================================== --- trunk/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/altera_avalon_st_sink_bfm.sv (revision 49) +++ trunk/avalon_lib/syn/ast_sink/altera_avalon_st_sink_bfm_171/sim/altera_avalon_st_sink_bfm.sv (nonexistent) @@ -1,463 +0,0 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $File: //acds/rel/17.1std/ip/sopc/components/verification/altera_avalon_st_sink_bfm/altera_avalon_st_sink_bfm.sv $ -// $Revision: #1 $ -// $Date: 2017/07/30 $ -// $Author: swbranch $ -//----------------------------------------------------------------------------- -// =head1 NAME -// altera_avalon_st_sink_bfm -// =head1 SYNOPSIS -// Bus Functional Model (BFM) for a Avalon Streaming Sink -//----------------------------------------------------------------------------- -// =head1 DESCRIPTION -// This is a Bus Functional Model (BFM) for a Avalon Streaming Sink. -// The behavior of each clock cycle of the ST protocol on the interface -// is governed by a transaction. Received bus cycles are captured as -// transactions and pushed into a response queue. Clients query received -// transactions by popping them off the queue one by one and extract -// information using the public API methods provided. Back pressure to -// a driving source is also applied using the API method set_ready. -//----------------------------------------------------------------------------- - -`timescale 1ps / 1ps - -module altera_avalon_st_sink_bfm( - clk, - reset, - - sink_data, - sink_channel, - sink_valid, - sink_startofpacket, - sink_endofpacket, - sink_error, - sink_empty, - sink_ready - ); - - // =head1 PARAMETERS - parameter ST_SYMBOL_W = 8; // Data symbol width in bits - parameter ST_NUMSYMBOLS = 4; // Number of symbols per word - parameter ST_CHANNEL_W = 0; // Channel width in bits - parameter ST_ERROR_W = 0; // Error width in bits - parameter ST_EMPTY_W = 0; // Empty width in bits - - parameter ST_READY_LATENCY = 0; // Number of cycles latency after ready (0 or 1 only) - parameter ST_MAX_CHANNELS = 1; // Maximum number of channels - - parameter USE_PACKET = 0; // Use packet pins on interface - parameter USE_CHANNEL = 0; // Use channel pins on interface - parameter USE_ERROR = 0; // Use error pin on interface - parameter USE_READY = 1; // Use ready pin on interface - parameter USE_VALID = 1; // Use valid pin on interface - parameter USE_EMPTY = 0; // Use empty pin on interface - - parameter ST_BEATSPERCYCLE = 1; // Max number of packets per cycle - parameter VHDL_ID = 0; // VHDL BFM ID number - - localparam ST_DATA_W = ST_SYMBOL_W * ST_NUMSYMBOLS; - localparam ST_MDATA_W = ST_BEATSPERCYCLE * ST_DATA_W; - localparam ST_MCHANNEL_W = ST_BEATSPERCYCLE * ST_CHANNEL_W; - localparam ST_MERROR_W = ST_BEATSPERCYCLE * ST_ERROR_W; - localparam ST_MEMPTY_W = ST_BEATSPERCYCLE * ST_EMPTY_W; - - // =head1 PINS - // =head2 Clock Interface - input clk; - input reset; - - // =head2 Avalon Streaming Source Interface - input [lindex(ST_MDATA_W): 0] sink_data; - input [lindex(ST_MCHANNEL_W): 0] sink_channel; - input [ST_BEATSPERCYCLE-1: 0] sink_valid; - input [ST_BEATSPERCYCLE-1: 0] sink_startofpacket; - input [ST_BEATSPERCYCLE-1: 0] sink_endofpacket; - input [lindex(ST_MERROR_W): 0] sink_error; - input [lindex(ST_MEMPTY_W): 0] sink_empty; - output sink_ready; - - // =cut - - function integer lindex; - // returns the left index for a vector having a declared width - // when width is 0, then the left index is set to 0 rather than -1 - input [31:0] width; - lindex = (width > 0) ? (width-1) : 0; - endfunction - -// synthesis translate_off - import verbosity_pkg::*; - - logic sink_ready; - - //-------------------------------------------------------------------------- - // Private Types and Variables - //-------------------------------------------------------------------------- - - typedef logic [lindex(ST_DATA_W) :0] STData_t; - typedef logic [lindex(ST_CHANNEL_W) :0] STChannel_t; - typedef logic [lindex(ST_EMPTY_W) :0] STEmpty_t; - typedef logic [lindex(ST_ERROR_W) :0] STError_t; - - typedef logic [lindex(ST_MDATA_W) :0] STMData_t; - typedef logic [lindex(ST_MCHANNEL_W) :0] STMChannel_t; - typedef logic [lindex(ST_MEMPTY_W) :0] STMEmpty_t; - typedef logic [lindex(ST_MERROR_W) :0] STMError_t; - typedef logic [ST_BEATSPERCYCLE-1 :0] STBeats_t; - - typedef struct packed - { - bit [31:0] idles; - logic startofpacket; - logic endofpacket; - STChannel_t channel; - STData_t data; - STError_t error; - STEmpty_t empty; - } Transaction_t; - - Transaction_t current_transaction[ST_BEATSPERCYCLE]; - Transaction_t query_transaction; - - Transaction_t transaction_queue[$]; - - string message = "*uninitialized*"; - logic ready = 0; - int idle_ctr = 0; - - STBeats_t sink_valid_qualified; - logic sink_ready_qualified; - - localparam MAX_READY_DELAY = 8; - logic [MAX_READY_DELAY-1:0] sink_ready_delayed; - - - //-------------------------------------------------------------------------- - // =head1 Public Methods API - // =pod - // This section describes the public methods in the application programming - // interface (API). In this case the application program is the test bench - // which instantiates and controls and queries state in this BFM component. - // Test programs must only use these public access methods and events to - // communicate with this BFM component. The API and the module pins - // are the only interfaces in this component that are guaranteed to be - // stable. The API will be maintained for the life of the product. - // While we cannot prevent a test program from directly accessing internal - // tasks, functions, or data private to the BFM, there is no guarantee that - // these will be present in the future. In fact, it is best for the user - // to assume that the underlying implementation of this component can - // and will change. - // =cut - //-------------------------------------------------------------------------- - - event signal_fatal_error; // public - // Signal that a fatal error has occurred. Terminates simulation. - - event signal_transaction_received; //public - // Signal that a transaction has been received and queued. - - event signal_sink_ready_assert; // public - // Signal that sink_ready is asserted thereby turning off back pressure. - - event signal_sink_ready_deassert; // public - // Signal that sink_ready is deasserted thereby turning on back pressure. - - function automatic string get_version(); // public - // Return BFM version string. For example, version 9.1 sp1 is "9.1sp1" - string ret_version = "__ACDS_VERSION_SHORT__"; - return ret_version; - endfunction - - task automatic init(); // public - // Drive interface to idle state. - $sformat(message, "%m: called init"); - print(VERBOSITY_DEBUG, message); - - drive_interface_idle(); - endtask - - task automatic set_ready( // public - bit state - ); - // Set the value of the interface ready signal. To assert back - // pressure, the state argument is set to 0 i.e. not ready. - // The parameter USE_READY must be set to 1 to enable this signal. - - if (USE_READY > 0) begin - $sformat(message, "%m: called set_ready"); - print(VERBOSITY_DEBUG, message); - - sink_ready <= state; - - if (state == 1'b1) - ->signal_sink_ready_assert; - else - ->signal_sink_ready_deassert; - end else begin - $sformat(message, "%m: Ignore set_ready() when USE_READY == 0"); - print(VERBOSITY_WARNING, message); - sink_ready <= 0; - end - endtask - - function automatic void pop_transaction(); // public - // Pop the transaction descriptor from the queue so that it can be - // queried with the get_transaction methods by the test bench. - if (reset) begin - $sformat(message, "%m: Illegal command while reset asserted"); - print(VERBOSITY_ERROR, message); - ->signal_fatal_error; - end - - query_transaction = transaction_queue.pop_back(); - - $sformat(message, "%m: called pop_transaction"); - print(VERBOSITY_DEBUG, message); - $sformat(message, "%m: Data: %x", query_transaction.data); - print(VERBOSITY_DEBUG, message); - $sformat(message, "%m: Channel: %0d", query_transaction.channel); - print(VERBOSITY_DEBUG, message); - $sformat(message, "%m: SOP: %0d EOP: %0d", - query_transaction.startofpacket, - query_transaction.endofpacket); - print(VERBOSITY_DEBUG, message); - endfunction - - function automatic bit[31:0] get_transaction_idles(); // public - // Return the number of idle cycles in the transaction - $sformat(message, "%m: called get_transaction_idles"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.idles; - endfunction - - function automatic logic [ST_DATA_W-1:0] get_transaction_data(); // public - // Return the data in the transaction - $sformat(message, "%m: called get_transaction_data"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.data; - endfunction - - function automatic logic [ST_CHANNEL_W-1:0] get_transaction_channel(); // public - // Return the channel identifier in the transaction - $sformat(message, "%m: called get_transaction_channel"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.channel; - endfunction - - function automatic logic get_transaction_sop(); // public - // Return the start of packet status in the transaction - $sformat(message, "%m: called get_transaction_sop"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.startofpacket; - endfunction - - function automatic logic get_transaction_eop(); // public - // Return the end of packet status in the transaction - $sformat(message, "%m: called get_transaction_eop"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.endofpacket; - endfunction - - function automatic logic [ST_ERROR_W-1:0] get_transaction_error(); // public - // Return the error status in the transaction - $sformat(message, "%m: called get_transaction_error"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.error; - endfunction - - function automatic logic [ST_EMPTY_W-1:0] get_transaction_empty(); // public - // Return the number of empty symbols in the transaction - $sformat(message, "%m: called get_transaction_empty"); - print(VERBOSITY_DEBUG, message); - - return query_transaction.empty; - endfunction - - function automatic int get_transaction_queue_size(); // public - // Return the length of the queue holding received transactions - $sformat(message, "%m: called get_transaction_queue_size"); - print(VERBOSITY_DEBUG, message); - - // Return the number of transactions in the internal queues. - return transaction_queue.size(); - endfunction - - // =cut - - //-------------------------------------------------------------------------- - // Private Methods - //-------------------------------------------------------------------------- - function int __floor( - int arg - ); - // returns the arg if it is greater than 0, else returns 0 - return (arg > 0) ? arg : 0; - endfunction - - task automatic drive_interface_idle(); - set_ready(0); - endtask - - function automatic void __hello(); - // Introduction Message to console - $sformat(message, "%m: - Hello from altera_avalon_st_sink_bfm."); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - $Revision: #1 $"); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - $Date: 2017/07/30 $"); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_SYMBOL_W = %0d", - ST_SYMBOL_W); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_NUMSYMBOLS = %0d", - ST_NUMSYMBOLS); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_CHANNEL_W = %0d", - ST_CHANNEL_W); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_ERROR_W = %0d", - ST_ERROR_W); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_EMPTY_W = %0d", - ST_EMPTY_W); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_READY_LATENCY = %0d", - ST_READY_LATENCY); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_MAX_CHANNELS = %0d", - ST_MAX_CHANNELS); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - ST_BEATSPERCYCLE = %0d", - ST_BEATSPERCYCLE); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - USE_PACKET = %0d", - USE_PACKET); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - USE_CHANNEL = %0d", - USE_CHANNEL); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - USE_ERROR = %0d", - USE_ERROR); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - USE_READY = %0d", - USE_READY); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - USE_VALID = %0d", - USE_VALID); - print(VERBOSITY_INFO, message); - $sformat(message, "%m: - USE_EMPTY = %0d", - USE_EMPTY); - print(VERBOSITY_INFO, message); - print_divider(VERBOSITY_INFO); - endfunction - - //-------------------------------------------------------------------------- - initial begin - __hello(); - end - - //-------------------------------------------------------------------------- - // Local Machinery - //-------------------------------------------------------------------------- - always @(signal_fatal_error) abort_simulation(); - - // delay chain for sink_ready back pressure output to account for latency - always @(posedge clk or posedge reset) begin - if (reset) begin - sink_ready_delayed <= 0; - end else begin - sink_ready_delayed <= {sink_ready_delayed[6:0], sink_ready}; - end - end - - assign sink_ready_qualified = (USE_READY == 0)? 1'b1 : - (ST_READY_LATENCY == 0)? sink_ready : - sink_ready_delayed[__floor(ST_READY_LATENCY-1)]; - - assign sink_valid_qualified = (USE_VALID == 0)? 1'b1 : sink_valid; - - always @(posedge clk or posedge reset) begin - if (reset) begin - transaction_queue = {}; - query_transaction = 0; - for (int i=0; i 0; clog2 = clog2 + 1) - i = i >> 1; - - return clog2; - endfunction - - function automatic int max( - bit [31:0] one, - bit [31:0] two - ); - if(one > two) - return one; - else - return two; - endfunction - - function automatic int lindex( - bit [31:0] width - ); - // returns the left index for a vector having a declared width - // when width is 0, then the left index is set to 0 rather than -1 - lindex = (width > 0) ? (width-1) : 0; - endfunction - - typedef enum int { - LOW = 0, - HIGH = 1, - RANDOM = 2, - UNKNOWN = 3 - } IdleOutputValue_t; - -endpackage - -`endif - Index: trunk/avalon_lib/syn/ast_monitor.qsys =================================================================== --- trunk/avalon_lib/syn/ast_monitor.qsys (revision 49) +++ trunk/avalon_lib/syn/ast_monitor.qsys (nonexistent) @@ -1,105 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: trunk/avalon_lib/syn/ast_sink.qsys =================================================================== --- trunk/avalon_lib/syn/ast_sink.qsys (revision 49) +++ trunk/avalon_lib/syn/ast_sink.qsys (nonexistent) @@ -1,91 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: trunk/axi4_lib/sim/src/axi4_bfm_pkg.sv =================================================================== --- trunk/axi4_lib/sim/src/axi4_bfm_pkg.sv (revision 49) +++ trunk/axi4_lib/sim/src/axi4_bfm_pkg.sv (nonexistent) @@ -1,563 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -// -------------------------------------------------------------------- -// -package axi4_bfm_pkg; - - // -------------------------------------------------------------------- - // - import tb_bfm_pkg::*; - import axi4_transaction_pkg::*; - - - // -------------------------------------------------------------------- - // - class ar_master_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m; - - - //-------------------------------------------------------------------- - function new - ( - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m - ); - - super.new(); - this.axi4_m = axi4_m; - - endfunction: new - - - // -------------------------------------------------------------------- - // - function void - ar_default; - - axi4_m.cb_m.araddr <= 'bx; - axi4_m.cb_m.arburst <= 'bx; - axi4_m.cb_m.arcache <= 'bx; - axi4_m.cb_m.arid <= 'bx; - axi4_m.cb_m.arlen <= 'bx; - axi4_m.cb_m.arlock <= 'bx; - axi4_m.cb_m.arprot <= 'bx; - axi4_m.cb_m.arqos <= 'bx; - axi4_m.cb_m.arregion <= 'bx; - axi4_m.cb_m.arsize <= 'bx; - axi4_m.cb_m.arvalid <= 0; - - endfunction: ar_default - - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - repeat(tr_h.delay_h.next()) @(axi4_m.cb_m); - - axi4_m.cb_m.araddr <= tr_h.addr; - axi4_m.cb_m.arid <= tr_h.id; - axi4_m.cb_m.arlen <= tr_h.len; - axi4_m.cb_m.arsize <= tr_h.size; - - axi4_m.cb_m.arburst <= tr_h.burst; - axi4_m.cb_m.arcache <= tr_h.cache; - axi4_m.cb_m.arlock <= tr_h.lock; - axi4_m.cb_m.arprot <= tr_h.prot; - axi4_m.cb_m.arqos <= tr_h.qos; - axi4_m.cb_m.arregion <= tr_h.region; - axi4_m.cb_m.arvalid <= 1; - - $display("^^^ %16.t | %m | master AR transaction @ 0x%08x |", $time, tr_h.addr); - - repeat(1) @(axi4_m.cb_m); - wait(axi4_m.cb_m.arready); - - axi4_m.zero_cycle_delay(); - ar_default(); - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: ar_master_transaction_class - - - // -------------------------------------------------------------------- - // - class r_master_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m; - - - //-------------------------------------------------------------------- - function new - ( - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m - ); - - super.new(); - this.axi4_m = axi4_m; - - endfunction: new - - - // -------------------------------------------------------------------- - // - function void - r_default; - - axi4_m.cb_m.rready <= 0; - - endfunction: r_default - - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - tr_h.data_h = new(tr_h.len); - - foreach(tr_h.payload_h.w[i]) - begin - repeat(tr_h.delay_h.next()) @(axi4_m.cb_m); - axi4_m.cb_m.rready <= 1; - repeat(1) @(axi4_m.cb_m); - - wait(axi4_m.cb_m.rvalid); - axi4_m.zero_cycle_delay(); - - tr_h.data_h.w[i] = axi4_m.cb_m.rdata; - - $display("^^^ %16.t | %m | master R transaction | %d | 0x%016x |", $time, i, tr_h.data_h.w[i]); - r_default(); - end - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: r_master_transaction_class - - - // -------------------------------------------------------------------- - // - class aw_master_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m; - - - //-------------------------------------------------------------------- - function new - ( - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m - ); - - super.new(); - this.axi4_m = axi4_m; - - endfunction: new - - - // -------------------------------------------------------------------- - // - function void - aw_default; - - axi4_m.cb_m.awaddr <= 'bx; - axi4_m.cb_m.awburst <= 'bx; - axi4_m.cb_m.awcache <= 'bx; - axi4_m.cb_m.awid <= 'bx; - axi4_m.cb_m.awlen <= 'bx; - axi4_m.cb_m.awlock <= 'bx; - axi4_m.cb_m.awprot <= 'bx; - axi4_m.cb_m.awqos <= 'bx; - axi4_m.cb_m.awregion <= 'bx; - axi4_m.cb_m.awsize <= 'bx; - axi4_m.cb_m.awvalid <= 0; - - endfunction: aw_default - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - repeat(tr_h.delay_h.next()) @(axi4_m.cb_m); - - axi4_m.cb_m.awaddr <= tr_h.addr; - axi4_m.cb_m.awid <= tr_h.id; - axi4_m.cb_m.awlen <= tr_h.len; - axi4_m.cb_m.awsize <= tr_h.size; - - axi4_m.cb_m.awburst <= tr_h.burst; - axi4_m.cb_m.awcache <= tr_h.cache; - axi4_m.cb_m.awlock <= tr_h.lock; - axi4_m.cb_m.awprot <= tr_h.prot; - axi4_m.cb_m.awqos <= tr_h.qos; - axi4_m.cb_m.awregion <= tr_h.region; - axi4_m.cb_m.awvalid <= 1; - - $display("^^^ %16.t | %m | master AW transaction @ 0x%08x |", $time, tr_h.addr); - - repeat(1) @(axi4_m.cb_m); - wait(axi4_m.cb_m.awready); - - axi4_m.zero_cycle_delay(); - aw_default(); - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: aw_master_transaction_class - - - // -------------------------------------------------------------------- - // - class w_master_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m; - - - //-------------------------------------------------------------------- - function new - ( - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m - ); - - super.new(); - this.axi4_m = axi4_m; - - endfunction: new - - - // -------------------------------------------------------------------- - // - function void - w_default; - - axi4_m.cb_m.wdata <= 'bx; - axi4_m.cb_m.wlast <= 'bx; - axi4_m.cb_m.wstrb <= {N{1'b1}}; - axi4_m.cb_m.wvalid <= 0; - - endfunction: w_default - - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - foreach(tr_h.payload_h.w[i]) - begin - repeat(tr_h.delay_h.next()) @(axi4_m.cb_m); - - axi4_m.cb_m.wdata <= tr_h.payload_h.w[i]; - // axi4_m.cb_m.wstrb <= tr_h.strb; // need to fix - - if(i < tr_h.payload_h.w.size - 1) - axi4_m.cb_m.wlast <= 0; - else - axi4_m.cb_m.wlast <= 1; - - axi4_m.cb_m.wvalid <= 1; - - repeat(1) @(axi4_m.cb_m); - wait(axi4_m.cb_m.wready); - - axi4_m.zero_cycle_delay(); - $display("^^^ %16.t | %m | master W transaction | %d | 0x%016x |", $time, i, tr_h.payload_h.w[i]); - w_default(); - end - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: w_master_transaction_class - - - // -------------------------------------------------------------------- - // - class b_master_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m; - - - //-------------------------------------------------------------------- - function new - ( - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m - ); - - super.new(); - this.axi4_m = axi4_m; - - endfunction: new - - - // -------------------------------------------------------------------- - // - function void - b_default; - - axi4_m.cb_m.bready <= 0; - - endfunction: b_default - - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - repeat(tr_h.delay_h.next()) @(axi4_m.cb_m); - axi4_m.cb_m.bready <= 1; - repeat(1) @(axi4_m.cb_m); - - wait(axi4_m.cb_m.bvalid); - axi4_m.zero_cycle_delay(); - - $display("^^^ %16.t | %m | master B transaction | 0x%x |", $time, axi4_m.cb_m.bresp); - b_default(); - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: b_master_transaction_class - - - // -------------------------------------------------------------------- - // - class axi4_master_bfm_class #(A = 32, N = 8, I = 1); - - ar_master_transaction_class #(.A(A), .N(N), .I(I)) ar_h; - r_master_transaction_class #(.A(A), .N(N), .I(I)) r_h; - aw_master_transaction_class #(.A(A), .N(N), .I(I)) aw_h; - w_master_transaction_class #(.A(A), .N(N), .I(I)) w_h; - b_master_transaction_class #(.A(A), .N(N), .I(I)) b_h; - - axi4_transaction_class tr_h; - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m; - - - //-------------------------------------------------------------------- - function new - ( - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m - ); - - this.axi4_m = axi4_m; - - ar_h = new(axi4_m); - r_h = new(axi4_m); - aw_h = new(axi4_m); - w_h = new(axi4_m); - b_h = new(axi4_m); - - ar_h.init(); - ar_h.ar_default(); - - r_h.init(); - r_h.r_default(); - - aw_h.init(); - aw_h.aw_default(); - - w_h.init(); - w_h.w_default(); - - b_h.init(); - b_h.b_default(); - - endfunction: new - - - // -------------------------------------------------------------------- - // - function void - init; - - endfunction: init - - - // -------------------------------------------------------------------- - // - task - basic_read - ( - input logic [(A-1):0] araddr, - input logic [7:0] arlen, - output logic [(8*N)-1:0] data[], - output logic [1:0] rresp - ); - - this.tr_h = new; - this.tr_h.basic_read(araddr, arlen); - - ar_h.put(tr_h); - r_h.put(tr_h); - - @(r_h.done); - data = tr_h.data_h.w; - rresp = tr_h.resp; - - endtask: basic_read - - - // -------------------------------------------------------------------- - // - task - basic_random_read_burst - ( - output logic [(8*N)-1:0] data[], - output logic [1:0] rresp - ); - - this.tr_h = new; - this.tr_h.basic_random_burst; - - ar_h.put(tr_h); - r_h.put(tr_h); - - @(r_h.done); - data = tr_h.data_h.w; - rresp = tr_h.resp; - - endtask: basic_random_read_burst - - - // -------------------------------------------------------------------- - // - task - basic_write - ( - input logic [(A-1):0] awaddr, - input logic [7:0] awlen, - input logic [(8*N)-1:0] data[], - output logic [1:0] bresp - ); - - this.tr_h = new; - this.tr_h.basic_write(awaddr, awlen); - - foreach(this.tr_h.payload_h.w[i]) - this.tr_h.payload_h.w[i] = data[i]; - - aw_h.put(tr_h); - w_h.put(tr_h); - b_h.put(tr_h); - - @(b_h.done); - bresp = tr_h.resp; - - endtask: basic_write - - - // -------------------------------------------------------------------- - // - task - basic_random_write_burst - ( - output logic [1:0] bresp - ); - - this.tr_h = new; - this.tr_h.basic_random_burst; - - aw_h.put(tr_h); - w_h.put(tr_h); - b_h.put(tr_h); - - @(b_h.done); - bresp = tr_h.resp; - - endtask: basic_random_write_burst - - - // -------------------------------------------------------------------- - // - endclass: axi4_master_bfm_class - - -// -------------------------------------------------------------------- -// -endpackage: axi4_bfm_pkg - - Index: trunk/axi4_lib/sim/src/tb_bfm.sv =================================================================== --- trunk/axi4_lib/sim/src/tb_bfm.sv (revision 49) +++ trunk/axi4_lib/sim/src/tb_bfm.sv (nonexistent) @@ -1,119 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_100mhz; - wire tb_clk = clk_100mhz; - wire tb_rst; - wire aclk = tb_clk; - wire aresetn = ~tb_rst; - - tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); - - - // -------------------------------------------------------------------- - // - localparam A = 32; - localparam N = 8; - - - // -------------------------------------------------------------------- - // - axi4_if #(.A(A), .N(N)) - axi4_bus(.*); - - axi4_checker #(.A(A), .N(N)) - axi4_in_check(.axi4_in(axi4_bus)); - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - // -------------------------------------------------------------------- - // - import axi4_simple_agent_pkg::*; - - - // -------------------------------------------------------------------- - // - axi4_master_bfm_if #(.A(A), .N(N)) - axi4_m(.axi4_s(axi4_bus), .*); - - axi4_slave_bfm_if #(.A(A), .N(N)) - axi4_s(.axi4_m(axi4_bus), .*); - - - // -------------------------------------------------------------------- - // - axi4_simple_agent_class bfm; - - initial - bfm = new(axi4_m, axi4_s); - - - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - - - // -------------------------------------------------------------------- - // test - the_test test( tb_clk, tb_rst ); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule - - - Index: trunk/axi4_lib/sim/src/axi4_bfm/axi4_slave_bfm_if.sv =================================================================== --- trunk/axi4_lib/sim/src/axi4_bfm/axi4_slave_bfm_if.sv (revision 49) +++ trunk/axi4_lib/sim/src/axi4_bfm/axi4_slave_bfm_if.sv (nonexistent) @@ -1,514 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -interface - axi4_slave_bfm_if - #( - A = 32, // address bus width - N = 8, // data bus width in bytes - I = 1 // ID width - ) - ( - axi4_if axi4_m, - input aresetn, - input aclk - ); - - logic [(A-1):0] araddr; - logic [1:0] arburst; - logic [3:0] arcache; - logic [(I-1):0] arid; - logic [7:0] arlen; - logic arlock; - logic [2:0] arprot; - logic [3:0] arqos; - logic arready; - logic [3:0] arregion; - logic [2:0] arsize; - logic arvalid; - logic [(A-1):0] awaddr; - logic [1:0] awburst; - logic [3:0] awcache; - logic [(I-1):0] awid; - logic [7:0] awlen; - logic awlock; - logic [2:0] awprot; - logic [3:0] awqos; - logic awready; - logic [3:0] awregion; - logic [2:0] awsize; - logic awvalid; - logic [(I-1):0] bid; - logic bready; - logic [1:0] bresp; - logic bvalid; - logic [(8*N)-1:0] rdata; - logic [(I-1):0] rid; - logic rlast; - logic rready; - logic [1:0] rresp; - logic rvalid; - logic [(8*N)-1:0] wdata; - logic [(I-1):0] wid; - logic wlast; - logic wready; - logic [N-1:0] wstrb; - logic wvalid; - - - // -------------------------------------------------------------------- - // - default clocking cb @(posedge aclk); - input arid; - input araddr; - input arburst; - input arcache; - input awid; - input arlen; - input arlock; - input arprot; - input arqos; - output arready; - input arregion; - input arsize; - input arvalid; - input awaddr; - input awburst; - input awcache; - input awlen; - input awlock; - input awprot; - input awqos; - output awready; - input awregion; - input awsize; - input awvalid; - input bready; - output bid; - output bresp; - output bvalid; - output rdata; - output rid; - output rlast; - input rready; - output rresp; - output rvalid; - input wdata; - input wid; - input wlast; - output wready; - input wstrb; - input wvalid; - input aresetn; - input aclk; - endclocking - - - // -------------------------------------------------------------------- - // - assign arid = axi4_m.arid; - assign araddr = axi4_m.araddr; - assign arburst = axi4_m.arburst; - assign arcache = axi4_m.arcache; - assign awid = axi4_m.awid; - assign arlen = axi4_m.arlen; - assign arlock = axi4_m.arlock; - assign arprot = axi4_m.arprot; - assign arqos = axi4_m.arqos; - assign axi4_m.arready = arready; - assign arregion = axi4_m.arregion; - assign arsize = axi4_m.arsize; - assign arvalid = axi4_m.arvalid; - assign awaddr = axi4_m.awaddr; - assign awburst = axi4_m.awburst; - assign awcache = axi4_m.awcache; - assign awlen = axi4_m.awlen; - assign awlock = axi4_m.awlock; - assign awprot = axi4_m.awprot; - assign awqos = axi4_m.awqos; - assign axi4_m.awready = awready; - assign awregion = axi4_m.awregion; - assign awsize = axi4_m.awsize; - assign awvalid = axi4_m.awvalid; - assign bready = axi4_m.bready; - assign axi4_m.bid = bid; - assign axi4_m.bresp = bresp; - assign axi4_m.bvalid = bvalid; - assign axi4_m.rdata = rdata; - assign axi4_m.rid = rid; - assign axi4_m.rlast = rlast; - assign rready = axi4_m.rready; - assign axi4_m.rresp = rresp; - assign axi4_m.rvalid = rvalid; - assign wdata = axi4_m.wdata; - assign wlast = axi4_m.wlast; - assign axi4_m.wready = wready; - assign wstrb = axi4_m.wstrb; - assign wvalid = axi4_m.wvalid; - - - // -------------------------------------------------------------------- - // - function void - ar_default; - - cb.arready <= 0; - - endfunction: ar_default - - - // -------------------------------------------------------------------- - // - function void - aw_default; - - cb.awready <= 0; - - endfunction: aw_default - - - // -------------------------------------------------------------------- - // - function void - r_default; - - cb.rdata <= 'bx; - cb.rid <= 'bx; - cb.rlast <= 'bx; - cb.rresp <= 0; - cb.rvalid <= 0; - - endfunction: r_default - - - // -------------------------------------------------------------------- - // - function void - w_default; - - cb.wready <= 0; - - endfunction: w_default - - - // -------------------------------------------------------------------- - // - function void - b_default; - - cb.bid <= 0; - cb.bresp <= 0; - cb.bvalid <= 0; - - endfunction: b_default - - - // -------------------------------------------------------------------- - // - function void - init; - - ar_default(); - r_default(); - aw_default(); - w_default(); - b_default(); - - endfunction: init - - - // -------------------------------------------------------------------- - // - task - zero_cycle_delay; - - ##0; - - endtask: zero_cycle_delay - - - // -------------------------------------------------------------------- - // - import tb_bfm_pkg::*; - import axi4_transaction_pkg::*; - - - // -------------------------------------------------------------------- - // - class r_slave_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - foreach(tr_h.payload_h.w[i]) - begin - ##(tr_h.delay_h.next()); - - cb.rdata <= tr_h.payload_h.w[i]; - cb.rresp <= tr_h.resp; - cb.rid <= tr_h.id; - - if(i < tr_h.payload_h.w.size - 1) - cb.rlast <= 0; - else - cb.rlast <= 1; - - cb.rvalid <= 1; - ##1; - - wait(cb.rready); - ##0; - - $display("^^^ %16.t | %m | slave R transaction | %d | 0x%016x |", $time, i, tr_h.payload_h.w[i]); - r_default(); - end - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: r_slave_transaction_class - - - // -------------------------------------------------------------------- - // - r_slave_transaction_class #(.A(A), .N(N), .I(I)) r_h; - - class ar_slave_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - ##(tr_h.delay_h.next()); - - cb.arready <= 1; - ##1; - - wait(cb.arvalid); - - ##0; - r_h.put(tr_h); - ar_default(); - - $display("^^^ %16.t | %m | slave AR transaction @ 0x%08x | 0x%016x |", $time, tr_h.addr, tr_h.payload_h.w[0]); - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: ar_slave_transaction_class - - - // -------------------------------------------------------------------- - // - class aw_slave_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - semaphore aw_semaphore; - - - //-------------------------------------------------------------------- - function new; - - super.new(); - this.aw_semaphore = new(0); - - endfunction: new - - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - ##(tr_h.delay_h.next()); - - cb.awready <= 1; - ##1; - - wait(cb.awvalid); - - ##0; - this.aw_semaphore.put(); - aw_default(); - - $display("^^^ %16.t | %m | slave AW transaction @ 0x%08x | 0x%016x |", $time, tr_h.addr, tr_h.payload_h.w[0]); - - ->this.done; - - endtask: transaction - - // -------------------------------------------------------------------- - // - endclass: aw_slave_transaction_class - - - // -------------------------------------------------------------------- - // - aw_slave_transaction_class #(.A(A), .N(N), .I(I)) aw_h; - - class b_slave_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - // Error: AXI4_ERRS_BRESP_AW: A slave must not give a write response before the write address. - // Spec: section A3.3.1 and figure A3-7. - aw_h.aw_semaphore.get(); // better way to do this??? - - ##(tr_h.delay_h.next()); - - cb.bresp <= tr_h.resp; - cb.bid <= tr_h.id; - - cb.bvalid <= 1; - ##1; - - wait(cb.bready); - ##0; - - $display("^^^ %16.t | %m | slave B transaction |", $time); - b_default(); - - ->this.done; - - endtask: transaction - - // -------------------------------------------------------------------- - // - endclass: b_slave_transaction_class - - - // -------------------------------------------------------------------- - // - b_slave_transaction_class #(.A(A), .N(N), .I(I)) b_h; - - class w_slave_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - tr_h.data_h = new(tr_h.len); - - foreach(tr_h.payload_h.w[i]) - begin - ##(tr_h.delay_h.next()); - - cb.wready <= 1; - ##1; - - wait(cb.wvalid); - ##0; - - tr_h.data_h.w[i] <= cb.wdata; - $display("^^^ %16.t | %m | slave W transaction | %d | 0x%016x |", $time, i, cb.wdata); - w_default(); - end - - b_h.put(tr_h); - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: w_slave_transaction_class - - - // -------------------------------------------------------------------- - // - ar_slave_transaction_class #(.A(A), .N(N), .I(I)) ar_h; - w_slave_transaction_class #(.A(A), .N(N), .I(I)) w_h; - - initial - begin - init(); - ar_h = new; - ar_h.init(); - r_h = new; - r_h.init(); - aw_h = new; - aw_h.init(); - w_h = new; - w_h.init(); - b_h = new; - b_h.init(); - end - - -// -------------------------------------------------------------------- -// - -endinterface - - Index: trunk/axi4_lib/sim/src/axi4_bfm/axi4_master_bfm_if.sv =================================================================== --- trunk/axi4_lib/sim/src/axi4_bfm/axi4_master_bfm_if.sv (revision 49) +++ trunk/axi4_lib/sim/src/axi4_bfm/axi4_master_bfm_if.sv (nonexistent) @@ -1,526 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -interface - axi4_master_bfm_if - #( - A = 32, // address bus width - N = 8, // data bus width in bytes - I = 1 // ID width - ) - ( - axi4_if axi4_s, - input aresetn, - input aclk - ); - - logic [(A-1):0] araddr; - logic [1:0] arburst; - logic [3:0] arcache; - logic [(I-1):0] arid; - logic [7:0] arlen; - logic arlock; - logic [2:0] arprot; - logic [3:0] arqos; - logic arready; - logic [3:0] arregion; - logic [2:0] arsize; - logic arvalid; - logic [(A-1):0] awaddr; - logic [1:0] awburst; - logic [3:0] awcache; - logic [(I-1):0] awid; - logic [7:0] awlen; - logic awlock; - logic [2:0] awprot; - logic [3:0] awqos; - logic awready; - logic [3:0] awregion; - logic [2:0] awsize; - logic awvalid; - logic [(I-1):0] bid; - logic bready; - logic [1:0] bresp; - logic bvalid; - logic [(8*N)-1:0] rdata; - logic [(I-1):0] rid; - logic rlast; - logic rready; - logic [1:0] rresp; - logic rvalid; - logic [(8*N)-1:0] wdata; - logic [(I-1):0] wid; - logic wlast; - logic wready; - logic [N-1:0] wstrb; - logic wvalid; - - - // -------------------------------------------------------------------- - // - default clocking cb @(posedge aclk); - output arid; - output araddr; - output arburst; - output arcache; - output awid; - output arlen; - output arlock; - output arprot; - output arqos; - input arready; - output arregion; - output arsize; - output arvalid; - output awaddr; - output awburst; - output awcache; - output awlen; - output awlock; - output awprot; - output awqos; - input awready; - output awregion; - output awsize; - output awvalid; - output bready; - input bid; - input bresp; - input bvalid; - input rdata; - input rid; - input rlast; - output rready; - input rresp; - input rvalid; - output wdata; - output wlast; - input wready; - output wstrb; - output wvalid; - input aresetn; - input aclk; - endclocking - - - // -------------------------------------------------------------------- - // - assign axi4_s.arid = arid; - assign axi4_s.araddr = araddr; - assign axi4_s.arburst = arburst; - assign axi4_s.arcache = arcache; - assign axi4_s.awid = awid; - assign axi4_s.arlen = arlen; - assign axi4_s.arlock = arlock; - assign axi4_s.arprot = arprot; - assign axi4_s.arqos = arqos; - assign arready = axi4_s.arready; - assign axi4_s.arregion = arregion; - assign axi4_s.arsize = arsize; - assign axi4_s.arvalid = arvalid; - assign axi4_s.awaddr = awaddr; - assign axi4_s.awburst = awburst; - assign axi4_s.awcache = awcache; - assign axi4_s.awlen = awlen; - assign axi4_s.awlock = awlock; - assign axi4_s.awprot = awprot; - assign axi4_s.awqos = awqos; - assign awready = axi4_s.awready; - assign axi4_s.awregion = awregion; - assign axi4_s.awsize = awsize; - assign axi4_s.awvalid = awvalid; - assign axi4_s.bready = bready; - assign bid = axi4_s.bid; - assign bresp = axi4_s.bresp; - assign bvalid = axi4_s.bvalid; - assign rdata = axi4_s.rdata; - assign rid = axi4_s.rid; - assign rlast = axi4_s.rlast; - assign axi4_s.rready = rready; - assign rresp = axi4_s.rresp; - assign rvalid = axi4_s.rvalid; - assign axi4_s.wdata = wdata; - assign axi4_s.wlast = wlast; - assign wready = axi4_s.wready; - assign axi4_s.wstrb = wstrb; - assign axi4_s.wvalid = wvalid; - - - // -------------------------------------------------------------------- - // - function void - ar_default; - - cb.araddr <= 'bx; - cb.arburst <= 'bx; - cb.arcache <= 'bx; - cb.arid <= 'bx; - cb.arlen <= 'bx; - cb.arlock <= 'bx; - cb.arprot <= 'bx; - cb.arqos <= 'bx; - cb.arregion <= 'bx; - cb.arsize <= 'bx; - cb.arvalid <= 0; - - endfunction: ar_default - - - // -------------------------------------------------------------------- - // - function void - aw_default; - - cb.awaddr <= 'bx; - cb.awburst <= 'bx; - cb.awcache <= 'bx; - cb.awid <= 'bx; - cb.awlen <= 'bx; - cb.awlock <= 'bx; - cb.awprot <= 'bx; - cb.awqos <= 'bx; - cb.awregion <= 'bx; - cb.awsize <= 'bx; - cb.awvalid <= 0; - - endfunction: aw_default - - - // -------------------------------------------------------------------- - // - function void - r_default; - - cb.rready <= 0; - - endfunction: r_default - - - // -------------------------------------------------------------------- - // - function void - w_default; - - cb.wdata <= 'bx; - cb.wlast <= 'bx; - cb.wstrb <= {N{1'b1}}; - cb.wvalid <= 0; - - endfunction: w_default - - - // -------------------------------------------------------------------- - // - function void - b_default; - - cb.bready <= 0; - - endfunction: b_default - - - // -------------------------------------------------------------------- - // - function void - init; - - ar_default(); - r_default(); - aw_default(); - w_default(); - b_default(); - - endfunction: init - - - // -------------------------------------------------------------------- - // - task - zero_cycle_delay; - - ##0; - - endtask: zero_cycle_delay - - - // -------------------------------------------------------------------- - // - import tb_bfm_pkg::*; - import axi4_transaction_pkg::*; - - - // -------------------------------------------------------------------- - // - class ar_master_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - ##(tr_h.delay_h.next()); - - cb.araddr <= tr_h.addr; - cb.arid <= tr_h.id; - cb.arlen <= tr_h.len; - cb.arsize <= tr_h.size; - - cb.arburst <= tr_h.burst; - cb.arcache <= tr_h.cache; - cb.arlock <= tr_h.lock; - cb.arprot <= tr_h.prot; - cb.arqos <= tr_h.qos; - cb.arregion <= tr_h.region; - cb.arvalid <= 1; - - $display("^^^ %16.t | %m | master AR transaction @ 0x%08x |", $time, tr_h.addr); - - ##1; - wait(cb.arready); - - ##0; - ar_default(); - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: ar_master_transaction_class - - - // -------------------------------------------------------------------- - // - class r_master_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - tr_h.data_h = new(tr_h.len); - - foreach(tr_h.payload_h.w[i]) - begin - ##(tr_h.delay_h.next()); - cb.rready <= 1; - ##1; - - wait(cb.rvalid); - ##0; - - tr_h.data_h.w[i] = cb.rdata; - - $display("^^^ %16.t | %m | master R transaction | %d | 0x%016x |", $time, i, tr_h.data_h.w[i]); - r_default(); - end - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: r_master_transaction_class - - - // -------------------------------------------------------------------- - // - class aw_master_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - ##(tr_h.delay_h.next()); - - cb.awaddr <= tr_h.addr; - cb.awid <= tr_h.id; - cb.awlen <= tr_h.len; - cb.awsize <= tr_h.size; - - cb.awburst <= tr_h.burst; - cb.awcache <= tr_h.cache; - cb.awlock <= tr_h.lock; - cb.awprot <= tr_h.prot; - cb.awqos <= tr_h.qos; - cb.awregion <= tr_h.region; - cb.awvalid <= 1; - - $display("^^^ %16.t | %m | master AW transaction @ 0x%08x |", $time, tr_h.addr); - - ##1; - wait(cb.awready); - - ##0; - aw_default(); - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: aw_master_transaction_class - - - // -------------------------------------------------------------------- - // - class w_master_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - foreach(tr_h.payload_h.w[i]) - begin - ##(tr_h.delay_h.next()); - - cb.wdata <= tr_h.payload_h.w[i]; - // cb.wstrb <= tr_h.strb; // need to fix - - if(i < tr_h.payload_h.w.size - 1) - cb.wlast <= 0; - else - cb.wlast <= 1; - - cb.wvalid <= 1; - - ##1; - wait(cb.wready); - - ##0; - $display("^^^ %16.t | %m | master W transaction | %d | 0x%016x |", $time, i, tr_h.payload_h.w[i]); - w_default(); - end - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: w_master_transaction_class - - - // -------------------------------------------------------------------- - // - class b_master_transaction_class #(A = 32, N = 8, I = 1) - extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I))); - - // -------------------------------------------------------------------- - // - task automatic - transaction - ( - ref T tr_h - ); - - ->this.start; - - ##(tr_h.delay_h.next()); - cb.bready <= 1; - ##1; - - wait(cb.bvalid); - ##0; - - $display("^^^ %16.t | %m | master B transaction | 0x%x |", $time, cb.bresp); - b_default(); - - ->this.done; - - endtask: transaction - - - // -------------------------------------------------------------------- - // - endclass: b_master_transaction_class - - - // -------------------------------------------------------------------- - // - ar_master_transaction_class #(.A(A), .N(N), .I(I)) ar_h; - r_master_transaction_class #(.A(A), .N(N), .I(I)) r_h; - aw_master_transaction_class #(.A(A), .N(N), .I(I)) aw_h; - w_master_transaction_class #(.A(A), .N(N), .I(I)) w_h; - b_master_transaction_class #(.A(A), .N(N), .I(I)) b_h; - - initial - begin - init(); - ar_h = new; - ar_h.init(); - r_h = new; - r_h.init(); - aw_h = new; - aw_h.init(); - w_h = new; - w_h.init(); - b_h = new; - b_h.init(); - end - - -// -------------------------------------------------------------------- -// - -endinterface - - Index: trunk/axi4_lib/sim/src/axi4_bfm/axi4_transaction_pkg.sv =================================================================== --- trunk/axi4_lib/sim/src/axi4_bfm/axi4_transaction_pkg.sv (revision 49) +++ trunk/axi4_lib/sim/src/axi4_bfm/axi4_transaction_pkg.sv (nonexistent) @@ -1,253 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package axi4_transaction_pkg; - - // -------------------------------------------------------------------- - // - class axi4_delay_class; - - rand int unsigned delay; - - - // -------------------------------------------------------------------- - // - function int unsigned - next; - - assert(this.randomize() with{delay dist {0 := 40, [1:3] := 40, [4:7] := 20};}); - return(delay); - - endfunction: next - - - // -------------------------------------------------------------------- - // - endclass: axi4_delay_class - - - // -------------------------------------------------------------------- - // - class axi4_payload_class #(N = 8); - - rand logic [(8*N)-1:0] w[]; - - - // -------------------------------------------------------------------- - // - function - new - ( - logic [7:0] len = 0 - ); - - this.w = new[len + 1]; - - endfunction: new - - - // -------------------------------------------------------------------- - // - function void - random - ( - logic [7:0] len = 0 - ); - - this.w = new[len + 1]; - assert(this.randomize()); - - endfunction: random - - - // -------------------------------------------------------------------- - // - endclass: axi4_payload_class - - - // -------------------------------------------------------------------- - // - class axi4_transaction_class #(A = 32, N = 8, I = 1); - - axi4_delay_class delay_h; - axi4_payload_class #(.N(N)) payload_h; - axi4_payload_class #(.N(N)) data_h; - rand logic [(A-1):0] addr = 'bz; - rand logic [1:0] burst = 2'b01; - rand logic [7:0] len = 0; - rand logic [2:0] size = $clog2(N); - rand logic [(I-1):0] id = 0; - rand logic [1:0] resp = 0; - - logic [3:0] cache = 0; - logic lock = 0; - logic [2:0] prot = 0; - logic [3:0] qos = 0; - logic [3:0] region = 0; - - constraint default_len - { - len dist {0 := 40, [1:15] := 40, [16:255] := 20}; - } - - - // -------------------------------------------------------------------- - // - function - new - ( - logic [7:0] len = 0 - ); - - this.payload_h = new(len + 1); - this.delay_h = new; - - endfunction: new - - - // -------------------------------------------------------------------- - // - function void - basic_random; - - assert(this.randomize() with - { - this.id == 0; - this.resp == 0; - this.burst == 2'b01; - this.len == 0; - this.size == $clog2(N); - }); - - this.payload_h.random(this.len); - - endfunction: basic_random - - - // -------------------------------------------------------------------- - // - function void - basic_random_burst; - - assert(this.randomize() with - { - this.addr[$clog2(N*8)-1:0] == 0; - this.id == 0; - this.resp == 0; - this.burst == 2'b01; - this.size == $clog2(N); - this.len dist {0 := 40, [1:3] := 40, [4:15] := 20}; - }); - - this.payload_h.random(this.len); - - endfunction: basic_random_burst - - - // -------------------------------------------------------------------- - // - function void - basic_read - ( - logic [(A-1):0] addr, - logic [7:0] len = 0 - ); - - this.id = 0; - this.resp = 0; - this.burst = 2'b01; - this.size = $clog2(N); - this.addr = addr; - this.len = len; - this.payload_h.random(len); - - endfunction: basic_read - - - // -------------------------------------------------------------------- - // - function void - basic_write - ( - logic [(A-1):0] addr, - logic [7:0] len = 0 - ); - - this.id = 0; - this.resp = 0; - this.burst = 2'b01; - this.size = $clog2(N); - this.addr = addr; - this.len = len; - this.payload_h.random(len); - - endfunction: basic_write - - - // -------------------------------------------------------------------- - // - function void copy - ( - axi4_transaction_class #(.A(A), .N(N), .I(I)) from - ); - - this.addr = from.addr; - this.burst = from.burst; - this.len = from.len; - this.size = from.size; - this.id = from.id; - this.resp = from.resp; - this.cache = from.cache; - this.lock = from.lock; - this.prot = from.prot; - this.qos = from.qos; - this.region = from.region; - - endfunction: copy - - - // -------------------------------------------------------------------- - // - virtual function axi4_transaction_class #(.A(A), .N(N), .I(I)) clone; - - clone = new(); - clone.copy(this); - return(clone); - - endfunction: clone - - - // -------------------------------------------------------------------- - // - endclass: axi4_transaction_class - - -// -------------------------------------------------------------------- -// -endpackage: axi4_transaction_pkg - Index: trunk/axi4_lib/sim/src/axi4_bfm/axi4_simple_agent_pkg.sv =================================================================== --- trunk/axi4_lib/sim/src/axi4_bfm/axi4_simple_agent_pkg.sv (revision 49) +++ trunk/axi4_lib/sim/src/axi4_bfm/axi4_simple_agent_pkg.sv (nonexistent) @@ -1,153 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package axi4_simple_agent_pkg; - - // -------------------------------------------------------------------- - // - import axi4_transaction_pkg::*; - - - // -------------------------------------------------------------------- - // - class axi4_simple_agent_class #(A = 32, N = 8, I = 1); - - axi4_transaction_class tr_h; - virtual axi4_master_bfm_if #(.A(A), .N(N), .I(I)) axi4_m; - virtual axi4_slave_bfm_if #(.A(A), .N(N), .I(I)) axi4_s; - - - //-------------------------------------------------------------------- - function new - ( - virtual axi4_master_bfm_if #(.A(A), .N(N), .I(I)) axi4_m, - virtual axi4_slave_bfm_if #(.A(A), .N(N), .I(I)) axi4_s - ); - - this.axi4_m = axi4_m; - this.axi4_s = axi4_s; - - endfunction: new - - - // -------------------------------------------------------------------- - // - task - basic_read - ( - input logic [(A-1):0] araddr, - input logic [7:0] arlen, - output logic [(8*N)-1:0] data[], - output logic [1:0] rresp - ); - - this.tr_h = new; - this.tr_h.basic_read(araddr, arlen); - - axi4_m.ar_h.put(tr_h); - axi4_s.ar_h.put(tr_h); - axi4_m.r_h.put(tr_h); - - @(axi4_m.r_h.done); - data = tr_h.data_h.w; - rresp = tr_h.resp; - - endtask: basic_read - - - // -------------------------------------------------------------------- - // - task - basic_write - ( - input logic [(A-1):0] awaddr, - input logic [7:0] awlen, - input logic [(8*N)-1:0] data[], - output logic [1:0] bresp - ); - - this.tr_h = new; - this.tr_h.basic_write(awaddr, awlen); - - foreach(this.tr_h.payload_h.w[i]) - this.tr_h.payload_h.w[i] = data[i]; - - axi4_m.aw_h.put(tr_h); - axi4_s.aw_h.put(tr_h); - axi4_m.w_h.put(tr_h); - axi4_s.w_h.put(tr_h); - axi4_m.b_h.put(tr_h); - - @(axi4_s.b_h.done); - bresp = tr_h.resp; - - endtask: basic_write - - - // -------------------------------------------------------------------- - // - task - basic_random_write - ( - input logic [(A-1):0] awaddr, - input logic [7:0] awlen, - output logic [1:0] bresp - ); - - this.tr_h = new; - this.tr_h.basic_write(awaddr, awlen); - - axi4_m.aw_h.put(tr_h); - axi4_s.aw_h.put(tr_h); - axi4_m.w_h.put(tr_h); - axi4_s.w_h.put(tr_h); - axi4_m.b_h.put(tr_h); - - @(axi4_s.b_h.done); - bresp = tr_h.resp; - - endtask: basic_random_write - - - // -------------------------------------------------------------------- - // - function void - init; - - endfunction: init - - - // -------------------------------------------------------------------- - // - endclass: axi4_simple_agent_class - - -// -------------------------------------------------------------------- -// -endpackage: axi4_simple_agent_pkg - Index: trunk/axi4_lib/sim/src/tb_axi4_memory.sv =================================================================== --- trunk/axi4_lib/sim/src/tb_axi4_memory.sv (revision 49) +++ trunk/axi4_lib/sim/src/tb_axi4_memory.sv (nonexistent) @@ -1,129 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_100mhz; - wire tb_clk = clk_100mhz; - wire tb_rst; - wire aclk = tb_clk; - wire aresetn = ~tb_rst; - - tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); - - - // -------------------------------------------------------------------- - // - localparam A = 32; - localparam N = 8; - - - // -------------------------------------------------------------------- - // - axi4_if #(.A(A), .N(N)) - axi4_s(.*); - - - // -------------------------------------------------------------------- - // - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - // -------------------------------------------------------------------- - // - axi4_checker #(.A(A), .N(N)) - axi4_s_check(.axi4_in(axi4_s)); - - - // // -------------------------------------------------------------------- - // // - // axi4_master_bfm_if #(.A(A), .N(N)) - // tb_axi4_m(.axi4_s(axi4_s), .*); - - - // -------------------------------------------------------------------- - // - import axi4_bfm_pkg::*; - - axi4_master_bfm_class bfm; - - initial - bfm = new(axi4_s); - - - // -------------------------------------------------------------------- - // - import axi4_memory_pkg::*; - - axi4_memory_class axi4_memory; - - initial - axi4_memory = new(axi4_s); - - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - - - // -------------------------------------------------------------------- - // test - the_test test( tb_clk, tb_rst ); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule - - - Index: trunk/axi4_lib/sim/src/tb_axi4_to_axis_agent_class_pkg.sv =================================================================== --- trunk/axi4_lib/sim/src/tb_axi4_to_axis_agent_class_pkg.sv (revision 49) +++ trunk/axi4_lib/sim/src/tb_axi4_to_axis_agent_class_pkg.sv (nonexistent) @@ -1,130 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package tb_axi4_to_axis_agent_class_pkg; - - // -------------------------------------------------------------------- - // - import axi4_memory_pkg::*; - import axis_bfm_pkg::*; - - - // -------------------------------------------------------------------- - // - class tb_axi4_to_axis_agent_class #(N, A, I, D, U); - - axi4_memory_class #(A, N, I) m_h; - axis_rx_bfm_class #(N, I, D, U) s_h; - memory_tr_class #(A, N, I) m_tr_h, m_tr_clone_h; - axis_tr_class #(N, I, D, U) s_tr_h; - - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m; - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out; - - mailbox #(memory_tr_class #(A, N, I)) q; - - - // -------------------------------------------------------------------- - // - task wait_for_sof; - @(posedge axis_out.cb_s.tuser); - $display("^^^ %16.t | %m", $time); - endtask: wait_for_sof - - - // -------------------------------------------------------------------- - // - task random_transaction(int addr, int size); - m_tr_h = new(); - m_tr_h.random(addr, size); - m_tr_clone_h = m_tr_h.clone(); - q.put(m_tr_clone_h); - m_h.load_words(addr, m_tr_h.data); - endtask: random_transaction - - - // -------------------------------------------------------------------- - // - task automatic - compare; - - $display("^^^ %16.t | %m", $time); - $display("^^^ %16.t | q.num = %d", $time, q.num); - $display("^^^ %16.t | s_h.q.num = %d", $time, s_h.q.num); - $display("^^^ %16.t | m_tr_h.data.size = %d", $time, m_tr_h.data.size); - - q.get(m_tr_h); - - for(int i = 0; i < m_tr_h.data.size; i += N) - begin - if(s_h.q.try_get(s_tr_h) == 0) - begin - $display("!!! %16.t | ERROR!!! try_get(s_tr_h) == 0", $time); - break; - end - - for(int k = 0; k < N; k++) - begin - if(s_tr_h.tdata[k*8 +: 8] != m_tr_h.data[i + k]) - begin - $display("!!! %16.t | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^", $time); - $display("!!! %16.t | ERROR!!! mismatch | i = %d | k = %d", $time, i, k); - $display("!!! %16.t | %x | %x |", $time, s_tr_h.tdata[k*8 +: 8], m_tr_h.data[i + k]); - $stop; - end - end - end - - $display("^^^ %16.t | %m | done!", $time); - - endtask: compare - - - //-------------------------------------------------------------------- - // - function new - ( - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m, - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out - ); - - this.axi4_m = axi4_m; - this.axis_out = axis_out; - m_h = new(axi4_m); - s_h = new(axis_out); - q = new(); - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: tb_axi4_to_axis_agent_class - -// -------------------------------------------------------------------- -// -endpackage: tb_axi4_to_axis_agent_class_pkg Index: trunk/axi4_lib/sim/src/tb_register_slice.sv =================================================================== --- trunk/axi4_lib/sim/src/tb_register_slice.sv (revision 49) +++ trunk/axi4_lib/sim/src/tb_register_slice.sv (nonexistent) @@ -1,133 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_100mhz; - wire tb_clk = clk_100mhz; - wire tb_rst; - wire aclk = tb_clk; - wire aresetn = ~tb_rst; - - tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); - - - // -------------------------------------------------------------------- - // - localparam A = 32; - localparam N = 8; - - - // -------------------------------------------------------------------- - // - axi4_if #(.A(A), .N(N)) - axi4_s(.*); - - axi4_if #(.A(A), .N(N)) - axi4_m(.*); - - - // -------------------------------------------------------------------- - // - axi4_register_slice #(.A(A), .N(N)) - dut(.*); - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - // -------------------------------------------------------------------- - // - axi4_checker #(.A(A), .N(N)) - axi4_s_check(.axi4_in(axi4_s)); - - axi4_checker #(.A(A), .N(N)) - axi4_m_check(.axi4_in(axi4_m)); - - - // -------------------------------------------------------------------- - // - import axi4_simple_agent_pkg::*; - - - // -------------------------------------------------------------------- - // - axi4_master_bfm_if #(.A(A), .N(N)) - tb_axi4_m(.axi4_s(axi4_s), .*); - - axi4_slave_bfm_if #(.A(A), .N(N)) - tb_axi4_s(.axi4_m(axi4_m), .*); - - - // -------------------------------------------------------------------- - // - axi4_simple_agent_class bfm; - - initial - bfm = new(tb_axi4_m, tb_axi4_s); - - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - - - // -------------------------------------------------------------------- - // test - the_test test( tb_clk, tb_rst ); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule - - - Index: trunk/axi4_lib/sim/src/axi4_models/axi4_arbiter_pkg.sv =================================================================== --- trunk/axi4_lib/sim/src/axi4_models/axi4_arbiter_pkg.sv (revision 49) +++ trunk/axi4_lib/sim/src/axi4_models/axi4_arbiter_pkg.sv (nonexistent) @@ -1,474 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package axi4_arbiter_pkg; - - // -------------------------------------------------------------------- - // - import axi4_models_pkg::*; - import bfm_pkg::*; - import logger_pkg::*; - - - // -------------------------------------------------------------------- - // - virtual class base_request_class #(A, N, I); - - string kind; - int id = -1; - - //-------------------------------------------------------------------- - // - pure virtual function void write_ax_if(axi4_channel_if_class #(A, N, I) channel); - pure virtual function void copy_ax_if(axi4_channel_if_class #(A, N, I) channel); - - - // -------------------------------------------------------------------- - // - endclass: base_request_class - - - // -------------------------------------------------------------------- - // - class write_request_class #(A, N, I) - extends base_request_class #(A, N, I); - - logic [(A-1):0] awaddr; - logic [1:0] awburst; - logic [(I-1):0] awid; - logic [7:0] awlen; - logic [2:0] awsize; - logic [3:0] awcache; - logic awlock; - logic [2:0] awprot; - logic [3:0] awqos; - logic [3:0] awregion; - - - // -------------------------------------------------------------------- - // - function void write_ax_if(axi4_channel_if_class #(A, N, I) channel); - axi4_aw_if_class #(A, N, I) aw_if_h; - $cast(aw_if_h, channel); - aw_if_h.awaddr = awaddr; - aw_if_h.awburst = awburst; - aw_if_h.awid = awid; - aw_if_h.awlen = awlen; - aw_if_h.awsize = awsize; - aw_if_h.awcache = awcache; - aw_if_h.awlock = awlock; - aw_if_h.awprot = awprot; - aw_if_h.awqos = awqos; - aw_if_h.awregion = awregion; - endfunction: write_ax_if - - - // -------------------------------------------------------------------- - // - function void copy_ax_if(axi4_channel_if_class #(A, N, I) channel); - axi4_aw_if_class #(A, N, I) aw_if_h; - $cast(aw_if_h, channel); - awaddr = aw_if_h.awaddr; - awburst = aw_if_h.awburst; - awid = aw_if_h.awid; - awlen = aw_if_h.awlen; - awsize = aw_if_h.awsize; - awcache = aw_if_h.awcache; - awlock = aw_if_h.awlock; - awprot = aw_if_h.awprot; - awqos = aw_if_h.awqos; - awregion = aw_if_h.awregion; - endfunction: copy_ax_if - - - //-------------------------------------------------------------------- - function new(int id); - super.new; - this.kind = "WRITE"; - this.id = id; - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: write_request_class - - - // -------------------------------------------------------------------- - // - class read_request_class #(A, N, I) - extends base_request_class #(A, N, I); - - logic [(A-1):0] araddr; - logic [1:0] arburst; - logic [(I-1):0] arid; - logic [7:0] arlen; - logic [2:0] arsize; - logic [3:0] arcache; - logic arlock; - logic [2:0] arprot; - logic [3:0] arqos; - logic [3:0] arregion; - - // -------------------------------------------------------------------- - // - function void write_ax_if(axi4_channel_if_class #(A, N, I) channel); - axi4_ar_if_class #(A, N, I) ar_if_h; - $cast(ar_if_h, channel); - ar_if_h.araddr = araddr; - ar_if_h.arburst = arburst; - ar_if_h.arid = arid; - ar_if_h.arlen = arlen; - ar_if_h.arsize = arsize; - ar_if_h.arcache = arcache; - ar_if_h.arlock = arlock; - ar_if_h.arprot = arprot; - ar_if_h.arqos = arqos; - ar_if_h.arregion = arregion; - endfunction: write_ax_if - - - // -------------------------------------------------------------------- - // - function void copy_ax_if(axi4_channel_if_class #(A, N, I) channel); - axi4_ar_if_class #(A, N, I) ar_if_h; - $cast(ar_if_h, channel); - araddr = ar_if_h.araddr; - arburst = ar_if_h.arburst; - arid = ar_if_h.arid; - arlen = ar_if_h.arlen; - arsize = ar_if_h.arsize; - arcache = ar_if_h.arcache; - arlock = ar_if_h.arlock; - arprot = ar_if_h.arprot; - arqos = ar_if_h.arqos; - arregion = ar_if_h.arregion; - endfunction: copy_ax_if - - - //-------------------------------------------------------------------- - function new(int id); - super.new; - this.kind = "READ"; - this.id = id; - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: read_request_class - - - // -------------------------------------------------------------------- - // - class requester_class #(A, N, I) - extends axi4_slave_model_class #(A, N, I); - - mailbox #(base_request_class #(A, N, I)) q; - semaphore read_done; - semaphore write_done; - int id = -1; - logger_class log; - - - // -------------------------------------------------------------------- - // - task automatic run_read_interface; - read_request_class #(A, N, I) r_req_h; - read_done = new; - forever - @(axi4_s.cb_s) - begin - ar_q_h.q.get(ar_if_h); - log.debug($sformatf("%m | start")); - log.debug($sformatf("%m | araddr = 0x%h", ar_if_h.araddr)); - log.debug($sformatf("%m | arlen = 0x%h", ar_if_h.arlen)); - r_req_h = new(id); - r_req_h.copy_ax_if(ar_if_h); - q.put(r_req_h); - read_done.get(); - log.debug($sformatf("%m | done")); - end - endtask: run_read_interface - - - // -------------------------------------------------------------------- - // - task run_write_interface; - write_request_class #(A, N, I) w_req_h; - write_done = new; - forever - @(axi4_s.cb_s) - begin - aw_q_h.q.get(aw_if_h); - log.debug($sformatf("%m | start")); - log.debug($sformatf("%m | awaddr = 0x%h", aw_if_h.awaddr)); - log.debug($sformatf("%m | awlen = 0x%h", aw_if_h.awlen)); - w_req_h = new(id); - w_req_h.copy_ax_if(aw_if_h); - q.put(w_req_h); - write_done.get(); - log.debug($sformatf("%m | done")); - end - endtask: run_write_interface - - - // -------------------------------------------------------------------- - // - task run_model; - wait(axi4_s.cb_s.aresetn); - axi4_s.zero_cycle_delay(); - - aw_q_h.run_q(); - w_q_h.run_q(); - b_q_h.run_q(); - ar_q_h.run_q(); - r_q_h.run_q(); - - fork - run_read_interface(); - join_none - - fork - run_write_interface(); - join_none - - endtask: run_model - - - //-------------------------------------------------------------------- - function new(int id, virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_s); - super.new(axi4_s); - this.aw_q_h = new(axi4_s, 2); - this.w_q_h = new(axi4_s, 16); - this.b_q_h = new(axi4_s, 2); - this.ar_q_h = new(axi4_s, 2); - this.r_q_h = new(axi4_s, 16); - this.id = id; - this.q = new(1); - this.log = new(); - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: requester_class - - - // -------------------------------------------------------------------- - // - class axi4_granter_class #(A, N, I) - extends axi4_master_model_class #(A, N, I); - - logger_class log; - - - // -------------------------------------------------------------------- - // - task run_model; - wait(axi4_m.cb_s.aresetn); - axi4_m.zero_cycle_delay(); - - aw_q_h.run_q(); - w_q_h.run_q(); - b_q_h.run_q(); - ar_q_h.run_q(); - r_q_h.run_q(); - endtask: run_model - - - //-------------------------------------------------------------------- - function new(virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m); - super.new(axi4_m); - this.aw_q_h = new(axi4_m, 2); - this.w_q_h = new(axi4_m, 16); - this.b_q_h = new(axi4_m, 2); - this.ar_q_h = new(axi4_m, 2); - this.r_q_h = new(axi4_m, 16); - this.log = new(); - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: axi4_granter_class - - - // -------------------------------------------------------------------- - // - class axi4_arbiter_class #(A, N, I); - - axi4_granter_class #(A, N, I) g_h; - requester_class #(A, N, I) r_h[]; - mailbox #(int) grant; - int count = -1; - int current = 0, previous; - logger_class log; - - - // -------------------------------------------------------------------- - // - task automatic do_read(requester_class #(A, N, I) r_h); - int id; - read_request_class #(A, N, I) r_req_h; - base_request_class #(A, N, I) request; - log.debug($sformatf("%m | read grant for %d", r_h.id)); - r_h.q.get(request); - $cast(r_req_h, request); - - g_h.ar_if_h = new(g_h.axi4_m); - r_req_h.write_ax_if(g_h.ar_if_h); - g_h.ar_q_h.q.put(g_h.ar_if_h); - - for(int i = 0; i < r_h.ar_if_h.arlen + 1; i++) - begin - g_h.r_if_h = new(g_h.axi4_m); - r_h.r_if_h = new(r_h.axi4_s); - g_h.r_q_h.q.get(g_h.r_if_h); - r_h.r_if_h.copy(g_h.r_if_h); - r_h.r_q_h.q.put(r_h.r_if_h); - @(r_h.axi4_s.cb_s); - end - - r_h.read_done.put(); - grant.get(id); - log.debug($sformatf("%m | read grant for %d done", id)); - endtask: do_read - - - // -------------------------------------------------------------------- - // - task automatic do_write(requester_class #(A, N, I) r_h); - int id; - write_request_class #(A, N, I) w_req_h; - base_request_class #(A, N, I) request; - log.debug($sformatf("%m | write grant for %d", r_h.id)); - r_h.q.get(request); - $cast(w_req_h, request); - - g_h.aw_if_h = new(g_h.axi4_m); - w_req_h.write_ax_if(g_h.aw_if_h); - g_h.aw_q_h.q.put(g_h.aw_if_h); - - for(int i = 0; i < r_h.aw_if_h.awlen + 1; i++) - begin - r_h.w_if_h = new(r_h.axi4_s); - g_h.w_if_h = new(g_h.axi4_m); - r_h.w_q_h.q.get(r_h.w_if_h); - g_h.w_if_h.copy(r_h.w_if_h); - g_h.w_q_h.q.put(g_h.w_if_h); - @(r_h.axi4_s.cb_s); - end - - g_h.b_q_h.q.get(g_h.b_if_h); - r_h.b_if_h = new(r_h.axi4_s); - r_h.b_if_h.copy(g_h.b_if_h); - r_h.b_q_h.q.put(r_h.b_if_h); - r_h.write_done.put(); - grant.get(id); - log.debug($sformatf("%m | write grant for %d done", id)); - endtask: do_write - - - // -------------------------------------------------------------------- - // - task automatic give_grant(requester_class #(A, N, I) r_h); - base_request_class #(A, N, I) request; - grant.put(r_h.id); - r_h.q.peek(request); - log.debug($sformatf("%m | %d got grant for %s", r_h.id, request.kind)); - - if(request.kind.toupper == "WRITE") - do_write(r_h); - else if(request.kind.toupper == "READ") - do_read(r_h); - else - $stop; - - current = (current + count + 1) % count; - log.debug($sformatf("%m | new current = %d", current)); - endtask: give_grant - - - // -------------------------------------------------------------------- - // - task automatic do_arbitration; - wait(g_h.axi4_m.cb_m.aresetn); - g_h.axi4_m.zero_cycle_delay(); - forever - @(g_h.axi4_m.cb_m) - begin - for(int i = current; i < current + count; i++) - if(r_h[i % count].q.num > 0) - begin - give_grant(r_h[i % count]); - break; - end - end - endtask: do_arbitration - - - //-------------------------------------------------------------------- - function void debug_enable; - log.debug_enable(); - g_h.log.debug_enable(); - foreach(r_h[i]) - r_h[i].log.debug_enable(); - endfunction: debug_enable - - - //-------------------------------------------------------------------- - function new - ( - virtual axi4_if #(A, N, I) axi4_s[], - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m - ); - this.grant = new(1); - this.g_h = new(axi4_m); - this.count = axi4_s.size; - this.r_h = new[axi4_s.size]; - this.log = new; - - foreach(axi4_s[i]) - r_h[i] = new(i, axi4_s[i]); - - fork - do_arbitration(); - join_none - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: axi4_arbiter_class - - -// -------------------------------------------------------------------- -// -endpackage: axi4_arbiter_pkg - Index: trunk/axi4_lib/sim/src/axi4_models/axi4_memory_pkg.sv =================================================================== --- trunk/axi4_lib/sim/src/axi4_models/axi4_memory_pkg.sv (revision 49) +++ trunk/axi4_lib/sim/src/axi4_models/axi4_memory_pkg.sv (nonexistent) @@ -1,369 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package axi4_memory_pkg; - - // -------------------------------------------------------------------- - // - import axi4_models_pkg::*; - import bfm_pkg::*; - import logger_pkg::*; - - - // -------------------------------------------------------------------- - // - class memory_tr_class #(A, N, I, type WORD_T = byte) - extends transaction_class #(memory_tr_class #(A, N, I)); - - rand int addr; - rand int size; - rand byte data[]; - - constraint default_addr - { - addr[$clog2(N*8)-1:0] == 0; - } - - constraint default_size - { - size dist {N := 40, [N*2:N*15] := 40, [N*16:N*255] := 20}; - } - - - //-------------------------------------------------------------------- - // - function void init(int addr, int size); - this.data = new[size]; - this.addr = addr; - this.size = size; - endfunction: init - - - //-------------------------------------------------------------------- - // - function void random(int addr, int size); - this.data = new[size]; - assert(this.randomize() with - { - this.addr == addr; // why not working? - this.size == size; - }); - this.addr = addr; - this.size = size; - endfunction: random - - - // -------------------------------------------------------------------- - // - task constant(int addr, int size, byte value[]); - init(addr, size); - this.data = new[size]; - for(int i = 0; i < size; i += value.size) - foreach(value[k]) - data[i + k] = value[k]; - endtask: constant - - - // -------------------------------------------------------------------- - // - task automatic counting(int addr, int count); - byte word[]; - int word_size = $bits(WORD_T) / 8; // word size in bytes - init(addr, count * word_size); - for(WORD_T i = 0; i < count; i++) - begin - word = {<< byte{i}}; - foreach(word[k]) - data[addr + (i * word_size) + k] = word[k]; - end - endtask: counting - - - // -------------------------------------------------------------------- - // - function void copy(TR_T from); - init(from.addr, from.size); - this.data = new[from.size]; - foreach(from.data[i]) - this.data[i] = from.data[i]; - endfunction: copy - - - //-------------------------------------------------------------------- - function new; - a_word_t_mod_n: assert($bits(WORD_T) % 8 == 0) else $fatal; - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: memory_tr_class - - - // -------------------------------------------------------------------- - // - class axi4_memory_class #(A, N, I, type WORD_T = byte) - extends axi4_slave_model_class #(.A(A), .N(N), .I(I)); - - logger_class log; - byte memory [*]; - - - // -------------------------------------------------------------------- - // - function void clear_all; - memory.delete; - endfunction: clear_all - - - // -------------------------------------------------------------------- - // - function void compare(memory_tr_class #(A, N, I, WORD_T) tr_h); - foreach(tr_h.data[i]) - if(memory.exists(tr_h.addr + i)) - begin - if(memory[tr_h.addr + i] != tr_h.data[i]) - log.error($sformatf("%m | 1 memory[0x%8.h] = 0x%2.h | 0x%2.h", tr_h.addr + i, memory[tr_h.addr + i], tr_h.data[i])); - end - else - log.error($sformatf("%m | 2 memory[0x%8.h] = 0x%2.h | 0x%2.h", tr_h.addr + i, 'bx, tr_h.data[i])); - endfunction: compare - - - // -------------------------------------------------------------------- - // - task display_memory(int offset, int count); - for(int i = 0; i < count; i++) - if(memory.exists(offset + i)) - $display("^^^ %16.t | %m | memory[0x%8.x] = 0x%2.x", $time, offset + i, memory[offset + i]); - else - $display("^^^ %16.t | %m | memory[0x%8.x] = 0x%2.x", $time, offset + i, 8'hxx); - endtask: display_memory - - - // -------------------------------------------------------------------- - // - task constant_fill(int offset, int count, int value); - for(int i = 0; i < count; i++) - memory[offset + i] = value; - endtask: constant_fill - - - // -------------------------------------------------------------------- - // - task counting_fill(int offset, int count); - for(int i = 0; i < count; i++) - memory[offset + i] = i; - endtask: counting_fill - - - // -------------------------------------------------------------------- - // - task dump_words(int offset, ref byte data[]); - foreach(data[i]) - if(memory.exists(offset + i)) - data[i] = memory[offset + i]; - else - data[i] = 'bx; - endtask: dump_words - - - // -------------------------------------------------------------------- - // - function reg [7:0] dump(int offset); - if(memory.exists(offset)) - return(memory[offset]); - else - return('bx); - endfunction: dump - - - // -------------------------------------------------------------------- - // - task load_words(int offset, byte data[]); - foreach(data[i]) - memory[offset + i] = data[i]; - endtask: load_words - - - // -------------------------------------------------------------------- - // - task load(int offset, reg [7:0] data); - memory[offset] = data; - endtask: load - - - // -------------------------------------------------------------------- - // - task run_read_interface; - int result; - logic [9:0] delay = 0; - int memory_addr; - - forever - @(axi4_s.cb_s) - begin - result = ar_q_h.q.try_peek(ar_if_h); - if(result != 0) - begin - log.debug($sformatf("araddr = 0x%h", ar_if_h.araddr)); - log.debug($sformatf("arlen = 0x%h", ar_if_h.arlen)); - delay = $urandom_range(9, 0); - if(delay > 6) - repeat($urandom_range(50, 1)) - @(axi4_s.cb_s); - - for(int i = 0; i < ar_if_h.arlen + 1; i++) - begin - memory_addr = ar_if_h.araddr + (i * (2 ** ar_if_h.arsize)); - for(int i = 0; i < ar_if_h.N; i++) - begin - if(memory.exists(memory_addr)) - r_if_h.rdata[i*8 +: 8] = memory[memory_addr]; - else - r_if_h.rdata[i*8 +: 8] = 8'hxx; - - memory_addr++; - end - log.debug($sformatf("rdata = 0x%h", r_if_h.rdata)); - - if(i == ar_if_h.arlen) - begin - ar_q_h.q.get(ar_if_h); - r_if_h.rlast = 1; - end - else - r_if_h.rlast = 0; - - r_if_h.rid = 0; - r_if_h.rresp = 0; - - r_q_h.q.put(r_if_h); - r_if_h = new(axi4_s); - - @(axi4_s.cb_s); - end - r_if_h.rlast = 0; - end - end - endtask: run_read_interface - - - // -------------------------------------------------------------------- - // - task run_write_interface; - - int result; - logic [9:0] delay = 0; - int memory_addr; - - forever - @(axi4_s.cb_s) - begin - result = aw_q_h.q.try_peek(aw_if_h); - if(result != 0) - begin - memory_addr = aw_if_h.awaddr; - log.debug($sformatf("awaddr = 0x%h", aw_if_h.awaddr)); - - delay = $urandom_range(9, 0); - if(delay > 6) - repeat($urandom_range(8, 1)) - @(axi4_s.cb_s); - - for(int i = 0; i < aw_if_h.awlen + 1; i++) - begin - w_q_h.q.get(w_if_h); - log.debug($sformatf("wdata = 0x%h", w_if_h.wdata)); - for(int k = 0; k < aw_if_h.N; k++) - begin - memory[memory_addr] = w_if_h.wdata[k*8 +: 8]; - memory_addr++; - end - - if(i == aw_if_h.awlen) - begin - b_if_h.bresp = 0; - b_if_h.bid = aw_if_h.awid; - b_q_h.q.put(b_if_h); - b_if_h = new(axi4_s); - aw_q_h.q.get(aw_if_h); - end - - @(axi4_s.cb_s); - end - end - end - - endtask: run_write_interface - - - // -------------------------------------------------------------------- - // - task run_model; - wait(axi4_s.cb_s.aresetn); - axi4_s.zero_cycle_delay(); - - aw_q_h.run_q(); - w_q_h.run_q(); - b_q_h.run_q(); - ar_q_h.run_q(); - r_q_h.run_q(); - - fork - run_write_interface(); - join_none - - fork - run_read_interface(); - join_none - endtask: run_model - - - //-------------------------------------------------------------------- - function new(virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_s); - super.new(axi4_s); - a_word_t_mod_n: assert($bits(WORD_T) % 8 == 0) else $fatal; - this.aw_q_h = new(axi4_s, 2); - this.w_q_h = new(axi4_s, 16); - this.b_q_h = new(axi4_s, 2); - this.ar_q_h = new(axi4_s, 2); - this.r_q_h = new(axi4_s, 16); - this.log = new(); - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: axi4_memory_class - - -// -------------------------------------------------------------------- -// -endpackage: axi4_memory_pkg - Index: trunk/axi4_lib/sim/src/axi4_models/tb_axi4_multi_port_memory.sv =================================================================== --- trunk/axi4_lib/sim/src/axi4_models/tb_axi4_multi_port_memory.sv (revision 49) +++ trunk/axi4_lib/sim/src/axi4_models/tb_axi4_multi_port_memory.sv (nonexistent) @@ -1,89 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -module - tb_axi4_multi_port_memory - #( - A = 32, // address bus width - N = 8, // data bus width in bytes - I = 1, // ID width - PORTS, - MAXWAITS = 256, - type WORD_T = byte - ) - ( - axi4_if axi4_s[PORTS], - - input aclk, - input aresetn - ); - - // -------------------------------------------------------------------- - // - import axis_bfm_pkg::*; - import axi4_memory_pkg::*; - import axi4_arbiter_pkg::*; - - - // -------------------------------------------------------------------- - // - axi4_if #(.A(A), .N(N), .I(I)) axi4_bus(.*); - - - // -------------------------------------------------------------------- - // - axi4_arbiter_class #(A, N, I) arb_h; - axi4_memory_class #(A, N, I, WORD_T) m_h; - - initial - begin - arb_h = new(axi4_s, axi4_bus); - m_h = new(axi4_bus); - end - - - // -------------------------------------------------------------------- - // - axi4_checker #(.A(A), .N(N), .MAXWAITS(MAXWAITS)) - axi4_bus_checker(.axi4_in(axi4_bus)); - - - // -------------------------------------------------------------------- - // - generate - begin: axi4_s_cherkers - for(genvar j = 0; j < PORTS; j++) - axi4_checker #(.A(A), .N(N), .MAXWAITS(MAXWAITS)) - axi4_checker_i(.axi4_in(axi4_s[j])); - end - endgenerate - - -// -------------------------------------------------------------------- -// -endmodule - Index: trunk/axi4_lib/sim/src/axi4_models/axi4_models_pkg.sv =================================================================== --- trunk/axi4_lib/sim/src/axi4_models/axi4_models_pkg.sv (revision 49) +++ trunk/axi4_lib/sim/src/axi4_models/axi4_models_pkg.sv (nonexistent) @@ -1,822 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -// -------------------------------------------------------------------- -// -package axi4_models_pkg; - - // -------------------------------------------------------------------- - // - virtual class axi4_channel_if_class #(A, N, I); - - virtual axi4_if #(A, N, I) axi4_bus; - event valid; - - - // -------------------------------------------------------------------- - // - pure virtual function void set_master_default; - pure virtual function void set_slave_default; - pure virtual function void copy(axi4_channel_if_class #(A, N, I) from); - pure virtual function void copy_if; - pure virtual function void drive_if; - pure virtual function void set_ready(bit value); - pure virtual function bit is_valid; - pure virtual function void set_valid(bit value); - pure virtual function bit is_ready; - pure virtual function bit is_transfer; - - - //-------------------------------------------------------------------- - function new(virtual axi4_if #(A, N, I) axi4_bus); - this.axi4_bus = axi4_bus; - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: axi4_channel_if_class - - - // -------------------------------------------------------------------- - // - class axi4_channel_sink_q_class #(A, N, I, type T = logic); - - virtual axi4_if #(A, N, I) axi4_bus; - T c_if_h; - int q_size; - mailbox #(T) q; - - - // -------------------------------------------------------------------- - // - function automatic void run_q; - int result; - c_if_h.set_ready(1'b1); - - fork - forever - @(axi4_bus.cb_s) - begin - if(c_if_h.is_transfer) - begin - result = q.try_put(c_if_h); - if(result == 0) - $error; - - c_if_h.copy_if(); - c_if_h = new(axi4_bus); - end - - if(q.num >= q_size) - c_if_h.set_ready(1'b0); - else - c_if_h.set_ready(1'b1); - end - join_none - endfunction: run_q - - - //-------------------------------------------------------------------- - function new( virtual axi4_if #(A, N, I) axi4_bus, int q_size); - this.axi4_bus = axi4_bus; - this.q_size = q_size; - this.q = new(q_size); - this.c_if_h = new(axi4_bus); - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: axi4_channel_sink_q_class - - - // -------------------------------------------------------------------- - // - class axi4_channel_source_q_class #(A, N, I, type T = logic); - - virtual axi4_if #(A, N, I) axi4_bus; - T c_if_h; - int q_size; - mailbox #(T) q; - - - // -------------------------------------------------------------------- - // - function automatic void run_q; - int result; - c_if_h.set_valid(1'b0); - - fork - forever - @(axi4_bus.cb_s) - begin - if(c_if_h.is_transfer) - begin - result = q.try_get(c_if_h); - if(result == 0) - $stop; - end - - result = q.try_peek(c_if_h); - if(result == 0) - c_if_h.set_valid(1'b0); - else - begin - c_if_h.set_valid(1'b1); - c_if_h.drive_if(); - end - end - join_none - endfunction: run_q - - - //-------------------------------------------------------------------- - function new(virtual axi4_if #(A, N, I) axi4_bus, int q_size); - this.axi4_bus = axi4_bus; - this.q_size = q_size; - this.q = new(q_size); - this.c_if_h = new(axi4_bus); - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: axi4_channel_source_q_class - - - // -------------------------------------------------------------------- - // - class axi4_aw_if_class #(A, N, I) - extends axi4_channel_if_class #(A, N, I); - - logic [(A-1):0] awaddr; - logic [1:0] awburst; - logic [(I-1):0] awid; - logic [7:0] awlen; - logic [2:0] awsize; - logic [3:0] awcache; - logic awlock; - logic [2:0] awprot; - logic [3:0] awqos; - logic [3:0] awregion; - - - // -------------------------------------------------------------------- - // - function void set_master_default; - axi4_bus.cb_m.awvalid <= 0; - endfunction: set_master_default - - - // -------------------------------------------------------------------- - // - function void set_slave_default; - axi4_bus.cb_s.awready <= 0; - endfunction: set_slave_default - - - // -------------------------------------------------------------------- - // - function void copy(axi4_channel_if_class #(A, N, I) from); - axi4_aw_if_class #(A, N, I) child; - $cast(child, from); - awaddr = child.awaddr; - awburst = child.awburst; - awid = child.awid; - awlen = child.awlen; - awsize = child.awsize; - awcache = child.awcache; - awlock = child.awlock; - awprot = child.awprot; - awqos = child.awqos; - awregion = child.awregion; - endfunction: copy - - - // -------------------------------------------------------------------- - // - function void copy_if; - awaddr = axi4_bus.cb_s.awaddr; - awburst = axi4_bus.cb_s.awburst; - awid = axi4_bus.cb_s.awid; - awlen = axi4_bus.cb_s.awlen; - awsize = axi4_bus.cb_s.awsize; - awcache = axi4_bus.cb_s.awcache; - awlock = axi4_bus.cb_s.awlock; - awprot = axi4_bus.cb_s.awprot; - awqos = axi4_bus.cb_s.awqos; - awregion = axi4_bus.cb_s.awregion; - endfunction: copy_if - - - // -------------------------------------------------------------------- - // - function void drive_if; - axi4_bus.cb_m.awaddr <= awaddr; - axi4_bus.cb_m.awburst <= awburst; - axi4_bus.cb_m.awid <= awid; - axi4_bus.cb_m.awlen <= awlen; - axi4_bus.cb_m.awsize <= awsize; - axi4_bus.cb_m.awcache <= awcache; - axi4_bus.cb_m.awlock <= awlock; - axi4_bus.cb_m.awprot <= awprot; - axi4_bus.cb_m.awqos <= awqos; - axi4_bus.cb_m.awregion <= awregion; - endfunction: drive_if - - - // -------------------------------------------------------------------- - // - function void set_ready(bit value); - axi4_bus.cb_s.awready <= value; - endfunction: set_ready - - - // -------------------------------------------------------------------- - // - function bit is_valid; - return(axi4_bus.cb_s.awvalid); - endfunction: is_valid - - - // -------------------------------------------------------------------- - // - function void set_valid(bit value); - axi4_bus.cb_m.awvalid <= value; - endfunction: set_valid - - - // -------------------------------------------------------------------- - // - function bit is_ready; - return(axi4_bus.cb_m.awready); - endfunction: is_ready - - - // -------------------------------------------------------------------- - // - function bit is_transfer; - return(axi4_bus.cb_m.awready & axi4_bus.cb_s.awvalid); - endfunction: is_transfer - - - //-------------------------------------------------------------------- - function new(virtual axi4_if #(A, N, I) axi4_bus); - super.new(axi4_bus); - endfunction: new - - // -------------------------------------------------------------------- - // - endclass: axi4_aw_if_class - - - // -------------------------------------------------------------------- - // - class axi4_ar_if_class #(A, N, I) - extends axi4_channel_if_class #(A, N, I); - - logic [(A-1):0] araddr; - logic [1:0] arburst; - logic [(I-1):0] arid; - logic [7:0] arlen; - logic [2:0] arsize; - logic [3:0] arcache; - logic arlock; - logic [2:0] arprot; - logic [3:0] arqos; - logic [3:0] arregion; - - - // -------------------------------------------------------------------- - // - virtual function void set_master_default; - axi4_bus.cb_m.arvalid <= 0; - endfunction: set_master_default - - - // -------------------------------------------------------------------- - // - virtual function void set_slave_default; - axi4_bus.cb_s.arready <= 0; - endfunction: set_slave_default - - - // -------------------------------------------------------------------- - // - virtual function void copy(axi4_channel_if_class #(A, N, I) from); - axi4_ar_if_class #(A, N, I) child; - $cast(child, from); - araddr = child.araddr; - arburst = child.arburst; - arid = child.arid; - arlen = child.arlen; - arsize = child.arsize; - arcache = child.arcache; - arlock = child.arlock; - arprot = child.arprot; - arqos = child.arqos; - arregion = child.arregion; - endfunction: copy - - - // -------------------------------------------------------------------- - // - virtual function void copy_if; - araddr = axi4_bus.cb_s.araddr; - arburst = axi4_bus.cb_s.arburst; - arid = axi4_bus.cb_s.arid; - arlen = axi4_bus.cb_s.arlen; - arsize = axi4_bus.cb_s.arsize; - arcache = axi4_bus.cb_s.arcache; - arlock = axi4_bus.cb_s.arlock; - arprot = axi4_bus.cb_s.arprot; - arqos = axi4_bus.cb_s.arqos; - arregion = axi4_bus.cb_s.arregion; - endfunction: copy_if - - - // -------------------------------------------------------------------- - // - virtual function void drive_if; - axi4_bus.cb_m.araddr <= araddr; - axi4_bus.cb_m.arburst <= arburst; - axi4_bus.cb_m.arid <= arid; - axi4_bus.cb_m.arlen <= arlen; - axi4_bus.cb_m.arsize <= arsize; - axi4_bus.cb_m.arcache <= arcache; - axi4_bus.cb_m.arlock <= arlock; - axi4_bus.cb_m.arprot <= arprot; - axi4_bus.cb_m.arqos <= arqos; - axi4_bus.cb_m.arregion <= arregion; - endfunction: drive_if - - - // -------------------------------------------------------------------- - // - virtual function void set_ready(bit value); - axi4_bus.cb_s.arready <= value; - endfunction: set_ready - - - // -------------------------------------------------------------------- - // - virtual function bit is_valid; - return(axi4_bus.cb_s.arvalid); - endfunction: is_valid - - - // -------------------------------------------------------------------- - // - function void set_valid(bit value); - axi4_bus.cb_m.arvalid <= value; - endfunction: set_valid - - - // -------------------------------------------------------------------- - // - function bit is_ready; - return(axi4_bus.cb_m.arready); - endfunction: is_ready - - - // -------------------------------------------------------------------- - // - function bit is_transfer; - return(axi4_bus.cb_m.arready & axi4_bus.cb_s.arvalid); - endfunction: is_transfer - - - //-------------------------------------------------------------------- - function new(virtual axi4_if #(A, N, I) axi4_bus); - super.new(axi4_bus); - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: axi4_ar_if_class - - - // -------------------------------------------------------------------- - // - class axi4_w_if_class #(A, N, I) - extends axi4_channel_if_class #(A, N, I); - - logic [(8*N)-1:0] wdata; - logic [(I-1):0] wid; - logic wlast; - logic [N-1:0] wstrb; - - - // -------------------------------------------------------------------- - // - function void set_master_default; - axi4_bus.cb_m.wvalid <= 0; - endfunction: set_master_default - - - // -------------------------------------------------------------------- - // - function void set_slave_default; - axi4_bus.cb_s.wready <= 0; - endfunction: set_slave_default - - - // -------------------------------------------------------------------- - // - function void copy(axi4_channel_if_class #(A, N, I) from); - axi4_w_if_class #(A, N, I) child; - $cast(child, from); - wdata = child.wdata; - wid = child.wid; - wlast = child.wlast; - wstrb = child.wstrb; - endfunction: copy - - - // -------------------------------------------------------------------- - // - function void copy_if; - wdata = axi4_bus.cb_s.wdata; - wid = axi4_bus.cb_s.wid; - wlast = axi4_bus.cb_s.wlast; - wstrb = axi4_bus.cb_s.wstrb; - endfunction: copy_if - - - // -------------------------------------------------------------------- - // - function void drive_if; - axi4_bus.cb_m.wdata <= wdata; - axi4_bus.cb_m.wid <= wid; - axi4_bus.cb_m.wlast <= wlast; - axi4_bus.cb_m.wstrb <= wstrb; - endfunction: drive_if - - - // -------------------------------------------------------------------- - // - function void set_ready(bit value); - axi4_bus.cb_s.wready <= value; - endfunction: set_ready - - - // -------------------------------------------------------------------- - // - function bit is_valid; - return(axi4_bus.cb_s.wvalid); - endfunction: is_valid - - - // -------------------------------------------------------------------- - // - function void set_valid(bit value); - axi4_bus.cb_m.wvalid <= value; - endfunction: set_valid - - - // -------------------------------------------------------------------- - // - function bit is_ready; - return(axi4_bus.cb_m.wready); - endfunction: is_ready - - - // -------------------------------------------------------------------- - // - function bit is_transfer; - return(axi4_bus.cb_m.wready & axi4_bus.cb_s.wvalid); - endfunction: is_transfer - - - //-------------------------------------------------------------------- - function new(virtual axi4_if #(A, N, I) axi4_bus); - super.new(axi4_bus); - endfunction: new - - // -------------------------------------------------------------------- - // - endclass: axi4_w_if_class - - - // -------------------------------------------------------------------- - // - class axi4_b_if_class #(A, N, I) - extends axi4_channel_if_class #(A, N, I); - - logic [(I-1):0] bid; - logic [1:0] bresp; - - - // -------------------------------------------------------------------- - // - function void set_master_default; - axi4_bus.cb_m.bready <= 0; - endfunction: set_master_default - - - // -------------------------------------------------------------------- - // - function void set_slave_default; - axi4_bus.cb_s.bvalid <= 0; - endfunction: set_slave_default - - - // -------------------------------------------------------------------- - // - function void copy(axi4_channel_if_class #(A, N, I) from); - axi4_b_if_class #(A, N, I) child; - $cast(child, from); - bid = child.bid; - bresp = child.bresp; - endfunction: copy - - - // -------------------------------------------------------------------- - // - function void copy_if; - bid = axi4_bus.cb_m.bid; - bresp = axi4_bus.cb_m.bresp; - endfunction: copy_if - - - // -------------------------------------------------------------------- - // - function void drive_if; - axi4_bus.cb_s.bid <= bid; - axi4_bus.cb_s.bresp <= bresp; - endfunction: drive_if - - - // -------------------------------------------------------------------- - // - function void set_ready(bit value); - axi4_bus.cb_m.bready <= value; - endfunction: set_ready - - - // -------------------------------------------------------------------- - // - function bit is_valid; - return(axi4_bus.cb_m.bvalid); - endfunction: is_valid - - - // -------------------------------------------------------------------- - // - function void set_valid(bit value); - axi4_bus.cb_s.bvalid <= value; - endfunction: set_valid - - - // -------------------------------------------------------------------- - // - function bit is_ready; - return(axi4_bus.cb_s.bready); - endfunction: is_ready - - - // -------------------------------------------------------------------- - // - function bit is_transfer; - return(axi4_bus.cb_s.bready & axi4_bus.cb_m.bvalid); - endfunction: is_transfer - - - //-------------------------------------------------------------------- - function new(virtual axi4_if #(A, N, I) axi4_bus); - super.new(axi4_bus); - endfunction: new - - // -------------------------------------------------------------------- - // - endclass: axi4_b_if_class - - // -------------------------------------------------------------------- - // - class axi4_r_if_class #(A, N, I) - extends axi4_channel_if_class #(A, N, I); - - logic [(8*N)-1:0] rdata; - logic [(I-1):0] rid; - logic rlast; - logic [1:0] rresp; - - - // -------------------------------------------------------------------- - // - function void set_master_default; - axi4_bus.cb_m.rready <= 0; - endfunction: set_master_default - - - // -------------------------------------------------------------------- - // - function void set_slave_default; - axi4_bus.cb_s.rvalid <= 0; - endfunction: set_slave_default - - - // -------------------------------------------------------------------- - // - function void copy(axi4_channel_if_class #(A, N, I) from); - axi4_r_if_class #(A, N, I) child; - $cast(child, from); - rdata = child.rdata; - rid = child.rid; - rlast = child.rlast; - rresp = child.rresp; - endfunction: copy - - - // -------------------------------------------------------------------- - // - function void copy_if; - rdata = axi4_bus.cb_m.rdata; - rid = axi4_bus.cb_m.rid; - rlast = axi4_bus.cb_m.rlast; - rresp = axi4_bus.cb_m.rresp; - endfunction: copy_if - - - // -------------------------------------------------------------------- - // - function void drive_if; - axi4_bus.cb_s.rdata <= rdata; - axi4_bus.cb_s.rid <= rid; - axi4_bus.cb_s.rlast <= rlast; - axi4_bus.cb_s.rresp <= rresp; - endfunction: drive_if - - - // -------------------------------------------------------------------- - // - function void set_ready(bit value); - axi4_bus.cb_m.rready <= value; - endfunction: set_ready - - - // -------------------------------------------------------------------- - // - function bit is_valid; - return(axi4_bus.cb_m.rvalid); - endfunction: is_valid - - - // -------------------------------------------------------------------- - // - function void set_valid(bit value); - axi4_bus.cb_s.rvalid <= value; - endfunction: set_valid - - - // -------------------------------------------------------------------- - // - function bit is_ready; - return(axi4_bus.cb_s.rready); - endfunction: is_ready - - - // -------------------------------------------------------------------- - // - function bit is_transfer; - return(axi4_bus.cb_s.rready & axi4_bus.cb_m.rvalid); - endfunction: is_transfer - - - //-------------------------------------------------------------------- - function new(virtual axi4_if #(A, N, I) axi4_bus); - super.new(axi4_bus); - endfunction: new - - // -------------------------------------------------------------------- - // - endclass: axi4_r_if_class - - - // -------------------------------------------------------------------- - // - virtual class axi4_master_model_class #(A, N, I); - - virtual axi4_if #(A, N, I) axi4_m; - axi4_aw_if_class #(A, N, I) aw_if_h; - axi4_channel_source_q_class #(A, N, I, axi4_aw_if_class #(A, N, I)) aw_q_h; - axi4_w_if_class #(A, N, I) w_if_h; - axi4_channel_source_q_class #(A, N, I, axi4_w_if_class #(A, N, I)) w_q_h; - axi4_b_if_class #(A, N, I) b_if_h; - axi4_channel_sink_q_class #(A, N, I, axi4_b_if_class #(A, N, I)) b_q_h; - axi4_ar_if_class #(A, N, I) ar_if_h; - axi4_channel_source_q_class #(A, N, I, axi4_ar_if_class #(A, N, I)) ar_q_h; - axi4_r_if_class #(A, N, I) r_if_h; - axi4_channel_sink_q_class #(A, N, I, axi4_r_if_class #(A, N, I)) r_q_h; - - - // -------------------------------------------------------------------- - // - pure virtual task run_model; - - - //-------------------------------------------------------------------- - function new(virtual axi4_if #(A, N, I) axi4_m); - this.axi4_m = axi4_m; - this.aw_if_h = new(axi4_m); - aw_if_h.set_master_default(); - this.w_if_h = new(axi4_m); - w_if_h.set_master_default(); - this.b_if_h = new(axi4_m); - b_if_h.set_master_default(); - this.ar_if_h = new(axi4_m); - ar_if_h.set_master_default(); - this.r_if_h = new(axi4_m); - r_if_h.set_master_default(); - - fork - run_model(); - join_none - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: axi4_master_model_class - - - // -------------------------------------------------------------------- - // - virtual class axi4_slave_model_class #(A, N, I); - - virtual axi4_if #(A, N, I) axi4_s; - axi4_aw_if_class #(A, N, I) aw_if_h; - axi4_channel_sink_q_class #(A, N, I, axi4_aw_if_class #(A, N, I)) aw_q_h; - axi4_w_if_class #(A, N, I) w_if_h; - axi4_channel_sink_q_class #(A, N, I, axi4_w_if_class #(A, N, I)) w_q_h; - axi4_b_if_class #(A, N, I) b_if_h; - axi4_channel_source_q_class #(A, N, I, axi4_b_if_class #(A, N, I)) b_q_h; - axi4_ar_if_class #(A, N, I) ar_if_h; - axi4_channel_sink_q_class #(A, N, I, axi4_ar_if_class #(A, N, I)) ar_q_h; - axi4_r_if_class #(A, N, I) r_if_h; - axi4_channel_source_q_class #(A, N, I, axi4_r_if_class #(A, N, I)) r_q_h; - - - // -------------------------------------------------------------------- - // - pure virtual task run_model; - - - //-------------------------------------------------------------------- - function new(virtual axi4_if #(A, N, I) axi4_s); - - this.axi4_s = axi4_s; - this.aw_if_h = new(axi4_s); - aw_if_h.set_slave_default(); - this.w_if_h = new(axi4_s); - w_if_h.set_slave_default(); - this.b_if_h = new(axi4_s); - b_if_h.set_slave_default(); - this.ar_if_h = new(axi4_s); - ar_if_h.set_slave_default(); - this.r_if_h = new(axi4_s); - r_if_h.set_slave_default(); - - fork - run_model(); - join_none - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: axi4_slave_model_class - - -// -------------------------------------------------------------------- -// -endpackage: axi4_models_pkg - - Index: trunk/axi4_lib/sim/src/legacy/tb_axi4_memory.sv =================================================================== --- trunk/axi4_lib/sim/src/legacy/tb_axi4_memory.sv (nonexistent) +++ trunk/axi4_lib/sim/src/legacy/tb_axi4_memory.sv (revision 50) @@ -0,0 +1,129 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + wire aclk = tb_clk; + wire aresetn = ~tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + localparam A = 32; + localparam N = 8; + + + // -------------------------------------------------------------------- + // + axi4_if #(.A(A), .N(N)) + axi4_s(.*); + + + // -------------------------------------------------------------------- + // + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + // -------------------------------------------------------------------- + // + axi4_checker #(.A(A), .N(N)) + axi4_s_check(.axi4_in(axi4_s)); + + + // // -------------------------------------------------------------------- + // // + // axi4_master_bfm_if #(.A(A), .N(N)) + // tb_axi4_m(.axi4_s(axi4_s), .*); + + + // -------------------------------------------------------------------- + // + import axi4_bfm_pkg::*; + + axi4_master_bfm_class bfm; + + initial + bfm = new(axi4_s); + + + // -------------------------------------------------------------------- + // + import axi4_memory_pkg::*; + + axi4_memory_class axi4_memory; + + initial + axi4_memory = new(axi4_s); + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test( tb_clk, tb_rst ); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: trunk/axi4_lib/sim/src/legacy/tb_axi4_to_axis_agent_class_pkg.sv =================================================================== --- trunk/axi4_lib/sim/src/legacy/tb_axi4_to_axis_agent_class_pkg.sv (nonexistent) +++ trunk/axi4_lib/sim/src/legacy/tb_axi4_to_axis_agent_class_pkg.sv (revision 50) @@ -0,0 +1,130 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +package tb_axi4_to_axis_agent_class_pkg; + + // -------------------------------------------------------------------- + // + import axi4_memory_pkg::*; + import axis_bfm_pkg::*; + + + // -------------------------------------------------------------------- + // + class tb_axi4_to_axis_agent_class #(N, A, I, D, U); + + axi4_memory_class #(A, N, I) m_h; + axis_rx_bfm_class #(N, I, D, U) s_h; + memory_tr_class #(A, N, I) m_tr_h, m_tr_clone_h; + axis_tr_class #(N, I, D, U) s_tr_h; + + virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m; + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out; + + mailbox #(memory_tr_class #(A, N, I)) q; + + + // -------------------------------------------------------------------- + // + task wait_for_sof; + @(posedge axis_out.cb_s.tuser); + $display("^^^ %16.t | %m", $time); + endtask: wait_for_sof + + + // -------------------------------------------------------------------- + // + task random_transaction(int addr, int size); + m_tr_h = new(); + m_tr_h.random(addr, size); + m_tr_clone_h = m_tr_h.clone(); + q.put(m_tr_clone_h); + m_h.load_words(addr, m_tr_h.data); + endtask: random_transaction + + + // -------------------------------------------------------------------- + // + task automatic + compare; + + $display("^^^ %16.t | %m", $time); + $display("^^^ %16.t | q.num = %d", $time, q.num); + $display("^^^ %16.t | s_h.q.num = %d", $time, s_h.q.num); + $display("^^^ %16.t | m_tr_h.data.size = %d", $time, m_tr_h.data.size); + + q.get(m_tr_h); + + for(int i = 0; i < m_tr_h.data.size; i += N) + begin + if(s_h.q.try_get(s_tr_h) == 0) + begin + $display("!!! %16.t | ERROR!!! try_get(s_tr_h) == 0", $time); + break; + end + + for(int k = 0; k < N; k++) + begin + if(s_tr_h.tdata[k*8 +: 8] != m_tr_h.data[i + k]) + begin + $display("!!! %16.t | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^", $time); + $display("!!! %16.t | ERROR!!! mismatch | i = %d | k = %d", $time, i, k); + $display("!!! %16.t | %x | %x |", $time, s_tr_h.tdata[k*8 +: 8], m_tr_h.data[i + k]); + $stop; + end + end + end + + $display("^^^ %16.t | %m | done!", $time); + + endtask: compare + + + //-------------------------------------------------------------------- + // + function new + ( + virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m, + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out + ); + + this.axi4_m = axi4_m; + this.axis_out = axis_out; + m_h = new(axi4_m); + s_h = new(axis_out); + q = new(); + endfunction: new + + + // -------------------------------------------------------------------- + // + endclass: tb_axi4_to_axis_agent_class + +// -------------------------------------------------------------------- +// +endpackage: tb_axi4_to_axis_agent_class_pkg Index: trunk/axi4_lib/sim/src/legacy/tb_bfm.sv =================================================================== --- trunk/axi4_lib/sim/src/legacy/tb_bfm.sv (nonexistent) +++ trunk/axi4_lib/sim/src/legacy/tb_bfm.sv (revision 50) @@ -0,0 +1,119 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + wire aclk = tb_clk; + wire aresetn = ~tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + localparam A = 32; + localparam N = 8; + + + // -------------------------------------------------------------------- + // + axi4_if #(.A(A), .N(N)) + axi4_bus(.*); + + axi4_checker #(.A(A), .N(N)) + axi4_in_check(.axi4_in(axi4_bus)); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + // -------------------------------------------------------------------- + // + import axi4_simple_agent_pkg::*; + + + // -------------------------------------------------------------------- + // + axi4_master_bfm_if #(.A(A), .N(N)) + axi4_m(.axi4_s(axi4_bus), .*); + + axi4_slave_bfm_if #(.A(A), .N(N)) + axi4_s(.axi4_m(axi4_bus), .*); + + + // -------------------------------------------------------------------- + // + axi4_simple_agent_class bfm; + + initial + bfm = new(axi4_m, axi4_s); + + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test( tb_clk, tb_rst ); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: trunk/axi4_lib/sim/src/legacy/tb_register_slice.sv =================================================================== --- trunk/axi4_lib/sim/src/legacy/tb_register_slice.sv (nonexistent) +++ trunk/axi4_lib/sim/src/legacy/tb_register_slice.sv (revision 50) @@ -0,0 +1,133 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + wire aclk = tb_clk; + wire aresetn = ~tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + localparam A = 32; + localparam N = 8; + + + // -------------------------------------------------------------------- + // + axi4_if #(.A(A), .N(N)) + axi4_s(.*); + + axi4_if #(.A(A), .N(N)) + axi4_m(.*); + + + // -------------------------------------------------------------------- + // + axi4_register_slice #(.A(A), .N(N)) + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + // -------------------------------------------------------------------- + // + axi4_checker #(.A(A), .N(N)) + axi4_s_check(.axi4_in(axi4_s)); + + axi4_checker #(.A(A), .N(N)) + axi4_m_check(.axi4_in(axi4_m)); + + + // -------------------------------------------------------------------- + // + import axi4_simple_agent_pkg::*; + + + // -------------------------------------------------------------------- + // + axi4_master_bfm_if #(.A(A), .N(N)) + tb_axi4_m(.axi4_s(axi4_s), .*); + + axi4_slave_bfm_if #(.A(A), .N(N)) + tb_axi4_s(.axi4_m(axi4_m), .*); + + + // -------------------------------------------------------------------- + // + axi4_simple_agent_class bfm; + + initial + bfm = new(tb_axi4_m, tb_axi4_s); + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test( tb_clk, tb_rst ); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: trunk/axi4_stream_lib/syn/src/axis_if.sv =================================================================== --- trunk/axi4_stream_lib/syn/src/axis_if.sv (revision 49) +++ trunk/axi4_stream_lib/syn/src/axis_if.sv (nonexistent) @@ -1,128 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -interface - axis_if - #( - N = 8, // data bus width in bytes - I = 1, // TID width - D = 1, // TDEST width - U = 1 // TUSER width - ) - ( - input aclk, - input aresetn - ); - wire tvalid; - wire tready; - wire [(8*N)-1:0] tdata; - wire [N-1:0] tstrb; - wire [N-1:0] tkeep; - wire tlast; - wire [I-1:0] tid; - wire [D-1:0] tdest; - wire [U-1:0] tuser; - - -// -------------------------------------------------------------------- -// synthesis translate_off - default clocking cb_m @(posedge aclk iff aresetn); - output tvalid; - input tready; - output tdata; - output tstrb; - output tkeep; - output tlast; - output tid; - output tdest; - output tuser; - endclocking - - - // -------------------------------------------------------------------- - // - clocking cb_s @(posedge aclk iff aresetn); - input tvalid; - output tready; - input tdata; - input tstrb; - input tkeep; - input tlast; - input tid; - input tdest; - input tuser; - endclocking - - - // -------------------------------------------------------------------- - // - modport - master - ( - input aresetn, - input aclk, - output tvalid, - input tready, - output tdata, - output tstrb, - output tkeep, - output tlast, - output tid, - output tdest, - output tuser, - clocking cb_m - ); - - - // -------------------------------------------------------------------- - // - modport - slave - ( - input aresetn, - input aclk, - input tvalid, - output tready, - input tdata, - input tstrb, - input tkeep, - input tlast, - input tid, - input tdest, - input tuser, - clocking cb_s - ); - - -// synthesis translate_on -// -------------------------------------------------------------------- - - -endinterface: axis_if - - Index: trunk/axi4_stream_lib/sim/src/axis_bfm_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/src/axis_bfm_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/src/axis_bfm_pkg.sv (nonexistent) @@ -1,220 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package axis_bfm_pkg; - - - // -------------------------------------------------------------------- - // - import q_pkg::*; - import bfm_pkg::*; - - - // -------------------------------------------------------------------- - // - class axis_tr_class #(N, I, D, U) - extends transaction_class #(axis_tr_class #(N, I, D, U)); - - rand logic [(8*N)-1:0] tdata; - rand logic [N-1:0] tstrb; - rand logic [N-1:0] tkeep; - rand logic tlast; - rand logic [I-1:0] tid; - rand logic [D-1:0] tdest; - rand logic [U-1:0] tuser; - - // -------------------------------------------------------------------- - // - function void copy(TR_T from); - // delay_class delay_h; - this.tdata = from.tdata; - this.tstrb = from.tstrb; - this.tkeep = from.tkeep; - this.tlast = from.tlast; - this.tid = from.tid; - this.tdest = from.tdest; - this.tuser = from.tuser; - endfunction: copy - - - // -------------------------------------------------------------------- - // - endclass: axis_tr_class - - - // -------------------------------------------------------------------- - // - class axis_tx_bfm_class #(N, I, D, U) - extends blocking_transmission_q_class #(axis_tr_class #(.N(N), .I(I), .D(D), .U(U))); - - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out; - - - //-------------------------------------------------------------------- - // - function void set_default; - axis_out.cb_m.tvalid <= 0; - axis_out.cb_m.tdata <= 'bx; - axis_out.cb_m.tstrb <= 'bx; - axis_out.cb_m.tkeep <= 'bx; - axis_out.cb_m.tlast <= 'bx; - axis_out.cb_m.tid <= 'bx; - axis_out.cb_m.tdest <= 'bx; - axis_out.cb_m.tuser <= 'bx; - endfunction: set_default - - - //-------------------------------------------------------------------- - // - task tx_transaction(axis_tr_class #(.N(N), .I(I), .D(D), .U(U)) tr_h); - axis_out.zero_cycle_delay(); - repeat(tr_h.delay_h.delay) @(axis_out.cb_m); - - axis_out.cb_m.tvalid <= 1; - axis_out.cb_m.tdata <= tr_h.tdata; - axis_out.cb_m.tstrb <= 0; - axis_out.cb_m.tkeep <= 0; - axis_out.cb_m.tlast <= tr_h.tlast; - axis_out.cb_m.tid <= 0; - axis_out.cb_m.tdest <= 0; - axis_out.cb_m.tuser <= tr_h.tuser; - - @(axis_out.cb_m); - wait(axis_out.cb_m.tready); - // @(axis_out.cb_m iff axis_out.cb_m.tready); - - set_default(); - endtask: tx_transaction - - - // -------------------------------------------------------------------- - // - event tx_done; - - task automatic transmit(ref Q_T tr_h); - tx_transaction(tr_h); - ->tx_done; - endtask: transmit - - - //-------------------------------------------------------------------- - // - task init; - set_default(); - endtask: init - - - //-------------------------------------------------------------------- - // - function new(virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out); - this.axis_out = axis_out; - tr_h = new(); - fork - init(); - join_none - $display("^^^ %16.t | %m", $time); - endfunction: new - - // -------------------------------------------------------------------- - // - endclass: axis_tx_bfm_class - - - // -------------------------------------------------------------------- - // - class axis_rx_bfm_class #(N, I, D, U) - extends blocking_receiver_q_class #(axis_tr_class #(.N(N), .I(I), .D(D), .U(U))); - - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in; - - - //-------------------------------------------------------------------- - // - function void set_tready(bit value); - axis_in.cb_s.tready <= value; - endfunction: set_tready - - - //-------------------------------------------------------------------- - // - task rx_transaction(axis_tr_class #(.N(N), .I(I), .D(D), .U(U)) tr_h); - repeat(tr_h.delay_h.delay) @(axis_in.cb_s); - axis_in.cb_s.tready <= 1; - - @(axis_in.cb_s); - wait(axis_in.cb_s.tvalid); - // @(axis_in.cb_s iff axis_in.cb_s.tvalid); - - tr_h.tdata <= axis_in.cb_s.tdata; - tr_h.tstrb <= axis_in.cb_s.tstrb; - tr_h.tkeep <= axis_in.cb_s.tkeep; - tr_h.tlast <= axis_in.cb_s.tlast; - tr_h.tid <= axis_in.cb_s.tid; - tr_h.tdest <= axis_in.cb_s.tdest; - tr_h.tuser <= axis_in.cb_s.tuser; - - axis_in.cb_s.tready <= 0; - endtask: rx_transaction - - - // -------------------------------------------------------------------- - // - event rx_frame_done; - - virtual task receive(ref Q_T tr_h); - tr_h = new(); - void'(tr_h.delay_h.next()); - rx_transaction(tr_h); - ->rx_frame_done; - endtask: receive - - - //-------------------------------------------------------------------- - // - task init; - set_tready(0); - endtask: init - - - //-------------------------------------------------------------------- - // - function new (virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in); - this.axis_in = axis_in; - fork - init(); - join_none - $display("^^^ %16.t | %m", $time); - endfunction: new - - endclass: axis_rx_bfm_class - - -// -------------------------------------------------------------------- -// -endpackage: axis_bfm_pkg - Index: trunk/axi4_stream_lib/sim/src/tb_axis_register_slice.sv =================================================================== --- trunk/axi4_stream_lib/sim/src/tb_axis_register_slice.sv (revision 49) +++ trunk/axi4_stream_lib/sim/src/tb_axis_register_slice.sv (nonexistent) @@ -1,159 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_200mhz; - wire tb_clk = clk_200mhz; - wire tb_rst; - wire aclk = tb_clk; - wire aresetn = ~tb_rst; - - tb_base #( .PERIOD(5_000) ) tb( clk_200mhz, tb_rst ); - - - // -------------------------------------------------------------------- - // - localparam TILES = 1; - localparam WIDTH = 32; // tile width - localparam HEIGHT = 16; // tile height - localparam OUTPUTS_PER_TILE = 1; // outputs per tile - localparam BYTES_PER_PIXEL = 2; - localparam BITS_PER_PIXEL = 16; - localparam VERTICAL_BLANKING = 20; - - - // -------------------------------------------------------------------- - // - localparam AVF_N = BYTES_PER_PIXEL * OUTPUTS_PER_TILE; // data bus width in bytes - localparam AVF_U = 1; // TUSER width - - axis_if #(.N(AVF_N), .U(AVF_U)) axis_in[TILES](.*); - axis_if #(.N(AVF_N), .U(AVF_U)) axis_out[TILES](.*); - - - // -------------------------------------------------------------------- - // - axis_register_slice #(.N(AVF_N), .U(AVF_U)) - dut - ( - .axis_en(1'b1), - .axis_in(axis_in.slave[0]), - .axis_out(axis_out.master[0]), - .* - ); - - - // -------------------------------------------------------------------- - // - import axis_video_frame_bfm_pkg::*; - import avf_agent_class_pkg::*; - - - // -------------------------------------------------------------------- - // - avf_agent_config_class avf_agent_config_h; - avf_agent_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE) avf_agent_h; - - initial - begin - - avf_agent_config_h = new - ( - .width(WIDTH), - .height(HEIGHT), - .bytes_per_pixel(BYTES_PER_PIXEL), - .bits_per_pixel(BITS_PER_PIXEL), - .tiles(TILES), - .outputs_per_tile(OUTPUTS_PER_TILE), - .name("AVF_"), - .vertical_blanking(VERTICAL_BLANKING) - ); - - avf_agent_config_h.tile[0].direction = RIGHT_DOWN; - - avf_agent_h = new - ( - .avf_agent_config(avf_agent_config_h), - .avf_axis_in_if(axis_out), - .avf_axis_out_if(axis_in) - ); - - avf_agent_h.init(); - - end - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - // -------------------------------------------------------------------- - // - - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - for(genvar j = 0; j < TILES; j++) - axis_video_debug #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE) avf_debug(axis_out[j]); - - - // -------------------------------------------------------------------- - // test - the_test test( tb_clk, tb_rst ); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule - - - Index: trunk/axi4_stream_lib/sim/src/tb_axis_upsizer_agent_class_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/src/tb_axis_upsizer_agent_class_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/src/tb_axis_upsizer_agent_class_pkg.sv (nonexistent) @@ -1,129 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package tb_axis_upsizer_agent_class_pkg; - - // -------------------------------------------------------------------- - // - import video_frame_pkg::*; - import axis_video_frame_bfm_pkg::*; - - - // -------------------------------------------------------------------- - // - class tb_axis_upsizer_agent_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_N, AVF_U, S); - - virtual axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if; - virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if; - - avf_config_class c_h; - - avf_tx_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_U) tx_h; - avf_rx_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE * S, AVF_U) rx_h; - - video_frame_class clone_h; - video_frame_class sent_f_h; - video_frame_class rx_f_h; - - mailbox #(video_frame_class) q; - - - // -------------------------------------------------------------------- - // - virtual task - queue_frame - ( - string pattern = "", - int pixel = 0 - ); - - if(pattern != "") - tx_h.make_frame(pattern, pixel); - - clone_h = tx_h.tx_bfm_h[0].f_h.clone(); - tx_h.tx_bfm_h[0].put(clone_h); - q.put(clone_h); - - $display("^^^ %16.t | %m | using %s pattern", $time, pattern); - - endtask: queue_frame - - - // -------------------------------------------------------------------- - // - virtual task automatic - compare_frame; - - int mismatch_count; - - $display("^^^ %16.t | %m", $time); - - q.get(sent_f_h); - rx_h.rx_bfm_h[0].get(rx_f_h); - mismatch_count = sent_f_h.compare(8, rx_f_h); - - endtask: compare_frame - - - //-------------------------------------------------------------------- - // - function void init(avf_config_class in_c_h, avf_config_class out_c_h); - - rx_h = new(in_c_h, '{avf_axis_in_if}); - tx_h = new(out_c_h, '{avf_axis_out_if}); - - this.q = new(); - - endfunction: init - - - //-------------------------------------------------------------------- - // - function new - ( - virtual axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if, - virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if - ); - - this.avf_axis_in_if = avf_axis_in_if; - this.avf_axis_out_if = avf_axis_out_if; - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: tb_axis_upsizer_agent_class - -// -------------------------------------------------------------------- -// -endpackage: tb_axis_upsizer_agent_class_pkg - - - - - Index: trunk/axi4_stream_lib/sim/src/tb_axis_upsizer_class_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/src/tb_axis_upsizer_class_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/src/tb_axis_upsizer_class_pkg.sv (nonexistent) @@ -1,114 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package tb_axis_upsizer_class_pkg; - - // -------------------------------------------------------------------- - // - import axis_video_frame_bfm_pkg::*; - import tb_axis_upsizer_agent_class_pkg::*; - - - // -------------------------------------------------------------------- - // - localparam WIDTH = 32; // tile width - localparam HEIGHT = 16; // tile height - localparam OUTPUTS_PER_TILE = 1; // outputs per tile - localparam BYTES_PER_PIXEL = 2; - localparam BITS_PER_PIXEL = 16; - localparam VERTICAL_BLANKING = 20; - - localparam S = 4; // tdata size multiplier - localparam AVF_N = BYTES_PER_PIXEL * OUTPUTS_PER_TILE; // data bus width in bytes - localparam AVF_U = 3; // TUSER width - - - // -------------------------------------------------------------------- - // - class tb_axis_upsizer_class - extends tb_axis_upsizer_agent_class #(BYTES_PER_PIXEL, OUTPUTS_PER_TILE, AVF_N, AVF_U, S); - - avf_config_class in_c_h; - avf_config_class out_c_h; - avf_tile_config_t tile_config[]; - - - //-------------------------------------------------------------------- - // - function new - ( - virtual axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if, - virtual axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis_out_if - ); - - super.new(avf_axis_in_if, avf_axis_out_if); - - this.tile_config = new[1]; - this.tile_config[0].direction = RIGHT_DOWN; - - this.in_c_h = new - ( - .width(WIDTH), - .height(HEIGHT), - .bytes_per_pixel(BYTES_PER_PIXEL), - .bits_per_pixel(BITS_PER_PIXEL), - .pixels_per_clk(OUTPUTS_PER_TILE * S), - .name("IN_"), - .vertical_blanking(VERTICAL_BLANKING), - .tile(tile_config) - ); - - this.out_c_h = new - ( - .width(WIDTH), - .height(HEIGHT), - .bytes_per_pixel(BYTES_PER_PIXEL), - .bits_per_pixel(BITS_PER_PIXEL), - .pixels_per_clk(OUTPUTS_PER_TILE), - .name("OUT_"), - .vertical_blanking(VERTICAL_BLANKING), - .tile(tile_config) - ); - - super.init(in_c_h, out_c_h); - - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: tb_axis_upsizer_class - -// -------------------------------------------------------------------- -// -endpackage: tb_axis_upsizer_class_pkg - - - - - Index: trunk/axi4_stream_lib/sim/src/tb_axis_to_axi4_agent_class_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/src/tb_axis_to_axi4_agent_class_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/src/tb_axis_to_axi4_agent_class_pkg.sv (nonexistent) @@ -1,158 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package tb_axis_to_axi4_agent_class_pkg; - - // -------------------------------------------------------------------- - // - import axi4_memory_pkg::*; - import axis_bfm_pkg::*; - - - // -------------------------------------------------------------------- - // - class tb_axis_to_axi4_agent_class #(N, A, I, D, U); - - axi4_memory_class #(A, N, I) m_h; - axis_tx_bfm_class #(N, I, D, U) s_h; - memory_tr_class #(A, N, I) m_tr_h; - axis_tr_class #(N, I, D, U) s_tr_h; - - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m; - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in; - - mailbox #(memory_tr_class #(A, N, I)) q; - - - // -------------------------------------------------------------------- - // - task wait_for_sof; - @(posedge axis_in.cb_s.tuser); - $display("^^^ %16.t | %m", $time); - endtask: wait_for_sof - - - // -------------------------------------------------------------------- - // - task wait_for_dma_done(int bvalid_count); - repeat(bvalid_count) - @(axi4_m.cb_s iff axi4_m.cb_m.bvalid & axi4_m.cb_s.bready); - $display("^^^ %16.t | %m", $time); - endtask: wait_for_dma_done - - - // -------------------------------------------------------------------- - // - task random_transaction(int addr, int size, int stride); - m_h.clear_all(); - m_tr_h = new(); - m_tr_h.random(addr, size); - q.put(m_tr_h); - - $display("^^^ %16.t | %m | m_tr_h.data.size = %x", $time, m_tr_h.data.size); - for(int i = 0; i < m_tr_h.data.size; i += N) - begin - s_tr_h = new(); - for(int k = 0; k < N; k++) - begin - s_tr_h.tdata[k*8 +: 8] = m_tr_h.data[i + k]; - end - - if(i == 0) - s_tr_h.tuser = 'b1; - else - s_tr_h.tuser = 'b0; - - if(i + N < m_tr_h.data.size) - s_tr_h.tlast = 1'b0; - else - s_tr_h.tlast = 1'b1; - - s_h.q.put(s_tr_h); - end - - wait_for_dma_done(size / stride); - endtask: random_transaction - - - // -------------------------------------------------------------------- - // - task automatic compare(int offset); - byte data[]; - - $display("^^^ %16.t | %m", $time); - $display("^^^ %16.t | q.num = %d", $time, q.num); - $display("^^^ %16.t | s_h.q.num = %d", $time, s_h.q.num); - $display("^^^ %16.t | m_tr_h.data.size = %d", $time, m_tr_h.data.size); - - if(q.try_get(m_tr_h) == 0) - begin - $display("!!! %16.t | ERROR!!! try_get(m_tr_h) == 0", $time); - $stop; - end - - data = new[m_tr_h.data.size]; - m_h.dump_words(offset, data); - - foreach(m_tr_h.data[i]) - if(data[i] != m_tr_h.data[i]) - begin - $display("!!! %16.t | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^", $time); - $display("!!! %16.t | %x ", $time, i); - $display("!!! %16.t | %x | %x |", $time, data[i], m_tr_h.data[i]); - $stop; - end - - $display("^^^ %16.t | %m | done!", $time); - - endtask: compare - - - //-------------------------------------------------------------------- - // - function new - ( - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m, - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in - ); - - this.axi4_m = axi4_m; - this.axis_in = axis_in; - m_h = new(axi4_m); - s_h = new(axis_in); - q = new(); - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: tb_axis_to_axi4_agent_class - -// -------------------------------------------------------------------- -// -endpackage: tb_axis_to_axi4_agent_class_pkg Index: trunk/axi4_stream_lib/sim/src/tb_axis_upsizer.sv =================================================================== --- trunk/axi4_stream_lib/sim/src/tb_axis_upsizer.sv (revision 49) +++ trunk/axi4_stream_lib/sim/src/tb_axis_upsizer.sv (nonexistent) @@ -1,144 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_200mhz; - wire tb_clk = clk_200mhz; - wire tb_rst; - - tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); - - - // -------------------------------------------------------------------- - // - wire tb_rst_s; - wire aclk = tb_clk; - wire aresetn = ~tb_rst_s; - - sync_reset - sync_reset_i(aclk, tb_rst, tb_rst_s); - - - // -------------------------------------------------------------------- - // - import tb_axis_upsizer_class_pkg::*; - - - // -------------------------------------------------------------------- - // - axis_if #(.N(AVF_N), .U(AVF_U)) axis_in(.*); - axis_if #(.N(AVF_N * S), .U(AVF_U * S)) axis_out(.*); - - - // -------------------------------------------------------------------- - // - axis_upsizer - #( - .N(AVF_N), // data bus width in bytes - .I(1), // TID width - .D(1), // TDEST width - .U(AVF_U), // TUSER width - .S(S), // tdata size multiplier - .USE_TSTRB(0), // set to 1 to enable, 0 to disable - .USE_TKEEP(0), // set to 1 to enable, 0 to disable - .BYTES_PER_TUSER(0) // bytes per tuser bit. Set to 0 for transfer based. - ) - dut(.*); - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - // -------------------------------------------------------------------- - // - axis_checker #(.N(AVF_N * S), .I(1), .D(1), .U(AVF_U)) - axis_checker_i(.*); - - - // -------------------------------------------------------------------- - // - axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if(.*); - - assign axis_out.tready = avf_axis_in_if.tready; - assign avf_axis_in_if.tvalid = axis_out.tvalid; - assign avf_axis_in_if.tdata = axis_out.tdata; - assign avf_axis_in_if.tuser = {axis_out.tuser[(AVF_U*S)-1], axis_out.tuser[1:0]}; - assign avf_axis_in_if.tlast = axis_out.tlast; - - - // -------------------------------------------------------------------- - // - tb_axis_upsizer_class a_h; - - initial - a_h = new(.avf_axis_in_if(avf_axis_in_if), .avf_axis_out_if(axis_in)); - - - // -------------------------------------------------------------------- - // - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - - - // -------------------------------------------------------------------- - // test - the_test test( tb_clk, tb_rst ); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule - - - Index: trunk/axi4_stream_lib/sim/tests/defparam_test_case.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/axi4_stream_lib/sim/tests/defparam_test_case.zip =================================================================== --- trunk/axi4_stream_lib/sim/tests/defparam_test_case.zip (revision 49) +++ trunk/axi4_stream_lib/sim/tests/defparam_test_case.zip (nonexistent)
trunk/axi4_stream_lib/sim/tests/defparam_test_case.zip Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/wip.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/wip.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/wip.do (nonexistent) @@ -1,11 +0,0 @@ -# - -# compile simulation files -vlog -f ./$env(SIM_TB).f - -vlog ./$env(SIM_TB)_pkg.sv -vlog ./tests_pkg.sv - -# simulation $root -vlog ./$env(SIM_TB).sv - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/init_test.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/init_test.do (nonexistent) @@ -1,42 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -# setup environment -do ../../../../scripts/sim_env.do -set env(SIM_TARGET) fpga -set env(SIM_TB) tb_axis_gear_box - -radix -hexadecimal - -make_lib work 1 - -sim_compile_lib $env(LIB_BASE_DIR) tb_packages -sim_compile_lib $env(LIB_BASE_DIR) bfm_packages -sim_compile_lib $env(LIB_BASE_DIR) axi4_lib -sim_compile_lib $env(LIB_BASE_DIR) qaz_lib -sim_compile_lib $env(LIB_BASE_DIR) sim - -# AXI4 streaming package -vlog ./axis_pkg.sv - -vlog ./$env(SIM_TB)_pkg.sv -vlog ./tests_base_pkg.sv -vlog ./tests_pkg.sv -vlog ./tb_dut_if.sv - -# simulation $root -vlog ./$env(SIM_TB).sv - -# compile simulation files -vlog -f ./$env(SIM_TB).f - -# # compile test last -# vlog ./the_test.sv - -# run the sim -sim_run_test - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box.f (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box.f (nonexistent) @@ -1,6 +0,0 @@ -# - -./axis_pkg.sv - -${PROJECT_DIR}/src/axis_gear_box.sv - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tests_base_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tests_base_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tests_base_pkg.sv (nonexistent) @@ -1,85 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -// -------------------------------------------------------------------- -// -package tests_base_pkg; - - // -------------------------------------------------------------------- - // - import uvm_pkg::*; - `include "uvm_macros.svh" - import tb_axis_gear_box_pkg::*; - - // -------------------------------------------------------------------- - // - virtual class test_base extends uvm_test; - `uvm_component_utils(test_base); - tb_env env_h; - - // -------------------------------------------------------------------- - // - function void build_phase(uvm_phase phase); - env_h = tb_env::type_id::create("env_h",this); - endfunction : build_phase - - // -------------------------------------------------------------------- - // - function new (string name, uvm_component parent); - super.new(name,parent); - endfunction : new - - // -------------------------------------------------------------------- - // - endclass : test_base - - // -------------------------------------------------------------------- - // - class test_debug_base extends test_base; - `uvm_component_utils(test_debug_base) - - // -------------------------------------------------------------------- - // - function new (string name, uvm_component parent); - super.new(name,parent); - endfunction : new - - // -------------------------------------------------------------------- - // - function void final_phase(uvm_phase phase); - super.final_phase(phase); - $display("^^^ %16.t | %m | Test Done!!!", $time); - $stop; - endfunction : final_phase - - // -------------------------------------------------------------------- - // - endclass : test_debug_base - -// -------------------------------------------------------------------- -// -endpackage: tests_base_pkg Index: trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_dut_if.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_dut_if.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_dut_if.sv (nonexistent) @@ -1,63 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -import tb_axis_gear_box_pkg::*; - -interface - tb_dut_if #(dut_config_t dut_cfg) - ( - input aclk, - input aresetn - ); - - // -------------------------------------------------------------------- - // - axis_if - #( - .N(dut_cfg.axis_cfg_in.N), - .I(dut_cfg.axis_cfg_in.I), - .D(dut_cfg.axis_cfg_in.D), - .U(dut_cfg.axis_cfg_in.U) - ) - axis_in(.*); - - // -------------------------------------------------------------------- - // - axis_if - #( - .N(dut_cfg.axis_cfg_out.N), - .I(dut_cfg.axis_cfg_out.I), - .D(dut_cfg.axis_cfg_out.D), - .U(dut_cfg.axis_cfg_out.U) - ) - axis_out(.*); - -// -------------------------------------------------------------------- -// -endinterface: tb_dut_if - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box.sv (nonexistent) @@ -1,90 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// ---------------------------------------------------------------------------- - -import tb_axis_gear_box_pkg::*; -import tests_pkg::*; -import uvm_pkg::*; -`include "uvm_macros.svh" - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_100mhz; - wire tb_clk = clk_100mhz; - wire tb_rst; - - tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); - - // -------------------------------------------------------------------- - // - wire tb_rst_s; - wire aclk = tb_clk; - wire aresetn = ~tb_rst_s; - wire clk = tb_clk; - wire reset = tb_rst_s; - - sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); - - // -------------------------------------------------------------------- - // - import tb_axis_gear_box_pkg::*; - - // -------------------------------------------------------------------- - // - tb_dut_if #(dut_cfg) dut_bus(.*); - - // -------------------------------------------------------------------- - // - axis_gear_box - dut - ( - .axis_in(dut_bus.axis_in), - .axis_out(dut_bus.axis_out), - .aclk(dut_bus.aclk), - .aresetn(dut_bus.aresetn) - ); - - // -------------------------------------------------------------------- - // - assign dut_bus.axis_out.tready = 1; - - // -------------------------------------------------------------------- - // - tb_dut_config #(dut_cfg) cfg_h; - - initial - begin - cfg_h = new(dut_bus); - uvm_config_db #(tb_dut_config #(dut_cfg))::set(null, "*env_h", "tb_dut_config", cfg_h); - run_test("t_debug"); - end - -// -------------------------------------------------------------------- -// -endmodule Index: trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tb_axis_gear_box_pkg.sv (nonexistent) @@ -1,139 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -package tb_axis_gear_box_pkg; - - // -------------------------------------------------------------------- - // - import uvm_pkg::*; - `include "uvm_macros.svh" - import axis_pkg::*; - - // -------------------------------------------------------------------- - // - typedef struct - { - axis_config_t axis_cfg_in; - axis_config_t axis_cfg_out; - } dut_config_t; - - localparam dut_config_t dut_cfg = - '{ - '{ N : 2 // data bus width in bytes. - , I : 1 // TID width - , D : 1 // TDEST width - , U : 1 // TUSER width - , USE_TSTRB : 0 - , USE_TKEEP : 0 - , USE_ROUTING : 0 - }, - '{ N : 2 // data bus width in bytes. - , I : 1 // TID width - , D : 1 // TDEST width - , U : 1 // TUSER width - , USE_TSTRB : 0 - , USE_TKEEP : 0 - , USE_ROUTING : 0 - } - }; - - // -------------------------------------------------------------------- - // - class tb_dut_config #(dut_config_t dut_cfg); - - virtual tb_dut_if #(dut_cfg) dut_bus; - - // -------------------------------------------------------------------- - // - function new(virtual tb_dut_if #(dut_cfg) dut_bus); - this.dut_bus = dut_bus; - endfunction : new - - // -------------------------------------------------------------------- - // - endclass : tb_dut_config - - // -------------------------------------------------------------------- - // - class tb_env extends uvm_env; - `uvm_component_utils(tb_env); - - // -------------------------------------------------------------------- - // - // coverage coverage_h; - // scoreboard scoreboard_h; - axis_agent #(dut_cfg.axis_cfg_in) agent_h; - - // -------------------------------------------------------------------- - // - function new (string name, uvm_component parent); - super.new(name,parent); - endfunction : new - - // -------------------------------------------------------------------- - // - function void build_phase(uvm_phase phase); - tb_dut_config #(dut_cfg) cfg_h; - if (!uvm_config_db#(tb_dut_config #(dut_cfg))::get(this, "", "tb_dut_config", cfg_h)) - `uvm_fatal(get_name(), "Couldn't get config object!") - - uvm_config_db - #( - virtual axis_if - #( .N(dut_cfg.axis_cfg_in.N) - , .I(dut_cfg.axis_cfg_in.I) - , .D(dut_cfg.axis_cfg_in.D) - , .U(dut_cfg.axis_cfg_in.U) - ) - )::set(this, "*agent_h", "axis_bus", cfg_h.dut_bus.axis_in); - - // // analysis - // coverage_h = coverage::type_id::create ("coverage_h",this); - // scoreboard_h = scoreboard::type_id::create("scoreboard",this); - - agent_h = axis_agent #(dut_cfg.axis_cfg_in)::type_id::create("agent_h", this); - - endfunction : build_phase - - // // -------------------------------------------------------------------- - // // - // function void connect_phase(uvm_phase phase); - - // endfunction : connect_phase - -// -------------------------------------------------------------------- -// -endclass : tb_env - -// -------------------------------------------------------------------- -// -endpackage: tb_axis_gear_box_pkg - - - - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/sim.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/sim.do (nonexistent) @@ -1,11 +0,0 @@ -# -# - -quit -sim - -vsim -novopt work.tb_top -# vsim -f ./sim.f work.tb_top - -# # log all signals -# log -r * - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tests_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tests_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/tests_pkg.sv (nonexistent) @@ -1,196 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -// -------------------------------------------------------------------- -// -package tests_pkg; - - // -------------------------------------------------------------------- - // - import uvm_pkg::*; - `include "uvm_macros.svh" - import axis_pkg::*; - import tb_axis_gear_box_pkg::*; - import tests_base_pkg::*; - - // -------------------------------------------------------------------- - // - class t_counting extends test_base; - `uvm_component_utils(t_counting) - - // -------------------------------------------------------------------- - // - function new(string name = "my_test", uvm_component parent); - super.new(name, parent); - endfunction - - // -------------------------------------------------------------------- - // - virtual function void end_of_elaboration_phase(uvm_phase phase); - uvm_phase run_phase = uvm_run_phase::get(); - run_phase.phase_done.set_drain_time(this, 300ns); - endfunction - - // -------------------------------------------------------------------- - // - virtual task run_phase(uvm_phase phase); - axis_counting_sequence #(dut_cfg.axis_cfg_in) seq_h; - super.run_phase(phase); - phase.raise_objection(this); - fork - repeat(3) - begin - seq_h = axis_counting_sequence #(dut_cfg.axis_cfg_in)::type_id::create("seq_h"); - seq_h.start(env_h.agent_h.sequencer); - end - join - phase.drop_objection(this); - endtask : run_phase - - // -------------------------------------------------------------------- - // - endclass : t_counting - // -------------------------------------------------------------------- - // - - // -------------------------------------------------------------------- - // - class gear_box_sequence #(dut_config_t dut_cfg) - extends uvm_sequence #(axis_sequence_item #(dut_cfg.axis_cfg_in)); - `uvm_object_param_utils(gear_box_sequence #(dut_cfg)) - - rand int length = 7 * 3; - - // -------------------------------------------------------------------- - // - typedef logic [15:0] packed_data_t[7]; - - function packed_data_t next_data(int init); - static logic [15:0] previous_value; - logic [13:0] unpacked_data[8]; - logic [15:0] packed_data[7]; - - if(init == 0) - previous_value = 0; - - foreach(unpacked_data[i]) - begin - unpacked_data[i] = previous_value; - // $display("^^^ %16.t | unpacked_data[%0.d] = %h", $time, i, unpacked_data[i]); - previous_value++; - end - - packed_data = {<<16{{<<14{unpacked_data}}}}; - - // $display("^^^ %16.t | %p", $time, packed_data); - - // foreach(packed_data[i]) - // $display("^^^ %16.t | packed_data[%0.d] = %h", $time, i, packed_data[i]); - - next_data = packed_data; - endfunction - - - // -------------------------------------------------------------------- - // - virtual task body(); - localparam CHUNKS = 3; - axis_sequence_item #(dut_cfg.axis_cfg_in) item; - logic [15:0] data[7]; - - item = axis_sequence_item #(dut_cfg.axis_cfg_in)::type_id::create("axis_sequence_item"); - - for(int i = 0; i < CHUNKS; i++) - begin - data = next_data(i); - - foreach(data[k]) - begin - start_item(item); - item.tdata = data[k]; - item.tlast = (i == CHUNKS - 1) & (k == 0); - item.tuser = 0; - finish_item(item); - // $display("^^^ %16.t | %d | %x", $time, (i * 7) + k, item.tdata); - end - end - - endtask - - // -------------------------------------------------------------------- - // - function new(string name = "gear_box_sequence"); - super.new(name); - endfunction - - // -------------------------------------------------------------------- - // - endclass : gear_box_sequence - - // -------------------------------------------------------------------- - // - class t_debug extends test_debug_base; - `uvm_component_utils(t_debug) - - // -------------------------------------------------------------------- - // - function new(string name = "t_debug", uvm_component parent); - super.new(name, parent); - endfunction - - // -------------------------------------------------------------------- - // - function void end_of_elaboration_phase(uvm_phase phase); - uvm_phase run_phase = uvm_run_phase::get(); - run_phase.phase_done.set_drain_time(this, 300ns); - endfunction - - // -------------------------------------------------------------------- - // - virtual task run_phase(uvm_phase phase); - gear_box_sequence #(dut_cfg) seq_h; - super.run_phase(phase); - phase.raise_objection(this); - - fork - repeat(3) - begin - seq_h = gear_box_sequence #(dut_cfg)::type_id::create("seq_h"); - seq_h.start(env_h.agent_h.sequencer); - end - join - - phase.drop_objection(this); - endtask : run_phase - - // -------------------------------------------------------------------- - // - endclass : t_debug - -// -------------------------------------------------------------------- -// -endpackage: tests_pkg Index: trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/axis_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/axis_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_gear_box/axis_pkg.sv (nonexistent) @@ -1,328 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -// -------------------------------------------------------------------- -// -package axis_pkg; - - // -------------------------------------------------------------------- - // - import uvm_pkg::*; - `include "uvm_macros.svh" - import bfm_pkg::*; - - // -------------------------------------------------------------------- - // - typedef struct - { - int unsigned N; // data bus width in bytes - int unsigned I; // TID width - int unsigned D; // TDEST width - int unsigned U; // TUSER width - bit USE_TSTRB; // set to 1 to enable, 0 to disable - bit USE_TKEEP; // set to 1 to enable, 0 to disable - bit USE_ROUTING; // set to 1 to enable, 0 to disable - } axis_config_t; - - // -------------------------------------------------------------------- - // - class axis_sequence_item #(axis_config_t cfg) - extends uvm_sequence_item; - `uvm_object_param_utils(axis_sequence_item #(cfg)) - - // -------------------------------------------------------------------- - // - localparam N = cfg.N; - localparam I = cfg.I; - localparam D = cfg.D; - localparam U = cfg.U; - localparam USE_TSTRB = cfg.USE_TSTRB; - localparam USE_TKEEP = cfg.USE_TKEEP; - localparam USE_ROUTING = cfg.USE_ROUTING; - - // -------------------------------------------------------------------- - // - delay_class delay_h; - rand logic [(8*N)-1:0] tdata; - rand logic [N-1:0] tstrb; - rand logic [N-1:0] tkeep; - rand logic tlast; - rand logic [I-1:0] tid; - rand logic [D-1:0] tdest; - rand logic [U-1:0] tuser; - - // -------------------------------------------------------------------- - // - function new(string name = ""); - super.new(name); - delay_h = new; - endfunction : new - - // -------------------------------------------------------------------- - // - function bit do_compare(uvm_object rhs, uvm_comparer comparer); - axis_sequence_item #(cfg) tested; - bit same; - - if (rhs==null) - `uvm_fatal(get_type_name(), "| %m | comparison to a null pointer"); - - if (!$cast(tested,rhs)) - same = 0; - else - same = super.do_compare(rhs, comparer) - & (tested.tdata == tdata) - & (USE_TSTRB ? (tested.tstrb == tstrb) : 1) - & (USE_TKEEP ? (tested.tkeep == tkeep) : 1) - & (tested.tlast == tlast) - & (USE_ROUTING ? (tested.tid == tid) : 1) - & (USE_ROUTING ? (tested.tdest == tdest) : 1) - & (tested.tuser == tuser); - return same; - endfunction : do_compare - - // -------------------------------------------------------------------- - // - function void do_copy(uvm_object rhs); - axis_sequence_item #(cfg) item; - assert(rhs != null) else - `uvm_fatal(get_type_name(), "| %m | copy null transaction"); - super.do_copy(rhs); - assert($cast(item,rhs)) else - `uvm_fatal(get_type_name(), "| %m | failed cast"); - tdata = item.tdata; - tstrb = item.tstrb; - tkeep = item.tkeep; - tlast = item.tlast; - tid = item.tid; - tdest = item.tdest; - tuser = item.tuser; - endfunction : do_copy - - // -------------------------------------------------------------------- - // - function string convert2string(); - string s0, s1; - s0 = $sformatf("| tdata: %h\n" ,tdata); - s1 = $sformatf("| tlast: %1h | tuser: %h" , tlast, tuser); - return {s1, s0}; - endfunction : convert2string - - // -------------------------------------------------------------------- - // - endclass : axis_sequence_item - - // -------------------------------------------------------------------- - // - class axis_driver #(parameter axis_config_t cfg) - extends uvm_driver #(axis_sequence_item #(cfg)); - `uvm_component_param_utils(axis_driver#(cfg)) - - // -------------------------------------------------------------------- - // - localparam N = cfg.N; - localparam I = cfg.I; - localparam D = cfg.D; - localparam U = cfg.U; - localparam USE_TSTRB = cfg.USE_TSTRB; - localparam USE_TKEEP = cfg.USE_TKEEP; - localparam USE_ROUTING = cfg.USE_ROUTING; - - // -------------------------------------------------------------------- - // - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus; - - //-------------------------------------------------------------------- - // - function void set_default; - axis_bus.cb_m.tvalid <= 0; - axis_bus.cb_m.tdata <= 'bx; - axis_bus.cb_m.tstrb <= 'bx; - axis_bus.cb_m.tkeep <= 'bx; - axis_bus.cb_m.tlast <= 'bx; - axis_bus.cb_m.tid <= 'bx; - axis_bus.cb_m.tdest <= 'bx; - axis_bus.cb_m.tuser <= 'bx; - endfunction: set_default - - //-------------------------------------------------------------------- - // - virtual task run_phase(uvm_phase phase); - axis_sequence_item #(cfg) item; - super.run_phase(phase); - - set_default(); - wait(~axis_bus.aresetn); - @(axis_bus.cb_m); - - forever - begin - // seq_item_port.try_next_item(item); - seq_item_port.get_next_item(item); - - axis_bus.cb_m.tvalid <= 1; - axis_bus.cb_m.tdata <= item.tdata; - axis_bus.cb_m.tstrb <= 0; - axis_bus.cb_m.tkeep <= 0; - axis_bus.cb_m.tlast <= item.tlast; - axis_bus.cb_m.tid <= 0; - axis_bus.cb_m.tdest <= 0; - axis_bus.cb_m.tuser <= item.tuser; - - @(axis_bus.cb_m); - wait(axis_bus.cb_m.tready); - // @(axis_bus.cb_m iff axis_bus.cb_m.tready); - - set_default(); - repeat(item.delay_h.next()) @(axis_bus.cb_m); - - seq_item_port.item_done(); - end - endtask : run_phase - - //-------------------------------------------------------------------- - // - function new(string name, uvm_component parent); - super.new(name, parent); - endfunction - - // -------------------------------------------------------------------- - // - endclass : axis_driver - - // -------------------------------------------------------------------- - // - class axis_sequencer #(axis_config_t cfg) - extends uvm_sequencer #(axis_sequence_item #(cfg)); - `uvm_component_param_utils(axis_sequencer #(cfg)) - - // -------------------------------------------------------------------- - // - function new(string name, uvm_component parent); - super.new(name, parent); - endfunction - - // -------------------------------------------------------------------- - // - endclass : axis_sequencer - - // -------------------------------------------------------------------- - // - class axis_counting_sequence #(axis_config_t cfg) - extends uvm_sequence #(axis_sequence_item #(cfg)); - `uvm_object_param_utils(axis_counting_sequence #(cfg)) - - rand int length = 16; - - // -------------------------------------------------------------------- - // - virtual task body(); - axis_sequence_item #(cfg) item; - - for(int i = 0; i < length; i++) - begin - item = axis_sequence_item #(cfg)::type_id::create("axis_sequence_item"); - - item.tdata = i; - item.tlast = (i == length - 1); - - start_item (item); - finish_item(item); - end - endtask - - // -------------------------------------------------------------------- - // - function new(string name = "axis_counting_sequence"); - super.new(name); - endfunction - - // -------------------------------------------------------------------- - // - endclass : axis_counting_sequence - - // -------------------------------------------------------------------- - // - class axis_agent #(axis_config_t cfg) - extends uvm_agent; - `uvm_component_param_utils(axis_agent #(cfg)) - - // -------------------------------------------------------------------- - // - localparam N = cfg.N; - localparam I = cfg.I; - localparam D = cfg.D; - localparam U = cfg.U; - localparam USE_TSTRB = cfg.USE_TSTRB; - localparam USE_TKEEP = cfg.USE_TKEEP; - localparam USE_ROUTING = cfg.USE_ROUTING; - - // -------------------------------------------------------------------- - // - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus; - - axis_driver #(cfg) driver; - // my_monitor #(cfg) monitor; - axis_sequencer #(cfg) sequencer; - - // -------------------------------------------------------------------- - // - virtual function void build_phase(uvm_phase phase); - super.build_phase(phase); - - if(!uvm_config_db #(virtual axis_if #(.N(N), .I(I), .D(D), .U(U)))::get(this, "", "axis_bus", axis_bus)) - `uvm_fatal(get_name(), "Couldn't get virtual interface!") - - driver = axis_driver #(cfg)::type_id::create("driver", this); - // monitor = my_monitor #(cfg)::type_id::create("monitor" , this); - sequencer = axis_sequencer #(cfg)::type_id::create("sequencer", this); - endfunction - - // -------------------------------------------------------------------- - // - virtual function void connect_phase(uvm_phase phase); - super.connect_phase(phase); - - driver.axis_bus = axis_bus; - // monitor.vif = vif; - - driver.seq_item_port.connect(sequencer.seq_item_export); - endfunction - - // -------------------------------------------------------------------- - // - function new(string name, uvm_component parent); - super.new(name, parent); - endfunction - - // -------------------------------------------------------------------- - // - endclass : axis_agent - -// -------------------------------------------------------------------- -// -endpackage: axis_pkg Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/init_test.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/init_test.do (nonexistent) @@ -1,35 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -# setup environment -do ../../../../scripts/sim_env.do -set env(SIM_TARGET) fpga -set env(SIM_TB) tb_recursive_axis_switch - -radix -hexadecimal - -make_lib work 1 - -sim_compile_lib $env(LIB_BASE_DIR) tb_packages -sim_compile_lib $env(LIB_BASE_DIR) bfm_packages -sim_compile_lib $env(LIB_BASE_DIR) axi4_lib -sim_compile_lib $env(LIB_BASE_DIR) qaz_lib -sim_compile_lib $env(LIB_BASE_DIR) sim - -# compile simulation files -vlog -f ./$env(SIM_TB).f - -# simulation $root -vlog ./$env(SIM_TB)_pkg.sv -vlog ./$env(SIM_TB).sv - -# compile test last -vlog ./the_test.sv - -# run the sim -sim_run_test - - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.f (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.f (nonexistent) @@ -1,5 +0,0 @@ -# - -${PROJECT_DIR}/src/axis_switch.sv -${PROJECT_DIR}/src/recursive_axis_switch.sv - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/the_test.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/the_test.sv (nonexistent) @@ -1,86 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - - -module the_test(input tb_clk, input tb_rst); - - // -------------------------------------------------------------------- - // - import tb_recursive_axis_switch_pkg::*; - - // -------------------------------------------------------------------- - // - int i = 0; - - task automatic run_the_test; - - // -------------------------------------------------------------------- - // insert test below - // -------------------------------------------------------------------- - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench begun.", $time); - $display("^^^---------------------------------"); - - // -------------------------------------------------------------------- - tb_top.tb.timeout_stop(2ms); - wait(~tb_rst); - - // -------------------------------------------------------------------- - #1us; - - // // -------------------------------------------------------------------- - // repeat(1)tb_top.a_h.queue_frame("counting"); - - // // -------------------------------------------------------------------- - // repeat(1) tb_top.a_h.queue_frame("random"); - // repeat(1)tb_top.a_h.queue_frame("counting"); - // repeat(3) tb_top.a_h.queue_frame("random"); - // tb_top.a_h.queue_frame("constant", 16'habba); - - // -------------------------------------------------------------------- - for(i = 0; i < SD; i++) - begin - force tb_top.select = i; - #1us; - tb_top.a_h.queue_frame("counting"); - #8us; - end - - // -------------------------------------------------------------------- - #5us; - - // -------------------------------------------------------------------- - // insert test above - // -------------------------------------------------------------------- - - endtask - - -endmodule - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch.sv (nonexistent) @@ -1,127 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// ---------------------------------------------------------------------------- - -`timescale 1ps/1ps - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_100mhz; - wire tb_clk = clk_100mhz; - wire tb_rst; - - tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); - - - // -------------------------------------------------------------------- - // - wire tb_rst_s; - wire aclk = tb_clk; - wire aresetn = ~tb_rst_s; - wire clk = tb_clk; - wire reset = tb_rst_s; - - sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); - - - // -------------------------------------------------------------------- - // - import tb_recursive_axis_switch_pkg::*; - - - // -------------------------------------------------------------------- - // - axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*); - axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[SD-1:0](.*); - - - // -------------------------------------------------------------------- - // - wire [SA-1:0] select = 0; - - recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA)) - dut(.*); - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - - // // -------------------------------------------------------------------- - // // - // initial - // axis_out.cb_s.tready <= 1; - - - // -------------------------------------------------------------------- - // - tb_recursive_axis_switch_class a_h; - - initial - a_h = new(axis_in, axis_out); - - - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - - - // -------------------------------------------------------------------- - // test - the_test test(tb_clk, tb_rst); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule - - - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/sim.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/sim.do (nonexistent) @@ -1,11 +0,0 @@ -# -# - -quit -sim - -vsim -novopt work.tb_top -# vsim -f ./sim.f work.tb_top - -# log all signals -log -r * - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_switch/tb_recursive_axis_switch_pkg.sv (nonexistent) @@ -1,142 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package tb_recursive_axis_switch_pkg; - - // -------------------------------------------------------------------- - // - import video_frame_pkg::*; - import axis_video_frame_bfm_pkg::*; - import avf_agent_class_pkg::*; - - - // -------------------------------------------------------------------- - // - localparam AW = 32; // active width - localparam AH = 16; // active height - localparam B = 2; // bytes per pixel - localparam T = 1; // pixels per clock - localparam VERTICAL_BLANKING = AW * 4; - localparam N = B * T; // data bus width in bytes - localparam I = 1; // TID width - localparam D = 1; // TDEST width - localparam U = 3; // TUSER width - localparam SA = 2; - localparam SD = 2 ** SA; - - - // -------------------------------------------------------------------- - // - class tb_recursive_axis_switch_class; - - avf_config_class c_h; - avf_tile_config_t tile_config[]; - - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[]; - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in; - - avf_tx_class #(B, T, U) tx_h; - avf_rx_class #(B, T, U) rx_h; - - // video_frame_class clone_h; - // video_frame_class sent_f_h; - // video_frame_class rx_f_h; - - // mailbox #(video_frame_class) q[]; - - - // -------------------------------------------------------------------- - // - task automatic - queue_frame - ( - string pattern = "", - int pixel = 0 - ); - video_frame_class clone_h; - - if(pattern != "") - tx_h.make_frame(pattern, pixel); - - foreach(tx_h.tx_bfm_h[i]) - begin - clone_h = tx_h.tx_bfm_h[i].f_h.clone(); - tx_h.tx_bfm_h[i].put(clone_h); - // q[i].put(clone_h); - end - - $display("^^^ %16.t | %m | using %s pattern", $time, pattern); - - endtask: queue_frame - - - //-------------------------------------------------------------------- - // - function new - ( - virtual axis_if #(.N(N), .U(U)) axis_in, - virtual axis_if #(.N(N), .U(U)) axis_out[] - ); - - this.axis_out = axis_out; - this.axis_in = axis_in; - - this.tile_config = new[T]; - this.tile_config[0].direction = RIGHT_DOWN; - - this.c_h = new - ( - .width(AW), - .height(AH), - .bytes_per_pixel(B), - .bits_per_pixel(B * 8), - .pixels_per_clk(T), - .name("AVR_"), - .vertical_blanking(VERTICAL_BLANKING), - .tile(tile_config) - ); - - rx_h = new(c_h, axis_out); - tx_h = new(c_h, '{axis_in}); - - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: tb_recursive_axis_switch_class - - -// -------------------------------------------------------------------- -// -endpackage: tb_recursive_axis_switch_pkg - - - - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/tb_axis_upsizer.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/tb_axis_upsizer.f (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/tb_axis_upsizer.f (nonexistent) @@ -1,6 +0,0 @@ -# - -${PROJECT_DIR}/sim/src/tb_axis_upsizer_agent_class_pkg.sv -${PROJECT_DIR}/sim/src/tb_axis_upsizer_class_pkg.sv - -${PROJECT_DIR}/src/axis_upsizer.sv Index: trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/init_test.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/init_test.do (nonexistent) @@ -1,37 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -set env(ROOT_DIR) ../../../../.. -set env(PROJECT_DIR) ../../.. -set env(SIM_TARGET) fpga - -# load sim procedures -do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do - -radix -hexadecimal - -make_lib work 1 - -sim_compile_all tb_packages -sim_compile_all bfm_packages -sim_compile_all axi4_lib -sim_compile_all qaz_libs -sim_compile_all sim -vlog -f ./tb_axis_upsizer.f - -# simulation $root -vlog $env(PROJECT_DIR)/sim/src/tb_axis_upsizer.sv - -# compile test last -vlog ./the_test.sv - -# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top - -# run the sim -sim_run_test - - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/the_test.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/the_test.sv (nonexistent) @@ -1,98 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - - -module - the_test( - input tb_clk, - input tb_rst - ); - - // -------------------------------------------------------------------- - // - int mismatch_count = 0; - - - // -------------------------------------------------------------------- - // - task run_the_test; - - // -------------------------------------------------------------------- - // insert test below - // -------------------------------------------------------------------- - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench begun.\n", $time); - $display("^^^---------------------------------"); - - // -------------------------------------------------------------------- - tb_top.tb.timeout_stop(50us); - - - // -------------------------------------------------------------------- - wait(tb_top.aresetn); - #1us; - - // -------------------------------------------------------------------- - repeat(3) tb_top.a_h.queue_frame("counting"); - repeat(3) tb_top.a_h.compare_frame(); - - // -------------------------------------------------------------------- - tb_top.a_h.tx_h.make_frame("constant", 16'habba); - tb_top.a_h.queue_frame(); - tb_top.a_h.compare_frame(); - - tb_top.a_h.queue_frame("random"); - tb_top.a_h.compare_frame(); - - tb_top.a_h.queue_frame("constant", 16'hbeef); - tb_top.a_h.compare_frame(); - - tb_top.a_h.queue_frame("random"); - tb_top.a_h.rx_h.wait_for_rx_frames(1); - tb_top.a_h.compare_frame(); - - tb_top.a_h.queue_frame("counting"); - tb_top.a_h.compare_frame(); - - repeat(3) tb_top.a_h.queue_frame("random"); - repeat(3) tb_top.a_h.compare_frame(); - - // -------------------------------------------------------------------- - #1us; - // #6us; - - // -------------------------------------------------------------------- - // insert test above - // -------------------------------------------------------------------- - - endtask - - -endmodule - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/sim.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_upsizer/sim.do (nonexistent) @@ -1,16 +0,0 @@ -# -# - - -quit -sim - -# vsim opt_tb_top -vsim -novopt work.tb_top -# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top - -# log all signals -log -r * - -# run -all - - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.f (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.f (nonexistent) @@ -1,6 +0,0 @@ -# - -${PROJECT_DIR}/src/recursive_axis_mux.sv -${PROJECT_DIR}/src/axis_catenate.sv -${PROJECT_DIR}/src/recursive_axis_catenate.sv - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/sim.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/sim.do (nonexistent) @@ -1,11 +0,0 @@ -# -# - -quit -sim - -vsim -novopt work.tb_top -# vsim -f ./sim.f work.tb_top - -# log all signals -log -r * - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate.sv (nonexistent) @@ -1,126 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// ---------------------------------------------------------------------------- - - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_100mhz; - wire tb_clk = clk_100mhz; - wire tb_rst; - - tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); - - - // -------------------------------------------------------------------- - // - wire tb_rst_s; - wire aclk = tb_clk; - wire aresetn = ~tb_rst_s; - wire clk = tb_clk; - wire reset = tb_rst_s; - - sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); - - - // -------------------------------------------------------------------- - // - import tb_recursive_axis_catenate_pkg::*; - - - // -------------------------------------------------------------------- - // - axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[MD-1:0](.*); - axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*); - - - // -------------------------------------------------------------------- - // - recursive_axis_catenate - #( - .N(N), - .I(I), - .D(D), - .U(U), - .U_IS_EOP(U_IS_EOP), - .MA(MA) - ) - dut(.*); - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - - // -------------------------------------------------------------------- - // - tb_recursive_axis_catenate_class a_h; - - initial - a_h = new(axis_in, axis_out); - - - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - - - // -------------------------------------------------------------------- - // test - the_test test(tb_clk, tb_rst); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule - - - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/tb_recursive_axis_catenate_pkg.sv (nonexistent) @@ -1,144 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package tb_recursive_axis_catenate_pkg; - - // -------------------------------------------------------------------- - // - import video_frame_pkg::*; - import axis_video_frame_bfm_pkg::*; - import avf_agent_class_pkg::*; - - - // -------------------------------------------------------------------- - // - localparam AW = 32; // active width - localparam AH = 16; // active height - localparam B = 2; // bytes per pixel - localparam T = 1; // pixels per clock - localparam VERTICAL_BLANKING = AW * 4; - localparam N = B * T; // data bus width in bytes - localparam I = 1; // TID width - localparam D = 1; // TDEST width - localparam U = 3; // TUSER width - // localparam U_IS_EOP = 2; - localparam U_IS_EOP = -1; - localparam MA = 2; - localparam MD = 2 ** MA; - - - // -------------------------------------------------------------------- - // - class tb_recursive_axis_catenate_class; - - avf_config_class c_h; - avf_tile_config_t tile_config[]; - - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out; - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[]; - - avf_tx_class #(B, T, U) tx_h; - avf_rx_class #(B, T, U) rx_h; - - // video_frame_class clone_h; - // video_frame_class sent_f_h; - // video_frame_class rx_f_h; - - // mailbox #(video_frame_class) q[]; - - - // -------------------------------------------------------------------- - // - task automatic - queue_frame - ( - string pattern = "", - int pixel = 0 - ); - video_frame_class clone_h; - - if(pattern != "") - tx_h.make_frame(pattern, pixel); - - foreach(tx_h.tx_bfm_h[i]) - begin - clone_h = tx_h.tx_bfm_h[i].f_h.clone(); - tx_h.tx_bfm_h[i].put(clone_h); - // q[i].put(clone_h); - end - - $display("^^^ %16.t | %m | using %s pattern", $time, pattern); - - endtask: queue_frame - - - //-------------------------------------------------------------------- - // - function new - ( - virtual axis_if #(.N(N), .U(U)) axis_in[], - virtual axis_if #(.N(N), .U(U)) axis_out - ); - - this.axis_out = axis_out; - this.axis_in = axis_in; - - this.tile_config = new[T]; - this.tile_config[0].direction = RIGHT_DOWN; - - this.c_h = new - ( - .width(AW), - .height(AH), - .bytes_per_pixel(B), - .bits_per_pixel(B * 8), - .pixels_per_clk(T), - .name("AVR_"), - .vertical_blanking(VERTICAL_BLANKING), - .tile(tile_config) - ); - - rx_h = new(c_h, '{axis_out}); - tx_h = new(c_h, axis_in); - - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: tb_recursive_axis_catenate_class - - -// -------------------------------------------------------------------- -// -endpackage: tb_recursive_axis_catenate_pkg - - - - - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/init_test.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/init_test.do (nonexistent) @@ -1,35 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -# setup environment -do ../../../../scripts/sim_env.do -set env(SIM_TARGET) fpga -set env(SIM_TB) tb_recursive_axis_catenate - -radix -hexadecimal - -make_lib work 1 - -sim_compile_lib $env(LIB_BASE_DIR) tb_packages -sim_compile_lib $env(LIB_BASE_DIR) bfm_packages -sim_compile_lib $env(LIB_BASE_DIR) axi4_lib -sim_compile_lib $env(LIB_BASE_DIR) qaz_lib -sim_compile_lib $env(LIB_BASE_DIR) sim - -# compile simulation files -vlog -f ./$env(SIM_TB).f - -# simulation $root -vlog ./$env(SIM_TB)_pkg.sv -vlog ./$env(SIM_TB).sv - -# compile test last -vlog ./the_test.sv - -# run the sim -sim_run_test - - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/the_test.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_catenate/the_test.sv (nonexistent) @@ -1,84 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - - -module the_test(input tb_clk, input tb_rst); - - // -------------------------------------------------------------------- - // - import tb_recursive_axis_catenate_pkg::*; - - // -------------------------------------------------------------------- - // - int i = 0; - - task automatic run_the_test; - - // -------------------------------------------------------------------- - // insert test below - // -------------------------------------------------------------------- - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench begun.", $time); - $display("^^^---------------------------------"); - - // -------------------------------------------------------------------- - tb_top.tb.timeout_stop(2ms); - wait(~tb_rst); - - // -------------------------------------------------------------------- - #1us; - - // -------------------------------------------------------------------- - repeat(10)tb_top.a_h.queue_frame("counting"); - - // // -------------------------------------------------------------------- - // repeat(1) tb_top.a_h.queue_frame("random"); - // repeat(1)tb_top.a_h.queue_frame("counting"); - // repeat(3) tb_top.a_h.queue_frame("random"); - // tb_top.a_h.queue_frame("constant", 16'habba); - - // // -------------------------------------------------------------------- - // for(i = 0; i < MD; i++) - // begin - // force tb_top.select = i; - // #20us; - // end - - // -------------------------------------------------------------------- - #100us; - - // -------------------------------------------------------------------- - // insert test above - // -------------------------------------------------------------------- - - endtask - - -endmodule - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/sim.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/sim.do (nonexistent) @@ -1,11 +0,0 @@ -# -# - -quit -sim - -vsim -novopt work.tb_top -# vsim -f ./sim.f work.tb_top - -# log all signals -log -r * - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.f (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.f (nonexistent) @@ -1,6 +0,0 @@ -# - -${PROJECT_DIR}/src/axis_switch.sv -${PROJECT_DIR}/src/recursive_axis_switch.sv - -${PROJECT_DIR}/src/axis_switch_allocator.sv Index: trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator.sv (nonexistent) @@ -1,118 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// ---------------------------------------------------------------------------- - - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_100mhz; - wire tb_clk = clk_100mhz; - wire tb_rst; - - tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); - - - // -------------------------------------------------------------------- - // - wire tb_rst_s; - wire aclk = tb_clk; - wire aresetn = ~tb_rst_s; - wire clk = tb_clk; - wire reset = tb_rst_s; - - sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); - - - // -------------------------------------------------------------------- - // - import tb_axis_switch_allocator_pkg::*; - - - // -------------------------------------------------------------------- - // - axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*); - axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[SD-1:0](.*); - - - // -------------------------------------------------------------------- - // - axis_switch_allocator #(.N(N), .I(I), .D(D), .U(U), .U_IS_EOP(U_IS_EOP), .SA(SA)) - dut(.*); - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - - // -------------------------------------------------------------------- - // - tb_axis_switch_allocator_class a_h; - - initial - a_h = new(axis_in, axis_out); - - - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - - - // -------------------------------------------------------------------- - // test - the_test test(tb_clk, tb_rst); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule - - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv (nonexistent) @@ -1,143 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package tb_axis_switch_allocator_pkg; - - // -------------------------------------------------------------------- - // - import video_frame_pkg::*; - import axis_video_frame_bfm_pkg::*; - import avf_agent_class_pkg::*; - - - // -------------------------------------------------------------------- - // - localparam AW = 32; // active width - localparam AH = 16; // active height - localparam B = 2; // bytes per pixel - localparam T = 1; // pixels per clock - localparam VERTICAL_BLANKING = AW * 4; - localparam N = B * T; // data bus width in bytes - localparam I = 1; // TID width - localparam D = 1; // TDEST width - localparam U = 3; // TUSER width - localparam U_IS_EOP = 2; - localparam SA = 3; - localparam SD = 2 ** SA; - - - // -------------------------------------------------------------------- - // - class tb_axis_switch_allocator_class; - - avf_config_class c_h; - avf_tile_config_t tile_config[]; - - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[]; - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in; - - avf_tx_class #(B, T, U) tx_h; - avf_rx_class #(B, T, U) rx_h; - - // video_frame_class clone_h; - // video_frame_class sent_f_h; - // video_frame_class rx_f_h; - - // mailbox #(video_frame_class) q[]; - - - // -------------------------------------------------------------------- - // - task automatic - queue_frame - ( - string pattern = "", - int pixel = 0 - ); - video_frame_class clone_h; - - if(pattern != "") - tx_h.make_frame(pattern, pixel); - - foreach(tx_h.tx_bfm_h[i]) - begin - clone_h = tx_h.tx_bfm_h[i].f_h.clone(); - tx_h.tx_bfm_h[i].put(clone_h); - // q[i].put(clone_h); - end - - $display("^^^ %16.t | %m | using %s pattern", $time, pattern); - - endtask: queue_frame - - - //-------------------------------------------------------------------- - // - function new - ( - virtual axis_if #(.N(N), .U(U)) axis_in, - virtual axis_if #(.N(N), .U(U)) axis_out[] - ); - - this.axis_out = axis_out; - this.axis_in = axis_in; - - this.tile_config = new[T]; - this.tile_config[0].direction = RIGHT_DOWN; - - this.c_h = new - ( - .width(AW), - .height(AH), - .bytes_per_pixel(B), - .bits_per_pixel(B * 8), - .pixels_per_clk(T), - .name("AVR_"), - .vertical_blanking(VERTICAL_BLANKING), - .tile(tile_config) - ); - - rx_h = new(c_h, axis_out); - tx_h = new(c_h, '{axis_in}); - - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: tb_axis_switch_allocator_class - - -// -------------------------------------------------------------------- -// -endpackage: tb_axis_switch_allocator_pkg - - - - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/init_test.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/init_test.do (nonexistent) @@ -1,35 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -# setup environment -do ../../../../scripts/sim_env.do -set env(SIM_TARGET) fpga -set env(SIM_TB) tb_axis_switch_allocator - -radix -hexadecimal - -make_lib work 1 - -sim_compile_lib $env(LIB_BASE_DIR) tb_packages -sim_compile_lib $env(LIB_BASE_DIR) bfm_packages -sim_compile_lib $env(LIB_BASE_DIR) axi4_lib -sim_compile_lib $env(LIB_BASE_DIR) qaz_lib -sim_compile_lib $env(LIB_BASE_DIR) sim - -# compile simulation files -vlog -f ./$env(SIM_TB).f - -# simulation $root -vlog ./$env(SIM_TB)_pkg.sv -vlog ./$env(SIM_TB).sv - -# compile test last -vlog ./the_test.sv - -# run the sim -sim_run_test - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/the_test.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_switch_allocator/the_test.sv (nonexistent) @@ -1,88 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - - -module the_test(input tb_clk, input tb_rst); - - // -------------------------------------------------------------------- - // - import tb_axis_switch_allocator_pkg::*; - - // -------------------------------------------------------------------- - // - int i = 0; - - task automatic run_the_test; - - // -------------------------------------------------------------------- - // insert test below - // -------------------------------------------------------------------- - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench begun.", $time); - $display("^^^---------------------------------"); - - // -------------------------------------------------------------------- - tb_top.tb.timeout_stop(2ms); - wait(~tb_rst); - - // -------------------------------------------------------------------- - #1us; - - // // -------------------------------------------------------------------- - // repeat(1)tb_top.a_h.queue_frame("counting"); - - // // -------------------------------------------------------------------- - // repeat(1) tb_top.a_h.queue_frame("random"); - // repeat(1)tb_top.a_h.queue_frame("counting"); - // repeat(3) tb_top.a_h.queue_frame("random"); - // tb_top.a_h.queue_frame("constant", 16'habba); - - // // -------------------------------------------------------------------- - // for(i = 0; i < SD; i++) - // begin - // #1us; - // tb_top.a_h.queue_frame("counting"); - // #8us; - // end - - // -------------------------------------------------------------------- - repeat(SD * 2) tb_top.a_h.queue_frame("counting"); - - // -------------------------------------------------------------------- - #100us; - - // -------------------------------------------------------------------- - // insert test above - // -------------------------------------------------------------------- - - endtask - - -endmodule - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/wip.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/wip.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/wip.do (nonexistent) @@ -1,11 +0,0 @@ -# - -vlog -f ./tb_axis_to_axi4_basic_dma.f - -# simulation $root -vlog ./tb_axis_to_axi4_basic_dma.sv - -# compile test last -vlog ./the_test.sv - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/init_test.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/init_test.do (nonexistent) @@ -1,34 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -# setup environment -do ../../../../scripts/sim_env.do -set env(SIM_TARGET) fpga -set env(SIM_TB) tb_axis_to_axi4_basic_dma - -radix -hexadecimal - -make_lib work 1 - -sim_compile_all tb_packages -sim_compile_all bfm_packages -sim_compile_all axi4_lib -sim_compile_all qaz_lib -sim_compile_all sim - -# compile simulation files -vlog -f ./$env(SIM_TB).f - -# simulation $root -vlog ./$env(SIM_TB)_pkg.sv -vlog ./$env(SIM_TB).sv - -# compile test last -vlog ./the_test.sv - -# run the sim -sim_run_test - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/the_test.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/the_test.sv (nonexistent) @@ -1,60 +0,0 @@ -// -------------------------------------------------------------------- -// -// -------------------------------------------------------------------- - -`timescale 1ps/1ps - - -module - the_test( - input tb_clk, - input tb_rst - ); - - // -------------------------------------------------------------------- - // - import tb_axis_to_axi4_basic_dma_pkg::*; - - - // -------------------------------------------------------------------- - // - task run_the_test; - - // -------------------------------------------------------------------- - // insert test below - // -------------------------------------------------------------------- - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench begun.", $time); - $display("^^^---------------------------------"); - - // -------------------------------------------------------------------- - tb_top.tb.timeout_stop(50us); - - // -------------------------------------------------------------------- - wait(tb_top.aresetn); - #200ns; - - // -------------------------------------------------------------------- - force tb_top.dma_enable = 1; - #100ns; - - // -------------------------------------------------------------------- - repeat(8) - begin - tb_top.a_h.random_transaction(BASE_ADDRESS, BUFFER_SIZE, N * BURST_LENGTH); - tb_top.a_h.compare(BASE_ADDRESS); - end - - // -------------------------------------------------------------------- - #200ns; - - // -------------------------------------------------------------------- - // insert test above - // -------------------------------------------------------------------- - - endtask - -// -------------------------------------------------------------------- -// -endmodule - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.f (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.f (nonexistent) @@ -1,12 +0,0 @@ -# - -${LIB_BASE_DIR}/axi4_stream_lib/sim/src/axis_bfm_pkg.sv -${LIB_BASE_DIR}/axi4_lib/sim/src/axi4_models/axi4_memory_pkg.sv - -${PROJECT_DIR}/sim/src/tb_axis_to_axi4_agent_class_pkg.sv - -${PROJECT_DIR}/src/axis_to_axi4_basic_dma.sv - -./${SIM_TB}_pkg.sv -./${SIM_TB}.sv - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.sv (nonexistent) @@ -1,115 +0,0 @@ -// -------------------------------------------------------------------- -// -// -------------------------------------------------------------------- - - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_200mhz; - wire tb_clk = clk_200mhz; - wire tb_rst; - - tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); - - - // -------------------------------------------------------------------- - // - wire tb_rst_s; - wire aclk = tb_clk; - wire aresetn = ~tb_rst_s; - - sync_reset - sync_reset_i(aclk, tb_rst, tb_rst_s); - - - // -------------------------------------------------------------------- - // - import tb_axis_to_axi4_basic_dma_pkg::*; - - - // -------------------------------------------------------------------- - // - axi4_if #(.A(A), .N(N), .I(I)) axi4_m(.*); - axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*); - - - // -------------------------------------------------------------------- - // - logic dma_enable = 0; - - axis_to_axi4_basic_dma - #( - .A(A), - .N(N), - .I(I), - .BASE_ADDRESS(BASE_ADDRESS), - .BUFFER_SIZE(BUFFER_SIZE), - .BURST_LENGTH(BURST_LENGTH), - .MAX_BURSTS(MAX_BURSTS), - .BYTES_PER_TUSER(BYTES_PER_TUSER) - ) - dut(.*); - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - // -------------------------------------------------------------------- - // - axi4_checker #(.A(A), .N(N), .MAXWAITS(64)) - axi4_checker_i(.axi4_in(axi4_m)); - - - // -------------------------------------------------------------------- - // - axis_checker #(.N(N), .I(I), .D(D), .U(U), .MAXWAITS(64)) - axis_checker_i(.axis_in(axis_in)); - - - // -------------------------------------------------------------------- - // - tb_axis_to_axi4_basic_dma_class a_h; - - initial - a_h = new(axi4_m, axis_in); - - - // -------------------------------------------------------------------- - // - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - - - // -------------------------------------------------------------------- - // test - the_test test(tb_clk, tb_rst); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule Index: trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/sim.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/sim.do (nonexistent) @@ -1,13 +0,0 @@ -# -# - -quit -sim - -vsim -novopt work.tb_top - -# log all signals -log -r * - -# run -all - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma_pkg.sv (nonexistent) @@ -1,58 +0,0 @@ -// -------------------------------------------------------------------- -// -// -------------------------------------------------------------------- - - -package tb_axis_to_axi4_basic_dma_pkg; - - // -------------------------------------------------------------------- - // - import tb_axis_to_axi4_agent_class_pkg::*; - - - // -------------------------------------------------------------------- - // - localparam BASE_ADDRESS = 32'h0000_0000; // must be on 4K boundry - localparam BUFFER_SIZE = 'h800; - localparam BURST_LENGTH = 8'h08; - localparam MAX_BURSTS = 4; - localparam BYTES_PER_TUSER = 2; // bytes per tuser bit. Set to 0 for transfer based. - - localparam N = 8; // data bus width in bytes - localparam A = 32; // address bus width - localparam I = 1; // ID width - localparam D = 1; // TDEST width - localparam U = N / BYTES_PER_TUSER; // TUSER width - - - // -------------------------------------------------------------------- - // - class tb_axis_to_axi4_basic_dma_class - extends tb_axis_to_axi4_agent_class #(N, A, I, D, U); - - - //-------------------------------------------------------------------- - // - function new - ( - virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m, - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in - ); - - super.new(.axi4_m(axi4_m), .axis_in(axis_in)); - - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: tb_axis_to_axi4_basic_dma_class - -// -------------------------------------------------------------------- -// -endpackage: tb_axis_to_axi4_basic_dma_pkg - - - - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/wip.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/wip.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/wip.do (nonexistent) @@ -1,12 +0,0 @@ -# - - -vlog -f ../../libs/axi4_stream_lib_verilog/axi4_stream_lib.f - -# simulation $root -vlog ../../src/tb_axis_register_slice.sv - -# compile test last -vlog ./the_test.sv - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/init_test.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/init_test.do (nonexistent) @@ -1,35 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -set env(ROOT_DIR) ../../../../.. -set env(PROJECT_DIR) ../../.. -set env(SIM_TARGET) fpga - -# load sim procedures -do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do - -radix -hexadecimal - -make_lib work 1 - -# sim_compile_all FPGA -sim_compile_all sim -sim_compile_all sync_fifo -sim_compile_all axi4_stream_lib - -# simulation $root -vlog $env(PROJECT_DIR)/sim/src/tb_axis_register_slice.sv - -# compile test last -vlog ./the_test.sv - -# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top - -# run the sim -sim_run_test - - - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/the_test.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/the_test.sv (nonexistent) @@ -1,79 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - - -module - the_test( - input tb_clk, - input tb_rst - ); - - // -------------------------------------------------------------------- - // - int mismatch_count = 0; - - - // -------------------------------------------------------------------- - // - task run_the_test; - - // -------------------------------------------------------------------- - // insert test below - // -------------------------------------------------------------------- - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench begun.\n", $time); - $display("^^^---------------------------------"); - // -------------------------------------------------------------------- - - // -------------------------------------------------------------------- - tb_top.tb.timeout_stop(4us); - wait(~tb_rst); - - - // -------------------------------------------------------------------- - repeat(100) @(posedge tb_clk); - tb_top.avf_agent_h.make_frame("counting"); - tb_top.avf_agent_h.get_frame(); - tb_top.avf_agent_h.put_frame(); - - wait(~tb_top.avf_agent_h.put_frame_active); - wait(~tb_top.avf_agent_h.get_frame_active); - - mismatch_count = tb_top.avf_agent_h.compare_frame(); - - - // -------------------------------------------------------------------- - // insert test above - // -------------------------------------------------------------------- - - endtask - - -endmodule - Index: trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/sim.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_axis_register_slice/sim.do (nonexistent) @@ -1,21 +0,0 @@ -# -# - - -quit -sim - -# vsim opt_tb_top - -vsim -novopt work.tb_top -# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top - -# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top -# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top - - -# # log all signals -# log -r * - -# run -all - - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.f (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.f (nonexistent) @@ -1,4 +0,0 @@ -# - -${PROJECT_DIR}/src/recursive_axis_mux.sv - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux.sv (nonexistent) @@ -1,126 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// ---------------------------------------------------------------------------- - - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_100mhz; - wire tb_clk = clk_100mhz; - wire tb_rst; - - tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); - - - // -------------------------------------------------------------------- - // - wire tb_rst_s; - wire aclk = tb_clk; - wire aresetn = ~tb_rst_s; - wire clk = tb_clk; - wire reset = tb_rst_s; - - sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); - - - // -------------------------------------------------------------------- - // - import tb_recursive_axis_mux_pkg::*; - - - // -------------------------------------------------------------------- - // - axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[MD-1:0](.*); - axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*); - - - // -------------------------------------------------------------------- - // - wire [MA-1:0] select = 0; - - recursive_axis_mux #(.N(N), .I(I), .D(D), .U(U), .MA(MA)) - dut(.*); - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - - // -------------------------------------------------------------------- - // - initial - axis_out.cb_s.tready <= 1; - - - // -------------------------------------------------------------------- - // - tb_recursive_axis_mux_class a_h; - - initial - a_h = new(axis_in, axis_out); - - - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - - - // -------------------------------------------------------------------- - // test - the_test test(tb_clk, tb_rst); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule - - - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux_pkg.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/tb_recursive_axis_mux_pkg.sv (nonexistent) @@ -1,142 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package tb_recursive_axis_mux_pkg; - - // -------------------------------------------------------------------- - // - import video_frame_pkg::*; - import axis_video_frame_bfm_pkg::*; - import avf_agent_class_pkg::*; - - - // -------------------------------------------------------------------- - // - localparam AW = 32; // active width - localparam AH = 16; // active height - localparam B = 2; // bytes per pixel - localparam T = 1; // pixels per clock - localparam VERTICAL_BLANKING = AW * 4; - localparam N = B * T; // data bus width in bytes - localparam I = 1; // TID width - localparam D = 1; // TDEST width - localparam U = 3; // TUSER width - localparam MA = 5; - localparam MD = 2 ** MA; - - - // -------------------------------------------------------------------- - // - class tb_recursive_axis_mux_class; - - avf_config_class c_h; - avf_tile_config_t tile_config[]; - - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out; - virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[]; - - avf_tx_class #(B, T, U) tx_h; - avf_rx_class #(B, T, U) rx_h; - - // video_frame_class clone_h; - // video_frame_class sent_f_h; - // video_frame_class rx_f_h; - - // mailbox #(video_frame_class) q[]; - - - // -------------------------------------------------------------------- - // - task automatic - queue_frame - ( - string pattern = "", - int pixel = 0 - ); - video_frame_class clone_h; - - if(pattern != "") - tx_h.make_frame(pattern, pixel); - - foreach(tx_h.tx_bfm_h[i]) - begin - clone_h = tx_h.tx_bfm_h[i].f_h.clone(); - tx_h.tx_bfm_h[i].put(clone_h); - // q[i].put(clone_h); - end - - $display("^^^ %16.t | %m | using %s pattern", $time, pattern); - - endtask: queue_frame - - - //-------------------------------------------------------------------- - // - function new - ( - virtual axis_if #(.N(N), .U(U)) axis_in[], - virtual axis_if #(.N(N), .U(U)) axis_out - ); - - this.axis_out = axis_out; - this.axis_in = axis_in; - - this.tile_config = new[T]; - this.tile_config[0].direction = RIGHT_DOWN; - - this.c_h = new - ( - .width(AW), - .height(AH), - .bytes_per_pixel(B), - .bits_per_pixel(B * 8), - .pixels_per_clk(T), - .name("AVR_"), - .vertical_blanking(VERTICAL_BLANKING), - .tile(tile_config) - ); - - rx_h = new(c_h, '{axis_out}); - tx_h = new(c_h, axis_in); - - endfunction: new - - - // -------------------------------------------------------------------- - // - endclass: tb_recursive_axis_mux_class - - -// -------------------------------------------------------------------- -// -endpackage: tb_recursive_axis_mux_pkg - - - - - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/init_test.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/init_test.do (nonexistent) @@ -1,35 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -# setup environment -do ../../../../scripts/sim_env.do -set env(SIM_TARGET) fpga -set env(SIM_TB) tb_recursive_axis_mux - -radix -hexadecimal - -make_lib work 1 - -sim_compile_lib $env(LIB_BASE_DIR) tb_packages -sim_compile_lib $env(LIB_BASE_DIR) bfm_packages -sim_compile_lib $env(LIB_BASE_DIR) axi4_lib -sim_compile_lib $env(LIB_BASE_DIR) qaz_lib -sim_compile_lib $env(LIB_BASE_DIR) sim - -# compile simulation files -vlog -f ./$env(SIM_TB).f - -# simulation $root -vlog ./$env(SIM_TB)_pkg.sv -vlog ./$env(SIM_TB).sv - -# compile test last -vlog ./the_test.sv - -# run the sim -sim_run_test - - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/the_test.sv (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/the_test.sv (nonexistent) @@ -1,84 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2017 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - - -module the_test(input tb_clk, input tb_rst); - - // -------------------------------------------------------------------- - // - import tb_recursive_axis_mux_pkg::*; - - // -------------------------------------------------------------------- - // - int i = 0; - - task automatic run_the_test; - - // -------------------------------------------------------------------- - // insert test below - // -------------------------------------------------------------------- - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench begun.", $time); - $display("^^^---------------------------------"); - - // -------------------------------------------------------------------- - // tb_top.tb.timeout_stop(2ms); - wait(~tb_rst); - - // -------------------------------------------------------------------- - #1us; - - // -------------------------------------------------------------------- - repeat(1)tb_top.a_h.queue_frame("counting"); - - // // -------------------------------------------------------------------- - // repeat(1) tb_top.a_h.queue_frame("random"); - // repeat(1)tb_top.a_h.queue_frame("counting"); - // repeat(3) tb_top.a_h.queue_frame("random"); - // tb_top.a_h.queue_frame("constant", 16'habba); - - // -------------------------------------------------------------------- - for(i = 0; i < MD; i++) - begin - force tb_top.select = i; - #20us; - end - - // -------------------------------------------------------------------- - #10us; - - // -------------------------------------------------------------------- - // insert test above - // -------------------------------------------------------------------- - - endtask - - -endmodule - Index: trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/sim.do (revision 49) +++ trunk/axi4_stream_lib/sim/tests/tb_recursive_axis_mux/sim.do (nonexistent) @@ -1,11 +0,0 @@ -# -# - -quit -sim - -vsim -novopt work.tb_top -# vsim -f ./sim.f work.tb_top - -# log all signals -log -r * - Index: trunk/axi4_stream_lib/sim/tests/legacy/defparam_test_case.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/axi4_stream_lib/sim/tests/legacy/defparam_test_case.zip =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/defparam_test_case.zip (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/defparam_test_case.zip (revision 50)
trunk/axi4_stream_lib/sim/tests/legacy/defparam_test_case.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/axis_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/axis_pkg.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/axis_pkg.sv (revision 50) @@ -0,0 +1,328 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// -------------------------------------------------------------------- +// +package axis_pkg; + + // -------------------------------------------------------------------- + // + import uvm_pkg::*; + `include "uvm_macros.svh" + import bfm_pkg::*; + + // -------------------------------------------------------------------- + // + typedef struct + { + int unsigned N; // data bus width in bytes + int unsigned I; // TID width + int unsigned D; // TDEST width + int unsigned U; // TUSER width + bit USE_TSTRB; // set to 1 to enable, 0 to disable + bit USE_TKEEP; // set to 1 to enable, 0 to disable + bit USE_ROUTING; // set to 1 to enable, 0 to disable + } axis_config_t; + + // -------------------------------------------------------------------- + // + class axis_sequence_item #(axis_config_t cfg) + extends uvm_sequence_item; + `uvm_object_param_utils(axis_sequence_item #(cfg)) + + // -------------------------------------------------------------------- + // + localparam N = cfg.N; + localparam I = cfg.I; + localparam D = cfg.D; + localparam U = cfg.U; + localparam USE_TSTRB = cfg.USE_TSTRB; + localparam USE_TKEEP = cfg.USE_TKEEP; + localparam USE_ROUTING = cfg.USE_ROUTING; + + // -------------------------------------------------------------------- + // + delay_class delay_h; + rand logic [(8*N)-1:0] tdata; + rand logic [N-1:0] tstrb; + rand logic [N-1:0] tkeep; + rand logic tlast; + rand logic [I-1:0] tid; + rand logic [D-1:0] tdest; + rand logic [U-1:0] tuser; + + // -------------------------------------------------------------------- + // + function new(string name = ""); + super.new(name); + delay_h = new; + endfunction : new + + // -------------------------------------------------------------------- + // + function bit do_compare(uvm_object rhs, uvm_comparer comparer); + axis_sequence_item #(cfg) tested; + bit same; + + if (rhs==null) + `uvm_fatal(get_type_name(), "| %m | comparison to a null pointer"); + + if (!$cast(tested,rhs)) + same = 0; + else + same = super.do_compare(rhs, comparer) + & (tested.tdata == tdata) + & (USE_TSTRB ? (tested.tstrb == tstrb) : 1) + & (USE_TKEEP ? (tested.tkeep == tkeep) : 1) + & (tested.tlast == tlast) + & (USE_ROUTING ? (tested.tid == tid) : 1) + & (USE_ROUTING ? (tested.tdest == tdest) : 1) + & (tested.tuser == tuser); + return same; + endfunction : do_compare + + // -------------------------------------------------------------------- + // + function void do_copy(uvm_object rhs); + axis_sequence_item #(cfg) item; + assert(rhs != null) else + `uvm_fatal(get_type_name(), "| %m | copy null transaction"); + super.do_copy(rhs); + assert($cast(item,rhs)) else + `uvm_fatal(get_type_name(), "| %m | failed cast"); + tdata = item.tdata; + tstrb = item.tstrb; + tkeep = item.tkeep; + tlast = item.tlast; + tid = item.tid; + tdest = item.tdest; + tuser = item.tuser; + endfunction : do_copy + + // -------------------------------------------------------------------- + // + function string convert2string(); + string s0, s1; + s0 = $sformatf("| tdata: %h\n" ,tdata); + s1 = $sformatf("| tlast: %1h | tuser: %h" , tlast, tuser); + return {s1, s0}; + endfunction : convert2string + + // -------------------------------------------------------------------- + // + endclass : axis_sequence_item + + // -------------------------------------------------------------------- + // + class axis_driver #(parameter axis_config_t cfg) + extends uvm_driver #(axis_sequence_item #(cfg)); + `uvm_component_param_utils(axis_driver#(cfg)) + + // -------------------------------------------------------------------- + // + localparam N = cfg.N; + localparam I = cfg.I; + localparam D = cfg.D; + localparam U = cfg.U; + localparam USE_TSTRB = cfg.USE_TSTRB; + localparam USE_TKEEP = cfg.USE_TKEEP; + localparam USE_ROUTING = cfg.USE_ROUTING; + + // -------------------------------------------------------------------- + // + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus; + + //-------------------------------------------------------------------- + // + function void set_default; + axis_bus.cb_m.tvalid <= 0; + axis_bus.cb_m.tdata <= 'bx; + axis_bus.cb_m.tstrb <= 'bx; + axis_bus.cb_m.tkeep <= 'bx; + axis_bus.cb_m.tlast <= 'bx; + axis_bus.cb_m.tid <= 'bx; + axis_bus.cb_m.tdest <= 'bx; + axis_bus.cb_m.tuser <= 'bx; + endfunction: set_default + + //-------------------------------------------------------------------- + // + virtual task run_phase(uvm_phase phase); + axis_sequence_item #(cfg) item; + super.run_phase(phase); + + set_default(); + wait(~axis_bus.aresetn); + @(axis_bus.cb_m); + + forever + begin + // seq_item_port.try_next_item(item); + seq_item_port.get_next_item(item); + + axis_bus.cb_m.tvalid <= 1; + axis_bus.cb_m.tdata <= item.tdata; + axis_bus.cb_m.tstrb <= 0; + axis_bus.cb_m.tkeep <= 0; + axis_bus.cb_m.tlast <= item.tlast; + axis_bus.cb_m.tid <= 0; + axis_bus.cb_m.tdest <= 0; + axis_bus.cb_m.tuser <= item.tuser; + + @(axis_bus.cb_m); + wait(axis_bus.cb_m.tready); + // @(axis_bus.cb_m iff axis_bus.cb_m.tready); + + set_default(); + repeat(item.delay_h.next()) @(axis_bus.cb_m); + + seq_item_port.item_done(); + end + endtask : run_phase + + //-------------------------------------------------------------------- + // + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction + + // -------------------------------------------------------------------- + // + endclass : axis_driver + + // -------------------------------------------------------------------- + // + class axis_sequencer #(axis_config_t cfg) + extends uvm_sequencer #(axis_sequence_item #(cfg)); + `uvm_component_param_utils(axis_sequencer #(cfg)) + + // -------------------------------------------------------------------- + // + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction + + // -------------------------------------------------------------------- + // + endclass : axis_sequencer + + // -------------------------------------------------------------------- + // + class axis_counting_sequence #(axis_config_t cfg) + extends uvm_sequence #(axis_sequence_item #(cfg)); + `uvm_object_param_utils(axis_counting_sequence #(cfg)) + + rand int length = 16; + + // -------------------------------------------------------------------- + // + virtual task body(); + axis_sequence_item #(cfg) item; + + for(int i = 0; i < length; i++) + begin + item = axis_sequence_item #(cfg)::type_id::create("axis_sequence_item"); + + item.tdata = i; + item.tlast = (i == length - 1); + + start_item (item); + finish_item(item); + end + endtask + + // -------------------------------------------------------------------- + // + function new(string name = "axis_counting_sequence"); + super.new(name); + endfunction + + // -------------------------------------------------------------------- + // + endclass : axis_counting_sequence + + // -------------------------------------------------------------------- + // + class axis_agent #(axis_config_t cfg) + extends uvm_agent; + `uvm_component_param_utils(axis_agent #(cfg)) + + // -------------------------------------------------------------------- + // + localparam N = cfg.N; + localparam I = cfg.I; + localparam D = cfg.D; + localparam U = cfg.U; + localparam USE_TSTRB = cfg.USE_TSTRB; + localparam USE_TKEEP = cfg.USE_TKEEP; + localparam USE_ROUTING = cfg.USE_ROUTING; + + // -------------------------------------------------------------------- + // + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus; + + axis_driver #(cfg) driver; + // my_monitor #(cfg) monitor; + axis_sequencer #(cfg) sequencer; + + // -------------------------------------------------------------------- + // + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + + if(!uvm_config_db #(virtual axis_if #(.N(N), .I(I), .D(D), .U(U)))::get(this, "", "axis_bus", axis_bus)) + `uvm_fatal(get_name(), "Couldn't get virtual interface!") + + driver = axis_driver #(cfg)::type_id::create("driver", this); + // monitor = my_monitor #(cfg)::type_id::create("monitor" , this); + sequencer = axis_sequencer #(cfg)::type_id::create("sequencer", this); + endfunction + + // -------------------------------------------------------------------- + // + virtual function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + + driver.axis_bus = axis_bus; + // monitor.vif = vif; + + driver.seq_item_port.connect(sequencer.seq_item_export); + endfunction + + // -------------------------------------------------------------------- + // + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction + + // -------------------------------------------------------------------- + // + endclass : axis_agent + +// -------------------------------------------------------------------- +// +endpackage: axis_pkg Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/init_test.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/init_test.do (revision 50) @@ -0,0 +1,42 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +# setup environment +do ../../../../scripts/sim_env.do +set env(SIM_TARGET) fpga +set env(SIM_TB) tb_axis_gear_box + +radix -hexadecimal + +make_lib work 1 + +sim_compile_lib $env(LIB_BASE_DIR) tb_packages +sim_compile_lib $env(LIB_BASE_DIR) bfm_packages +sim_compile_lib $env(LIB_BASE_DIR) axi4_lib +sim_compile_lib $env(LIB_BASE_DIR) qaz_lib +sim_compile_lib $env(LIB_BASE_DIR) sim + +# AXI4 streaming package +vlog ./axis_pkg.sv + +vlog ./$env(SIM_TB)_pkg.sv +vlog ./tests_base_pkg.sv +vlog ./tests_pkg.sv +vlog ./tb_dut_if.sv + +# simulation $root +vlog ./$env(SIM_TB).sv + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +# # compile test last +# vlog ./the_test.sv + +# run the sim +sim_run_test + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/sim.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/sim.do (revision 50) @@ -0,0 +1,11 @@ +# +# + +quit -sim + +vsim -novopt work.tb_top +# vsim -f ./sim.f work.tb_top + +# # log all signals +# log -r * + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box.f (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box.f (revision 50) @@ -0,0 +1,6 @@ +# + +./axis_pkg.sv + +${PROJECT_DIR}/src/axis_gear_box.sv + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box.sv (revision 50) @@ -0,0 +1,90 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// ---------------------------------------------------------------------------- + +import tb_axis_gear_box_pkg::*; +import tests_pkg::*; +import uvm_pkg::*; +`include "uvm_macros.svh" + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + // -------------------------------------------------------------------- + // + wire tb_rst_s; + wire aclk = tb_clk; + wire aresetn = ~tb_rst_s; + wire clk = tb_clk; + wire reset = tb_rst_s; + + sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); + + // -------------------------------------------------------------------- + // + import tb_axis_gear_box_pkg::*; + + // -------------------------------------------------------------------- + // + tb_dut_if #(dut_cfg) dut_bus(.*); + + // -------------------------------------------------------------------- + // + axis_gear_box + dut + ( + .axis_in(dut_bus.axis_in), + .axis_out(dut_bus.axis_out), + .aclk(dut_bus.aclk), + .aresetn(dut_bus.aresetn) + ); + + // -------------------------------------------------------------------- + // + assign dut_bus.axis_out.tready = 1; + + // -------------------------------------------------------------------- + // + tb_dut_config #(dut_cfg) cfg_h; + + initial + begin + cfg_h = new(dut_bus); + uvm_config_db #(tb_dut_config #(dut_cfg))::set(null, "*env_h", "tb_dut_config", cfg_h); + run_test("t_debug"); + end + +// -------------------------------------------------------------------- +// +endmodule Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box_pkg.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_axis_gear_box_pkg.sv (revision 50) @@ -0,0 +1,139 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +package tb_axis_gear_box_pkg; + + // -------------------------------------------------------------------- + // + import uvm_pkg::*; + `include "uvm_macros.svh" + import axis_pkg::*; + + // -------------------------------------------------------------------- + // + typedef struct + { + axis_config_t axis_cfg_in; + axis_config_t axis_cfg_out; + } dut_config_t; + + localparam dut_config_t dut_cfg = + '{ + '{ N : 2 // data bus width in bytes. + , I : 1 // TID width + , D : 1 // TDEST width + , U : 1 // TUSER width + , USE_TSTRB : 0 + , USE_TKEEP : 0 + , USE_ROUTING : 0 + }, + '{ N : 2 // data bus width in bytes. + , I : 1 // TID width + , D : 1 // TDEST width + , U : 1 // TUSER width + , USE_TSTRB : 0 + , USE_TKEEP : 0 + , USE_ROUTING : 0 + } + }; + + // -------------------------------------------------------------------- + // + class tb_dut_config #(dut_config_t dut_cfg); + + virtual tb_dut_if #(dut_cfg) dut_bus; + + // -------------------------------------------------------------------- + // + function new(virtual tb_dut_if #(dut_cfg) dut_bus); + this.dut_bus = dut_bus; + endfunction : new + + // -------------------------------------------------------------------- + // + endclass : tb_dut_config + + // -------------------------------------------------------------------- + // + class tb_env extends uvm_env; + `uvm_component_utils(tb_env); + + // -------------------------------------------------------------------- + // + // coverage coverage_h; + // scoreboard scoreboard_h; + axis_agent #(dut_cfg.axis_cfg_in) agent_h; + + // -------------------------------------------------------------------- + // + function new (string name, uvm_component parent); + super.new(name,parent); + endfunction : new + + // -------------------------------------------------------------------- + // + function void build_phase(uvm_phase phase); + tb_dut_config #(dut_cfg) cfg_h; + if (!uvm_config_db#(tb_dut_config #(dut_cfg))::get(this, "", "tb_dut_config", cfg_h)) + `uvm_fatal(get_name(), "Couldn't get config object!") + + uvm_config_db + #( + virtual axis_if + #( .N(dut_cfg.axis_cfg_in.N) + , .I(dut_cfg.axis_cfg_in.I) + , .D(dut_cfg.axis_cfg_in.D) + , .U(dut_cfg.axis_cfg_in.U) + ) + )::set(this, "*agent_h", "axis_bus", cfg_h.dut_bus.axis_in); + + // // analysis + // coverage_h = coverage::type_id::create ("coverage_h",this); + // scoreboard_h = scoreboard::type_id::create("scoreboard",this); + + agent_h = axis_agent #(dut_cfg.axis_cfg_in)::type_id::create("agent_h", this); + + endfunction : build_phase + + // // -------------------------------------------------------------------- + // // + // function void connect_phase(uvm_phase phase); + + // endfunction : connect_phase + +// -------------------------------------------------------------------- +// +endclass : tb_env + +// -------------------------------------------------------------------- +// +endpackage: tb_axis_gear_box_pkg + + + + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_dut_if.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_dut_if.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tb_dut_if.sv (revision 50) @@ -0,0 +1,63 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +import tb_axis_gear_box_pkg::*; + +interface + tb_dut_if #(dut_config_t dut_cfg) + ( + input aclk, + input aresetn + ); + + // -------------------------------------------------------------------- + // + axis_if + #( + .N(dut_cfg.axis_cfg_in.N), + .I(dut_cfg.axis_cfg_in.I), + .D(dut_cfg.axis_cfg_in.D), + .U(dut_cfg.axis_cfg_in.U) + ) + axis_in(.*); + + // -------------------------------------------------------------------- + // + axis_if + #( + .N(dut_cfg.axis_cfg_out.N), + .I(dut_cfg.axis_cfg_out.I), + .D(dut_cfg.axis_cfg_out.D), + .U(dut_cfg.axis_cfg_out.U) + ) + axis_out(.*); + +// -------------------------------------------------------------------- +// +endinterface: tb_dut_if + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tests_base_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tests_base_pkg.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tests_base_pkg.sv (revision 50) @@ -0,0 +1,85 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// -------------------------------------------------------------------- +// +package tests_base_pkg; + + // -------------------------------------------------------------------- + // + import uvm_pkg::*; + `include "uvm_macros.svh" + import tb_axis_gear_box_pkg::*; + + // -------------------------------------------------------------------- + // + virtual class test_base extends uvm_test; + `uvm_component_utils(test_base); + tb_env env_h; + + // -------------------------------------------------------------------- + // + function void build_phase(uvm_phase phase); + env_h = tb_env::type_id::create("env_h",this); + endfunction : build_phase + + // -------------------------------------------------------------------- + // + function new (string name, uvm_component parent); + super.new(name,parent); + endfunction : new + + // -------------------------------------------------------------------- + // + endclass : test_base + + // -------------------------------------------------------------------- + // + class test_debug_base extends test_base; + `uvm_component_utils(test_debug_base) + + // -------------------------------------------------------------------- + // + function new (string name, uvm_component parent); + super.new(name,parent); + endfunction : new + + // -------------------------------------------------------------------- + // + function void final_phase(uvm_phase phase); + super.final_phase(phase); + $display("^^^ %16.t | %m | Test Done!!!", $time); + $stop; + endfunction : final_phase + + // -------------------------------------------------------------------- + // + endclass : test_debug_base + +// -------------------------------------------------------------------- +// +endpackage: tests_base_pkg Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tests_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tests_pkg.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/tests_pkg.sv (revision 50) @@ -0,0 +1,196 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// -------------------------------------------------------------------- +// +package tests_pkg; + + // -------------------------------------------------------------------- + // + import uvm_pkg::*; + `include "uvm_macros.svh" + import axis_pkg::*; + import tb_axis_gear_box_pkg::*; + import tests_base_pkg::*; + + // -------------------------------------------------------------------- + // + class t_counting extends test_base; + `uvm_component_utils(t_counting) + + // -------------------------------------------------------------------- + // + function new(string name = "my_test", uvm_component parent); + super.new(name, parent); + endfunction + + // -------------------------------------------------------------------- + // + virtual function void end_of_elaboration_phase(uvm_phase phase); + uvm_phase run_phase = uvm_run_phase::get(); + run_phase.phase_done.set_drain_time(this, 300ns); + endfunction + + // -------------------------------------------------------------------- + // + virtual task run_phase(uvm_phase phase); + axis_counting_sequence #(dut_cfg.axis_cfg_in) seq_h; + super.run_phase(phase); + phase.raise_objection(this); + fork + repeat(3) + begin + seq_h = axis_counting_sequence #(dut_cfg.axis_cfg_in)::type_id::create("seq_h"); + seq_h.start(env_h.agent_h.sequencer); + end + join + phase.drop_objection(this); + endtask : run_phase + + // -------------------------------------------------------------------- + // + endclass : t_counting + // -------------------------------------------------------------------- + // + + // -------------------------------------------------------------------- + // + class gear_box_sequence #(dut_config_t dut_cfg) + extends uvm_sequence #(axis_sequence_item #(dut_cfg.axis_cfg_in)); + `uvm_object_param_utils(gear_box_sequence #(dut_cfg)) + + rand int length = 7 * 3; + + // -------------------------------------------------------------------- + // + typedef logic [15:0] packed_data_t[7]; + + function packed_data_t next_data(int init); + static logic [15:0] previous_value; + logic [13:0] unpacked_data[8]; + logic [15:0] packed_data[7]; + + if(init == 0) + previous_value = 0; + + foreach(unpacked_data[i]) + begin + unpacked_data[i] = previous_value; + // $display("^^^ %16.t | unpacked_data[%0.d] = %h", $time, i, unpacked_data[i]); + previous_value++; + end + + packed_data = {<<16{{<<14{unpacked_data}}}}; + + // $display("^^^ %16.t | %p", $time, packed_data); + + // foreach(packed_data[i]) + // $display("^^^ %16.t | packed_data[%0.d] = %h", $time, i, packed_data[i]); + + next_data = packed_data; + endfunction + + + // -------------------------------------------------------------------- + // + virtual task body(); + localparam CHUNKS = 3; + axis_sequence_item #(dut_cfg.axis_cfg_in) item; + logic [15:0] data[7]; + + item = axis_sequence_item #(dut_cfg.axis_cfg_in)::type_id::create("axis_sequence_item"); + + for(int i = 0; i < CHUNKS; i++) + begin + data = next_data(i); + + foreach(data[k]) + begin + start_item(item); + item.tdata = data[k]; + item.tlast = (i == CHUNKS - 1) & (k == 0); + item.tuser = 0; + finish_item(item); + // $display("^^^ %16.t | %d | %x", $time, (i * 7) + k, item.tdata); + end + end + + endtask + + // -------------------------------------------------------------------- + // + function new(string name = "gear_box_sequence"); + super.new(name); + endfunction + + // -------------------------------------------------------------------- + // + endclass : gear_box_sequence + + // -------------------------------------------------------------------- + // + class t_debug extends test_debug_base; + `uvm_component_utils(t_debug) + + // -------------------------------------------------------------------- + // + function new(string name = "t_debug", uvm_component parent); + super.new(name, parent); + endfunction + + // -------------------------------------------------------------------- + // + function void end_of_elaboration_phase(uvm_phase phase); + uvm_phase run_phase = uvm_run_phase::get(); + run_phase.phase_done.set_drain_time(this, 300ns); + endfunction + + // -------------------------------------------------------------------- + // + virtual task run_phase(uvm_phase phase); + gear_box_sequence #(dut_cfg) seq_h; + super.run_phase(phase); + phase.raise_objection(this); + + fork + repeat(3) + begin + seq_h = gear_box_sequence #(dut_cfg)::type_id::create("seq_h"); + seq_h.start(env_h.agent_h.sequencer); + end + join + + phase.drop_objection(this); + endtask : run_phase + + // -------------------------------------------------------------------- + // + endclass : t_debug + +// -------------------------------------------------------------------- +// +endpackage: tests_pkg Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/wip.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/wip.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_gear_box/wip.do (revision 50) @@ -0,0 +1,11 @@ +# + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +vlog ./$env(SIM_TB)_pkg.sv +vlog ./tests_pkg.sv + +# simulation $root +vlog ./$env(SIM_TB).sv + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/init_test.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/init_test.do (revision 50) @@ -0,0 +1,35 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +set env(ROOT_DIR) ../../../../.. +set env(PROJECT_DIR) ../../.. +set env(SIM_TARGET) fpga + +# load sim procedures +do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do + +radix -hexadecimal + +make_lib work 1 + +# sim_compile_all FPGA +sim_compile_all sim +sim_compile_all sync_fifo +sim_compile_all axi4_stream_lib + +# simulation $root +vlog $env(PROJECT_DIR)/sim/src/tb_axis_register_slice.sv + +# compile test last +vlog ./the_test.sv + +# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top + +# run the sim +sim_run_test + + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/sim.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/sim.do (revision 50) @@ -0,0 +1,21 @@ +# +# + + +quit -sim + +# vsim opt_tb_top + +vsim -novopt work.tb_top +# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top + +# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top +# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top + + +# # log all signals +# log -r * + +# run -all + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/the_test.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/the_test.sv (revision 50) @@ -0,0 +1,79 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module + the_test( + input tb_clk, + input tb_rst + ); + + // -------------------------------------------------------------------- + // + int mismatch_count = 0; + + + // -------------------------------------------------------------------- + // + task run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.\n", $time); + $display("^^^---------------------------------"); + // -------------------------------------------------------------------- + + // -------------------------------------------------------------------- + tb_top.tb.timeout_stop(4us); + wait(~tb_rst); + + + // -------------------------------------------------------------------- + repeat(100) @(posedge tb_clk); + tb_top.avf_agent_h.make_frame("counting"); + tb_top.avf_agent_h.get_frame(); + tb_top.avf_agent_h.put_frame(); + + wait(~tb_top.avf_agent_h.put_frame_active); + wait(~tb_top.avf_agent_h.get_frame_active); + + mismatch_count = tb_top.avf_agent_h.compare_frame(); + + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/wip.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/wip.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_register_slice/wip.do (revision 50) @@ -0,0 +1,12 @@ +# + + +vlog -f ../../libs/axi4_stream_lib_verilog/axi4_stream_lib.f + +# simulation $root +vlog ../../src/tb_axis_register_slice.sv + +# compile test last +vlog ./the_test.sv + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/init_test.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/init_test.do (revision 50) @@ -0,0 +1,35 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +# setup environment +do ../../../../scripts/sim_env.do +set env(SIM_TARGET) fpga +set env(SIM_TB) tb_axis_switch_allocator + +radix -hexadecimal + +make_lib work 1 + +sim_compile_lib $env(LIB_BASE_DIR) tb_packages +sim_compile_lib $env(LIB_BASE_DIR) bfm_packages +sim_compile_lib $env(LIB_BASE_DIR) axi4_lib +sim_compile_lib $env(LIB_BASE_DIR) qaz_lib +sim_compile_lib $env(LIB_BASE_DIR) sim + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +# simulation $root +vlog ./$env(SIM_TB)_pkg.sv +vlog ./$env(SIM_TB).sv + +# compile test last +vlog ./the_test.sv + +# run the sim +sim_run_test + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/sim.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/sim.do (revision 50) @@ -0,0 +1,11 @@ +# +# + +quit -sim + +vsim -novopt work.tb_top +# vsim -f ./sim.f work.tb_top + +# log all signals +log -r * + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator.f (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator.f (revision 50) @@ -0,0 +1,6 @@ +# + +${PROJECT_DIR}/src/axis_switch.sv +${PROJECT_DIR}/src/recursive_axis_switch.sv + +${PROJECT_DIR}/src/axis_switch_allocator.sv Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator.sv (revision 50) @@ -0,0 +1,118 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// ---------------------------------------------------------------------------- + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + wire tb_rst_s; + wire aclk = tb_clk; + wire aresetn = ~tb_rst_s; + wire clk = tb_clk; + wire reset = tb_rst_s; + + sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); + + + // -------------------------------------------------------------------- + // + import tb_axis_switch_allocator_pkg::*; + + + // -------------------------------------------------------------------- + // + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*); + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[SD-1:0](.*); + + + // -------------------------------------------------------------------- + // + axis_switch_allocator #(.N(N), .I(I), .D(D), .U(U), .U_IS_EOP(U_IS_EOP), .SA(SA)) + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + + // -------------------------------------------------------------------- + // + tb_axis_switch_allocator_class a_h; + + initial + a_h = new(axis_in, axis_out); + + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test(tb_clk, tb_rst); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/tb_axis_switch_allocator_pkg.sv (revision 50) @@ -0,0 +1,143 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +package tb_axis_switch_allocator_pkg; + + // -------------------------------------------------------------------- + // + import video_frame_pkg::*; + import axis_video_frame_bfm_pkg::*; + import avf_agent_class_pkg::*; + + + // -------------------------------------------------------------------- + // + localparam AW = 32; // active width + localparam AH = 16; // active height + localparam B = 2; // bytes per pixel + localparam T = 1; // pixels per clock + localparam VERTICAL_BLANKING = AW * 4; + localparam N = B * T; // data bus width in bytes + localparam I = 1; // TID width + localparam D = 1; // TDEST width + localparam U = 3; // TUSER width + localparam U_IS_EOP = 2; + localparam SA = 3; + localparam SD = 2 ** SA; + + + // -------------------------------------------------------------------- + // + class tb_axis_switch_allocator_class; + + avf_config_class c_h; + avf_tile_config_t tile_config[]; + + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[]; + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in; + + avf_tx_class #(B, T, U) tx_h; + avf_rx_class #(B, T, U) rx_h; + + // video_frame_class clone_h; + // video_frame_class sent_f_h; + // video_frame_class rx_f_h; + + // mailbox #(video_frame_class) q[]; + + + // -------------------------------------------------------------------- + // + task automatic + queue_frame + ( + string pattern = "", + int pixel = 0 + ); + video_frame_class clone_h; + + if(pattern != "") + tx_h.make_frame(pattern, pixel); + + foreach(tx_h.tx_bfm_h[i]) + begin + clone_h = tx_h.tx_bfm_h[i].f_h.clone(); + tx_h.tx_bfm_h[i].put(clone_h); + // q[i].put(clone_h); + end + + $display("^^^ %16.t | %m | using %s pattern", $time, pattern); + + endtask: queue_frame + + + //-------------------------------------------------------------------- + // + function new + ( + virtual axis_if #(.N(N), .U(U)) axis_in, + virtual axis_if #(.N(N), .U(U)) axis_out[] + ); + + this.axis_out = axis_out; + this.axis_in = axis_in; + + this.tile_config = new[T]; + this.tile_config[0].direction = RIGHT_DOWN; + + this.c_h = new + ( + .width(AW), + .height(AH), + .bytes_per_pixel(B), + .bits_per_pixel(B * 8), + .pixels_per_clk(T), + .name("AVR_"), + .vertical_blanking(VERTICAL_BLANKING), + .tile(tile_config) + ); + + rx_h = new(c_h, axis_out); + tx_h = new(c_h, '{axis_in}); + + endfunction: new + + + // -------------------------------------------------------------------- + // + endclass: tb_axis_switch_allocator_class + + +// -------------------------------------------------------------------- +// +endpackage: tb_axis_switch_allocator_pkg + + + + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/the_test.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_switch_allocator/the_test.sv (revision 50) @@ -0,0 +1,88 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module the_test(input tb_clk, input tb_rst); + + // -------------------------------------------------------------------- + // + import tb_axis_switch_allocator_pkg::*; + + // -------------------------------------------------------------------- + // + int i = 0; + + task automatic run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.", $time); + $display("^^^---------------------------------"); + + // -------------------------------------------------------------------- + tb_top.tb.timeout_stop(2ms); + wait(~tb_rst); + + // -------------------------------------------------------------------- + #1us; + + // // -------------------------------------------------------------------- + // repeat(1)tb_top.a_h.queue_frame("counting"); + + // // -------------------------------------------------------------------- + // repeat(1) tb_top.a_h.queue_frame("random"); + // repeat(1)tb_top.a_h.queue_frame("counting"); + // repeat(3) tb_top.a_h.queue_frame("random"); + // tb_top.a_h.queue_frame("constant", 16'habba); + + // // -------------------------------------------------------------------- + // for(i = 0; i < SD; i++) + // begin + // #1us; + // tb_top.a_h.queue_frame("counting"); + // #8us; + // end + + // -------------------------------------------------------------------- + repeat(SD * 2) tb_top.a_h.queue_frame("counting"); + + // -------------------------------------------------------------------- + #100us; + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/init_test.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/init_test.do (revision 50) @@ -0,0 +1,34 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +# setup environment +do ../../../../scripts/sim_env.do +set env(SIM_TARGET) fpga +set env(SIM_TB) tb_axis_to_axi4_basic_dma + +radix -hexadecimal + +make_lib work 1 + +sim_compile_all tb_packages +sim_compile_all bfm_packages +sim_compile_all axi4_lib +sim_compile_all qaz_lib +sim_compile_all sim + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +# simulation $root +vlog ./$env(SIM_TB)_pkg.sv +vlog ./$env(SIM_TB).sv + +# compile test last +vlog ./the_test.sv + +# run the sim +sim_run_test + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/sim.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/sim.do (revision 50) @@ -0,0 +1,13 @@ +# +# + +quit -sim + +vsim -novopt work.tb_top + +# log all signals +log -r * + +# run -all + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.f (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.f (revision 50) @@ -0,0 +1,12 @@ +# + +${LIB_BASE_DIR}/axi4_stream_lib/sim/src/axis_bfm_pkg.sv +${LIB_BASE_DIR}/axi4_lib/sim/src/axi4_models/axi4_memory_pkg.sv + +${PROJECT_DIR}/sim/src/tb_axis_to_axi4_agent_class_pkg.sv + +${PROJECT_DIR}/src/axis_to_axi4_basic_dma.sv + +./${SIM_TB}_pkg.sv +./${SIM_TB}.sv + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma.sv (revision 50) @@ -0,0 +1,115 @@ +// -------------------------------------------------------------------- +// +// -------------------------------------------------------------------- + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_200mhz; + wire tb_clk = clk_200mhz; + wire tb_rst; + + tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + wire tb_rst_s; + wire aclk = tb_clk; + wire aresetn = ~tb_rst_s; + + sync_reset + sync_reset_i(aclk, tb_rst, tb_rst_s); + + + // -------------------------------------------------------------------- + // + import tb_axis_to_axi4_basic_dma_pkg::*; + + + // -------------------------------------------------------------------- + // + axi4_if #(.A(A), .N(N), .I(I)) axi4_m(.*); + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*); + + + // -------------------------------------------------------------------- + // + logic dma_enable = 0; + + axis_to_axi4_basic_dma + #( + .A(A), + .N(N), + .I(I), + .BASE_ADDRESS(BASE_ADDRESS), + .BUFFER_SIZE(BUFFER_SIZE), + .BURST_LENGTH(BURST_LENGTH), + .MAX_BURSTS(MAX_BURSTS), + .BYTES_PER_TUSER(BYTES_PER_TUSER) + ) + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + // -------------------------------------------------------------------- + // + axi4_checker #(.A(A), .N(N), .MAXWAITS(64)) + axi4_checker_i(.axi4_in(axi4_m)); + + + // -------------------------------------------------------------------- + // + axis_checker #(.N(N), .I(I), .D(D), .U(U), .MAXWAITS(64)) + axis_checker_i(.axis_in(axis_in)); + + + // -------------------------------------------------------------------- + // + tb_axis_to_axi4_basic_dma_class a_h; + + initial + a_h = new(axi4_m, axis_in); + + + // -------------------------------------------------------------------- + // + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test(tb_clk, tb_rst); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma_pkg.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/tb_axis_to_axi4_basic_dma_pkg.sv (revision 50) @@ -0,0 +1,58 @@ +// -------------------------------------------------------------------- +// +// -------------------------------------------------------------------- + + +package tb_axis_to_axi4_basic_dma_pkg; + + // -------------------------------------------------------------------- + // + import tb_axis_to_axi4_agent_class_pkg::*; + + + // -------------------------------------------------------------------- + // + localparam BASE_ADDRESS = 32'h0000_0000; // must be on 4K boundry + localparam BUFFER_SIZE = 'h800; + localparam BURST_LENGTH = 8'h08; + localparam MAX_BURSTS = 4; + localparam BYTES_PER_TUSER = 2; // bytes per tuser bit. Set to 0 for transfer based. + + localparam N = 8; // data bus width in bytes + localparam A = 32; // address bus width + localparam I = 1; // ID width + localparam D = 1; // TDEST width + localparam U = N / BYTES_PER_TUSER; // TUSER width + + + // -------------------------------------------------------------------- + // + class tb_axis_to_axi4_basic_dma_class + extends tb_axis_to_axi4_agent_class #(N, A, I, D, U); + + + //-------------------------------------------------------------------- + // + function new + ( + virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m, + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in + ); + + super.new(.axi4_m(axi4_m), .axis_in(axis_in)); + + endfunction: new + + + // -------------------------------------------------------------------- + // + endclass: tb_axis_to_axi4_basic_dma_class + +// -------------------------------------------------------------------- +// +endpackage: tb_axis_to_axi4_basic_dma_pkg + + + + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/the_test.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/the_test.sv (revision 50) @@ -0,0 +1,60 @@ +// -------------------------------------------------------------------- +// +// -------------------------------------------------------------------- + +`timescale 1ps/1ps + + +module + the_test( + input tb_clk, + input tb_rst + ); + + // -------------------------------------------------------------------- + // + import tb_axis_to_axi4_basic_dma_pkg::*; + + + // -------------------------------------------------------------------- + // + task run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.", $time); + $display("^^^---------------------------------"); + + // -------------------------------------------------------------------- + tb_top.tb.timeout_stop(50us); + + // -------------------------------------------------------------------- + wait(tb_top.aresetn); + #200ns; + + // -------------------------------------------------------------------- + force tb_top.dma_enable = 1; + #100ns; + + // -------------------------------------------------------------------- + repeat(8) + begin + tb_top.a_h.random_transaction(BASE_ADDRESS, BUFFER_SIZE, N * BURST_LENGTH); + tb_top.a_h.compare(BASE_ADDRESS); + end + + // -------------------------------------------------------------------- + #200ns; + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + +// -------------------------------------------------------------------- +// +endmodule + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/wip.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/wip.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_to_axi4_basic_dma/wip.do (revision 50) @@ -0,0 +1,11 @@ +# + +vlog -f ./tb_axis_to_axi4_basic_dma.f + +# simulation $root +vlog ./tb_axis_to_axi4_basic_dma.sv + +# compile test last +vlog ./the_test.sv + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/init_test.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/init_test.do (revision 50) @@ -0,0 +1,37 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +set env(ROOT_DIR) ../../../../.. +set env(PROJECT_DIR) ../../.. +set env(SIM_TARGET) fpga + +# load sim procedures +do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do + +radix -hexadecimal + +make_lib work 1 + +sim_compile_all tb_packages +sim_compile_all bfm_packages +sim_compile_all axi4_lib +sim_compile_all qaz_libs +sim_compile_all sim +vlog -f ./tb_axis_upsizer.f + +# simulation $root +vlog $env(PROJECT_DIR)/sim/src/tb_axis_upsizer.sv + +# compile test last +vlog ./the_test.sv + +# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top + +# run the sim +sim_run_test + + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/sim.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/sim.do (revision 50) @@ -0,0 +1,16 @@ +# +# + + +quit -sim + +# vsim opt_tb_top +vsim -novopt work.tb_top +# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top + +# log all signals +log -r * + +# run -all + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/tb_axis_upsizer.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/tb_axis_upsizer.f (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/tb_axis_upsizer.f (revision 50) @@ -0,0 +1,6 @@ +# + +${PROJECT_DIR}/sim/src/tb_axis_upsizer_agent_class_pkg.sv +${PROJECT_DIR}/sim/src/tb_axis_upsizer_class_pkg.sv + +${PROJECT_DIR}/src/axis_upsizer.sv Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/the_test.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_axis_upsizer/the_test.sv (revision 50) @@ -0,0 +1,98 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module + the_test( + input tb_clk, + input tb_rst + ); + + // -------------------------------------------------------------------- + // + int mismatch_count = 0; + + + // -------------------------------------------------------------------- + // + task run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.\n", $time); + $display("^^^---------------------------------"); + + // -------------------------------------------------------------------- + tb_top.tb.timeout_stop(50us); + + + // -------------------------------------------------------------------- + wait(tb_top.aresetn); + #1us; + + // -------------------------------------------------------------------- + repeat(3) tb_top.a_h.queue_frame("counting"); + repeat(3) tb_top.a_h.compare_frame(); + + // -------------------------------------------------------------------- + tb_top.a_h.tx_h.make_frame("constant", 16'habba); + tb_top.a_h.queue_frame(); + tb_top.a_h.compare_frame(); + + tb_top.a_h.queue_frame("random"); + tb_top.a_h.compare_frame(); + + tb_top.a_h.queue_frame("constant", 16'hbeef); + tb_top.a_h.compare_frame(); + + tb_top.a_h.queue_frame("random"); + tb_top.a_h.rx_h.wait_for_rx_frames(1); + tb_top.a_h.compare_frame(); + + tb_top.a_h.queue_frame("counting"); + tb_top.a_h.compare_frame(); + + repeat(3) tb_top.a_h.queue_frame("random"); + repeat(3) tb_top.a_h.compare_frame(); + + // -------------------------------------------------------------------- + #1us; + // #6us; + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/init_test.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/init_test.do (revision 50) @@ -0,0 +1,35 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +# setup environment +do ../../../../scripts/sim_env.do +set env(SIM_TARGET) fpga +set env(SIM_TB) tb_recursive_axis_catenate + +radix -hexadecimal + +make_lib work 1 + +sim_compile_lib $env(LIB_BASE_DIR) tb_packages +sim_compile_lib $env(LIB_BASE_DIR) bfm_packages +sim_compile_lib $env(LIB_BASE_DIR) axi4_lib +sim_compile_lib $env(LIB_BASE_DIR) qaz_lib +sim_compile_lib $env(LIB_BASE_DIR) sim + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +# simulation $root +vlog ./$env(SIM_TB)_pkg.sv +vlog ./$env(SIM_TB).sv + +# compile test last +vlog ./the_test.sv + +# run the sim +sim_run_test + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/sim.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/sim.do (revision 50) @@ -0,0 +1,11 @@ +# +# + +quit -sim + +vsim -novopt work.tb_top +# vsim -f ./sim.f work.tb_top + +# log all signals +log -r * + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/tb_recursive_axis_catenate.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/tb_recursive_axis_catenate.f (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/tb_recursive_axis_catenate.f (revision 50) @@ -0,0 +1,6 @@ +# + +${PROJECT_DIR}/src/recursive_axis_mux.sv +${PROJECT_DIR}/src/axis_catenate.sv +${PROJECT_DIR}/src/recursive_axis_catenate.sv + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/tb_recursive_axis_catenate.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/tb_recursive_axis_catenate.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/tb_recursive_axis_catenate.sv (revision 50) @@ -0,0 +1,126 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// ---------------------------------------------------------------------------- + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + wire tb_rst_s; + wire aclk = tb_clk; + wire aresetn = ~tb_rst_s; + wire clk = tb_clk; + wire reset = tb_rst_s; + + sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); + + + // -------------------------------------------------------------------- + // + import tb_recursive_axis_catenate_pkg::*; + + + // -------------------------------------------------------------------- + // + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[MD-1:0](.*); + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*); + + + // -------------------------------------------------------------------- + // + recursive_axis_catenate + #( + .N(N), + .I(I), + .D(D), + .U(U), + .U_IS_EOP(U_IS_EOP), + .MA(MA) + ) + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + + // -------------------------------------------------------------------- + // + tb_recursive_axis_catenate_class a_h; + + initial + a_h = new(axis_in, axis_out); + + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test(tb_clk, tb_rst); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/tb_recursive_axis_catenate_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/tb_recursive_axis_catenate_pkg.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/tb_recursive_axis_catenate_pkg.sv (revision 50) @@ -0,0 +1,144 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +package tb_recursive_axis_catenate_pkg; + + // -------------------------------------------------------------------- + // + import video_frame_pkg::*; + import axis_video_frame_bfm_pkg::*; + import avf_agent_class_pkg::*; + + + // -------------------------------------------------------------------- + // + localparam AW = 32; // active width + localparam AH = 16; // active height + localparam B = 2; // bytes per pixel + localparam T = 1; // pixels per clock + localparam VERTICAL_BLANKING = AW * 4; + localparam N = B * T; // data bus width in bytes + localparam I = 1; // TID width + localparam D = 1; // TDEST width + localparam U = 3; // TUSER width + // localparam U_IS_EOP = 2; + localparam U_IS_EOP = -1; + localparam MA = 2; + localparam MD = 2 ** MA; + + + // -------------------------------------------------------------------- + // + class tb_recursive_axis_catenate_class; + + avf_config_class c_h; + avf_tile_config_t tile_config[]; + + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out; + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[]; + + avf_tx_class #(B, T, U) tx_h; + avf_rx_class #(B, T, U) rx_h; + + // video_frame_class clone_h; + // video_frame_class sent_f_h; + // video_frame_class rx_f_h; + + // mailbox #(video_frame_class) q[]; + + + // -------------------------------------------------------------------- + // + task automatic + queue_frame + ( + string pattern = "", + int pixel = 0 + ); + video_frame_class clone_h; + + if(pattern != "") + tx_h.make_frame(pattern, pixel); + + foreach(tx_h.tx_bfm_h[i]) + begin + clone_h = tx_h.tx_bfm_h[i].f_h.clone(); + tx_h.tx_bfm_h[i].put(clone_h); + // q[i].put(clone_h); + end + + $display("^^^ %16.t | %m | using %s pattern", $time, pattern); + + endtask: queue_frame + + + //-------------------------------------------------------------------- + // + function new + ( + virtual axis_if #(.N(N), .U(U)) axis_in[], + virtual axis_if #(.N(N), .U(U)) axis_out + ); + + this.axis_out = axis_out; + this.axis_in = axis_in; + + this.tile_config = new[T]; + this.tile_config[0].direction = RIGHT_DOWN; + + this.c_h = new + ( + .width(AW), + .height(AH), + .bytes_per_pixel(B), + .bits_per_pixel(B * 8), + .pixels_per_clk(T), + .name("AVR_"), + .vertical_blanking(VERTICAL_BLANKING), + .tile(tile_config) + ); + + rx_h = new(c_h, '{axis_out}); + tx_h = new(c_h, axis_in); + + endfunction: new + + + // -------------------------------------------------------------------- + // + endclass: tb_recursive_axis_catenate_class + + +// -------------------------------------------------------------------- +// +endpackage: tb_recursive_axis_catenate_pkg + + + + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/the_test.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_catenate/the_test.sv (revision 50) @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module the_test(input tb_clk, input tb_rst); + + // -------------------------------------------------------------------- + // + import tb_recursive_axis_catenate_pkg::*; + + // -------------------------------------------------------------------- + // + int i = 0; + + task automatic run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.", $time); + $display("^^^---------------------------------"); + + // -------------------------------------------------------------------- + tb_top.tb.timeout_stop(2ms); + wait(~tb_rst); + + // -------------------------------------------------------------------- + #1us; + + // -------------------------------------------------------------------- + repeat(10)tb_top.a_h.queue_frame("counting"); + + // // -------------------------------------------------------------------- + // repeat(1) tb_top.a_h.queue_frame("random"); + // repeat(1)tb_top.a_h.queue_frame("counting"); + // repeat(3) tb_top.a_h.queue_frame("random"); + // tb_top.a_h.queue_frame("constant", 16'habba); + + // // -------------------------------------------------------------------- + // for(i = 0; i < MD; i++) + // begin + // force tb_top.select = i; + // #20us; + // end + + // -------------------------------------------------------------------- + #100us; + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/init_test.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/init_test.do (revision 50) @@ -0,0 +1,35 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +# setup environment +do ../../../../scripts/sim_env.do +set env(SIM_TARGET) fpga +set env(SIM_TB) tb_recursive_axis_mux + +radix -hexadecimal + +make_lib work 1 + +sim_compile_lib $env(LIB_BASE_DIR) tb_packages +sim_compile_lib $env(LIB_BASE_DIR) bfm_packages +sim_compile_lib $env(LIB_BASE_DIR) axi4_lib +sim_compile_lib $env(LIB_BASE_DIR) qaz_lib +sim_compile_lib $env(LIB_BASE_DIR) sim + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +# simulation $root +vlog ./$env(SIM_TB)_pkg.sv +vlog ./$env(SIM_TB).sv + +# compile test last +vlog ./the_test.sv + +# run the sim +sim_run_test + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/sim.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/sim.do (revision 50) @@ -0,0 +1,11 @@ +# +# + +quit -sim + +vsim -novopt work.tb_top +# vsim -f ./sim.f work.tb_top + +# log all signals +log -r * + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/tb_recursive_axis_mux.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/tb_recursive_axis_mux.f (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/tb_recursive_axis_mux.f (revision 50) @@ -0,0 +1,4 @@ +# + +${PROJECT_DIR}/src/recursive_axis_mux.sv + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/tb_recursive_axis_mux.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/tb_recursive_axis_mux.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/tb_recursive_axis_mux.sv (revision 50) @@ -0,0 +1,126 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// ---------------------------------------------------------------------------- + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + wire tb_rst_s; + wire aclk = tb_clk; + wire aresetn = ~tb_rst_s; + wire clk = tb_clk; + wire reset = tb_rst_s; + + sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); + + + // -------------------------------------------------------------------- + // + import tb_recursive_axis_mux_pkg::*; + + + // -------------------------------------------------------------------- + // + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[MD-1:0](.*); + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*); + + + // -------------------------------------------------------------------- + // + wire [MA-1:0] select = 0; + + recursive_axis_mux #(.N(N), .I(I), .D(D), .U(U), .MA(MA)) + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + + // -------------------------------------------------------------------- + // + initial + axis_out.cb_s.tready <= 1; + + + // -------------------------------------------------------------------- + // + tb_recursive_axis_mux_class a_h; + + initial + a_h = new(axis_in, axis_out); + + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test(tb_clk, tb_rst); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/tb_recursive_axis_mux_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/tb_recursive_axis_mux_pkg.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/tb_recursive_axis_mux_pkg.sv (revision 50) @@ -0,0 +1,142 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +package tb_recursive_axis_mux_pkg; + + // -------------------------------------------------------------------- + // + import video_frame_pkg::*; + import axis_video_frame_bfm_pkg::*; + import avf_agent_class_pkg::*; + + + // -------------------------------------------------------------------- + // + localparam AW = 32; // active width + localparam AH = 16; // active height + localparam B = 2; // bytes per pixel + localparam T = 1; // pixels per clock + localparam VERTICAL_BLANKING = AW * 4; + localparam N = B * T; // data bus width in bytes + localparam I = 1; // TID width + localparam D = 1; // TDEST width + localparam U = 3; // TUSER width + localparam MA = 5; + localparam MD = 2 ** MA; + + + // -------------------------------------------------------------------- + // + class tb_recursive_axis_mux_class; + + avf_config_class c_h; + avf_tile_config_t tile_config[]; + + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out; + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[]; + + avf_tx_class #(B, T, U) tx_h; + avf_rx_class #(B, T, U) rx_h; + + // video_frame_class clone_h; + // video_frame_class sent_f_h; + // video_frame_class rx_f_h; + + // mailbox #(video_frame_class) q[]; + + + // -------------------------------------------------------------------- + // + task automatic + queue_frame + ( + string pattern = "", + int pixel = 0 + ); + video_frame_class clone_h; + + if(pattern != "") + tx_h.make_frame(pattern, pixel); + + foreach(tx_h.tx_bfm_h[i]) + begin + clone_h = tx_h.tx_bfm_h[i].f_h.clone(); + tx_h.tx_bfm_h[i].put(clone_h); + // q[i].put(clone_h); + end + + $display("^^^ %16.t | %m | using %s pattern", $time, pattern); + + endtask: queue_frame + + + //-------------------------------------------------------------------- + // + function new + ( + virtual axis_if #(.N(N), .U(U)) axis_in[], + virtual axis_if #(.N(N), .U(U)) axis_out + ); + + this.axis_out = axis_out; + this.axis_in = axis_in; + + this.tile_config = new[T]; + this.tile_config[0].direction = RIGHT_DOWN; + + this.c_h = new + ( + .width(AW), + .height(AH), + .bytes_per_pixel(B), + .bits_per_pixel(B * 8), + .pixels_per_clk(T), + .name("AVR_"), + .vertical_blanking(VERTICAL_BLANKING), + .tile(tile_config) + ); + + rx_h = new(c_h, '{axis_out}); + tx_h = new(c_h, axis_in); + + endfunction: new + + + // -------------------------------------------------------------------- + // + endclass: tb_recursive_axis_mux_class + + +// -------------------------------------------------------------------- +// +endpackage: tb_recursive_axis_mux_pkg + + + + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/the_test.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_mux/the_test.sv (revision 50) @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module the_test(input tb_clk, input tb_rst); + + // -------------------------------------------------------------------- + // + import tb_recursive_axis_mux_pkg::*; + + // -------------------------------------------------------------------- + // + int i = 0; + + task automatic run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.", $time); + $display("^^^---------------------------------"); + + // -------------------------------------------------------------------- + // tb_top.tb.timeout_stop(2ms); + wait(~tb_rst); + + // -------------------------------------------------------------------- + #1us; + + // -------------------------------------------------------------------- + repeat(1)tb_top.a_h.queue_frame("counting"); + + // // -------------------------------------------------------------------- + // repeat(1) tb_top.a_h.queue_frame("random"); + // repeat(1)tb_top.a_h.queue_frame("counting"); + // repeat(3) tb_top.a_h.queue_frame("random"); + // tb_top.a_h.queue_frame("constant", 16'habba); + + // -------------------------------------------------------------------- + for(i = 0; i < MD; i++) + begin + force tb_top.select = i; + #20us; + end + + // -------------------------------------------------------------------- + #10us; + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/init_test.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/init_test.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/init_test.do (revision 50) @@ -0,0 +1,35 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +# setup environment +do ../../../../scripts/sim_env.do +set env(SIM_TARGET) fpga +set env(SIM_TB) tb_recursive_axis_switch + +radix -hexadecimal + +make_lib work 1 + +sim_compile_lib $env(LIB_BASE_DIR) tb_packages +sim_compile_lib $env(LIB_BASE_DIR) bfm_packages +sim_compile_lib $env(LIB_BASE_DIR) axi4_lib +sim_compile_lib $env(LIB_BASE_DIR) qaz_lib +sim_compile_lib $env(LIB_BASE_DIR) sim + +# compile simulation files +vlog -f ./$env(SIM_TB).f + +# simulation $root +vlog ./$env(SIM_TB)_pkg.sv +vlog ./$env(SIM_TB).sv + +# compile test last +vlog ./the_test.sv + +# run the sim +sim_run_test + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/sim.do =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/sim.do (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/sim.do (revision 50) @@ -0,0 +1,11 @@ +# +# + +quit -sim + +vsim -novopt work.tb_top +# vsim -f ./sim.f work.tb_top + +# log all signals +log -r * + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/tb_recursive_axis_switch.f =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/tb_recursive_axis_switch.f (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/tb_recursive_axis_switch.f (revision 50) @@ -0,0 +1,5 @@ +# + +${PROJECT_DIR}/src/axis_switch.sv +${PROJECT_DIR}/src/recursive_axis_switch.sv + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/tb_recursive_axis_switch.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/tb_recursive_axis_switch.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/tb_recursive_axis_switch.sv (revision 50) @@ -0,0 +1,127 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// ---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_100mhz; + wire tb_clk = clk_100mhz; + wire tb_rst; + + tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + wire tb_rst_s; + wire aclk = tb_clk; + wire aresetn = ~tb_rst_s; + wire clk = tb_clk; + wire reset = tb_rst_s; + + sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s); + + + // -------------------------------------------------------------------- + // + import tb_recursive_axis_switch_pkg::*; + + + // -------------------------------------------------------------------- + // + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*); + axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[SD-1:0](.*); + + + // -------------------------------------------------------------------- + // + wire [SA-1:0] select = 0; + + recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA)) + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + + // // -------------------------------------------------------------------- + // // + // initial + // axis_out.cb_s.tready <= 1; + + + // -------------------------------------------------------------------- + // + tb_recursive_axis_switch_class a_h; + + initial + a_h = new(axis_in, axis_out); + + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test(tb_clk, tb_rst); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/tb_recursive_axis_switch_pkg.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/tb_recursive_axis_switch_pkg.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/tb_recursive_axis_switch_pkg.sv (revision 50) @@ -0,0 +1,142 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +package tb_recursive_axis_switch_pkg; + + // -------------------------------------------------------------------- + // + import video_frame_pkg::*; + import axis_video_frame_bfm_pkg::*; + import avf_agent_class_pkg::*; + + + // -------------------------------------------------------------------- + // + localparam AW = 32; // active width + localparam AH = 16; // active height + localparam B = 2; // bytes per pixel + localparam T = 1; // pixels per clock + localparam VERTICAL_BLANKING = AW * 4; + localparam N = B * T; // data bus width in bytes + localparam I = 1; // TID width + localparam D = 1; // TDEST width + localparam U = 3; // TUSER width + localparam SA = 2; + localparam SD = 2 ** SA; + + + // -------------------------------------------------------------------- + // + class tb_recursive_axis_switch_class; + + avf_config_class c_h; + avf_tile_config_t tile_config[]; + + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out[]; + virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in; + + avf_tx_class #(B, T, U) tx_h; + avf_rx_class #(B, T, U) rx_h; + + // video_frame_class clone_h; + // video_frame_class sent_f_h; + // video_frame_class rx_f_h; + + // mailbox #(video_frame_class) q[]; + + + // -------------------------------------------------------------------- + // + task automatic + queue_frame + ( + string pattern = "", + int pixel = 0 + ); + video_frame_class clone_h; + + if(pattern != "") + tx_h.make_frame(pattern, pixel); + + foreach(tx_h.tx_bfm_h[i]) + begin + clone_h = tx_h.tx_bfm_h[i].f_h.clone(); + tx_h.tx_bfm_h[i].put(clone_h); + // q[i].put(clone_h); + end + + $display("^^^ %16.t | %m | using %s pattern", $time, pattern); + + endtask: queue_frame + + + //-------------------------------------------------------------------- + // + function new + ( + virtual axis_if #(.N(N), .U(U)) axis_in, + virtual axis_if #(.N(N), .U(U)) axis_out[] + ); + + this.axis_out = axis_out; + this.axis_in = axis_in; + + this.tile_config = new[T]; + this.tile_config[0].direction = RIGHT_DOWN; + + this.c_h = new + ( + .width(AW), + .height(AH), + .bytes_per_pixel(B), + .bits_per_pixel(B * 8), + .pixels_per_clk(T), + .name("AVR_"), + .vertical_blanking(VERTICAL_BLANKING), + .tile(tile_config) + ); + + rx_h = new(c_h, axis_out); + tx_h = new(c_h, '{axis_in}); + + endfunction: new + + + // -------------------------------------------------------------------- + // + endclass: tb_recursive_axis_switch_class + + +// -------------------------------------------------------------------- +// +endpackage: tb_recursive_axis_switch_pkg + + + + + Index: trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/the_test.sv =================================================================== --- trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/the_test.sv (nonexistent) +++ trunk/axi4_stream_lib/sim/tests/legacy/tb_recursive_axis_switch/the_test.sv (revision 50) @@ -0,0 +1,86 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2017 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module the_test(input tb_clk, input tb_rst); + + // -------------------------------------------------------------------- + // + import tb_recursive_axis_switch_pkg::*; + + // -------------------------------------------------------------------- + // + int i = 0; + + task automatic run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.", $time); + $display("^^^---------------------------------"); + + // -------------------------------------------------------------------- + tb_top.tb.timeout_stop(2ms); + wait(~tb_rst); + + // -------------------------------------------------------------------- + #1us; + + // // -------------------------------------------------------------------- + // repeat(1)tb_top.a_h.queue_frame("counting"); + + // // -------------------------------------------------------------------- + // repeat(1) tb_top.a_h.queue_frame("random"); + // repeat(1)tb_top.a_h.queue_frame("counting"); + // repeat(3) tb_top.a_h.queue_frame("random"); + // tb_top.a_h.queue_frame("constant", 16'habba); + + // -------------------------------------------------------------------- + for(i = 0; i < SD; i++) + begin + force tb_top.select = i; + #1us; + tb_top.a_h.queue_frame("counting"); + #8us; + end + + // -------------------------------------------------------------------- + #5us; + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: trunk/axi4_stream_lib/src/data_to_axis_fsm.sv =================================================================== --- trunk/axi4_stream_lib/src/data_to_axis_fsm.sv (revision 49) +++ trunk/axi4_stream_lib/src/data_to_axis_fsm.sv (nonexistent) @@ -1,106 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -module - data_to_axis_fsm - ( - input axis_en, - output axis_tvalid, - input axis_tready, - - input fifo_watermark, // OK to use fifo_almost_full if FIFO is synchronous, assert to flush also - input fifo_empty, - output fifo_rd_en, - - output data_to_axis_fsm_error, - - input aclk, - input aresetn - ); - - //--------------------------------------------------- - // state machine binary definitions - enum reg [3:0] { - IDLE_STATE = 4'b0001, - TVALID = 4'b0010, - TREADY = 4'b0100, - ERROR_STATE = 4'b1000 - } state, next_state; - - - //--------------------------------------------------- - // state machine flop - always_ff @(posedge aclk) - if(~aresetn) - state <= IDLE_STATE; - else - state <= next_state; - - - //--------------------------------------------------- - // state machine - always_comb - case(state) - IDLE_STATE: if(axis_en & fifo_watermark & ~fifo_empty) - if(axis_tready) - next_state <= TREADY; - else - next_state <= TVALID; - else - next_state <= IDLE_STATE; - - TVALID: if(axis_tready) // wait for slave to be ready - next_state <= TREADY; - else - next_state <= TVALID; - - TREADY: if(fifo_empty) // slave can accept data - next_state <= IDLE_STATE; - else if(axis_tready) - next_state <= TREADY; - else - next_state <= TVALID; - - ERROR_STATE: next_state <= IDLE_STATE; - - default: next_state <= ERROR_STATE; - - endcase - - - //--------------------------------------------------- - // outputs - assign axis_tvalid = (next_state == TVALID) | (next_state == TREADY); - assign fifo_rd_en = axis_tvalid & axis_tready; - assign data_to_axis_fsm_error = (state == ERROR_STATE); - - -endmodule - - - Index: trunk/axi4_stream_lib/src/axis_flow_control.sv =================================================================== --- trunk/axi4_stream_lib/src/axis_flow_control.sv (revision 49) +++ trunk/axi4_stream_lib/src/axis_flow_control.sv (nonexistent) @@ -1,127 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -module - axis_flow_control - #( - N = 8, // data bus width in bytes - I = 0, // TID width - D = 0, // TDEST width - U = 1, // TUSER width - USE_TSTRB = 0, // set to 1 to enable, 0 to disable - USE_TKEEP = 0 // set to 1 to enable, 0 to disable - ) - ( - input axis_en, - input flow_enable, // enable / disable incoming tready & tvalid - input [1:0] tready_to_master_select, // 00:force 0, 01:force 1, 1X:from_slave - input [1:0] tvalid_to_master_select, // 00:force 0, 01:force 1, 1X:from_slave - output tready_from_slave, // from input of mux - output tvalid_from_slave, // from input of mux - axis_if.slave axis_in, - axis_if.master axis_out, - input aclk, - input aresetn - ); - - // -------------------------------------------------------------------- - // - localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1; - - fifo_write_if #(.W(W)) fifo_sink(aclk, ~aresetn); - fifo_read_if #(.W(W)) fifo_source(aclk, ~aresetn); - - tiny_sync_fifo #(.W(W)) - tiny_sync_fifo_i(.source(fifo_sink.fifo), .sink(fifo_source.fifo)); - - - // -------------------------------------------------------------------- - // - wire data_to_axis_fsm_error; - - data_to_axis_fsm - data_to_axis_fsm_i - ( - .axis_tvalid(tvalid_from_slave), // axis_out.tvalid - .axis_tready(flow_enable & axis_out.tready), - .fifo_empty(fifo_source.empty), - .fifo_rd_en(fifo_source.rd_en), - .fifo_watermark(1'b1), - .* - ); - - - // -------------------------------------------------------------------- - // - reg axis_in_tready_r; - assign axis_in.tready = axis_in_tready_r; - - always_comb - case(tready_to_master_select) - 2'b00: axis_in_tready_r = 0; - 2'b01: axis_in_tready_r = 1; - 2'b10: axis_in_tready_r = tready_from_slave; - 2'b11: axis_in_tready_r = tready_from_slave; - endcase - - - // -------------------------------------------------------------------- - // - reg axis_out_tvalid_r; - assign axis_out.tvalid = axis_out_tvalid_r; - - always_comb - case(tvalid_to_master_select) - 2'b00: axis_out_tvalid_r = 0; - 2'b01: axis_out_tvalid_r = 1; - 2'b10: axis_out_tvalid_r = tvalid_from_slave; - 2'b11: axis_out_tvalid_r = tvalid_from_slave; - endcase - - - // -------------------------------------------------------------------- - // - assign tready_from_slave = ~fifo_sink.full; // axis_in.tready - - assign fifo_sink.wr_en = flow_enable & axis_in.tvalid & ~fifo_sink.full; - assign fifo_sink.wr_data = - { - axis_in.tdata, - axis_in.tlast, - axis_in.tuser - }; - - assign - { - axis_out.tdata, - axis_out.tlast, - axis_out.tuser - } = fifo_source.rd_data; - - -endmodule - Index: trunk/axi4_stream_lib/src/axis_to_memory.sv =================================================================== --- trunk/axi4_stream_lib/src/axis_to_memory.sv (nonexistent) +++ trunk/axi4_stream_lib/src/axis_to_memory.sv (revision 50) @@ -0,0 +1,129 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2019 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module + axis_to_memory + #( + W, // data width in bits + A, // address width in bits + P = 1 // pipeline delay + ) + ( + axis_if axis_ar, + axis_if axis_r, + output wr, + output [A-1:0] addr, + output [W-1:0] din, + input [W-1:0] dout, + input aclk, + input aresetn + ); + + // -------------------------------------------------------------------- + localparam CW = ($clog2(P) == 0) ? 1 : $clog2(P); + localparam D = 2 ** CW; + localparam UB = $clog2(D); + + // -------------------------------------------------------------------- + reg [P-1:0] pipeline; + wire ar = axis_ar.tready & axis_ar.tvalid; + wire rd_ready = pipeline[0]; + wire bypass; + + generate + if(P > 1) begin: pipeline_gen + always_ff @(posedge aclk) + if(~aresetn) + pipeline <= 0; + else + pipeline <= {ar, pipeline[P-1:1]}; + end + else begin: min_pipeline_gen // P == 1 + always_ff @(posedge aclk) + if(~aresetn) + pipeline <= 0; + else + pipeline <= ar; + end + endgenerate + + // -------------------------------------------------------------------- + wire wr_full; + wire [W-1:0] wr_data = dout; + wire wr_en = bypass ? 0 : rd_ready; + wire rd_empty; + wire [W-1:0] rd_data; + wire rd_en = axis_r.tready & axis_r.tvalid & ~bypass; + wire [UB:0] count; + + sync_fifo #(W, D) fifo_i(.clk(aclk), .reset(~aresetn), .*); + + // -------------------------------------------------------------------- + // assign bypass = rd_empty & (count != 0) & rd_ready; + assign bypass = 0; + + // // -------------------------------------------------------------------- + // logic [$clog2($bits(pipeline)+1)-1:0] in_pipeline; + + // always_comb begin + // in_pipeline = '0; + + // foreach(pipeline[idx]) begin + // in_pipeline += pipeline[idx]; + // end + // end + + // -------------------------------------------------------------------- + reg [$clog2($bits(pipeline)+1)-1:0] pipeline_count; + reg [$clog2($bits(pipeline)+1)-1:0] next_pipeline_count; + + always_comb + case({rd_ready, ar}) + 2'b0_0: next_pipeline_count = pipeline_count; + 2'b0_1: next_pipeline_count = pipeline_count + 1; + 2'b1_0: next_pipeline_count = pipeline_count - 1; + 2'b1_1: next_pipeline_count = pipeline_count; + endcase + + always_ff @(posedge aclk) + if(~aresetn) + pipeline_count <= 0; + else + pipeline_count <= next_pipeline_count; + + // -------------------------------------------------------------------- + assign axis_ar.tready = (pipeline_count + count < D) | rd_en; + assign axis_r.tdata = bypass ? dout : rd_data; + assign axis_r.tlast = 1; + assign axis_r.tvalid = ~rd_empty | bypass; + + // -------------------------------------------------------------------- + assign wr = 0; + // assign addr = axis_ar.tdata; + +// -------------------------------------------------------------------- +endmodule Index: trunk/basal/sim/src/fifo_agent_pkg.sv =================================================================== --- trunk/basal/sim/src/fifo_agent_pkg.sv (revision 49) +++ trunk/basal/sim/src/fifo_agent_pkg.sv (nonexistent) @@ -1,102 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package fifo_agent_pkg; - - // -------------------------------------------------------------------- - // - import fifo_bfm_pkg::*; - - class fifo_agent_class #(W = 8); - - fifo_bfm_class source_fifo; - fifo_bfm_class sink_fifo; - fifo_transaction_class tr_h; - fifo_transaction_class clone_h; - - //-------------------------------------------------------------------- - function - new - ( - virtual fifo_write_if #(.W(W)) source, - virtual fifo_read_if #(.W(W)) sink - ); - - this.source_fifo = new(.source(source)); - this.sink_fifo = new(.sink(sink)); - this.tr_h = new(); - - endfunction: new - - - // -------------------------------------------------------------------- - // - function void init; - - source_fifo.init("source", SOURCE); - sink_fifo.init("sink", SINK); - - endfunction: init - - - // -------------------------------------------------------------------- - // - task automatic - start_q; - - source_fifo.fifo_write_q(); - sink_fifo.fifo_read_q(); - - endtask: start_q - - - // -------------------------------------------------------------------- - // - task automatic - queue_random; - - if (!tr_h.randomize()) - begin - $display("^^^ %16.t | %m | ERROR! randomize error", $time); - $stop; - end - - clone_h = tr_h.clone(); - source_fifo.fifo_tr_q.put(clone_h); - sink_fifo.fifo_tr_q.put(clone_h); - - endtask: queue_random - - - // -------------------------------------------------------------------- - // - - endclass: fifo_agent_class - -endpackage: fifo_agent_pkg - Index: trunk/basal/sim/src/fifo_bfm_pkg.sv =================================================================== --- trunk/basal/sim/src/fifo_bfm_pkg.sv (revision 49) +++ trunk/basal/sim/src/fifo_bfm_pkg.sv (nonexistent) @@ -1,380 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -package fifo_bfm_pkg; - - typedef enum - { - SOURCE, - SINK, - BOTH - } fifo_type_t; - - // -------------------------------------------------------------------- - // - class fifo_transaction_class; - - rand int data; - rand int write_delay = 0; - rand int read_delay = 0; - - constraint default_write_delay - { - write_delay >= 0 && write_delay <= 4; - write_delay dist {0 := 60, [1:4] :=40 }; - } - - constraint default_read_delay - { - read_delay >= 0 && read_delay <= 4; - read_delay dist {0 := 60, [1:4] :=40 }; - } - - - // -------------------------------------------------------------------- - // - function void copy - ( - ref fifo_transaction_class from - ); - - // $display("^^^ %16.t | %m", $time); - - this.data = from.data; - this.write_delay = from.write_delay; - this.read_delay = from.read_delay; - - endfunction: copy - - - // -------------------------------------------------------------------- - // - extern virtual function fifo_transaction_class clone(); - // virtual function fifo_transaction_class clone(); - - // $display("^^^ %16.t | %m", $time); - - // clone = new(); - // clone.copy(this); - // return(clone); - - // endfunction: clone - - - // -------------------------------------------------------------------- - // - - endclass: fifo_transaction_class - - - // -------------------------------------------------------------------- - // - function fifo_transaction_class fifo_transaction_class::clone(); - - // $display("^^^ %16.t | %m", $time); - - clone = new(); - clone.copy(this); - - endfunction: clone - - - // -------------------------------------------------------------------- - // - class fifo_bfm_class #(W = 8); - - string fifo_name; - fifo_type_t fifo_type; - - virtual fifo_write_if #(.W(W)) source = null; - virtual fifo_read_if #(.W(W)) sink = null; - fifo_transaction_class fifo_tr = new(); - - - //-------------------------------------------------------------------- - function new - ( - virtual fifo_write_if #(.W(W)) source = null, - virtual fifo_read_if #(.W(W)) sink = null - ); - - if(source != null) - this.source = source; - - if(sink != null) - this.sink = sink; - - endfunction: new - - - // -------------------------------------------------------------------- - // - function void - init - ( - input string fifo_name, - input fifo_type_t fifo_type - ); - - this.fifo_name = fifo_name; - this.fifo_type = fifo_type; - - if(fifo_type == SOURCE) - source.cb_s.wr_en <= 0; - else if(fifo_type == SINK) - sink.cb_s.rd_en <= 0; - else if(fifo_type == BOTH) - if((this.source == null) | (this.sink == null)) - begin - $display("^^^ %16.t | %m | ERROR! %s fifo_type == BOTH with null class", $time, fifo_type.name); - $stop; - end - else - begin - source.cb_s.wr_en <= 0; - sink.cb_s.rd_en <= 0; - end - else - begin - $display("^^^ %16.t | %m | ERROR! fifo_type %s is invalid", $time, fifo_type.name); - $stop; - end - - $display("^^^ %16.t | %m | initialization of %s for %s", $time, fifo_name, fifo_type.name); - - endfunction: init - - - // -------------------------------------------------------------------- - // - task - write - ( - input [W-1:0] wr_data, - input int write_delay = 0 - ); - - source.cb_s.wr_data <= wr_data; - source.cb_s.wr_en <= 0; - - source.zero_cycle_delay(); - - if(write_delay != 0) - repeat(write_delay) @(source.cb_s); - - @(source.cb_s iff (source.cb_s.full == 0)); - // @(source.cb_s iff (~source.cb_s.full)); - source.cb_s.wr_en <= 1; - - @(posedge source.clk); - source.cb_s.wr_en <= 0; - - endtask: write - - - // -------------------------------------------------------------------- - // - task - fork_write - ( - input [W-1:0] wr_data, - input int write_delay = 0 - ); - - fork - write(wr_data, write_delay); - join_none - - #0; - - endtask: fork_write - - - // -------------------------------------------------------------------- - // - mailbox #(int) rd_data_q = new(); - - task - read - ( - input int read_delay = 0 - ); - - sink.cb_s.rd_en <= 0; - - sink.zero_cycle_delay(); - - if(read_delay != 0) - repeat(read_delay) @(sink.cb_s); - - @(sink.cb_s iff (sink.cb_s.empty == 0)); - // @(sink.cb_s iff (~sink.cb_s.empty)); - sink.cb_s.rd_en <= 1; - - @(posedge sink.clk); - - sink.cb_s.rd_en <= 0; - - rd_data_q.put(sink.cb_s.rd_data); - - endtask: read - - - // -------------------------------------------------------------------- - // - task automatic - fork_read - ( - input int read_delay = 0 - ); - - fork - read(read_delay); - join_none - - #0; - - endtask: fork_read - - - // -------------------------------------------------------------------- - // - mailbox #(fifo_transaction_class) fifo_tr_q; - semaphore fifo_tr_q_semaphore = new(1); - - - // -------------------------------------------------------------------- - // - event fifo_write_done; - - task automatic - fifo_write_q; - - if((fifo_type != SOURCE) & (fifo_type == BOTH)) - begin - $display("^^^ %16.t | %m | ERROR! wrong fifo_type |", $time); - return; - end - - if(fifo_tr_q_semaphore.try_get() == 0) - begin - $display("^^^ %16.t | %m | ERROR! fifo_tr_q_semaphore.try_get() == 0 |", $time); - return; - end - - $display("^^^ %16.t | %m is active |", $time); - - this.fifo_tr_q = new(); - - fifo_write_fork : fork - forever - begin - - fifo_tr_q.get(fifo_tr); - fork_write(fifo_tr.data, fifo_tr.write_delay); - - wait fork; - - ->fifo_write_done; - end - join_none - - #0; - - endtask: fifo_write_q - - - // -------------------------------------------------------------------- - // - fifo_transaction_class fifo_tr_clone; - event fifo_read_done; - logic [W - 1:0] rd_data; - logic [W - 1:0] rd_result; - int compare_result; - int compare_errors = 0; - - task automatic - fifo_read_q; - - if((fifo_type != SINK) & (fifo_type == BOTH)) - begin - $display("^^^ %16.t | %m | ERROR! wrong fifo_type |", $time); - return; - end - - - if(fifo_tr_q_semaphore.try_get() == 0) - begin - $display("^^^ %16.t | %m | ERROR! fifo_tr_q_semaphore.try_get() == 0 |", $time); - return; - end - - $display("^^^ %16.t | %m is active |", $time); - - this.fifo_tr_q = new(); - fifo_tr_clone = fifo_tr.clone(); - - fifo_read_q_fork : fork - forever - begin - - fifo_tr_q.get(fifo_tr); - fork_read(fifo_tr.read_delay); - - wait fork; - - ->fifo_read_done; - - rd_data_q.get(rd_result); - rd_data = fifo_tr.data; - - if(rd_result != rd_data) - begin - $display("^^^ %16.t | %m | ERROR! rd_result != fifo_tr.data |", $time); - $display("^^^ %16.t | %m | rd_result = %h |", $time, rd_result); - $display("^^^ %16.t | %m | fifo_tr.data = %h |", $time, fifo_tr.data); - end - - // compare_result = avf_in_frame.compare(8, f_h); - // compare_errors += compare_result; - - end - join_none - - #0; - - endtask: fifo_read_q - - - // -------------------------------------------------------------------- - // - - endclass: fifo_bfm_class - -endpackage: fifo_bfm_pkg - Index: trunk/basal/sim/src/legacy/fifo_agent_pkg.sv =================================================================== --- trunk/basal/sim/src/legacy/fifo_agent_pkg.sv (nonexistent) +++ trunk/basal/sim/src/legacy/fifo_agent_pkg.sv (revision 50) @@ -0,0 +1,102 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +package fifo_agent_pkg; + + // -------------------------------------------------------------------- + // + import fifo_bfm_pkg::*; + + class fifo_agent_class #(W = 8); + + fifo_bfm_class source_fifo; + fifo_bfm_class sink_fifo; + fifo_transaction_class tr_h; + fifo_transaction_class clone_h; + + //-------------------------------------------------------------------- + function + new + ( + virtual fifo_write_if #(.W(W)) source, + virtual fifo_read_if #(.W(W)) sink + ); + + this.source_fifo = new(.source(source)); + this.sink_fifo = new(.sink(sink)); + this.tr_h = new(); + + endfunction: new + + + // -------------------------------------------------------------------- + // + function void init; + + source_fifo.init("source", SOURCE); + sink_fifo.init("sink", SINK); + + endfunction: init + + + // -------------------------------------------------------------------- + // + task automatic + start_q; + + source_fifo.fifo_write_q(); + sink_fifo.fifo_read_q(); + + endtask: start_q + + + // -------------------------------------------------------------------- + // + task automatic + queue_random; + + if (!tr_h.randomize()) + begin + $display("^^^ %16.t | %m | ERROR! randomize error", $time); + $stop; + end + + clone_h = tr_h.clone(); + source_fifo.fifo_tr_q.put(clone_h); + sink_fifo.fifo_tr_q.put(clone_h); + + endtask: queue_random + + + // -------------------------------------------------------------------- + // + + endclass: fifo_agent_class + +endpackage: fifo_agent_pkg + Index: trunk/basal/sim/src/legacy/fifo_bfm_pkg.sv =================================================================== --- trunk/basal/sim/src/legacy/fifo_bfm_pkg.sv (nonexistent) +++ trunk/basal/sim/src/legacy/fifo_bfm_pkg.sv (revision 50) @@ -0,0 +1,380 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +package fifo_bfm_pkg; + + typedef enum + { + SOURCE, + SINK, + BOTH + } fifo_type_t; + + // -------------------------------------------------------------------- + // + class fifo_transaction_class; + + rand int data; + rand int write_delay = 0; + rand int read_delay = 0; + + constraint default_write_delay + { + write_delay >= 0 && write_delay <= 4; + write_delay dist {0 := 60, [1:4] :=40 }; + } + + constraint default_read_delay + { + read_delay >= 0 && read_delay <= 4; + read_delay dist {0 := 60, [1:4] :=40 }; + } + + + // -------------------------------------------------------------------- + // + function void copy + ( + ref fifo_transaction_class from + ); + + // $display("^^^ %16.t | %m", $time); + + this.data = from.data; + this.write_delay = from.write_delay; + this.read_delay = from.read_delay; + + endfunction: copy + + + // -------------------------------------------------------------------- + // + extern virtual function fifo_transaction_class clone(); + // virtual function fifo_transaction_class clone(); + + // $display("^^^ %16.t | %m", $time); + + // clone = new(); + // clone.copy(this); + // return(clone); + + // endfunction: clone + + + // -------------------------------------------------------------------- + // + + endclass: fifo_transaction_class + + + // -------------------------------------------------------------------- + // + function fifo_transaction_class fifo_transaction_class::clone(); + + // $display("^^^ %16.t | %m", $time); + + clone = new(); + clone.copy(this); + + endfunction: clone + + + // -------------------------------------------------------------------- + // + class fifo_bfm_class #(W = 8); + + string fifo_name; + fifo_type_t fifo_type; + + virtual fifo_write_if #(.W(W)) source = null; + virtual fifo_read_if #(.W(W)) sink = null; + fifo_transaction_class fifo_tr = new(); + + + //-------------------------------------------------------------------- + function new + ( + virtual fifo_write_if #(.W(W)) source = null, + virtual fifo_read_if #(.W(W)) sink = null + ); + + if(source != null) + this.source = source; + + if(sink != null) + this.sink = sink; + + endfunction: new + + + // -------------------------------------------------------------------- + // + function void + init + ( + input string fifo_name, + input fifo_type_t fifo_type + ); + + this.fifo_name = fifo_name; + this.fifo_type = fifo_type; + + if(fifo_type == SOURCE) + source.cb_s.wr_en <= 0; + else if(fifo_type == SINK) + sink.cb_s.rd_en <= 0; + else if(fifo_type == BOTH) + if((this.source == null) | (this.sink == null)) + begin + $display("^^^ %16.t | %m | ERROR! %s fifo_type == BOTH with null class", $time, fifo_type.name); + $stop; + end + else + begin + source.cb_s.wr_en <= 0; + sink.cb_s.rd_en <= 0; + end + else + begin + $display("^^^ %16.t | %m | ERROR! fifo_type %s is invalid", $time, fifo_type.name); + $stop; + end + + $display("^^^ %16.t | %m | initialization of %s for %s", $time, fifo_name, fifo_type.name); + + endfunction: init + + + // -------------------------------------------------------------------- + // + task + write + ( + input [W-1:0] wr_data, + input int write_delay = 0 + ); + + source.cb_s.wr_data <= wr_data; + source.cb_s.wr_en <= 0; + + source.zero_cycle_delay(); + + if(write_delay != 0) + repeat(write_delay) @(source.cb_s); + + @(source.cb_s iff (source.cb_s.full == 0)); + // @(source.cb_s iff (~source.cb_s.full)); + source.cb_s.wr_en <= 1; + + @(posedge source.clk); + source.cb_s.wr_en <= 0; + + endtask: write + + + // -------------------------------------------------------------------- + // + task + fork_write + ( + input [W-1:0] wr_data, + input int write_delay = 0 + ); + + fork + write(wr_data, write_delay); + join_none + + #0; + + endtask: fork_write + + + // -------------------------------------------------------------------- + // + mailbox #(int) rd_data_q = new(); + + task + read + ( + input int read_delay = 0 + ); + + sink.cb_s.rd_en <= 0; + + sink.zero_cycle_delay(); + + if(read_delay != 0) + repeat(read_delay) @(sink.cb_s); + + @(sink.cb_s iff (sink.cb_s.empty == 0)); + // @(sink.cb_s iff (~sink.cb_s.empty)); + sink.cb_s.rd_en <= 1; + + @(posedge sink.clk); + + sink.cb_s.rd_en <= 0; + + rd_data_q.put(sink.cb_s.rd_data); + + endtask: read + + + // -------------------------------------------------------------------- + // + task automatic + fork_read + ( + input int read_delay = 0 + ); + + fork + read(read_delay); + join_none + + #0; + + endtask: fork_read + + + // -------------------------------------------------------------------- + // + mailbox #(fifo_transaction_class) fifo_tr_q; + semaphore fifo_tr_q_semaphore = new(1); + + + // -------------------------------------------------------------------- + // + event fifo_write_done; + + task automatic + fifo_write_q; + + if((fifo_type != SOURCE) & (fifo_type == BOTH)) + begin + $display("^^^ %16.t | %m | ERROR! wrong fifo_type |", $time); + return; + end + + if(fifo_tr_q_semaphore.try_get() == 0) + begin + $display("^^^ %16.t | %m | ERROR! fifo_tr_q_semaphore.try_get() == 0 |", $time); + return; + end + + $display("^^^ %16.t | %m is active |", $time); + + this.fifo_tr_q = new(); + + fifo_write_fork : fork + forever + begin + + fifo_tr_q.get(fifo_tr); + fork_write(fifo_tr.data, fifo_tr.write_delay); + + wait fork; + + ->fifo_write_done; + end + join_none + + #0; + + endtask: fifo_write_q + + + // -------------------------------------------------------------------- + // + fifo_transaction_class fifo_tr_clone; + event fifo_read_done; + logic [W - 1:0] rd_data; + logic [W - 1:0] rd_result; + int compare_result; + int compare_errors = 0; + + task automatic + fifo_read_q; + + if((fifo_type != SINK) & (fifo_type == BOTH)) + begin + $display("^^^ %16.t | %m | ERROR! wrong fifo_type |", $time); + return; + end + + + if(fifo_tr_q_semaphore.try_get() == 0) + begin + $display("^^^ %16.t | %m | ERROR! fifo_tr_q_semaphore.try_get() == 0 |", $time); + return; + end + + $display("^^^ %16.t | %m is active |", $time); + + this.fifo_tr_q = new(); + fifo_tr_clone = fifo_tr.clone(); + + fifo_read_q_fork : fork + forever + begin + + fifo_tr_q.get(fifo_tr); + fork_read(fifo_tr.read_delay); + + wait fork; + + ->fifo_read_done; + + rd_data_q.get(rd_result); + rd_data = fifo_tr.data; + + if(rd_result != rd_data) + begin + $display("^^^ %16.t | %m | ERROR! rd_result != fifo_tr.data |", $time); + $display("^^^ %16.t | %m | rd_result = %h |", $time, rd_result); + $display("^^^ %16.t | %m | fifo_tr.data = %h |", $time, fifo_tr.data); + end + + // compare_result = avf_in_frame.compare(8, f_h); + // compare_errors += compare_result; + + end + join_none + + #0; + + endtask: fifo_read_q + + + // -------------------------------------------------------------------- + // + + endclass: fifo_bfm_class + +endpackage: fifo_bfm_pkg + Index: trunk/basal/sim/tests/tb_tiny_async_fifo/tb_tiny_async_fifo.sv =================================================================== --- trunk/basal/sim/tests/tb_tiny_async_fifo/tb_tiny_async_fifo.sv (revision 49) +++ trunk/basal/sim/tests/tb_tiny_async_fifo/tb_tiny_async_fifo.sv (nonexistent) @@ -1,122 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_200mhz; - wire tb_clk = clk_200mhz; - wire tb_rst; - wire aclk = tb_clk; - wire aresetn = ~tb_rst; - - tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); - - // wire clk_100mhz; - // tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz); - - - // -------------------------------------------------------------------- - // - localparam W = 8; - - fifo_write_if #(.W(W)) source(clk_200mhz, tb_rst); - fifo_read_if #(.W(W)) sink(clk_200mhz, tb_rst); - - - // -------------------------------------------------------------------- - // - tiny_async_fifo - dut(.*); - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - // -------------------------------------------------------------------- - // - // import fifo_bfm_pkg::*; - - // fifo_bfm_class bfm = new(source, sink); - - // initial - // bfm.init("", BOTH); - - - // -------------------------------------------------------------------- - // - import fifo_agent_pkg::*; - - fifo_agent_class bfm = new(source, sink); - - initial - begin - bfm.init(); - bfm.start_q(); - end - - - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - - - // -------------------------------------------------------------------- - // test - the_test test( tb_clk, tb_rst ); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule - - - Index: trunk/basal/sim/tests/tb_tiny_async_fifo/wip.do =================================================================== --- trunk/basal/sim/tests/tb_tiny_async_fifo/wip.do (revision 49) +++ trunk/basal/sim/tests/tb_tiny_async_fifo/wip.do (nonexistent) @@ -1,13 +0,0 @@ -# - - -vlog -f ../../libs/async_fifo_verilog/tiny_async_fifo.f -# vlog -f ../../libs/sim_verilog/fifo_bfm.f - -# simulation $root -vlog ../../src/tb_tiny_async_fifo.sv - -# compile test last -vlog ./the_test.sv - - Index: trunk/basal/sim/tests/tb_tiny_async_fifo/init_test.do =================================================================== --- trunk/basal/sim/tests/tb_tiny_async_fifo/init_test.do (revision 49) +++ trunk/basal/sim/tests/tb_tiny_async_fifo/init_test.do (nonexistent) @@ -1,33 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -set env(ROOT_DIR) ../../../../.. -set env(PROJECT_DIR) ../../.. -set env(SIM_TARGET) fpga - -# load sim procedures -do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do - -radix -hexadecimal - -make_lib work 1 - -sim_compile_all async_fifo -sim_compile_all sim - -# simulation $root -vlog $env(PROJECT_DIR)/sim/src/tb_tiny_async_fifo.sv - -# compile test last -vlog ./the_test.sv - -# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top - -# run the sim -sim_run_test - - - Index: trunk/basal/sim/tests/tb_tiny_async_fifo/the_test.sv =================================================================== --- trunk/basal/sim/tests/tb_tiny_async_fifo/the_test.sv (revision 49) +++ trunk/basal/sim/tests/tb_tiny_async_fifo/the_test.sv (nonexistent) @@ -1,77 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - - -module - the_test( - input tb_clk, - input tb_rst - ); - - // -------------------------------------------------------------------- - // - int data; - - - // -------------------------------------------------------------------- - // - task run_the_test; - - // -------------------------------------------------------------------- - // insert test below - // -------------------------------------------------------------------- - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench begun.\n", $time); - $display("^^^---------------------------------"); - // -------------------------------------------------------------------- - - tb_top.tb.timeout_stop(1000ms); - - - // -------------------------------------------------------------------- - wait(~tb_rst); - - - // -------------------------------------------------------------------- - - repeat(20) @(posedge tb_clk); - - repeat(100) tb_top.bfm.queue_random(); - repeat(500) @(posedge tb_clk); - - - // -------------------------------------------------------------------- - // insert test above - // -------------------------------------------------------------------- - - endtask - - -endmodule - Index: trunk/basal/sim/tests/tb_tiny_async_fifo/sim.do =================================================================== --- trunk/basal/sim/tests/tb_tiny_async_fifo/sim.do (revision 49) +++ trunk/basal/sim/tests/tb_tiny_async_fifo/sim.do (nonexistent) @@ -1,21 +0,0 @@ -# -# - - -quit -sim - -# vsim opt_tb_top - -vsim -novopt work.tb_top -# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top - -# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top -# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top - - -# # log all signals -# log -r * - -# run -all - - Index: trunk/basal/sim/tests/tb_tiny_sync_fifo/the_test.sv =================================================================== --- trunk/basal/sim/tests/tb_tiny_sync_fifo/the_test.sv (revision 49) +++ trunk/basal/sim/tests/tb_tiny_sync_fifo/the_test.sv (nonexistent) @@ -1,88 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - - -module - the_test( - input tb_clk, - input tb_rst - ); - - // -------------------------------------------------------------------- - // - int data; - - - // -------------------------------------------------------------------- - // - task run_the_test; - - // -------------------------------------------------------------------- - // insert test below - // -------------------------------------------------------------------- - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench begun.\n", $time); - $display("^^^---------------------------------"); - // -------------------------------------------------------------------- - - tb_top.tb.timeout_stop(1000ms); - - - // -------------------------------------------------------------------- - wait(~tb_rst); - - - // -------------------------------------------------------------------- - - repeat(10) @(posedge tb_clk); - - repeat(100) tb_top.bfm.queue_random(); - - - // tb_top.bfm.write(8'h22, 0); - // tb_top.bfm.write(8'haa, 0); - // tb_top.bfm.read(10); - // tb_top.bfm.write(8'hff, 5); - // tb_top.bfm.read(0); - // tb_top.bfm.read(0); - // tb_top.bfm.write(8'h11, 1); - - - repeat(1000) @(posedge tb_clk); - - - // -------------------------------------------------------------------- - // insert test above - // -------------------------------------------------------------------- - - endtask - - -endmodule - Index: trunk/basal/sim/tests/tb_tiny_sync_fifo/sim.do =================================================================== --- trunk/basal/sim/tests/tb_tiny_sync_fifo/sim.do (revision 49) +++ trunk/basal/sim/tests/tb_tiny_sync_fifo/sim.do (nonexistent) @@ -1,21 +0,0 @@ -# -# - - -quit -sim - -# vsim opt_tb_top - -vsim -novopt work.tb_top -# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top - -# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top -# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top - - -# # log all signals -# log -r * - -# run -all - - Index: trunk/basal/sim/tests/tb_tiny_sync_fifo/tb_tiny_sync_fifo.sv =================================================================== --- trunk/basal/sim/tests/tb_tiny_sync_fifo/tb_tiny_sync_fifo.sv (revision 49) +++ trunk/basal/sim/tests/tb_tiny_sync_fifo/tb_tiny_sync_fifo.sv (nonexistent) @@ -1,122 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -module tb_top(); - - // -------------------------------------------------------------------- - // test bench clock & reset - wire clk_200mhz; - wire tb_clk = clk_200mhz; - wire tb_rst; - wire aclk = tb_clk; - wire aresetn = ~tb_rst; - - tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); - - // wire clk_100mhz; - // tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz); - - - // -------------------------------------------------------------------- - // - localparam W = 8; - - fifo_write_if #(.W(W)) source(clk_200mhz, tb_rst); - fifo_read_if #(.W(W)) sink(clk_200mhz, tb_rst); - - - // -------------------------------------------------------------------- - // - tiny_sync_fifo - dut(.*); - - - // -------------------------------------------------------------------- - // sim models - // | | | | | | | | | | | | | | | | | - // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - - // -------------------------------------------------------------------- - // - // import fifo_bfm_pkg::*; - - // fifo_bfm_class bfm = new(source, sink); - - // initial - // bfm.init("", BOTH); - - - // -------------------------------------------------------------------- - // - import fifo_agent_pkg::*; - - fifo_agent_class bfm = new(source, sink); - - initial - begin - bfm.init(); - bfm.start_q(); - end - - - - // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' - // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ - // | | | | | | | | | | | | | | | | | - // sim models - // -------------------------------------------------------------------- - - - // -------------------------------------------------------------------- - // debug wires - - - // -------------------------------------------------------------------- - // test - the_test test( tb_clk, tb_rst ); - - initial - begin - - test.run_the_test(); - - $display("^^^---------------------------------"); - $display("^^^ %16.t | Testbench done.", $time); - $display("^^^---------------------------------"); - - $display("^^^---------------------------------"); - - $stop(); - - end - -endmodule - - - Index: trunk/basal/sim/tests/tb_tiny_sync_fifo/wip.do =================================================================== --- trunk/basal/sim/tests/tb_tiny_sync_fifo/wip.do (revision 49) +++ trunk/basal/sim/tests/tb_tiny_sync_fifo/wip.do (nonexistent) @@ -1,13 +0,0 @@ -# - - -vlog -f ../../libs/FPGA_verilog/tiny_fifo.f -vlog -f ../../libs/sim_verilog/fifo_bfm.f - -# simulation $root -vlog ../../src/tb_tiny_sync_fifo.sv - -# compile test last -vlog ./the_test.sv - - Index: trunk/basal/sim/tests/tb_tiny_sync_fifo/init_test.do =================================================================== --- trunk/basal/sim/tests/tb_tiny_sync_fifo/init_test.do (revision 49) +++ trunk/basal/sim/tests/tb_tiny_sync_fifo/init_test.do (nonexistent) @@ -1,33 +0,0 @@ -# ------------------------------------ -# -# ------------------------------------ - -global env - -set env(ROOT_DIR) ../../../../.. -set env(PROJECT_DIR) ../../.. -set env(SIM_TARGET) fpga - -# load sim procedures -do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do - -radix -hexadecimal - -make_lib work 1 - -sim_compile_all sync_fifo -sim_compile_all sim - -# simulation $root -vlog $env(PROJECT_DIR)/sim/src/tb_tiny_sync_fifo.sv - -# compile test last -vlog ./the_test.sv - -# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top - -# run the sim -sim_run_test - - - Index: trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/init_test.do =================================================================== --- trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/init_test.do (nonexistent) +++ trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/init_test.do (revision 50) @@ -0,0 +1,33 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +set env(ROOT_DIR) ../../../../.. +set env(PROJECT_DIR) ../../.. +set env(SIM_TARGET) fpga + +# load sim procedures +do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do + +radix -hexadecimal + +make_lib work 1 + +sim_compile_all async_fifo +sim_compile_all sim + +# simulation $root +vlog $env(PROJECT_DIR)/sim/src/tb_tiny_async_fifo.sv + +# compile test last +vlog ./the_test.sv + +# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top + +# run the sim +sim_run_test + + + Index: trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/sim.do =================================================================== --- trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/sim.do (nonexistent) +++ trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/sim.do (revision 50) @@ -0,0 +1,21 @@ +# +# + + +quit -sim + +# vsim opt_tb_top + +vsim -novopt work.tb_top +# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top + +# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top +# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top + + +# # log all signals +# log -r * + +# run -all + + Index: trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/tb_tiny_async_fifo.sv =================================================================== --- trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/tb_tiny_async_fifo.sv (nonexistent) +++ trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/tb_tiny_async_fifo.sv (revision 50) @@ -0,0 +1,122 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_200mhz; + wire tb_clk = clk_200mhz; + wire tb_rst; + wire aclk = tb_clk; + wire aresetn = ~tb_rst; + + tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); + + // wire clk_100mhz; + // tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz); + + + // -------------------------------------------------------------------- + // + localparam W = 8; + + fifo_write_if #(.W(W)) source(clk_200mhz, tb_rst); + fifo_read_if #(.W(W)) sink(clk_200mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + tiny_async_fifo + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + // -------------------------------------------------------------------- + // + // import fifo_bfm_pkg::*; + + // fifo_bfm_class bfm = new(source, sink); + + // initial + // bfm.init("", BOTH); + + + // -------------------------------------------------------------------- + // + import fifo_agent_pkg::*; + + fifo_agent_class bfm = new(source, sink); + + initial + begin + bfm.init(); + bfm.start_q(); + end + + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test( tb_clk, tb_rst ); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/the_test.sv =================================================================== --- trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/the_test.sv (nonexistent) +++ trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/the_test.sv (revision 50) @@ -0,0 +1,77 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module + the_test( + input tb_clk, + input tb_rst + ); + + // -------------------------------------------------------------------- + // + int data; + + + // -------------------------------------------------------------------- + // + task run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.\n", $time); + $display("^^^---------------------------------"); + // -------------------------------------------------------------------- + + tb_top.tb.timeout_stop(1000ms); + + + // -------------------------------------------------------------------- + wait(~tb_rst); + + + // -------------------------------------------------------------------- + + repeat(20) @(posedge tb_clk); + + repeat(100) tb_top.bfm.queue_random(); + repeat(500) @(posedge tb_clk); + + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/wip.do =================================================================== --- trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/wip.do (nonexistent) +++ trunk/basal/sim/tests/legacy/tb_tiny_async_fifo/wip.do (revision 50) @@ -0,0 +1,13 @@ +# + + +vlog -f ../../libs/async_fifo_verilog/tiny_async_fifo.f +# vlog -f ../../libs/sim_verilog/fifo_bfm.f + +# simulation $root +vlog ../../src/tb_tiny_async_fifo.sv + +# compile test last +vlog ./the_test.sv + + Index: trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/init_test.do =================================================================== --- trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/init_test.do (nonexistent) +++ trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/init_test.do (revision 50) @@ -0,0 +1,33 @@ +# ------------------------------------ +# +# ------------------------------------ + +global env + +set env(ROOT_DIR) ../../../../.. +set env(PROJECT_DIR) ../../.. +set env(SIM_TARGET) fpga + +# load sim procedures +do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do + +radix -hexadecimal + +make_lib work 1 + +sim_compile_all sync_fifo +sim_compile_all sim + +# simulation $root +vlog $env(PROJECT_DIR)/sim/src/tb_tiny_sync_fifo.sv + +# compile test last +vlog ./the_test.sv + +# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top + +# run the sim +sim_run_test + + + Index: trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/sim.do =================================================================== --- trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/sim.do (nonexistent) +++ trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/sim.do (revision 50) @@ -0,0 +1,21 @@ +# +# + + +quit -sim + +# vsim opt_tb_top + +vsim -novopt work.tb_top +# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top + +# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top +# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top + + +# # log all signals +# log -r * + +# run -all + + Index: trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/tb_tiny_sync_fifo.sv =================================================================== --- trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/tb_tiny_sync_fifo.sv (nonexistent) +++ trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/tb_tiny_sync_fifo.sv (revision 50) @@ -0,0 +1,122 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +module tb_top(); + + // -------------------------------------------------------------------- + // test bench clock & reset + wire clk_200mhz; + wire tb_clk = clk_200mhz; + wire tb_rst; + wire aclk = tb_clk; + wire aresetn = ~tb_rst; + + tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); + + // wire clk_100mhz; + // tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz); + + + // -------------------------------------------------------------------- + // + localparam W = 8; + + fifo_write_if #(.W(W)) source(clk_200mhz, tb_rst); + fifo_read_if #(.W(W)) sink(clk_200mhz, tb_rst); + + + // -------------------------------------------------------------------- + // + tiny_sync_fifo + dut(.*); + + + // -------------------------------------------------------------------- + // sim models + // | | | | | | | | | | | | | | | | | + // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + + // -------------------------------------------------------------------- + // + // import fifo_bfm_pkg::*; + + // fifo_bfm_class bfm = new(source, sink); + + // initial + // bfm.init("", BOTH); + + + // -------------------------------------------------------------------- + // + import fifo_agent_pkg::*; + + fifo_agent_class bfm = new(source, sink); + + initial + begin + bfm.init(); + bfm.start_q(); + end + + + + // ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' + // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ + // | | | | | | | | | | | | | | | | | + // sim models + // -------------------------------------------------------------------- + + + // -------------------------------------------------------------------- + // debug wires + + + // -------------------------------------------------------------------- + // test + the_test test( tb_clk, tb_rst ); + + initial + begin + + test.run_the_test(); + + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench done.", $time); + $display("^^^---------------------------------"); + + $display("^^^---------------------------------"); + + $stop(); + + end + +endmodule + + + Index: trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/the_test.sv =================================================================== --- trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/the_test.sv (nonexistent) +++ trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/the_test.sv (revision 50) @@ -0,0 +1,88 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2015 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + + +module + the_test( + input tb_clk, + input tb_rst + ); + + // -------------------------------------------------------------------- + // + int data; + + + // -------------------------------------------------------------------- + // + task run_the_test; + + // -------------------------------------------------------------------- + // insert test below + // -------------------------------------------------------------------- + $display("^^^---------------------------------"); + $display("^^^ %16.t | Testbench begun.\n", $time); + $display("^^^---------------------------------"); + // -------------------------------------------------------------------- + + tb_top.tb.timeout_stop(1000ms); + + + // -------------------------------------------------------------------- + wait(~tb_rst); + + + // -------------------------------------------------------------------- + + repeat(10) @(posedge tb_clk); + + repeat(100) tb_top.bfm.queue_random(); + + + // tb_top.bfm.write(8'h22, 0); + // tb_top.bfm.write(8'haa, 0); + // tb_top.bfm.read(10); + // tb_top.bfm.write(8'hff, 5); + // tb_top.bfm.read(0); + // tb_top.bfm.read(0); + // tb_top.bfm.write(8'h11, 1); + + + repeat(1000) @(posedge tb_clk); + + + // -------------------------------------------------------------------- + // insert test above + // -------------------------------------------------------------------- + + endtask + + +endmodule + Index: trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/wip.do =================================================================== --- trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/wip.do (nonexistent) +++ trunk/basal/sim/tests/legacy/tb_tiny_sync_fifo/wip.do (revision 50) @@ -0,0 +1,13 @@ +# + + +vlog -f ../../libs/FPGA_verilog/tiny_fifo.f +vlog -f ../../libs/sim_verilog/fifo_bfm.f + +# simulation $root +vlog ../../src/tb_tiny_sync_fifo.sv + +# compile test last +vlog ./the_test.sv + + Index: trunk/basal/src/FIFOs/tiny_async_fifo.sv =================================================================== --- trunk/basal/src/FIFOs/tiny_async_fifo.sv (revision 49) +++ trunk/basal/src/FIFOs/tiny_async_fifo.sv (nonexistent) @@ -1,189 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2015 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -module - tiny_async_fifo - #( - parameter W = 8 - ) - ( - output wr_full, - input [W-1:0] wr_data, - input wr_en, - input wr_clk, - input wr_reset, - - output rd_empty, - output [W-1:0] rd_data, - input rd_en, - input rd_clk, - input rd_reset - ); - - // -------------------------------------------------------------------- - // - wire writing = wr_en && ~wr_full; - wire reading = rd_en && ~rd_empty; - - - // -------------------------------------------------------------------- - // - function logic [1:0] - grey_counter_2_bit - ( - input logic [1:0] count - ); - - case(count) - 2'b00: grey_counter_2_bit = 2'b00; - 2'b01: grey_counter_2_bit = 2'b01; - 2'b10: grey_counter_2_bit = 2'b11; - 2'b11: grey_counter_2_bit = 2'b10; - endcase - - endfunction - - - // -------------------------------------------------------------------- - // sync grey_wr_ptr to rd clk domain - reg [1:0] grey_wr_ptr; - reg [1:0] grey_wr_ptr_r; - reg [1:0] grey_wr_ptr_s; - - always_ff @(posedge rd_clk) - if(rd_reset) - {grey_wr_ptr_s, grey_wr_ptr_r} <= 0; - else - {grey_wr_ptr_s, grey_wr_ptr_r} <= {grey_wr_ptr_r, grey_wr_ptr}; - - - // -------------------------------------------------------------------- - // sync grey_rd_ptr to wr clk domain - reg [1:0] grey_rd_ptr; - reg [1:0] grey_rd_ptr_r; - reg [1:0] grey_rd_ptr_s; - - always_ff @(posedge wr_clk) - if(rd_reset) - {grey_rd_ptr_s, grey_rd_ptr_r} <= 0; - else - {grey_rd_ptr_s, grey_rd_ptr_r} <= {grey_rd_ptr_r, grey_rd_ptr}; - - - // -------------------------------------------------------------------- - // - reg [1:0] bin_rd_ptr; - wire [1:0] bin_rd_ptr_next = bin_rd_ptr + reading; - - always_ff @(posedge rd_clk) - if(rd_reset) - bin_rd_ptr <= 0; - else - bin_rd_ptr <= bin_rd_ptr_next; - - - // -------------------------------------------------------------------- - // - wire [1:0] grey_rd_ptr_next = grey_counter_2_bit(bin_rd_ptr_next); - - always_ff @(posedge rd_clk) - if(rd_reset) - grey_rd_ptr <= 0; - else - grey_rd_ptr <= grey_rd_ptr_next; - - - // -------------------------------------------------------------------- - // - reg asf_empty_r; - - always_ff @(posedge rd_clk) - if(rd_reset) - asf_empty_r <= 1; - else - asf_empty_r <= (grey_rd_ptr_next == grey_wr_ptr_s); - - - // -------------------------------------------------------------------- - // - reg [1:0] bin_wr_ptr; - wire [1:0] bin_wr_ptr_next = bin_wr_ptr + writing; - - always_ff @(posedge wr_clk) - if(wr_reset) - bin_wr_ptr <= 0; - else - bin_wr_ptr <= bin_wr_ptr_next; - - - // -------------------------------------------------------------------- - // - wire [1:0] grey_wr_ptr_next = grey_counter_2_bit(bin_wr_ptr_next); - - always_ff @(posedge wr_clk) - if(wr_reset) - grey_wr_ptr <= 0; - else - grey_wr_ptr <= grey_wr_ptr_next; - - - // -------------------------------------------------------------------- - // - reg asf_full_r; - - always_ff @(posedge wr_clk) - if(wr_reset) - asf_full_r <= 1; - else - asf_full_r <= (grey_wr_ptr_next == ~grey_rd_ptr_s); - - - // -------------------------------------------------------------------- - // - reg [W-1:0] data_0_r; - reg [W-1:0] data_1_r; - wire [W-1:0] rd_data_mux = bin_rd_ptr[0] ? data_1_r : data_0_r; - assign rd_data = rd_data_mux; - - always_ff @(posedge wr_clk) - if (writing) - if(bin_wr_ptr[0]) - data_1_r <= wr_data; - else - data_0_r <= wr_data; - - - // -------------------------------------------------------------------- - // - assign rd_empty = asf_empty_r; - assign wr_full = asf_full_r; - - -endmodule - - Index: trunk/basal/src/FIFOs/sync_fifo.sv =================================================================== --- trunk/basal/src/FIFOs/sync_fifo.sv (revision 49) +++ trunk/basal/src/FIFOs/sync_fifo.sv (revision 50) @@ -25,7 +25,6 @@ //// //// ////////////////////////////////////////////////////////////////////// - module sync_fifo #( @@ -37,11 +36,9 @@ output wr_full, input [W-1:0] wr_data, input wr_en, - output rd_empty, output [W-1:0] rd_data, input rd_en, - output [UB:0] count, input clk, input reset @@ -48,12 +45,21 @@ ); // -------------------------------------------------------------------- - // generate begin: fifo_gen if(D == 2) begin - assign count = 0; + reg [UB:0] count_r; + assign count = count_r; + + always_comb + case({wr_full, rd_empty}) + 2'b0_0: count_r = 1; + 2'b0_1: count_r = 0; + 2'b1_0: count_r = 2; + 2'b1_1: count_r = 'x; // should never happen + endcase + tiny_sync_fifo #(.W(W)) tiny_sync_fifo_i(.*); end @@ -73,7 +79,6 @@ end endgenerate - // -------------------------------------------------------------------- // synthesis translate_off always_ff @(posedge clk) @@ -85,9 +90,5 @@ // synthesis translate_on // -------------------------------------------------------------------- - // -------------------------------------------------------------------- -// endmodule - -
/trunk/basal/src/misc/barrel_shifter.v
0,0 → 1,73
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module
barrel_shifter
#(
parameter W = 32,
parameter D = W,
parameter UB = $clog2(D)
)
(
input direction, // right = 0, left = 1
input op, // logical = 0, arithmetic = 1; left arithmetic not supported
input [UB-1:0] amount, // 0 not allowed
input [W-1:0] data_in,
output [W-1:0] data_out,
 
input reset,
input clk
);
 
// --------------------------------------------------------------------
wire [W-1:0] out [UB:0];
wire shift_in = direction & op ? data_in[W-1] : 0;
genvar j, k;
 
// --------------------------------------------------------------------
generate
for(k = 0; k < D; k = k + 1)
begin : reversal
assign out[5][k] = direction ? data_in[k] : data_in[D - 1 - k];
assign data_out[k] = direction ? out[0][k] : out[0][D - 1 - k];
end
endgenerate
 
// --------------------------------------------------------------------
generate
for(j = 0; j < UB; j = j + 1)
for(k = 0; k < D; k = k + 1)
begin : shifter
if(k > D - 1 - (2**j))
assign out[j][k] = amount[j] ? shift_in : out[j+1][k];
else
assign out[j][k] = amount[j] ? out[j+1][k + (2**j)] : out[j+1][k];
end
endgenerate
 
// --------------------------------------------------------------------
endmodule
/trunk/camera_link/docs/ds90cr286.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
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-0000258211 00000 n -0000258359 00000 n -0000258502 00000 n -0000258645 00000 n -trailer -<< -/Size 1729 -/ID[] ->> -startxref -173 -%%EOF Index: trunk/sim/libs/bfm_packages_verilog/axis_bfm.f =================================================================== --- trunk/sim/libs/bfm_packages_verilog/axis_bfm.f (revision 49) +++ trunk/sim/libs/bfm_packages_verilog/axis_bfm.f (nonexistent) @@ -1,9 +0,0 @@ -# - -${LIB_BASE_DIR}/axi4_stream_lib/sim/src/axis_bfm_pkg.sv - - - - - - Index: trunk/sim/libs/bfm_packages_verilog/axi4_models.f =================================================================== --- trunk/sim/libs/bfm_packages_verilog/axi4_models.f (revision 49) +++ trunk/sim/libs/bfm_packages_verilog/axi4_models.f (nonexistent) @@ -1,6 +0,0 @@ -# - -${LIB_BASE_DIR}/axi4_lib/sim/src/axi4_models/axi4_models_pkg.sv -${LIB_BASE_DIR}/axi4_lib/sim/src/axi4_models/axi4_memory_pkg.sv -${LIB_BASE_DIR}/axi4_lib/sim/src/axi4_models/axi4_arbiter_pkg.sv - Index: trunk/sim/libs/bfm_packages_verilog/BFM.f =================================================================== --- trunk/sim/libs/bfm_packages_verilog/BFM.f (revision 49) +++ trunk/sim/libs/bfm_packages_verilog/BFM.f (revision 50) @@ -1,4 +1,3 @@ # ${LIB_BASE_DIR}/BFM/src/tb/tb_pkg.sv -${LIB_BASE_DIR}/BFM/src/tb/tb_bfm_pkg.sv
/trunk/sim/libs/qaz_lib_verilog/basal.f
1,38 → 1,15
#
 
${LIB_BASE_DIR}/basal/src/8b10b/decode_8b10b.v
${LIB_BASE_DIR}/basal/src/8b10b/encode_8b10b.v
 
${LIB_BASE_DIR}/basal/src/FIFOs/bc_sync_fifo.v
${LIB_BASE_DIR}/basal/src/FIFOs/sync_fifo.sv
${LIB_BASE_DIR}/basal/src/FIFOs/tiny_sync_fifo.sv
${LIB_BASE_DIR}/basal/src/FIFOs/async_fifo.sv
 
${LIB_BASE_DIR}/basal/src/misc/bit_connect_big_to_little.v
${LIB_BASE_DIR}/basal/src/misc/bit_connect_little_to_big.v
${LIB_BASE_DIR}/basal/src/misc/bit_swap_big_to_little.v
${LIB_BASE_DIR}/basal/src/misc/bit_swap_little_to_big.v
${LIB_BASE_DIR}/basal/src/misc/one_hot_encoder.sv
${LIB_BASE_DIR}/basal/src/misc/pulse_stretcher.v
${LIB_BASE_DIR}/basal/src/misc/recursive_mux.sv
${LIB_BASE_DIR}/basal/src/misc/sr_latch.v
 
${LIB_BASE_DIR}/basal/src/PRBS/cf_pnmon.v
${LIB_BASE_DIR}/basal/src/PRBS/pcie_scrambler.v
${LIB_BASE_DIR}/basal/src/PRBS/prbs_23_to_16.v
${LIB_BASE_DIR}/basal/src/PRBS/prbs_23_to_64.v
${LIB_BASE_DIR}/basal/src/PRBS/prbs_23_to_8.v
${LIB_BASE_DIR}/basal/src/PRBS/prbs_7_to_14.v
${LIB_BASE_DIR}/basal/src/PRBS/prbs_7_to_8.v
 
${LIB_BASE_DIR}/basal/src/RAM/asym_ram_sdp_read_wider.v
${LIB_BASE_DIR}/basal/src/RAM/asym_ram_sdp_write_wider.v
${LIB_BASE_DIR}/basal/src/RAM/bram_tdp.v
${LIB_BASE_DIR}/basal/src/RAM/byte_enabled_simple_dual_port_ram.sv
${LIB_BASE_DIR}/basal/src/RAM/read_mixed_width_ram.sv
${LIB_BASE_DIR}/basal/src/RAM/write_mixed_width_ram.sv
 
${LIB_BASE_DIR}/basal/src/synchronize/synchronizer.v
${LIB_BASE_DIR}/basal/src/synchronize/sync_reset.v
${LIB_BASE_DIR}/basal/src/synchronize/pulse_synchronizer.v
 
/trunk/sim/libs/sim_verilog/axi4_models.f File deleted
/trunk/sim/libs/sim_verilog/BFM.f
1,5 → 1,5
#
 
${LIB_BASE_DIR}/BFM/src/tb/tb_base.sv
${LIB_BASE_DIR}/BFM/src/tb/tb_clk.sv
${LIB_BASE_DIR}/BFM/src/tb/tb_clk_class.sv
# ${LIB_BASE_DIR}/BFM/src/tb/tb_clk.sv
# ${LIB_BASE_DIR}/BFM/src/tb/tb_clk_class.sv
/trunk/sim/libs/tb_packages_verilog/BFM.f
1,8 → 1,5
#
 
${LIB_BASE_DIR}/BFM/src/tb/tb_clk_pkg.sv
${LIB_BASE_DIR}/BFM/src/tb/q_pkg.sv
${LIB_BASE_DIR}/BFM/src/tb/bfm_pkg.sv
${LIB_BASE_DIR}/BFM/src/tb/logger_pkg.sv
# ${LIB_BASE_DIR}/BFM/src/tb/tb_clk_pkg.sv
 
${LIB_BASE_DIR}/BFM/src/video_frame/video_frame_pkg.sv

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