URL
https://opencores.org/ocsvn/qspiflash/qspiflash/trunk
Subversion Repositories qspiflash
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- from Rev 11 to Rev 10
- ↔ Reverse comparison
Rev 11 → Rev 10
/qspiflash/trunk/rtl/Makefile
File deleted
/qspiflash/trunk/rtl/eqspiflash.v
725,7 → 725,6
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reg [3:0] rd_state; |
reg r_leave_xip, r_xip, r_quad, r_requested; |
reg [3:0] invalid_ack_pipe; |
initial rd_state = `RD_IDLE; |
initial o_data_ack = 1'b0; |
initial o_bus_ack = 1'b0; |
737,7 → 736,6
o_spi_recycle <= 1'b0; |
if (i_spi_valid) |
o_data <= i_spi_data; |
invalid_ack_pipe <= { invalid_ack_pipe[2:0], accepted }; |
case(rd_state) |
`RD_IDLE: begin |
r_requested <= 1'b0; |
778,8 → 776,9
o_spi_spd <= 1'b0; |
o_spi_len <= 2'b11; |
o_spi_wr <= (~r_requested)||(i_piperd); |
invalid_ack_pipe[0] <= (!r_requested); |
o_data_ack <= (!invalid_ack_pipe[3])&&(i_spi_valid)&&(r_requested); |
// if (accepted) |
// o_spi_wr <= (i_piperd); |
o_data_ack <= (r_requested)&&(i_spi_valid); |
o_bus_ack <= (r_requested)&&(accepted)&&(i_piperd); |
r_requested <= (r_requested)||(accepted); |
if ((i_spi_valid)&&(~o_spi_wr)) |
791,14 → 790,13
o_spi_spd <= 1'b1; |
o_spi_len <= 2'b11; |
o_spi_recycle <= (r_leave_xip)? 1'b1: 1'b0; |
invalid_ack_pipe[0] <= (!r_requested); |
r_requested <= (r_requested)||(accepted); |
o_data_ack <= (!invalid_ack_pipe[3])&&(i_spi_valid)&&(r_requested)&&(~r_leave_xip); |
o_data_ack <= (r_requested)&&(i_spi_valid)&&(~r_leave_xip); |
o_bus_ack <= (r_requested)&&(accepted)&&(i_piperd)&&(~r_leave_xip); |
o_spi_wr <= (~r_requested)||(i_piperd); |
// if (accepted) |
// o_spi_wr <= (i_piperd); |
if (accepted) // only happens if (o_spi_wr) |
if (accepted) |
o_data <= i_spi_data; |
if ((i_spi_valid)&&(~o_spi_wr)) |
rd_state <= ((r_leave_xip)||(~r_xip))?`RD_GO_TO_IDLE:`RD_GO_TO_XIP; |
841,17 → 839,12
o_bus_ack <= i_readreq; |
end end |
`RD_GO_TO_IDLE: begin |
if ((!invalid_ack_pipe[3])&&(i_spi_valid)&&(~r_leave_xip)) |
o_data_ack <= 1'b1; |
o_qspi_req <= 1'b0; |
o_spi_wr <= 1'b0; |
o_qspi_req <= 1'b0; |
if ((i_spi_stopped)&&(~i_grant)) |
rd_state <= `RD_IDLE; |
end |
`RD_GO_TO_XIP: begin |
r_requested <= 1'b0; |
if ((i_spi_valid)&&(!invalid_ack_pipe[3])) |
o_data_ack <= 1'b1; |
o_qspi_req <= 1'b1; |
o_spi_wr <= 1'b0; |
if (i_spi_stopped) |
932,7 → 925,7
accepted <= (~i_spi_busy)&&(i_qspi_grant)&&(o_spi_wr)&&(~accepted); |
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reg cyc, chk_wip, valid_status; |
reg cyc, chk_wip; |
reg [3:0] wr_state; |
initial wr_state = `WR_IDLE; |
initial cyc = 1'b0; |
941,9 → 934,9
chk_wip <= 1'b0; |
o_bus_ack <= 1'b0; |
o_data_ack <= 1'b0; |
cyc <= (cyc)&&(~i_endpipe); |
case(wr_state) |
`WR_IDLE: begin |
valid_status <= 1'b0; |
o_qspi_req <= 1'b0; |
cyc <= 1'b0; |
if (i_ereq) |
1007,7 → 1000,6
o_spi_spd <= i_quad; |
o_spi_hold <= 1'b1; |
o_spi_word <= i_data; |
cyc <= (cyc)&&(~i_endpipe); |
if (~cyc) |
wr_state <= `WR_WAIT_ON_STOP; |
else if (i_pipewr) |
1069,7 → 1061,6
o_spi_word <= 32'h00; |
if (accepted) |
wr_state <= `WR_READ_STATUS; |
valid_status <= 1'b0; |
end |
`WR_READ_STATUS: begin |
o_wip <= 1'b1; |
1081,8 → 1072,6
o_spi_dir <= 1'b1; // Read |
o_spi_word <= 32'h00; |
if (i_spi_valid) |
valid_status <= 1'b1; |
if ((i_spi_valid)&&(valid_status)) |
chk_wip <= 1'b1; |
if ((chk_wip)&&(~i_spi_data[0])) |
wr_state <= `WR_WAIT_ON_FINAL_STOP; |
1158,7 → 1147,6
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reg [2:0] ctstate; |
reg accepted; |
reg [3:0] invalid_ack_pipe; |
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initial accepted = 1'b0; |
1165,7 → 1153,7
always @(posedge i_clk) |
accepted <= (~i_spi_busy)&&(i_grant)&&(o_spi_wr)&&(~accepted); |
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reg r_ctdat_len, ctbus_ack, first_valid; |
reg r_ctdat_len, ctbus_ack; |
assign ctdat_len = { 1'b0, r_ctdat_len }; |
|
// First step, calculate the values for our state machine |
1277,7 → 1265,6
o_spi_wr <= 1'b1; |
o_bus_ack <= 1'b0; |
o_data_ack <= 1'b0; |
invalid_ack_pipe <= { invalid_ack_pipe[2:0], accepted }; |
if (i_spi_valid) |
o_data <= i_spi_data; |
case(ctstate) |
1317,13 → 1304,11
ctstate <= (ctdat_wr)?`CT_WAIT_FOR_IDLE:`CT_READ_DATA; |
if ((accepted)&&(ctdat_wr)) |
o_data_ack <= 1'b1; |
first_valid <= 1'b0; |
end |
`CT_READ_DATA: begin |
o_spi_wr <= 1'b0; // No more words to go, just to wait |
o_spi_req <= 1'b1; |
invalid_ack_pipe[0] <= 1'b0; |
if ((i_spi_valid)&&(!invalid_ack_pipe[3])) // for a value to read |
if (i_spi_valid) // for a value to read |
begin |
o_data_ack <= 1'b1; |
o_data <= i_spi_data; |
1441,9 → 1426,8
reg nxt_data_ack, nxt_data_spi; |
reg [31:0] nxt_data; |
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reg set_val, chk_wip, first_valid; |
reg set_val, chk_wip; |
reg [2:0] set_addr; |
reg [3:0] invalid_ack_pipe; |
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always @(posedge i_clk) |
begin // Depends upon state[4], otp_rd, otp_wr, otp_pipe, id_req, accepted, last_addr |
1454,7 → 1438,6
nxt_data_spi <= 1'b0; |
chk_wip <= 1'b0; |
set_val <= 1'b0; |
invalid_ack_pipe <= { invalid_ack_pipe[2:0], accepted }; |
if ((id_loaded)&&(id_read_request)) |
begin |
nxt_data_ack <= 1'b1; |
1471,7 → 1454,6
o_spi_word[6:0] <= { req_addr[4:0], 2'b00 }; |
r_data <= i_data; |
o_wip <= 1'b0; |
first_valid <= 1'b0; |
if (otp_read_request) |
begin |
// o_spi_word <= { 8'h48, 8'h00, 8'h00, 8'h00 }; |
1516,12 → 1498,11
end |
`ID_READ_DATA_COMMAND: begin |
o_spi_len <= 2'b11; // 32-bits |
o_spi_wr <= 1'b1; // Still transmitting |
o_spi_wr <= (~last_addr); // Still transmitting |
o_spi_dir <= 1'b1; // Read from SPI |
o_qspi_req <= 1'b1; |
if (accepted) |
id_state <= `ID_GET_DATA; |
first_valid <= 1'b0; |
end |
`ID_GET_DATA: begin |
o_spi_len <= 2'b11; // 32-bits |
1528,8 → 1509,7
o_spi_wr <= (~last_addr); // Still transmitting |
o_spi_dir <= 1'b1; // Read from SPI |
o_qspi_req <= 1'b1; |
invalid_ack_pipe[0] <= 1'b0; |
if((i_spi_valid)&&(!invalid_ack_pipe[3])) |
if (i_spi_valid) // same as accepted |
begin |
set_val <= 1'b1; |
set_addr <= lcl_id_addr[2:0]; |
1562,13 → 1542,12
`ID_OTP_CLEAR: begin |
o_spi_wr <= 1'b1; // Still writing |
o_spi_dir <= 1'b1; // Read from SPI |
o_spi_len <= 2'b11; // Read 32 bits |
o_spi_len <= 2'b11; // Read from SPI |
if (accepted) |
id_state <= `ID_OTP_GET_DATA; |
end |
`ID_OTP_GET_DATA: begin |
invalid_ack_pipe[0] <= 1'b0; |
if ((i_spi_valid)&&(!invalid_ack_pipe[3])) |
if (i_spi_valid) |
begin |
id_state <= `ID_FINAL_STOP; |
nxt_data_ack <= 1'b1; |
1617,8 → 1596,7
o_spi_dir <= 1'b1; // Read |
o_spi_len <= 2'b00; // 8 bits |
// o_spi_word <= dont care |
invalid_ack_pipe[0] <= 1'b0; |
if ((i_spi_valid)&&(~invalid_ack_pipe[3])) |
if (i_spi_valid) |
chk_wip <= 1'b1; |
if ((chk_wip)&&(~i_spi_data[0])) |
begin |
/qspiflash/trunk/rtl/lleqspi.v
1,6 → 1,6
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: lleqspi.v |
// Filename: llqspi.v |
// |
// Project: Wishbone Controlled Quad SPI Flash Controller |
// |
70,7 → 70,7
input i_dir; // 0 -> read, 1 -> write to SPI |
input i_recycle; // 0 = 20ns, 1 = 50ns |
output reg [31:0] o_word; |
output reg o_valid; |
output wire o_valid; |
output reg o_busy; |
// Interface with the QSPI lines |
output reg o_sck; |
83,6 → 83,100
// assign o_dbg = { state, spi_len, |
// o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat }; |
|
// Timing: |
// |
// Tick Clk BSY/WR CS_n BIT/MO STATE |
// 0 1 0/0 1 - |
// 1 1 0/1 1 - |
// 2 1 1/0 0 - QSPI_START |
// 3 0 1/0 0 - QSPI_START |
// 4 0 1/0 0 0 QSPI_BITS |
// 5 1 1/0 0 0 QSPI_BITS |
// 6 0 1/0 0 1 QSPI_BITS |
// 7 1 1/0 0 1 QSPI_BITS |
// 8 0 1/0 0 2 QSPI_BITS |
// 9 1 1/0 0 2 QSPI_BITS |
// 10 0 1/0 0 3 QSPI_BITS |
// 11 1 1/0 0 3 QSPI_BITS |
// 12 0 1/0 0 4 QSPI_BITS |
// 13 1 1/0 0 4 QSPI_BITS |
// 14 0 1/0 0 5 QSPI_BITS |
// 15 1 1/0 0 5 QSPI_BITS |
// 16 0 1/0 0 6 QSPI_BITS |
// 17 1 1/1 0 6 QSPI_BITS |
// 18 0 1/1 0 7 QSPI_READY |
// 19 1 0/1 0 7 QSPI_READY |
// 20 0 1/0/V 0 8 QSPI_BITS |
// 21 1 1/0 0 8 QSPI_BITS |
// 22 0 1/0 0 9 QSPI_BITS |
// 23 1 1/0 0 9 QSPI_BITS |
// 24 0 1/0 0 10 QSPI_BITS |
// 25 1 1/0 0 10 QSPI_BITS |
// 26 0 1/0 0 11 QSPI_BITS |
// 27 1 1/0 0 11 QSPI_BITS |
// 28 0 1/0 0 12 QSPI_BITS |
// 29 1 1/0 0 12 QSPI_BITS |
// 30 0 1/0 0 13 QSPI_BITS |
// 31 1 1/0 0 13 QSPI_BITS |
// 32 0 1/0 0 14 QSPI_BITS |
// 33 1 1/0 0 14 QSPI_BITS |
// 34 0 1/0 0 15 QSPI_READY |
// 35 1 1/0 0 15 QSPI_READY |
// 36 1 1/0/V 0 - QSPI_STOP |
// 37 1 1/0 0 - QSPI_STOPB |
// 38 1 1/0 1 - QSPI_IDLE |
// 39 1 0/0 1 - |
// Now, let's switch from single bit to quad mode |
// 40 1 0/0 1 - QSPI_IDLE |
// 41 1 0/1 1 - QSPI_IDLE |
// 42 1 1/0 0 - QSPI_START |
// 43 0 1/0 0 - QSPI_START |
// 44 0 1/0 0 0 QSPI_BITS |
// 45 1 1/0 0 0 QSPI_BITS |
// 46 0 1/0 0 1 QSPI_BITS |
// 47 1 1/0 0 1 QSPI_BITS |
// 48 0 1/0 0 2 QSPI_BITS |
// 49 1 1/0 0 2 QSPI_BITS |
// 50 0 1/0 0 3 QSPI_BITS |
// 51 1 1/0 0 3 QSPI_BITS |
// 52 0 1/0 0 4 QSPI_BITS |
// 53 1 1/0 0 4 QSPI_BITS |
// 54 0 1/0 0 5 QSPI_BITS |
// 55 1 1/0 0 5 QSPI_BITS |
// 56 0 1/0 0 6 QSPI_BITS |
// 57 1 1/1/QR 0 6 QSPI_BITS |
// 58 0 1/1/QR 0 7 QSPI_READY |
// 59 1 0/1/QR 0 7 QSPI_READY |
// 60 0 1/0/?/V 0 8-11 QSPI_BITS |
// 61 1 1/0/? 0 8-11 QSPI_BITS |
// 62 0 1/0/? 0 12-15 QSPI_BITS |
// 63 1 1/0/? 0 12-15 QSPI_BITS |
// 64 1 1/0/?/V 0 - QSPI_STOP |
// 65 1 1/0/? 0 - QSPI_STOPB |
// 66 1 1/0/? 1 - QSPI_IDLE |
// 67 1 0/0 1 - QSPI_IDLE |
// Now let's try something entirely in Quad read mode, from the |
// beginning |
// 68 1 0/1/QR 1 - QSPI_IDLE |
// 69 1 1/0 0 - QSPI_START |
// 70 0 1/0 0 - QSPI_START |
// 71 0 1/0 0 0-3 QSPI_BITS |
// 72 1 1/0 0 0-3 QSPI_BITS |
// 73 0 1/1/QR 0 4-7 QSPI_BITS |
// 74 1 0/1/QR 0 4-7 QSPI_BITS |
// 75 0 1/?/?/V 0 8-11 QSPI_BITS |
// 76 1 1/?/? 0 8-11 QSPI_BITS |
// 77 0 1/1/QR 0 12-15 QSPI_BITS |
// 78 1 0/1/QR 0 12-15 QSPI_BITS |
// 79 0 1/?/?/V 0 16-19 QSPI_BITS |
// 80 1 1/0 0 16-19 QSPI_BITS |
// 81 0 1/0 0 20-23 QSPI_BITS |
// 82 1 1/0 0 20-23 QSPI_BITS |
// 83 1 1/0/V 0 - QSPI_STOP |
// 84 1 1/0 0 - QSPI_STOPB |
// 85 1 1/0 1 - QSPI_IDLE |
// 86 1 0/0 1 - QSPI_IDLE |
|
wire i_miso; |
assign i_miso = i_dat[1]; |
|
297,43 → 391,22
*/ |
end |
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`define EXTRA_DELAY |
wire rd_input_N, rd_valid_N, r_spd_N; |
`ifdef EXTRA_DELAY |
reg [2:0] rd_input_p, rd_valid_p, r_spd_p; |
always @(posedge i_clk) |
rd_input_p <= { rd_input_p[1:0], rd_input }; |
always @(posedge i_clk) |
rd_valid_p <= { rd_valid_p[1:0], rd_valid }; |
always @(posedge i_clk) |
r_spd_p <= { r_spd_p[1:0], r_spd }; |
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assign rd_input_N = rd_input_p[2]; |
assign rd_valid_N = rd_valid_p[2]; |
assign r_spd_N = r_spd_p[2]; |
`else |
assign rd_input_N = rd_input; |
assign rd_valid_N = rd_valid; |
assign r_spd_N = rd_spd; |
`endif |
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always @(posedge i_clk) |
begin |
// if ((state == `EQSPI_IDLE)||(rd_valid_N)) |
if (o_valid) |
if ((state == `EQSPI_IDLE)||(rd_valid)) |
r_input <= 31'h00; |
if ((rd_input_N)&&(r_spd_N)) |
else if ((rd_input)&&(r_spd)) |
r_input <= { r_input[26:0], i_dat }; |
else if (rd_input_N) |
else if (rd_input) |
r_input <= { r_input[29:0], i_miso }; |
|
if ((rd_valid_N)&&(r_spd_N)) |
if ((rd_valid)&&(r_spd)) |
o_word <= { r_input[27:0], i_dat }; |
else if (rd_valid_N) |
else if (rd_valid) |
o_word <= { r_input[30:0], i_miso }; |
o_valid <= rd_valid_N; |
end |
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assign o_valid = rd_valid; |
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endmodule |
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