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https://opencores.org/ocsvn/qspiflash/qspiflash/trunk
Subversion Repositories qspiflash
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/qspiflash/trunk
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Rev 4 → Rev 5
/doc/spec.pdf
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/doc/src/spec.tex
14,7 → 14,7
%% |
%% |
%% Creator: Dan Gisselquist |
%% Gisselquist Tecnology, LLC |
%% Gisselquist Technology, LLC |
%% |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
%% |
45,7 → 45,7
\title{Specification} |
\author{Dan Gisselquist, Ph.D.} |
\email{dgisselq\at opencores.org} |
\revision{Rev.~0.1} |
\revision{Rev.~0.2} |
\begin{document} |
\pagestyle{gqtekspecplain} |
\titlepage |
67,6 → 67,7
copy. |
\end{license} |
\begin{revisionhistory} |
0.2 & 5/26/2015 & Gisselquist & Minor spelling changes\\\hline |
0.1 & 5/13/2015 & Gisselquist & First Draft \\\hline |
\end{revisionhistory} |
% Revision History |
566,7 → 567,7
Revision level of wishbone & WB B4 spec \\\hline |
Type of interface & Slave, (Block) Read/Write \\\hline |
Port size & 32--bit \\\hline |
Port granulity & 32--bit \\\hline |
Port granularity & 32--bit \\\hline |
Maximum Operand Size & 32--bit \\\hline |
Data transfer ordering & Little Endian \\\hline |
Clock constraints & Must be 100~MHz or slower \\\hline |
577,6 → 578,7
{\tt i\_wb\_ctrl\_stb} & {\tt STB\_I} \\ |
{\tt i\_wb\_data\_stb} & {\tt STB\_I} \\ |
{\tt i\_wb\_we} & {\tt WE\_I} \\ |
{\tt i\_wb\_addr} & {\tt ADR\_I} \\ |
{\tt i\_wb\_data} & {\tt DAT\_I} \\ |
{\tt o\_wb\_ack} & {\tt ACK\_O} \\ |
{\tt o\_wb\_stall} & {\tt STALL\_O} \\ |