Subversion Repositories ram_wb

/ram_wb/trunk/rtl/verilog/RAM_wb_sc_dw.v File deleted

ram_wb/trunk/rtl/verilog/RAM_wb_sc_dw.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: ram_wb/trunk/rtl/verilog/ram_wb_sc_dw.v =================================================================== --- ram_wb/trunk/rtl/verilog/ram_wb_sc_dw.v (nonexistent) +++ ram_wb/trunk/rtl/verilog/ram_wb_sc_dw.v (revision 4) @@ -0,0 +1,40 @@ +module RAM_wb_sc_dw + ( + d_a, + q_a, + adr_a, + we_a, + q_b, + adr_b, + d_b, + we_b, + clk + ); + parameter DATA_WIDTH = 32; + parameter ADDR_WIDTH = 11; + parameter MEM_SIZE = 2048; + + input [(DATA_WIDTH-1):0] d_a; + input [(ADDR_WIDTH-1):0] adr_a; + input [(ADDR_WIDTH-1):0] adr_b; + input we_a; + output [(DATA_WIDTH-1):0] q_b; + input [(DATA_WIDTH-1):0] d_b; + output reg [(DATA_WIDTH-1):0] q_a; + input we_b; + input clk; + reg [(DATA_WIDTH-1):0] q_b; + reg [DATA_WIDTH-1:0] ram [0:MEM_SIZE - 1] ; + always @ (posedge clk) + begin + q_a <= ram[adr_a]; + if (we_a) + ram[adr_a] <= d_a; + end + always @ (posedge clk) + begin + q_b <= ram[adr_b]; + if (we_b) + ram[adr_b] <= d_b; + end +endmodule

ram_wb/trunk/rtl/verilog/ram_wb_sc_dw.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mergeinfo ## -0,0 +0,0 ##