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/ram_wb/trunk/rtl/verilog/ram_wb_sc_dw.v
1,40 → 1,83
module RAM_wb_sc_dw
(
d_a,
q_a,
adr_a,
we_a,
q_b,
adr_b,
d_b,
we_b,
clk
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 11;
parameter MEM_SIZE = 2048;
// True dual port RAM as found in ACTEL proasic3 devices
module ram_sc_dw (d_a, q_a, adr_a, we_a, q_b, adr_b, d_b, we_b, clk);
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
input we_a;
output [(DATA_WIDTH-1):0] q_b;
input [(DATA_WIDTH-1):0] d_b;
output reg [(DATA_WIDTH-1):0] q_a;
input we_b;
input clk;
reg [(DATA_WIDTH-1):0] q_b;
reg [DATA_WIDTH-1:0] ram [0:MEM_SIZE - 1] ;
parameter dat_width = 32;
parameter adr_width = 11;
parameter mem_size = 2048;
input [dat_width-1:0] d_a;
input [adr_width-1:0] adr_a;
input [adr_width-1:0] adr_b;
input we_a;
output reg [dat_width-1:0] q_b;
input [dat_width-1:0] d_b;
output reg [dat_width-1:0] q_a;
input we_b;
input clk;
 
reg [dat_width-1:0] ram [0:mem_size - 1] ;
always @ (posedge clk)
begin
q_a <= ram[adr_a];
if (we_a)
ram[adr_a] <= d_a;
ram[adr_a] <= d_a;
end
always @ (posedge clk)
begin
q_b <= ram[adr_b];
q_b <= ram[adr_b];
if (we_b)
ram[adr_b] <= d_b;
end
endmodule
 
// wrapper for the above dual port RAM
module ram (dat_i, dat_o, adr_i, we_i, rst, clk );
 
parameter dat_width = 32;
parameter adr_width = 11;
parameter mem_size = 2048;
input [dat_width-1:0] dat_i;
input [adr_width-1:0] adr_i;
input we_i;
output [dat_width-1:0] dat_o;
input rst;
input clk;
 
reg sel;
wire [dat_width-1:0] q_a, q_b;
 
// when adr_i[adr_width-1] = 0 => use a side
// when adr_i[adr_width-1] = 1 => use b side
// delay one clock cycle since read has one pipeline stage
always @ (posedge clk or posedge rst)
if (rst)
sel <= 1'b0;
else
sel <= adr_i[adr_width-1];
assign dat_o = !sel ? q_a : q_b;
ram_sc_dw
#
(
.dat_width(dat_width),
.adr_width(adr_width-1),
.mem_size(mem_size/2)
)
ram0
(
.d_a(dat_i),
.q_a(q_a),
.adr_a(adr_i[adr_width-2:0]),
.we_a(we_i & !adr_i[adr_width-1]),
.q_b(q_b),
.adr_b(adr_i[adr_width-2:0]),
.d_b(dat_i),
.we_b(we_i & adr_i[adr_width-1]),
.clk(clk)
);
 
endmodule // ram
/ram_wb/trunk/rtl/verilog/ram_wb.v
1,68 → 1,60
module ram_wb ( dat_i, dat_o, adr_i, we_i, sel_i, cyc_i, stb_i, ack_o, cti_i, clk_i, rst_i);
 
 
module RAM_wb ( dat_i, dat_o, adr_i, we_i, sel_i, cyc_i, stb_i, ack_o, cti_i, clk_i, rst_i);
 
parameter ram_wb_adr_width = `RAM_WB_ADR_WIDTH;
parameter ram_wb_mem_size = `RAM_WB_MEM_SIZE;
parameter ram_wb_dat_width = `RAM_WB_DAT_WIDTH;
parameter dat_width = `RAM_WB_DAT_WIDTH;
parameter adr_width = `RAM_WB_ADR_WIDTH;
parameter mem_size = `RAM_WB_MEM_SIZE;
// wishbone signals
input [31:0] dat_i;
output [31:0] dat_o;
input [ram_wb_adr_width-1:2] adr_i;
input we_i;
input [3:0] sel_i;
input cyc_i;
input stb_i;
output reg ack_o;
input [2:0] cti_i;
 
input [31:0] dat_i;
output [31:0] dat_o;
input [adr_width-1:2] adr_i;
input we_i;
input [3:0] sel_i;
input cyc_i;
input stb_i;
output reg ack_o;
input [2:0] cti_i;
// clock
input clk_i;
input clk_i;
// async reset
input rst_i;
 
wire [31:0] wr_data;
input rst_i;
wire [31:0] wr_data;
// mux for data to ram
assign wr_data[31:24] = sel_i[3] ? dat_i[31:24] : dat_o[31:24];
assign wr_data[23:16] = sel_i[2] ? dat_i[23:16] : dat_o[23:16];
assign wr_data[15: 8] = sel_i[1] ? dat_i[15: 8] : dat_o[15: 8];
assign wr_data[ 7: 0] = sel_i[0] ? dat_i[ 7: 0] : dat_o[ 7: 0];
 
 
//vfifo_dual_port_ram_sc_dw
ram_wb_sc_dw
/* #
ram
#
(
.DATA_WIDTH(32),
.ADDR_WIDTH(11)
)*/
ram
.DATA_WIDTH(dat_width),
.ADDR_WIDTH(adr_width),
.MEM_SIZE(mem_size)
)
ram0
(
.d_a(wr_data),
.q_a(),
.adr_a(adr_i),
.we_a(we_i & ack_o),
.q_b(dat_o),
.adr_b(adr_i),
.d_b(32'h0),
.we_b(1'b0),
.dat_i(wr_data),
.dat_o(dat_o),
.adr_i(adr_i),
.we_i(we_i & ack_o),
.clk(clk_i)
);
// ack_o
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
ack_o <= 1'b0;
else
if (!ack_o)
if (!ack_o) begin
if (cyc_i & stb_i)
ack_o <= 1'b1;
else
if ((sel_i != 4'b1111) | (ct_i == 3'b000) | (cti_i == 3'b111))
ack_o <= 1'b0;
ack_o <= 1'b1; end
else
if ((sel_i != 4'b1111) | (cti_i == 3'b000) | (cti_i == 3'b111))
ack_o <= 1'b0;
endmodule

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